2 comedi/drivers/amplc_dio200_common.c
4 Common support code for "amplc_dio200" and "amplc_dio200_pci".
6 Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/>
8 COMEDI - Linux Control and Measurement Device Interface
9 Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
22 #include <linux/module.h>
23 #include <linux/interrupt.h>
25 #include "../comedidev.h"
27 #include "amplc_dio200.h"
28 #include "comedi_fc.h"
31 /* 8255 control register bits */
32 #define CR_C_LO_IO 0x01
34 #define CR_B_MODE 0x04
35 #define CR_C_HI_IO 0x08
37 #define CR_A_MODE(a) ((a)<<5)
40 /* 200 series registers */
41 #define DIO200_IO_SIZE 0x20
42 #define DIO200_PCIE_IO_SIZE 0x4000
43 #define DIO200_XCLK_SCE 0x18 /* Group X clock selection register */
44 #define DIO200_YCLK_SCE 0x19 /* Group Y clock selection register */
45 #define DIO200_ZCLK_SCE 0x1a /* Group Z clock selection register */
46 #define DIO200_XGAT_SCE 0x1b /* Group X gate selection register */
47 #define DIO200_YGAT_SCE 0x1c /* Group Y gate selection register */
48 #define DIO200_ZGAT_SCE 0x1d /* Group Z gate selection register */
49 #define DIO200_INT_SCE 0x1e /* Interrupt enable/status register */
50 /* Extra registers for new PCIe boards */
51 #define DIO200_ENHANCE 0x20 /* 1 to enable enhanced features */
52 #define DIO200_VERSION 0x24 /* Hardware version register */
53 #define DIO200_TS_CONFIG 0x600 /* Timestamp timer config register */
54 #define DIO200_TS_COUNT 0x602 /* Timestamp timer count register */
57 * Functions for constructing value for DIO_200_?CLK_SCE and
58 * DIO_200_?GAT_SCE registers:
60 * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2.
61 * 'chan' is the channel: 0, 1 or 2.
62 * 'source' is the signal source: 0 to 7, or 0 to 31 for "enhanced" boards.
64 static unsigned char clk_gat_sce(unsigned int which, unsigned int chan,
67 return (which << 5) | (chan << 3) |
68 ((source & 030) << 3) | (source & 007);
71 static unsigned char clk_sce(unsigned int which, unsigned int chan,
74 return clk_gat_sce(which, chan, source);
77 static unsigned char gat_sce(unsigned int which, unsigned int chan,
80 return clk_gat_sce(which, chan, source);
84 * Periods of the internal clock sources in nanoseconds.
86 static const unsigned int clock_period[32] = {
87 [1] = 100, /* 10 MHz */
88 [2] = 1000, /* 1 MHz */
89 [3] = 10000, /* 100 kHz */
90 [4] = 100000, /* 10 kHz */
91 [5] = 1000000, /* 1 kHz */
92 [11] = 50, /* 20 MHz (enhanced boards) */
93 /* clock sources 12 and later reserved for enhanced boards */
97 * Timestamp timer configuration register (for new PCIe boards).
99 #define TS_CONFIG_RESET 0x100 /* Reset counter to zero. */
100 #define TS_CONFIG_CLK_SRC_MASK 0x0FF /* Clock source. */
101 #define TS_CONFIG_MAX_CLK_SRC 2 /* Maximum clock source value. */
104 * Periods of the timestamp timer clock sources in nanoseconds.
106 static const unsigned int ts_clock_period[TS_CONFIG_MAX_CLK_SRC + 1] = {
107 1, /* 1 nanosecond (but with 20 ns granularity). */
108 1000, /* 1 microsecond. */
109 1000000, /* 1 millisecond. */
112 struct dio200_subdev_8254 {
113 unsigned int ofs; /* Counter base offset */
114 unsigned int clk_sce_ofs; /* CLK_SCE base address */
115 unsigned int gat_sce_ofs; /* GAT_SCE base address */
116 int which; /* Bit 5 of CLK_SCE or GAT_SCE */
117 unsigned int clock_src[3]; /* Current clock sources */
118 unsigned int gate_src[3]; /* Current gate sources */
122 struct dio200_subdev_8255 {
123 unsigned int ofs; /* DIO base offset */
126 struct dio200_subdev_intr {
129 unsigned int valid_isns;
130 unsigned int enabled_isns;
131 unsigned int stopcount;
135 static inline const struct dio200_layout *
136 dio200_board_layout(const struct dio200_board *board)
138 return &board->layout;
141 static inline const struct dio200_layout *
142 dio200_dev_layout(struct comedi_device *dev)
144 return dio200_board_layout(comedi_board(dev));
148 * Read 8-bit register.
150 static unsigned char dio200_read8(struct comedi_device *dev,
153 const struct dio200_board *thisboard = comedi_board(dev);
155 offset <<= thisboard->mainshift;
158 return readb(dev->mmio + offset);
159 return inb(dev->iobase + offset);
163 * Write 8-bit register.
165 static void dio200_write8(struct comedi_device *dev, unsigned int offset,
168 const struct dio200_board *thisboard = comedi_board(dev);
170 offset <<= thisboard->mainshift;
173 writeb(val, dev->mmio + offset);
175 outb(val, dev->iobase + offset);
179 * Read 32-bit register.
181 static unsigned int dio200_read32(struct comedi_device *dev,
184 const struct dio200_board *thisboard = comedi_board(dev);
186 offset <<= thisboard->mainshift;
189 return readl(dev->mmio + offset);
190 return inl(dev->iobase + offset);
194 * Write 32-bit register.
196 static void dio200_write32(struct comedi_device *dev, unsigned int offset,
199 const struct dio200_board *thisboard = comedi_board(dev);
201 offset <<= thisboard->mainshift;
204 writel(val, dev->mmio + offset);
206 outl(val, dev->iobase + offset);
210 * 'insn_bits' function for an 'INTERRUPT' subdevice.
213 dio200_subdev_intr_insn_bits(struct comedi_device *dev,
214 struct comedi_subdevice *s,
215 struct comedi_insn *insn, unsigned int *data)
217 const struct dio200_layout *layout = dio200_dev_layout(dev);
218 struct dio200_subdev_intr *subpriv = s->private;
220 if (layout->has_int_sce) {
221 /* Just read the interrupt status register. */
222 data[1] = dio200_read8(dev, subpriv->ofs) & subpriv->valid_isns;
224 /* No interrupt status register. */
232 * Called to stop acquisition for an 'INTERRUPT' subdevice.
234 static void dio200_stop_intr(struct comedi_device *dev,
235 struct comedi_subdevice *s)
237 const struct dio200_layout *layout = dio200_dev_layout(dev);
238 struct dio200_subdev_intr *subpriv = s->private;
240 subpriv->active = false;
241 subpriv->enabled_isns = 0;
242 if (layout->has_int_sce)
243 dio200_write8(dev, subpriv->ofs, 0);
247 * Called to start acquisition for an 'INTERRUPT' subdevice.
249 static int dio200_start_intr(struct comedi_device *dev,
250 struct comedi_subdevice *s)
254 const struct dio200_layout *layout = dio200_dev_layout(dev);
255 struct dio200_subdev_intr *subpriv = s->private;
256 struct comedi_cmd *cmd = &s->async->cmd;
259 if (cmd->stop_src == TRIG_COUNT && subpriv->stopcount == 0) {
260 /* An empty acquisition! */
261 s->async->events |= COMEDI_CB_EOA;
262 subpriv->active = false;
265 /* Determine interrupt sources to enable. */
268 for (n = 0; n < cmd->chanlist_len; n++)
269 isn_bits |= (1U << CR_CHAN(cmd->chanlist[n]));
271 isn_bits &= subpriv->valid_isns;
272 /* Enable interrupt sources. */
273 subpriv->enabled_isns = isn_bits;
274 if (layout->has_int_sce)
275 dio200_write8(dev, subpriv->ofs, isn_bits);
281 static int dio200_inttrig_start_intr(struct comedi_device *dev,
282 struct comedi_subdevice *s,
283 unsigned int trig_num)
285 struct dio200_subdev_intr *subpriv = s->private;
286 struct comedi_cmd *cmd = &s->async->cmd;
290 if (trig_num != cmd->start_arg)
293 spin_lock_irqsave(&subpriv->spinlock, flags);
294 s->async->inttrig = NULL;
296 event = dio200_start_intr(dev, s);
298 spin_unlock_irqrestore(&subpriv->spinlock, flags);
301 comedi_event(dev, s);
306 static void dio200_read_scan_intr(struct comedi_device *dev,
307 struct comedi_subdevice *s,
308 unsigned int triggered)
310 struct dio200_subdev_intr *subpriv = s->private;
311 struct comedi_cmd *cmd = &s->async->cmd;
316 for (n = 0; n < cmd->chanlist_len; n++) {
317 ch = CR_CHAN(cmd->chanlist[n]);
318 if (triggered & (1U << ch))
321 /* Write the scan to the buffer. */
322 if (comedi_buf_put(s, val)) {
323 s->async->events |= (COMEDI_CB_BLOCK | COMEDI_CB_EOS);
325 /* Error! Stop acquisition. */
326 dio200_stop_intr(dev, s);
327 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW;
328 dev_err(dev->class_dev, "buffer overflow\n");
331 /* Check for end of acquisition. */
332 if (cmd->stop_src == TRIG_COUNT) {
333 if (subpriv->stopcount > 0) {
334 subpriv->stopcount--;
335 if (subpriv->stopcount == 0) {
336 s->async->events |= COMEDI_CB_EOA;
337 dio200_stop_intr(dev, s);
344 * This is called from the interrupt service routine to handle a read
345 * scan on an 'INTERRUPT' subdevice.
347 static int dio200_handle_read_intr(struct comedi_device *dev,
348 struct comedi_subdevice *s)
350 const struct dio200_layout *layout = dio200_dev_layout(dev);
351 struct dio200_subdev_intr *subpriv = s->private;
354 unsigned cur_enabled;
355 unsigned int oldevents;
360 spin_lock_irqsave(&subpriv->spinlock, flags);
361 oldevents = s->async->events;
362 if (layout->has_int_sce) {
364 * Collect interrupt sources that have triggered and disable
365 * them temporarily. Loop around until no extra interrupt
366 * sources have triggered, at which point, the valid part of
367 * the interrupt status register will read zero, clearing the
368 * cause of the interrupt.
370 * Mask off interrupt sources already seen to avoid infinite
371 * loop in case of misconfiguration.
373 cur_enabled = subpriv->enabled_isns;
374 while ((intstat = (dio200_read8(dev, subpriv->ofs) &
375 subpriv->valid_isns & ~triggered)) != 0) {
376 triggered |= intstat;
377 cur_enabled &= ~triggered;
378 dio200_write8(dev, subpriv->ofs, cur_enabled);
382 * No interrupt status register. Assume the single interrupt
383 * source has triggered.
385 triggered = subpriv->enabled_isns;
390 * Some interrupt sources have triggered and have been
391 * temporarily disabled to clear the cause of the interrupt.
393 * Reenable them NOW to minimize the time they are disabled.
395 cur_enabled = subpriv->enabled_isns;
396 if (layout->has_int_sce)
397 dio200_write8(dev, subpriv->ofs, cur_enabled);
399 if (subpriv->active) {
401 * The command is still active.
403 * Ignore interrupt sources that the command isn't
404 * interested in (just in case there's a race
407 if (triggered & subpriv->enabled_isns)
408 /* Collect scan data. */
409 dio200_read_scan_intr(dev, s, triggered);
412 spin_unlock_irqrestore(&subpriv->spinlock, flags);
414 if (oldevents != s->async->events)
415 comedi_event(dev, s);
417 return (triggered != 0);
421 * 'cancel' function for an 'INTERRUPT' subdevice.
423 static int dio200_subdev_intr_cancel(struct comedi_device *dev,
424 struct comedi_subdevice *s)
426 struct dio200_subdev_intr *subpriv = s->private;
429 spin_lock_irqsave(&subpriv->spinlock, flags);
431 dio200_stop_intr(dev, s);
433 spin_unlock_irqrestore(&subpriv->spinlock, flags);
439 * 'do_cmdtest' function for an 'INTERRUPT' subdevice.
442 dio200_subdev_intr_cmdtest(struct comedi_device *dev,
443 struct comedi_subdevice *s, struct comedi_cmd *cmd)
447 /* Step 1 : check if triggers are trivially valid */
449 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
450 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
451 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
452 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
453 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
458 /* Step 2a : make sure trigger sources are unique */
460 err |= cfc_check_trigger_is_unique(cmd->start_src);
461 err |= cfc_check_trigger_is_unique(cmd->stop_src);
463 /* Step 2b : and mutually compatible */
468 /* Step 3: check if arguments are trivially valid */
470 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
471 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
472 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
473 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
475 switch (cmd->stop_src) {
477 /* any count allowed */
480 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
489 /* step 4: fix up any arguments */
491 /* if (err) return 4; */
497 * 'do_cmd' function for an 'INTERRUPT' subdevice.
499 static int dio200_subdev_intr_cmd(struct comedi_device *dev,
500 struct comedi_subdevice *s)
502 struct comedi_cmd *cmd = &s->async->cmd;
503 struct dio200_subdev_intr *subpriv = s->private;
507 spin_lock_irqsave(&subpriv->spinlock, flags);
508 subpriv->active = true;
510 /* Set up end of acquisition. */
511 if (cmd->stop_src == TRIG_COUNT)
512 subpriv->stopcount = cmd->stop_arg;
514 subpriv->stopcount = 0;
516 if (cmd->start_src == TRIG_INT)
517 s->async->inttrig = dio200_inttrig_start_intr;
519 event = dio200_start_intr(dev, s);
521 spin_unlock_irqrestore(&subpriv->spinlock, flags);
524 comedi_event(dev, s);
530 * This function initializes an 'INTERRUPT' subdevice.
533 dio200_subdev_intr_init(struct comedi_device *dev, struct comedi_subdevice *s,
534 unsigned int offset, unsigned valid_isns)
536 const struct dio200_layout *layout = dio200_dev_layout(dev);
537 struct dio200_subdev_intr *subpriv;
539 subpriv = comedi_alloc_spriv(s, sizeof(*subpriv));
543 subpriv->ofs = offset;
544 subpriv->valid_isns = valid_isns;
545 spin_lock_init(&subpriv->spinlock);
547 if (layout->has_int_sce)
548 /* Disable interrupt sources. */
549 dio200_write8(dev, subpriv->ofs, 0);
551 s->type = COMEDI_SUBD_DI;
552 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
553 if (layout->has_int_sce) {
554 s->n_chan = DIO200_MAX_ISNS;
555 s->len_chanlist = DIO200_MAX_ISNS;
557 /* No interrupt source register. Support single channel. */
561 s->range_table = &range_digital;
563 s->insn_bits = dio200_subdev_intr_insn_bits;
564 s->do_cmdtest = dio200_subdev_intr_cmdtest;
565 s->do_cmd = dio200_subdev_intr_cmd;
566 s->cancel = dio200_subdev_intr_cancel;
572 * Interrupt service routine.
574 static irqreturn_t dio200_interrupt(int irq, void *d)
576 struct comedi_device *dev = d;
577 struct dio200_private *devpriv = dev->private;
578 struct comedi_subdevice *s;
584 if (devpriv->intr_sd >= 0) {
585 s = &dev->subdevices[devpriv->intr_sd];
586 handled = dio200_handle_read_intr(dev, s);
591 return IRQ_RETVAL(handled);
595 * Read an '8254' counter subdevice channel.
598 dio200_subdev_8254_read_chan(struct comedi_device *dev,
599 struct comedi_subdevice *s, unsigned int chan)
601 struct dio200_subdev_8254 *subpriv = s->private;
606 dio200_write8(dev, subpriv->ofs + i8254_control_reg, val);
608 val = dio200_read8(dev, subpriv->ofs + chan);
609 val += dio200_read8(dev, subpriv->ofs + chan) << 8;
614 * Write an '8254' subdevice channel.
617 dio200_subdev_8254_write_chan(struct comedi_device *dev,
618 struct comedi_subdevice *s, unsigned int chan,
621 struct dio200_subdev_8254 *subpriv = s->private;
624 dio200_write8(dev, subpriv->ofs + chan, count & 0xff);
625 dio200_write8(dev, subpriv->ofs + chan, (count >> 8) & 0xff);
629 * Set mode of an '8254' subdevice channel.
632 dio200_subdev_8254_set_mode(struct comedi_device *dev,
633 struct comedi_subdevice *s, unsigned int chan,
636 struct dio200_subdev_8254 *subpriv = s->private;
640 byte |= 0x30; /* access order: lsb, msb */
641 byte |= (mode & 0xf); /* counter mode and BCD|binary */
642 dio200_write8(dev, subpriv->ofs + i8254_control_reg, byte);
646 * Read status byte of an '8254' counter subdevice channel.
649 dio200_subdev_8254_status(struct comedi_device *dev,
650 struct comedi_subdevice *s, unsigned int chan)
652 struct dio200_subdev_8254 *subpriv = s->private;
655 dio200_write8(dev, subpriv->ofs + i8254_control_reg,
658 return dio200_read8(dev, subpriv->ofs + chan);
662 * Handle 'insn_read' for an '8254' counter subdevice.
665 dio200_subdev_8254_read(struct comedi_device *dev, struct comedi_subdevice *s,
666 struct comedi_insn *insn, unsigned int *data)
668 struct dio200_subdev_8254 *subpriv = s->private;
669 int chan = CR_CHAN(insn->chanspec);
673 for (n = 0; n < insn->n; n++) {
674 spin_lock_irqsave(&subpriv->spinlock, flags);
675 data[n] = dio200_subdev_8254_read_chan(dev, s, chan);
676 spin_unlock_irqrestore(&subpriv->spinlock, flags);
682 * Handle 'insn_write' for an '8254' counter subdevice.
685 dio200_subdev_8254_write(struct comedi_device *dev, struct comedi_subdevice *s,
686 struct comedi_insn *insn, unsigned int *data)
688 struct dio200_subdev_8254 *subpriv = s->private;
689 int chan = CR_CHAN(insn->chanspec);
693 for (n = 0; n < insn->n; n++) {
694 spin_lock_irqsave(&subpriv->spinlock, flags);
695 dio200_subdev_8254_write_chan(dev, s, chan, data[n]);
696 spin_unlock_irqrestore(&subpriv->spinlock, flags);
702 * Set gate source for an '8254' counter subdevice channel.
705 dio200_subdev_8254_set_gate_src(struct comedi_device *dev,
706 struct comedi_subdevice *s,
707 unsigned int counter_number,
708 unsigned int gate_src)
710 const struct dio200_layout *layout = dio200_dev_layout(dev);
711 struct dio200_subdev_8254 *subpriv = s->private;
714 if (!layout->has_clk_gat_sce)
716 if (counter_number > 2)
718 if (gate_src > (layout->has_enhancements ? 31 : 7))
721 subpriv->gate_src[counter_number] = gate_src;
722 byte = gat_sce(subpriv->which, counter_number, gate_src);
723 dio200_write8(dev, subpriv->gat_sce_ofs, byte);
729 * Get gate source for an '8254' counter subdevice channel.
732 dio200_subdev_8254_get_gate_src(struct comedi_device *dev,
733 struct comedi_subdevice *s,
734 unsigned int counter_number)
736 const struct dio200_layout *layout = dio200_dev_layout(dev);
737 struct dio200_subdev_8254 *subpriv = s->private;
739 if (!layout->has_clk_gat_sce)
741 if (counter_number > 2)
744 return subpriv->gate_src[counter_number];
748 * Set clock source for an '8254' counter subdevice channel.
751 dio200_subdev_8254_set_clock_src(struct comedi_device *dev,
752 struct comedi_subdevice *s,
753 unsigned int counter_number,
754 unsigned int clock_src)
756 const struct dio200_layout *layout = dio200_dev_layout(dev);
757 struct dio200_subdev_8254 *subpriv = s->private;
760 if (!layout->has_clk_gat_sce)
762 if (counter_number > 2)
764 if (clock_src > (layout->has_enhancements ? 31 : 7))
767 subpriv->clock_src[counter_number] = clock_src;
768 byte = clk_sce(subpriv->which, counter_number, clock_src);
769 dio200_write8(dev, subpriv->clk_sce_ofs, byte);
775 * Get clock source for an '8254' counter subdevice channel.
778 dio200_subdev_8254_get_clock_src(struct comedi_device *dev,
779 struct comedi_subdevice *s,
780 unsigned int counter_number,
781 unsigned int *period_ns)
783 const struct dio200_layout *layout = dio200_dev_layout(dev);
784 struct dio200_subdev_8254 *subpriv = s->private;
787 if (!layout->has_clk_gat_sce)
789 if (counter_number > 2)
792 clock_src = subpriv->clock_src[counter_number];
793 *period_ns = clock_period[clock_src];
798 * Handle 'insn_config' for an '8254' counter subdevice.
801 dio200_subdev_8254_config(struct comedi_device *dev, struct comedi_subdevice *s,
802 struct comedi_insn *insn, unsigned int *data)
804 struct dio200_subdev_8254 *subpriv = s->private;
806 int chan = CR_CHAN(insn->chanspec);
809 spin_lock_irqsave(&subpriv->spinlock, flags);
811 case INSN_CONFIG_SET_COUNTER_MODE:
812 if (data[1] > (I8254_MODE5 | I8254_BCD))
815 dio200_subdev_8254_set_mode(dev, s, chan, data[1]);
817 case INSN_CONFIG_8254_READ_STATUS:
818 data[1] = dio200_subdev_8254_status(dev, s, chan);
820 case INSN_CONFIG_SET_GATE_SRC:
821 ret = dio200_subdev_8254_set_gate_src(dev, s, chan, data[2]);
825 case INSN_CONFIG_GET_GATE_SRC:
826 ret = dio200_subdev_8254_get_gate_src(dev, s, chan);
833 case INSN_CONFIG_SET_CLOCK_SRC:
834 ret = dio200_subdev_8254_set_clock_src(dev, s, chan, data[1]);
838 case INSN_CONFIG_GET_CLOCK_SRC:
839 ret = dio200_subdev_8254_get_clock_src(dev, s, chan, &data[2]);
850 spin_unlock_irqrestore(&subpriv->spinlock, flags);
851 return ret < 0 ? ret : insn->n;
855 * This function initializes an '8254' counter subdevice.
858 dio200_subdev_8254_init(struct comedi_device *dev, struct comedi_subdevice *s,
861 const struct dio200_layout *layout = dio200_dev_layout(dev);
862 struct dio200_subdev_8254 *subpriv;
865 subpriv = comedi_alloc_spriv(s, sizeof(*subpriv));
869 s->type = COMEDI_SUBD_COUNTER;
870 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
873 s->insn_read = dio200_subdev_8254_read;
874 s->insn_write = dio200_subdev_8254_write;
875 s->insn_config = dio200_subdev_8254_config;
877 spin_lock_init(&subpriv->spinlock);
878 subpriv->ofs = offset;
879 if (layout->has_clk_gat_sce) {
880 /* Derive CLK_SCE and GAT_SCE register offsets from
882 subpriv->clk_sce_ofs = DIO200_XCLK_SCE + (offset >> 3);
883 subpriv->gat_sce_ofs = DIO200_XGAT_SCE + (offset >> 3);
884 subpriv->which = (offset >> 2) & 1;
887 /* Initialize channels. */
888 for (chan = 0; chan < 3; chan++) {
889 dio200_subdev_8254_set_mode(dev, s, chan,
890 I8254_MODE0 | I8254_BINARY);
891 if (layout->has_clk_gat_sce) {
892 /* Gate source 0 is VCC (logic 1). */
893 dio200_subdev_8254_set_gate_src(dev, s, chan, 0);
894 /* Clock source 0 is the dedicated clock input. */
895 dio200_subdev_8254_set_clock_src(dev, s, chan, 0);
903 * This function sets I/O directions for an '8255' DIO subdevice.
905 static void dio200_subdev_8255_set_dir(struct comedi_device *dev,
906 struct comedi_subdevice *s)
908 struct dio200_subdev_8255 *subpriv = s->private;
912 /* 1 in io_bits indicates output, 1 in config indicates input */
913 if (!(s->io_bits & 0x0000ff))
915 if (!(s->io_bits & 0x00ff00))
917 if (!(s->io_bits & 0x0f0000))
918 config |= CR_C_LO_IO;
919 if (!(s->io_bits & 0xf00000))
920 config |= CR_C_HI_IO;
921 dio200_write8(dev, subpriv->ofs + 3, config);
924 static int dio200_subdev_8255_bits(struct comedi_device *dev,
925 struct comedi_subdevice *s,
926 struct comedi_insn *insn,
929 struct dio200_subdev_8255 *subpriv = s->private;
933 mask = comedi_dio_update_state(s, data);
936 dio200_write8(dev, subpriv->ofs, s->state & 0xff);
938 dio200_write8(dev, subpriv->ofs + 1,
939 (s->state >> 8) & 0xff);
941 dio200_write8(dev, subpriv->ofs + 2,
942 (s->state >> 16) & 0xff);
945 val = dio200_read8(dev, subpriv->ofs);
946 val |= dio200_read8(dev, subpriv->ofs + 1) << 8;
947 val |= dio200_read8(dev, subpriv->ofs + 2) << 16;
955 * Handle 'insn_config' for an '8255' DIO subdevice.
957 static int dio200_subdev_8255_config(struct comedi_device *dev,
958 struct comedi_subdevice *s,
959 struct comedi_insn *insn,
962 unsigned int chan = CR_CHAN(insn->chanspec);
975 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
979 dio200_subdev_8255_set_dir(dev, s);
985 * This function initializes an '8255' DIO subdevice.
987 * offset is the offset to the 8255 chip.
989 static int dio200_subdev_8255_init(struct comedi_device *dev,
990 struct comedi_subdevice *s,
993 struct dio200_subdev_8255 *subpriv;
995 subpriv = comedi_alloc_spriv(s, sizeof(*subpriv));
999 subpriv->ofs = offset;
1001 s->type = COMEDI_SUBD_DIO;
1002 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1004 s->range_table = &range_digital;
1006 s->insn_bits = dio200_subdev_8255_bits;
1007 s->insn_config = dio200_subdev_8255_config;
1008 dio200_subdev_8255_set_dir(dev, s);
1013 * Handle 'insn_read' for a timer subdevice.
1015 static int dio200_subdev_timer_read(struct comedi_device *dev,
1016 struct comedi_subdevice *s,
1017 struct comedi_insn *insn,
1022 for (n = 0; n < insn->n; n++)
1023 data[n] = dio200_read32(dev, DIO200_TS_COUNT);
1028 * Reset timer subdevice.
1030 static void dio200_subdev_timer_reset(struct comedi_device *dev,
1031 struct comedi_subdevice *s)
1035 clock = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1036 dio200_write32(dev, DIO200_TS_CONFIG, clock | TS_CONFIG_RESET);
1037 dio200_write32(dev, DIO200_TS_CONFIG, clock);
1041 * Get timer subdevice clock source and period.
1043 static void dio200_subdev_timer_get_clock_src(struct comedi_device *dev,
1044 struct comedi_subdevice *s,
1046 unsigned int *period)
1050 clk = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1052 *period = (clk < ARRAY_SIZE(ts_clock_period)) ?
1053 ts_clock_period[clk] : 0;
1057 * Set timer subdevice clock source.
1059 static int dio200_subdev_timer_set_clock_src(struct comedi_device *dev,
1060 struct comedi_subdevice *s,
1063 if (src > TS_CONFIG_MAX_CLK_SRC)
1065 dio200_write32(dev, DIO200_TS_CONFIG, src);
1070 * Handle 'insn_config' for a timer subdevice.
1072 static int dio200_subdev_timer_config(struct comedi_device *dev,
1073 struct comedi_subdevice *s,
1074 struct comedi_insn *insn,
1080 case INSN_CONFIG_RESET:
1081 dio200_subdev_timer_reset(dev, s);
1083 case INSN_CONFIG_SET_CLOCK_SRC:
1084 ret = dio200_subdev_timer_set_clock_src(dev, s, data[1]);
1088 case INSN_CONFIG_GET_CLOCK_SRC:
1089 dio200_subdev_timer_get_clock_src(dev, s, &data[1], &data[2]);
1095 return ret < 0 ? ret : insn->n;
1099 * This function initializes a timer subdevice.
1101 * Uses the timestamp timer registers. There is only one timestamp timer.
1103 static int dio200_subdev_timer_init(struct comedi_device *dev,
1104 struct comedi_subdevice *s)
1106 s->type = COMEDI_SUBD_TIMER;
1107 s->subdev_flags = SDF_READABLE | SDF_LSAMPL;
1109 s->maxdata = 0xFFFFFFFF;
1110 s->insn_read = dio200_subdev_timer_read;
1111 s->insn_config = dio200_subdev_timer_config;
1115 void amplc_dio200_set_enhance(struct comedi_device *dev, unsigned char val)
1117 dio200_write8(dev, DIO200_ENHANCE, val);
1119 EXPORT_SYMBOL_GPL(amplc_dio200_set_enhance);
1121 int amplc_dio200_common_attach(struct comedi_device *dev, unsigned int irq,
1122 unsigned long req_irq_flags)
1124 const struct dio200_board *thisboard = comedi_board(dev);
1125 struct dio200_private *devpriv = dev->private;
1126 const struct dio200_layout *layout = dio200_board_layout(thisboard);
1127 struct comedi_subdevice *s;
1132 devpriv->intr_sd = -1;
1134 ret = comedi_alloc_subdevices(dev, layout->n_subdevs);
1138 for (n = 0; n < dev->n_subdevices; n++) {
1139 s = &dev->subdevices[n];
1140 switch (layout->sdtype[n]) {
1142 /* counter subdevice (8254) */
1143 ret = dio200_subdev_8254_init(dev, s,
1149 /* digital i/o subdevice (8255) */
1150 ret = dio200_subdev_8255_init(dev, s,
1156 /* 'INTERRUPT' subdevice */
1158 ret = dio200_subdev_intr_init(dev, s,
1164 devpriv->intr_sd = n;
1166 s->type = COMEDI_SUBD_UNUSED;
1170 ret = dio200_subdev_timer_init(dev, s);
1175 s->type = COMEDI_SUBD_UNUSED;
1179 sdx = devpriv->intr_sd;
1180 if (sdx >= 0 && sdx < dev->n_subdevices)
1181 dev->read_subdev = &dev->subdevices[sdx];
1183 if (request_irq(irq, dio200_interrupt, req_irq_flags,
1184 dev->board_name, dev) >= 0) {
1187 dev_warn(dev->class_dev,
1188 "warning! irq %u unavailable!\n", irq);
1194 EXPORT_SYMBOL_GPL(amplc_dio200_common_attach);
1196 void amplc_dio200_common_detach(struct comedi_device *dev)
1199 free_irq(dev->irq, dev);
1203 EXPORT_SYMBOL_GPL(amplc_dio200_common_detach);
1205 static int __init amplc_dio200_common_init(void)
1209 module_init(amplc_dio200_common_init);
1211 static void __exit amplc_dio200_common_exit(void)
1214 module_exit(amplc_dio200_common_exit);
1216 MODULE_AUTHOR("Comedi http://www.comedi.org");
1217 MODULE_DESCRIPTION("Comedi helper for amplc_dio200 and amplc_dio200_pci");
1218 MODULE_LICENSE("GPL");