2 comedi/drivers/amplc_dio200_common.c
4 Common support code for "amplc_dio200" and "amplc_dio200_pci".
6 Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/>
8 COMEDI - Linux Control and Measurement Device Interface
9 Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
22 #include <linux/module.h>
23 #include <linux/interrupt.h>
25 #include "../comedidev.h"
27 #include "amplc_dio200.h"
28 #include "comedi_fc.h"
31 /* 8255 control register bits */
32 #define CR_C_LO_IO 0x01
34 #define CR_B_MODE 0x04
35 #define CR_C_HI_IO 0x08
37 #define CR_A_MODE(a) ((a)<<5)
40 /* 200 series registers */
41 #define DIO200_IO_SIZE 0x20
42 #define DIO200_PCIE_IO_SIZE 0x4000
43 #define DIO200_XCLK_SCE 0x18 /* Group X clock selection register */
44 #define DIO200_YCLK_SCE 0x19 /* Group Y clock selection register */
45 #define DIO200_ZCLK_SCE 0x1a /* Group Z clock selection register */
46 #define DIO200_XGAT_SCE 0x1b /* Group X gate selection register */
47 #define DIO200_YGAT_SCE 0x1c /* Group Y gate selection register */
48 #define DIO200_ZGAT_SCE 0x1d /* Group Z gate selection register */
49 #define DIO200_INT_SCE 0x1e /* Interrupt enable/status register */
50 /* Extra registers for new PCIe boards */
51 #define DIO200_ENHANCE 0x20 /* 1 to enable enhanced features */
52 #define DIO200_VERSION 0x24 /* Hardware version register */
53 #define DIO200_TS_CONFIG 0x600 /* Timestamp timer config register */
54 #define DIO200_TS_COUNT 0x602 /* Timestamp timer count register */
57 * Functions for constructing value for DIO_200_?CLK_SCE and
58 * DIO_200_?GAT_SCE registers:
60 * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2.
61 * 'chan' is the channel: 0, 1 or 2.
62 * 'source' is the signal source: 0 to 7, or 0 to 31 for "enhanced" boards.
64 static unsigned char clk_gat_sce(unsigned int which, unsigned int chan,
67 return (which << 5) | (chan << 3) |
68 ((source & 030) << 3) | (source & 007);
71 static unsigned char clk_sce(unsigned int which, unsigned int chan,
74 return clk_gat_sce(which, chan, source);
77 static unsigned char gat_sce(unsigned int which, unsigned int chan,
80 return clk_gat_sce(which, chan, source);
84 * Periods of the internal clock sources in nanoseconds.
86 static const unsigned int clock_period[32] = {
87 [1] = 100, /* 10 MHz */
88 [2] = 1000, /* 1 MHz */
89 [3] = 10000, /* 100 kHz */
90 [4] = 100000, /* 10 kHz */
91 [5] = 1000000, /* 1 kHz */
92 [11] = 50, /* 20 MHz (enhanced boards) */
93 /* clock sources 12 and later reserved for enhanced boards */
97 * Timestamp timer configuration register (for new PCIe boards).
99 #define TS_CONFIG_RESET 0x100 /* Reset counter to zero. */
100 #define TS_CONFIG_CLK_SRC_MASK 0x0FF /* Clock source. */
101 #define TS_CONFIG_MAX_CLK_SRC 2 /* Maximum clock source value. */
104 * Periods of the timestamp timer clock sources in nanoseconds.
106 static const unsigned int ts_clock_period[TS_CONFIG_MAX_CLK_SRC + 1] = {
107 1, /* 1 nanosecond (but with 20 ns granularity). */
108 1000, /* 1 microsecond. */
109 1000000, /* 1 millisecond. */
112 struct dio200_subdev_8254 {
113 unsigned int ofs; /* Counter base offset */
114 unsigned int clk_sce_ofs; /* CLK_SCE base address */
115 unsigned int gat_sce_ofs; /* GAT_SCE base address */
116 int which; /* Bit 5 of CLK_SCE or GAT_SCE */
117 unsigned int clock_src[3]; /* Current clock sources */
118 unsigned int gate_src[3]; /* Current gate sources */
122 struct dio200_subdev_8255 {
123 unsigned int ofs; /* DIO base offset */
126 struct dio200_subdev_intr {
129 unsigned int valid_isns;
130 unsigned int enabled_isns;
131 unsigned int stopcount;
135 static inline const struct dio200_layout *
136 dio200_board_layout(const struct dio200_board *board)
138 return &board->layout;
141 static inline const struct dio200_layout *
142 dio200_dev_layout(struct comedi_device *dev)
144 return dio200_board_layout(comedi_board(dev));
148 * Read 8-bit register.
150 static unsigned char dio200_read8(struct comedi_device *dev,
153 const struct dio200_board *thisboard = comedi_board(dev);
154 struct dio200_private *devpriv = dev->private;
156 offset <<= thisboard->mainshift;
157 if (devpriv->io.regtype == io_regtype)
158 return inb(devpriv->io.u.iobase + offset);
160 return readb(devpriv->io.u.membase + offset);
164 * Write 8-bit register.
166 static void dio200_write8(struct comedi_device *dev, unsigned int offset,
169 const struct dio200_board *thisboard = comedi_board(dev);
170 struct dio200_private *devpriv = dev->private;
172 offset <<= thisboard->mainshift;
173 if (devpriv->io.regtype == io_regtype)
174 outb(val, devpriv->io.u.iobase + offset);
176 writeb(val, devpriv->io.u.membase + offset);
180 * Read 32-bit register.
182 static unsigned int dio200_read32(struct comedi_device *dev,
185 const struct dio200_board *thisboard = comedi_board(dev);
186 struct dio200_private *devpriv = dev->private;
188 offset <<= thisboard->mainshift;
189 if (devpriv->io.regtype == io_regtype)
190 return inl(devpriv->io.u.iobase + offset);
192 return readl(devpriv->io.u.membase + offset);
196 * Write 32-bit register.
198 static void dio200_write32(struct comedi_device *dev, unsigned int offset,
201 const struct dio200_board *thisboard = comedi_board(dev);
202 struct dio200_private *devpriv = dev->private;
204 offset <<= thisboard->mainshift;
205 if (devpriv->io.regtype == io_regtype)
206 outl(val, devpriv->io.u.iobase + offset);
208 writel(val, devpriv->io.u.membase + offset);
212 * 'insn_bits' function for an 'INTERRUPT' subdevice.
215 dio200_subdev_intr_insn_bits(struct comedi_device *dev,
216 struct comedi_subdevice *s,
217 struct comedi_insn *insn, unsigned int *data)
219 const struct dio200_layout *layout = dio200_dev_layout(dev);
220 struct dio200_subdev_intr *subpriv = s->private;
222 if (layout->has_int_sce) {
223 /* Just read the interrupt status register. */
224 data[1] = dio200_read8(dev, subpriv->ofs) & subpriv->valid_isns;
226 /* No interrupt status register. */
234 * Called to stop acquisition for an 'INTERRUPT' subdevice.
236 static void dio200_stop_intr(struct comedi_device *dev,
237 struct comedi_subdevice *s)
239 const struct dio200_layout *layout = dio200_dev_layout(dev);
240 struct dio200_subdev_intr *subpriv = s->private;
242 subpriv->active = false;
243 subpriv->enabled_isns = 0;
244 if (layout->has_int_sce)
245 dio200_write8(dev, subpriv->ofs, 0);
249 * Called to start acquisition for an 'INTERRUPT' subdevice.
251 static int dio200_start_intr(struct comedi_device *dev,
252 struct comedi_subdevice *s)
256 const struct dio200_layout *layout = dio200_dev_layout(dev);
257 struct dio200_subdev_intr *subpriv = s->private;
258 struct comedi_cmd *cmd = &s->async->cmd;
261 if (cmd->stop_src == TRIG_COUNT && subpriv->stopcount == 0) {
262 /* An empty acquisition! */
263 s->async->events |= COMEDI_CB_EOA;
264 subpriv->active = false;
267 /* Determine interrupt sources to enable. */
270 for (n = 0; n < cmd->chanlist_len; n++)
271 isn_bits |= (1U << CR_CHAN(cmd->chanlist[n]));
273 isn_bits &= subpriv->valid_isns;
274 /* Enable interrupt sources. */
275 subpriv->enabled_isns = isn_bits;
276 if (layout->has_int_sce)
277 dio200_write8(dev, subpriv->ofs, isn_bits);
283 static int dio200_inttrig_start_intr(struct comedi_device *dev,
284 struct comedi_subdevice *s,
285 unsigned int trig_num)
287 struct dio200_subdev_intr *subpriv = s->private;
288 struct comedi_cmd *cmd = &s->async->cmd;
292 if (trig_num != cmd->start_arg)
295 spin_lock_irqsave(&subpriv->spinlock, flags);
296 s->async->inttrig = NULL;
298 event = dio200_start_intr(dev, s);
300 spin_unlock_irqrestore(&subpriv->spinlock, flags);
303 comedi_event(dev, s);
308 static void dio200_read_scan_intr(struct comedi_device *dev,
309 struct comedi_subdevice *s,
310 unsigned int triggered)
312 struct dio200_subdev_intr *subpriv = s->private;
313 struct comedi_cmd *cmd = &s->async->cmd;
318 for (n = 0; n < cmd->chanlist_len; n++) {
319 ch = CR_CHAN(cmd->chanlist[n]);
320 if (triggered & (1U << ch))
323 /* Write the scan to the buffer. */
324 if (comedi_buf_put(s, val)) {
325 s->async->events |= (COMEDI_CB_BLOCK | COMEDI_CB_EOS);
327 /* Error! Stop acquisition. */
328 dio200_stop_intr(dev, s);
329 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW;
330 comedi_error(dev, "buffer overflow");
333 /* Check for end of acquisition. */
334 if (cmd->stop_src == TRIG_COUNT) {
335 if (subpriv->stopcount > 0) {
336 subpriv->stopcount--;
337 if (subpriv->stopcount == 0) {
338 s->async->events |= COMEDI_CB_EOA;
339 dio200_stop_intr(dev, s);
346 * This is called from the interrupt service routine to handle a read
347 * scan on an 'INTERRUPT' subdevice.
349 static int dio200_handle_read_intr(struct comedi_device *dev,
350 struct comedi_subdevice *s)
352 const struct dio200_layout *layout = dio200_dev_layout(dev);
353 struct dio200_subdev_intr *subpriv = s->private;
356 unsigned cur_enabled;
357 unsigned int oldevents;
362 spin_lock_irqsave(&subpriv->spinlock, flags);
363 oldevents = s->async->events;
364 if (layout->has_int_sce) {
366 * Collect interrupt sources that have triggered and disable
367 * them temporarily. Loop around until no extra interrupt
368 * sources have triggered, at which point, the valid part of
369 * the interrupt status register will read zero, clearing the
370 * cause of the interrupt.
372 * Mask off interrupt sources already seen to avoid infinite
373 * loop in case of misconfiguration.
375 cur_enabled = subpriv->enabled_isns;
376 while ((intstat = (dio200_read8(dev, subpriv->ofs) &
377 subpriv->valid_isns & ~triggered)) != 0) {
378 triggered |= intstat;
379 cur_enabled &= ~triggered;
380 dio200_write8(dev, subpriv->ofs, cur_enabled);
384 * No interrupt status register. Assume the single interrupt
385 * source has triggered.
387 triggered = subpriv->enabled_isns;
392 * Some interrupt sources have triggered and have been
393 * temporarily disabled to clear the cause of the interrupt.
395 * Reenable them NOW to minimize the time they are disabled.
397 cur_enabled = subpriv->enabled_isns;
398 if (layout->has_int_sce)
399 dio200_write8(dev, subpriv->ofs, cur_enabled);
401 if (subpriv->active) {
403 * The command is still active.
405 * Ignore interrupt sources that the command isn't
406 * interested in (just in case there's a race
409 if (triggered & subpriv->enabled_isns)
410 /* Collect scan data. */
411 dio200_read_scan_intr(dev, s, triggered);
414 spin_unlock_irqrestore(&subpriv->spinlock, flags);
416 if (oldevents != s->async->events)
417 comedi_event(dev, s);
419 return (triggered != 0);
423 * 'cancel' function for an 'INTERRUPT' subdevice.
425 static int dio200_subdev_intr_cancel(struct comedi_device *dev,
426 struct comedi_subdevice *s)
428 struct dio200_subdev_intr *subpriv = s->private;
431 spin_lock_irqsave(&subpriv->spinlock, flags);
433 dio200_stop_intr(dev, s);
435 spin_unlock_irqrestore(&subpriv->spinlock, flags);
441 * 'do_cmdtest' function for an 'INTERRUPT' subdevice.
444 dio200_subdev_intr_cmdtest(struct comedi_device *dev,
445 struct comedi_subdevice *s, struct comedi_cmd *cmd)
449 /* Step 1 : check if triggers are trivially valid */
451 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
452 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
453 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
454 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
455 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
460 /* Step 2a : make sure trigger sources are unique */
462 err |= cfc_check_trigger_is_unique(cmd->start_src);
463 err |= cfc_check_trigger_is_unique(cmd->stop_src);
465 /* Step 2b : and mutually compatible */
470 /* Step 3: check if arguments are trivially valid */
472 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
473 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
474 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
475 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
477 switch (cmd->stop_src) {
479 /* any count allowed */
482 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
491 /* step 4: fix up any arguments */
493 /* if (err) return 4; */
499 * 'do_cmd' function for an 'INTERRUPT' subdevice.
501 static int dio200_subdev_intr_cmd(struct comedi_device *dev,
502 struct comedi_subdevice *s)
504 struct comedi_cmd *cmd = &s->async->cmd;
505 struct dio200_subdev_intr *subpriv = s->private;
509 spin_lock_irqsave(&subpriv->spinlock, flags);
510 subpriv->active = true;
512 /* Set up end of acquisition. */
513 if (cmd->stop_src == TRIG_COUNT)
514 subpriv->stopcount = cmd->stop_arg;
516 subpriv->stopcount = 0;
518 if (cmd->start_src == TRIG_INT)
519 s->async->inttrig = dio200_inttrig_start_intr;
521 event = dio200_start_intr(dev, s);
523 spin_unlock_irqrestore(&subpriv->spinlock, flags);
526 comedi_event(dev, s);
532 * This function initializes an 'INTERRUPT' subdevice.
535 dio200_subdev_intr_init(struct comedi_device *dev, struct comedi_subdevice *s,
536 unsigned int offset, unsigned valid_isns)
538 const struct dio200_layout *layout = dio200_dev_layout(dev);
539 struct dio200_subdev_intr *subpriv;
541 subpriv = comedi_alloc_spriv(s, sizeof(*subpriv));
545 subpriv->ofs = offset;
546 subpriv->valid_isns = valid_isns;
547 spin_lock_init(&subpriv->spinlock);
549 if (layout->has_int_sce)
550 /* Disable interrupt sources. */
551 dio200_write8(dev, subpriv->ofs, 0);
553 s->type = COMEDI_SUBD_DI;
554 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
555 if (layout->has_int_sce) {
556 s->n_chan = DIO200_MAX_ISNS;
557 s->len_chanlist = DIO200_MAX_ISNS;
559 /* No interrupt source register. Support single channel. */
563 s->range_table = &range_digital;
565 s->insn_bits = dio200_subdev_intr_insn_bits;
566 s->do_cmdtest = dio200_subdev_intr_cmdtest;
567 s->do_cmd = dio200_subdev_intr_cmd;
568 s->cancel = dio200_subdev_intr_cancel;
574 * Interrupt service routine.
576 static irqreturn_t dio200_interrupt(int irq, void *d)
578 struct comedi_device *dev = d;
579 struct dio200_private *devpriv = dev->private;
580 struct comedi_subdevice *s;
586 if (devpriv->intr_sd >= 0) {
587 s = &dev->subdevices[devpriv->intr_sd];
588 handled = dio200_handle_read_intr(dev, s);
593 return IRQ_RETVAL(handled);
597 * Read an '8254' counter subdevice channel.
600 dio200_subdev_8254_read_chan(struct comedi_device *dev,
601 struct comedi_subdevice *s, unsigned int chan)
603 struct dio200_subdev_8254 *subpriv = s->private;
608 dio200_write8(dev, subpriv->ofs + i8254_control_reg, val);
610 val = dio200_read8(dev, subpriv->ofs + chan);
611 val += dio200_read8(dev, subpriv->ofs + chan) << 8;
616 * Write an '8254' subdevice channel.
619 dio200_subdev_8254_write_chan(struct comedi_device *dev,
620 struct comedi_subdevice *s, unsigned int chan,
623 struct dio200_subdev_8254 *subpriv = s->private;
626 dio200_write8(dev, subpriv->ofs + chan, count & 0xff);
627 dio200_write8(dev, subpriv->ofs + chan, (count >> 8) & 0xff);
631 * Set mode of an '8254' subdevice channel.
634 dio200_subdev_8254_set_mode(struct comedi_device *dev,
635 struct comedi_subdevice *s, unsigned int chan,
638 struct dio200_subdev_8254 *subpriv = s->private;
642 byte |= 0x30; /* access order: lsb, msb */
643 byte |= (mode & 0xf); /* counter mode and BCD|binary */
644 dio200_write8(dev, subpriv->ofs + i8254_control_reg, byte);
648 * Read status byte of an '8254' counter subdevice channel.
651 dio200_subdev_8254_status(struct comedi_device *dev,
652 struct comedi_subdevice *s, unsigned int chan)
654 struct dio200_subdev_8254 *subpriv = s->private;
657 dio200_write8(dev, subpriv->ofs + i8254_control_reg,
660 return dio200_read8(dev, subpriv->ofs + chan);
664 * Handle 'insn_read' for an '8254' counter subdevice.
667 dio200_subdev_8254_read(struct comedi_device *dev, struct comedi_subdevice *s,
668 struct comedi_insn *insn, unsigned int *data)
670 struct dio200_subdev_8254 *subpriv = s->private;
671 int chan = CR_CHAN(insn->chanspec);
675 for (n = 0; n < insn->n; n++) {
676 spin_lock_irqsave(&subpriv->spinlock, flags);
677 data[n] = dio200_subdev_8254_read_chan(dev, s, chan);
678 spin_unlock_irqrestore(&subpriv->spinlock, flags);
684 * Handle 'insn_write' for an '8254' counter subdevice.
687 dio200_subdev_8254_write(struct comedi_device *dev, struct comedi_subdevice *s,
688 struct comedi_insn *insn, unsigned int *data)
690 struct dio200_subdev_8254 *subpriv = s->private;
691 int chan = CR_CHAN(insn->chanspec);
695 for (n = 0; n < insn->n; n++) {
696 spin_lock_irqsave(&subpriv->spinlock, flags);
697 dio200_subdev_8254_write_chan(dev, s, chan, data[n]);
698 spin_unlock_irqrestore(&subpriv->spinlock, flags);
704 * Set gate source for an '8254' counter subdevice channel.
707 dio200_subdev_8254_set_gate_src(struct comedi_device *dev,
708 struct comedi_subdevice *s,
709 unsigned int counter_number,
710 unsigned int gate_src)
712 const struct dio200_layout *layout = dio200_dev_layout(dev);
713 struct dio200_subdev_8254 *subpriv = s->private;
716 if (!layout->has_clk_gat_sce)
718 if (counter_number > 2)
720 if (gate_src > (layout->has_enhancements ? 31 : 7))
723 subpriv->gate_src[counter_number] = gate_src;
724 byte = gat_sce(subpriv->which, counter_number, gate_src);
725 dio200_write8(dev, subpriv->gat_sce_ofs, byte);
731 * Get gate source for an '8254' counter subdevice channel.
734 dio200_subdev_8254_get_gate_src(struct comedi_device *dev,
735 struct comedi_subdevice *s,
736 unsigned int counter_number)
738 const struct dio200_layout *layout = dio200_dev_layout(dev);
739 struct dio200_subdev_8254 *subpriv = s->private;
741 if (!layout->has_clk_gat_sce)
743 if (counter_number > 2)
746 return subpriv->gate_src[counter_number];
750 * Set clock source for an '8254' counter subdevice channel.
753 dio200_subdev_8254_set_clock_src(struct comedi_device *dev,
754 struct comedi_subdevice *s,
755 unsigned int counter_number,
756 unsigned int clock_src)
758 const struct dio200_layout *layout = dio200_dev_layout(dev);
759 struct dio200_subdev_8254 *subpriv = s->private;
762 if (!layout->has_clk_gat_sce)
764 if (counter_number > 2)
766 if (clock_src > (layout->has_enhancements ? 31 : 7))
769 subpriv->clock_src[counter_number] = clock_src;
770 byte = clk_sce(subpriv->which, counter_number, clock_src);
771 dio200_write8(dev, subpriv->clk_sce_ofs, byte);
777 * Get clock source for an '8254' counter subdevice channel.
780 dio200_subdev_8254_get_clock_src(struct comedi_device *dev,
781 struct comedi_subdevice *s,
782 unsigned int counter_number,
783 unsigned int *period_ns)
785 const struct dio200_layout *layout = dio200_dev_layout(dev);
786 struct dio200_subdev_8254 *subpriv = s->private;
789 if (!layout->has_clk_gat_sce)
791 if (counter_number > 2)
794 clock_src = subpriv->clock_src[counter_number];
795 *period_ns = clock_period[clock_src];
800 * Handle 'insn_config' for an '8254' counter subdevice.
803 dio200_subdev_8254_config(struct comedi_device *dev, struct comedi_subdevice *s,
804 struct comedi_insn *insn, unsigned int *data)
806 struct dio200_subdev_8254 *subpriv = s->private;
808 int chan = CR_CHAN(insn->chanspec);
811 spin_lock_irqsave(&subpriv->spinlock, flags);
813 case INSN_CONFIG_SET_COUNTER_MODE:
814 if (data[1] > (I8254_MODE5 | I8254_BCD))
817 dio200_subdev_8254_set_mode(dev, s, chan, data[1]);
819 case INSN_CONFIG_8254_READ_STATUS:
820 data[1] = dio200_subdev_8254_status(dev, s, chan);
822 case INSN_CONFIG_SET_GATE_SRC:
823 ret = dio200_subdev_8254_set_gate_src(dev, s, chan, data[2]);
827 case INSN_CONFIG_GET_GATE_SRC:
828 ret = dio200_subdev_8254_get_gate_src(dev, s, chan);
835 case INSN_CONFIG_SET_CLOCK_SRC:
836 ret = dio200_subdev_8254_set_clock_src(dev, s, chan, data[1]);
840 case INSN_CONFIG_GET_CLOCK_SRC:
841 ret = dio200_subdev_8254_get_clock_src(dev, s, chan, &data[2]);
852 spin_unlock_irqrestore(&subpriv->spinlock, flags);
853 return ret < 0 ? ret : insn->n;
857 * This function initializes an '8254' counter subdevice.
860 dio200_subdev_8254_init(struct comedi_device *dev, struct comedi_subdevice *s,
863 const struct dio200_layout *layout = dio200_dev_layout(dev);
864 struct dio200_subdev_8254 *subpriv;
867 subpriv = comedi_alloc_spriv(s, sizeof(*subpriv));
871 s->type = COMEDI_SUBD_COUNTER;
872 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
875 s->insn_read = dio200_subdev_8254_read;
876 s->insn_write = dio200_subdev_8254_write;
877 s->insn_config = dio200_subdev_8254_config;
879 spin_lock_init(&subpriv->spinlock);
880 subpriv->ofs = offset;
881 if (layout->has_clk_gat_sce) {
882 /* Derive CLK_SCE and GAT_SCE register offsets from
884 subpriv->clk_sce_ofs = DIO200_XCLK_SCE + (offset >> 3);
885 subpriv->gat_sce_ofs = DIO200_XGAT_SCE + (offset >> 3);
886 subpriv->which = (offset >> 2) & 1;
889 /* Initialize channels. */
890 for (chan = 0; chan < 3; chan++) {
891 dio200_subdev_8254_set_mode(dev, s, chan,
892 I8254_MODE0 | I8254_BINARY);
893 if (layout->has_clk_gat_sce) {
894 /* Gate source 0 is VCC (logic 1). */
895 dio200_subdev_8254_set_gate_src(dev, s, chan, 0);
896 /* Clock source 0 is the dedicated clock input. */
897 dio200_subdev_8254_set_clock_src(dev, s, chan, 0);
905 * This function sets I/O directions for an '8255' DIO subdevice.
907 static void dio200_subdev_8255_set_dir(struct comedi_device *dev,
908 struct comedi_subdevice *s)
910 struct dio200_subdev_8255 *subpriv = s->private;
914 /* 1 in io_bits indicates output, 1 in config indicates input */
915 if (!(s->io_bits & 0x0000ff))
917 if (!(s->io_bits & 0x00ff00))
919 if (!(s->io_bits & 0x0f0000))
920 config |= CR_C_LO_IO;
921 if (!(s->io_bits & 0xf00000))
922 config |= CR_C_HI_IO;
923 dio200_write8(dev, subpriv->ofs + 3, config);
926 static int dio200_subdev_8255_bits(struct comedi_device *dev,
927 struct comedi_subdevice *s,
928 struct comedi_insn *insn,
931 struct dio200_subdev_8255 *subpriv = s->private;
935 mask = comedi_dio_update_state(s, data);
938 dio200_write8(dev, subpriv->ofs, s->state & 0xff);
940 dio200_write8(dev, subpriv->ofs + 1,
941 (s->state >> 8) & 0xff);
943 dio200_write8(dev, subpriv->ofs + 2,
944 (s->state >> 16) & 0xff);
947 val = dio200_read8(dev, subpriv->ofs);
948 val |= dio200_read8(dev, subpriv->ofs + 1) << 8;
949 val |= dio200_read8(dev, subpriv->ofs + 2) << 16;
957 * Handle 'insn_config' for an '8255' DIO subdevice.
959 static int dio200_subdev_8255_config(struct comedi_device *dev,
960 struct comedi_subdevice *s,
961 struct comedi_insn *insn,
964 unsigned int chan = CR_CHAN(insn->chanspec);
977 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
981 dio200_subdev_8255_set_dir(dev, s);
987 * This function initializes an '8255' DIO subdevice.
989 * offset is the offset to the 8255 chip.
991 static int dio200_subdev_8255_init(struct comedi_device *dev,
992 struct comedi_subdevice *s,
995 struct dio200_subdev_8255 *subpriv;
997 subpriv = comedi_alloc_spriv(s, sizeof(*subpriv));
1001 subpriv->ofs = offset;
1003 s->type = COMEDI_SUBD_DIO;
1004 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1006 s->range_table = &range_digital;
1008 s->insn_bits = dio200_subdev_8255_bits;
1009 s->insn_config = dio200_subdev_8255_config;
1010 dio200_subdev_8255_set_dir(dev, s);
1015 * Handle 'insn_read' for a timer subdevice.
1017 static int dio200_subdev_timer_read(struct comedi_device *dev,
1018 struct comedi_subdevice *s,
1019 struct comedi_insn *insn,
1024 for (n = 0; n < insn->n; n++)
1025 data[n] = dio200_read32(dev, DIO200_TS_COUNT);
1030 * Reset timer subdevice.
1032 static void dio200_subdev_timer_reset(struct comedi_device *dev,
1033 struct comedi_subdevice *s)
1037 clock = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1038 dio200_write32(dev, DIO200_TS_CONFIG, clock | TS_CONFIG_RESET);
1039 dio200_write32(dev, DIO200_TS_CONFIG, clock);
1043 * Get timer subdevice clock source and period.
1045 static void dio200_subdev_timer_get_clock_src(struct comedi_device *dev,
1046 struct comedi_subdevice *s,
1048 unsigned int *period)
1052 clk = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
1054 *period = (clk < ARRAY_SIZE(ts_clock_period)) ?
1055 ts_clock_period[clk] : 0;
1059 * Set timer subdevice clock source.
1061 static int dio200_subdev_timer_set_clock_src(struct comedi_device *dev,
1062 struct comedi_subdevice *s,
1065 if (src > TS_CONFIG_MAX_CLK_SRC)
1067 dio200_write32(dev, DIO200_TS_CONFIG, src);
1072 * Handle 'insn_config' for a timer subdevice.
1074 static int dio200_subdev_timer_config(struct comedi_device *dev,
1075 struct comedi_subdevice *s,
1076 struct comedi_insn *insn,
1082 case INSN_CONFIG_RESET:
1083 dio200_subdev_timer_reset(dev, s);
1085 case INSN_CONFIG_SET_CLOCK_SRC:
1086 ret = dio200_subdev_timer_set_clock_src(dev, s, data[1]);
1090 case INSN_CONFIG_GET_CLOCK_SRC:
1091 dio200_subdev_timer_get_clock_src(dev, s, &data[1], &data[2]);
1097 return ret < 0 ? ret : insn->n;
1101 * This function initializes a timer subdevice.
1103 * Uses the timestamp timer registers. There is only one timestamp timer.
1105 static int dio200_subdev_timer_init(struct comedi_device *dev,
1106 struct comedi_subdevice *s)
1108 s->type = COMEDI_SUBD_TIMER;
1109 s->subdev_flags = SDF_READABLE | SDF_LSAMPL;
1111 s->maxdata = 0xFFFFFFFF;
1112 s->insn_read = dio200_subdev_timer_read;
1113 s->insn_config = dio200_subdev_timer_config;
1117 void amplc_dio200_set_enhance(struct comedi_device *dev, unsigned char val)
1119 dio200_write8(dev, DIO200_ENHANCE, val);
1121 EXPORT_SYMBOL_GPL(amplc_dio200_set_enhance);
1123 int amplc_dio200_common_attach(struct comedi_device *dev, unsigned int irq,
1124 unsigned long req_irq_flags)
1126 const struct dio200_board *thisboard = comedi_board(dev);
1127 struct dio200_private *devpriv = dev->private;
1128 const struct dio200_layout *layout = dio200_board_layout(thisboard);
1129 struct comedi_subdevice *s;
1134 devpriv->intr_sd = -1;
1136 ret = comedi_alloc_subdevices(dev, layout->n_subdevs);
1140 for (n = 0; n < dev->n_subdevices; n++) {
1141 s = &dev->subdevices[n];
1142 switch (layout->sdtype[n]) {
1144 /* counter subdevice (8254) */
1145 ret = dio200_subdev_8254_init(dev, s,
1151 /* digital i/o subdevice (8255) */
1152 ret = dio200_subdev_8255_init(dev, s,
1158 /* 'INTERRUPT' subdevice */
1160 ret = dio200_subdev_intr_init(dev, s,
1166 devpriv->intr_sd = n;
1168 s->type = COMEDI_SUBD_UNUSED;
1172 ret = dio200_subdev_timer_init(dev, s);
1177 s->type = COMEDI_SUBD_UNUSED;
1181 sdx = devpriv->intr_sd;
1182 if (sdx >= 0 && sdx < dev->n_subdevices)
1183 dev->read_subdev = &dev->subdevices[sdx];
1185 if (request_irq(irq, dio200_interrupt, req_irq_flags,
1186 dev->board_name, dev) >= 0) {
1189 dev_warn(dev->class_dev,
1190 "warning! irq %u unavailable!\n", irq);
1196 EXPORT_SYMBOL_GPL(amplc_dio200_common_attach);
1198 void amplc_dio200_common_detach(struct comedi_device *dev)
1200 const struct dio200_board *thisboard = comedi_board(dev);
1201 struct dio200_private *devpriv = dev->private;
1203 if (!thisboard || !devpriv)
1206 free_irq(dev->irq, dev);
1208 EXPORT_SYMBOL_GPL(amplc_dio200_common_detach);
1210 static int __init amplc_dio200_common_init(void)
1214 module_init(amplc_dio200_common_init);
1216 static void __exit amplc_dio200_common_exit(void)
1219 module_exit(amplc_dio200_common_exit);
1221 MODULE_AUTHOR("Comedi http://www.comedi.org");
1222 MODULE_DESCRIPTION("Comedi helper for amplc_dio200 and amplc_dio200_pci");
1223 MODULE_LICENSE("GPL");