drivers/staging/comedi/drivers/cb_pcidas64.c

   1 /*
   2     comedi/drivers/cb_pcidas64.c
   3     This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
   4     64xx, 60xx, and 4020 cards.
   5
   6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7     Copyright (C) 2001, 2002 Frank Mori Hess
   8
   9     Thanks also go to the following people:
  10
  11     Steve Rosenbluth, for providing the source code for
  12     his pci-das6402 driver, and source code for working QNX pci-6402
  13     drivers by Greg Laird and Mariusz Bogacz.  None of the code was
  14     used directly here, but it was useful as an additional source of
  15     documentation on how to program the boards.
  16
  17     John Sims, for much testing and feedback on pcidas-4020 support.
  18
  19     COMEDI - Linux Control and Measurement Device Interface
  20     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  21
  22     This program is free software; you can redistribute it and/or modify
  23     it under the terms of the GNU General Public License as published by
  24     the Free Software Foundation; either version 2 of the License, or
  25     (at your option) any later version.
  26
  27     This program is distributed in the hope that it will be useful,
  28     but WITHOUT ANY WARRANTY; without even the implied warranty of
  29     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30     GNU General Public License for more details.
  31
  32     You should have received a copy of the GNU General Public License
  33     along with this program; if not, write to the Free Software
  34     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  35
  36 ************************************************************************/
  37
  38 /*
  39
  40 Driver: cb_pcidas64
  41 Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series with the PLX 9080 PCI controller
  42 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  43 Status: works
  44 Updated: 2002-10-09
  45 Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
  46   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
  47   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
  48   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
  49   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
  50   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
  51   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
  52   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
  53   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
  54
  55 Configuration options:
  56    [0] - PCI bus of device (optional)
  57    [1] - PCI slot of device (optional)
  58
  59 These boards may be autocalibrated with the comedi_calibrate utility.
  60
  61 To select the bnc trigger input on the 4020 (instead of the dio input),
  62 specify a nonzero channel in the chanspec.  If you wish to use an external
  63 master clock on the 4020, you may do so by setting the scan_begin_src
  64 to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
  65 to configure the divisor to use for the external clock.
  66
  67 Some devices are not identified because the PCI device IDs are not yet
  68 known. If you have such a board, please file a bug report at
  69 https://bugs.comedi.org.
  70
  71 */
  72
  73 /*
  74
  75 TODO:
  76         make it return error if user attempts an ai command that uses the
  77                 external queue, and an ao command simultaneously
  78         user counter subdevice
  79         there are a number of boards this driver will support when they are
  80                 fully released, but does not yet since the pci device id numbers
  81                 are not yet available.
  82         support prescaled 100khz clock for slow pacing (not available on 6000 series?)
  83         make ao fifo size adjustable like ai fifo
  84 */
  85
  86 #include "../comedidev.h"
  87 #include <linux/delay.h>
  88 #include <linux/interrupt.h>
  89
  90 #include "8253.h"
  91 #include "8255.h"
  92 #include "plx9080.h"
  93 #include "comedi_fc.h"
  94
  95 #undef PCIDAS64_DEBUG           /*  disable debugging code */
  96 /* #define PCIDAS64_DEBUG         enable debugging code */
  97
  98 #ifdef PCIDAS64_DEBUG
  99 #define DEBUG_PRINT(format, args...)  printk(format , ## args)
 100 #else
 101 #define DEBUG_PRINT(format, args...)
 102 #endif
 103
 104 #define TIMER_BASE 25           /*  40MHz master clock */
 105 #define PRESCALED_TIMER_BASE    10000   /*  100kHz 'prescaled' clock for slow acquisition, maybe I'll support this someday */
 106 #define DMA_BUFFER_SIZE 0x1000
 107
 108 #define PCI_VENDOR_ID_COMPUTERBOARDS    0x1307
 109
 110 /* maximum value that can be loaded into board's 24-bit counters*/
 111 static const int max_counter_value = 0xffffff;
 112
 113 /* PCI-DAS64xxx base addresses */
 114
 115 /* indices of base address regions */
 116 enum base_address_regions {
 117         PLX9080_BADDRINDEX = 0,
 118         MAIN_BADDRINDEX = 2,
 119         DIO_COUNTER_BADDRINDEX = 3,
 120 };
 121
 122 /* priv(dev)->main_iobase registers */
 123 enum write_only_registers {
 124         INTR_ENABLE_REG = 0x0,  /*  interrupt enable register */
 125         HW_CONFIG_REG = 0x2,    /*  hardware config register */
 126         DAQ_SYNC_REG = 0xc,
 127         DAQ_ATRIG_LOW_4020_REG = 0xc,
 128         ADC_CONTROL0_REG = 0x10,        /*  adc control register 0 */
 129         ADC_CONTROL1_REG = 0x12,        /*  adc control register 1 */
 130         CALIBRATION_REG = 0x14,
 131         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,   /*  lower 16 bits of adc sample interval counter */
 132         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,   /*  upper 8 bits of adc sample interval counter */
 133         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,    /*  lower 16 bits of delay interval counter */
 134         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,    /*  upper 8 bits of delay interval counter */
 135         ADC_COUNT_LOWER_REG = 0x1e,     /*  lower 16 bits of hardware conversion/scan counter */
 136         ADC_COUNT_UPPER_REG = 0x20,     /*  upper 8 bits of hardware conversion/scan counter */
 137         ADC_START_REG = 0x22,   /*  software trigger to start acquisition */
 138         ADC_CONVERT_REG = 0x24, /*  initiates single conversion */
 139         ADC_QUEUE_CLEAR_REG = 0x26,     /*  clears adc queue */
 140         ADC_QUEUE_LOAD_REG = 0x28,      /*  loads adc queue */
 141         ADC_BUFFER_CLEAR_REG = 0x2a,
 142         ADC_QUEUE_HIGH_REG = 0x2c,      /*  high channel for internal queue, use adc_chan_bits() inline above */
 143         DAC_CONTROL0_REG = 0x50,        /*  dac control register 0 */
 144         DAC_CONTROL1_REG = 0x52,        /*  dac control register 0 */
 145         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,   /*  lower 16 bits of dac sample interval counter */
 146         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,   /*  upper 8 bits of dac sample interval counter */
 147         DAC_SELECT_REG = 0x60,
 148         DAC_START_REG = 0x64,
 149         DAC_BUFFER_CLEAR_REG = 0x66,    /*  clear dac buffer */
 150 };
 151 static inline unsigned int dac_convert_reg(unsigned int channel)
 152 {
 153         return 0x70 + (2 * (channel & 0x1));
 154 }
 155
 156 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
 157 {
 158         return 0x70 + (4 * (channel & 0x1));
 159 }
 160
 161 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
 162 {
 163         return 0x72 + (4 * (channel & 0x1));
 164 }
 165
 166 enum read_only_registers {
 167         HW_STATUS_REG = 0x0,    /*  hardware status register, reading this apparently clears pending interrupts as well */
 168         PIPE1_READ_REG = 0x4,
 169         ADC_READ_PNTR_REG = 0x8,
 170         LOWER_XFER_REG = 0x10,
 171         ADC_WRITE_PNTR_REG = 0xc,
 172         PREPOST_REG = 0x14,
 173 };
 174
 175 enum read_write_registers {
 176         I8255_4020_REG = 0x48,  /*  8255 offset, for 4020 only */
 177         ADC_QUEUE_FIFO_REG = 0x100,     /*  external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
 178         ADC_FIFO_REG = 0x200,   /* adc data fifo */
 179         DAC_FIFO_REG = 0x300,   /* dac data fifo, has weird interactions with external channel queue */
 180 };
 181
 182 /* priv(dev)->dio_counter_iobase registers */
 183 enum dio_counter_registers {
 184         DIO_8255_OFFSET = 0x0,
 185         DO_REG = 0x20,
 186         DI_REG = 0x28,
 187         DIO_DIRECTION_60XX_REG = 0x40,
 188         DIO_DATA_60XX_REG = 0x48,
 189 };
 190
 191 /* bit definitions for write-only registers */
 192
 193 enum intr_enable_contents {
 194         ADC_INTR_SRC_MASK = 0x3,        /*  bits that set adc interrupt source */
 195         ADC_INTR_QFULL_BITS = 0x0,      /*  interrupt fifo quater full */
 196         ADC_INTR_EOC_BITS = 0x1,        /*  interrupt end of conversion */
 197         ADC_INTR_EOSCAN_BITS = 0x2,     /*  interrupt end of scan */
 198         ADC_INTR_EOSEQ_BITS = 0x3,      /*  interrupt end of sequence (probably wont use this it's pretty fancy) */
 199         EN_ADC_INTR_SRC_BIT = 0x4,      /*  enable adc interrupt source */
 200         EN_ADC_DONE_INTR_BIT = 0x8,     /*  enable adc acquisition done interrupt */
 201         DAC_INTR_SRC_MASK = 0x30,
 202         DAC_INTR_QEMPTY_BITS = 0x0,
 203         DAC_INTR_HIGH_CHAN_BITS = 0x10,
 204         EN_DAC_INTR_SRC_BIT = 0x40,     /*  enable dac interrupt source */
 205         EN_DAC_DONE_INTR_BIT = 0x80,
 206         EN_ADC_ACTIVE_INTR_BIT = 0x200, /*  enable adc active interrupt */
 207         EN_ADC_STOP_INTR_BIT = 0x400,   /*  enable adc stop trigger interrupt */
 208         EN_DAC_ACTIVE_INTR_BIT = 0x800, /*  enable dac active interrupt */
 209         EN_DAC_UNDERRUN_BIT = 0x4000,   /*  enable dac underrun status bit */
 210         EN_ADC_OVERRUN_BIT = 0x8000,    /*  enable adc overrun status bit */
 211 };
 212
 213 enum hw_config_contents {
 214         MASTER_CLOCK_4020_MASK = 0x3,   /*  bits that specify master clock source for 4020 */
 215         INTERNAL_CLOCK_4020_BITS = 0x1, /*  use 40 MHz internal master clock for 4020 */
 216         BNC_CLOCK_4020_BITS = 0x2,      /*  use BNC input for master clock */
 217         EXT_CLOCK_4020_BITS = 0x3,      /*  use dio input for master clock */
 218         EXT_QUEUE_BIT = 0x200,  /*  use external channel/gain queue (more versatile than internal queue) */
 219         SLOW_DAC_BIT = 0x400,   /*  use 225 nanosec strobe when loading dac instead of 50 nanosec */
 220         HW_CONFIG_DUMMY_BITS = 0x2000,  /*  bit with unknown function yet given as default value in pci-das64 manual */
 221         DMA_CH_SELECT_BIT = 0x8000,     /*  bit selects channels 1/0 for analog input/output, otherwise 0/1 */
 222         FIFO_SIZE_REG = 0x4,    /*  allows adjustment of fifo sizes */
 223         DAC_FIFO_SIZE_MASK = 0xff00,    /*  bits that set dac fifo size */
 224         DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */
 225 };
 226 #define DAC_FIFO_SIZE 0x2000
 227
 228 enum daq_atrig_low_4020_contents {
 229         EXT_AGATE_BNC_BIT = 0x8000,     /*  use trig/ext clk bnc input for analog gate signal */
 230         EXT_STOP_TRIG_BNC_BIT = 0x4000, /*  use trig/ext clk bnc input for external stop trigger signal */
 231         EXT_START_TRIG_BNC_BIT = 0x2000,        /*  use trig/ext clk bnc input for external start trigger signal */
 232 };
 233 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
 234 {
 235         return threshold & 0xfff;
 236 }
 237
 238 enum adc_control0_contents {
 239         ADC_GATE_SRC_MASK = 0x3,        /*  bits that select gate */
 240         ADC_SOFT_GATE_BITS = 0x1,       /*  software gate */
 241         ADC_EXT_GATE_BITS = 0x2,        /*  external digital gate */
 242         ADC_ANALOG_GATE_BITS = 0x3,     /*  analog level gate */
 243         ADC_GATE_LEVEL_BIT = 0x4,       /*  level-sensitive gate (for digital) */
 244         ADC_GATE_POLARITY_BIT = 0x8,    /*  gate active low */
 245         ADC_START_TRIG_SOFT_BITS = 0x10,
 246         ADC_START_TRIG_EXT_BITS = 0x20,
 247         ADC_START_TRIG_ANALOG_BITS = 0x30,
 248         ADC_START_TRIG_MASK = 0x30,
 249         ADC_START_TRIG_FALLING_BIT = 0x40,      /*  trig 1 uses falling edge */
 250         ADC_EXT_CONV_FALLING_BIT = 0x800,       /*  external pacing uses falling edge */
 251         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,     /*  enable hardware scan counter */
 252         ADC_DMA_DISABLE_BIT = 0x4000,   /*  disables dma */
 253         ADC_ENABLE_BIT = 0x8000,        /*  master adc enable */
 254 };
 255
 256 enum adc_control1_contents {
 257         ADC_QUEUE_CONFIG_BIT = 0x1,     /*  should be set for boards with > 16 channels */
 258         CONVERT_POLARITY_BIT = 0x10,
 259         EOC_POLARITY_BIT = 0x20,
 260         ADC_SW_GATE_BIT = 0x40, /*  software gate of adc */
 261         ADC_DITHER_BIT = 0x200, /*  turn on extra noise for dithering */
 262         RETRIGGER_BIT = 0x800,
 263         ADC_LO_CHANNEL_4020_MASK = 0x300,
 264         ADC_HI_CHANNEL_4020_MASK = 0xc00,
 265         TWO_CHANNEL_4020_BITS = 0x1000, /*  two channel mode for 4020 */
 266         FOUR_CHANNEL_4020_BITS = 0x2000,        /*  four channel mode for 4020 */
 267         CHANNEL_MODE_4020_MASK = 0x3000,
 268         ADC_MODE_MASK = 0xf000,
 269 };
 270 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
 271 {
 272         return (channel & 0x3) << 8;
 273 };
 274
 275 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
 276 {
 277         return (channel & 0x3) << 10;
 278 };
 279
 280 static inline uint16_t adc_mode_bits(unsigned int mode)
 281 {
 282         return (mode & 0xf) << 12;
 283 };
 284
 285 enum calibration_contents {
 286         SELECT_8800_BIT = 0x1,
 287         SELECT_8402_64XX_BIT = 0x2,
 288         SELECT_1590_60XX_BIT = 0x2,
 289         CAL_EN_64XX_BIT = 0x40, /*  calibration enable for 64xx series */
 290         SERIAL_DATA_IN_BIT = 0x80,
 291         SERIAL_CLOCK_BIT = 0x100,
 292         CAL_EN_60XX_BIT = 0x200,        /*  calibration enable for 60xx series */
 293         CAL_GAIN_BIT = 0x800,
 294 };
 295 /* calibration sources for 6025 are:
 296  *  0 : ground
 297  *  1 : 10V
 298  *  2 : 5V
 299  *  3 : 0.5V
 300  *  4 : 0.05V
 301  *  5 : ground
 302  *  6 : dac channel 0
 303  *  7 : dac channel 1
 304  */
 305 static inline uint16_t adc_src_bits(unsigned int source)
 306 {
 307         return (source & 0xf) << 3;
 308 };
 309
 310 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
 311 {
 312         return (channel & 0x3) << 8;
 313 };
 314
 315 enum adc_queue_load_contents {
 316         UNIP_BIT = 0x800,       /*  unipolar/bipolar bit */
 317         ADC_SE_DIFF_BIT = 0x1000,       /*  single-ended/ differential bit */
 318         ADC_COMMON_BIT = 0x2000,        /*  non-referenced single-ended (common-mode input) */
 319         QUEUE_EOSEQ_BIT = 0x4000,       /*  queue end of sequence */
 320         QUEUE_EOSCAN_BIT = 0x8000,      /*  queue end of scan */
 321 };
 322 static inline uint16_t adc_chan_bits(unsigned int channel)
 323 {
 324         return channel & 0x3f;
 325 };
 326
 327 enum dac_control0_contents {
 328         DAC_ENABLE_BIT = 0x8000,        /*  dac controller enable bit */
 329         DAC_CYCLIC_STOP_BIT = 0x4000,
 330         DAC_WAVEFORM_MODE_BIT = 0x100,
 331         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
 332         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
 333         WAVEFORM_TRIG_MASK = 0x30,
 334         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
 335         WAVEFORM_TRIG_SOFT_BITS = 0x10,
 336         WAVEFORM_TRIG_EXT_BITS = 0x20,
 337         WAVEFORM_TRIG_ADC1_BITS = 0x30,
 338         WAVEFORM_TRIG_FALLING_BIT = 0x8,
 339         WAVEFORM_GATE_LEVEL_BIT = 0x4,
 340         WAVEFORM_GATE_ENABLE_BIT = 0x2,
 341         WAVEFORM_GATE_SELECT_BIT = 0x1,
 342 };
 343
 344 enum dac_control1_contents {
 345         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
 346         DAC1_EXT_REF_BIT = 0x200,
 347         DAC0_EXT_REF_BIT = 0x100,
 348         DAC_OUTPUT_ENABLE_BIT = 0x80,   /*  dac output enable bit */
 349         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
 350         DAC_SW_GATE_BIT = 0x20,
 351         DAC1_UNIPOLAR_BIT = 0x8,
 352         DAC0_UNIPOLAR_BIT = 0x2,
 353 };
 354
 355 /* bit definitions for read-only registers */
 356 enum hw_status_contents {
 357         DAC_UNDERRUN_BIT = 0x1,
 358         ADC_OVERRUN_BIT = 0x2,
 359         DAC_ACTIVE_BIT = 0x4,
 360         ADC_ACTIVE_BIT = 0x8,
 361         DAC_INTR_PENDING_BIT = 0x10,
 362         ADC_INTR_PENDING_BIT = 0x20,
 363         DAC_DONE_BIT = 0x40,
 364         ADC_DONE_BIT = 0x80,
 365         EXT_INTR_PENDING_BIT = 0x100,
 366         ADC_STOP_BIT = 0x200,
 367 };
 368 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
 369 {
 370         return (hw_status_bits >> 10) & 0x3;
 371 };
 372
 373 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
 374 {
 375         return (prepost_bits >> 6) & 0x3;
 376 }
 377
 378 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
 379 {
 380         return (prepost_bits >> 12) & 0x3;
 381 }
 382
 383 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
 384 {
 385         return (prepost_bits >> 14) & 0x3;
 386 }
 387
 388 /* I2C addresses for 4020 */
 389 enum i2c_addresses {
 390         RANGE_CAL_I2C_ADDR = 0x20,
 391         CALDAC0_I2C_ADDR = 0xc,
 392         CALDAC1_I2C_ADDR = 0xd,
 393 };
 394
 395 enum range_cal_i2c_contents {
 396         ADC_SRC_4020_MASK = 0x70,       /*  bits that set what source the adc converter measures */
 397         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,       /*  make bnc trig/ext clock threshold 0V instead of 2.5V */
 398 };
 399 static inline uint8_t adc_src_4020_bits(unsigned int source)
 400 {
 401         return (source << 4) & ADC_SRC_4020_MASK;
 402 };
 403
 404 static inline uint8_t attenuate_bit(unsigned int channel)
 405 {
 406         /*  attenuate channel (+-5V input range) */
 407         return 1 << (channel & 0x3);
 408 };
 409
 410 /* analog input ranges for 64xx boards */
 411 static const struct comedi_lrange ai_ranges_64xx = {
 412         8,
 413         {
 414          BIP_RANGE(10),
 415          BIP_RANGE(5),
 416          BIP_RANGE(2.5),
 417          BIP_RANGE(1.25),
 418          UNI_RANGE(10),
 419          UNI_RANGE(5),
 420          UNI_RANGE(2.5),
 421          UNI_RANGE(1.25)
 422          }
 423 };
 424
 425 /* analog input ranges for 60xx boards */
 426 static const struct comedi_lrange ai_ranges_60xx = {
 427         4,
 428         {
 429          BIP_RANGE(10),
 430          BIP_RANGE(5),
 431          BIP_RANGE(0.5),
 432          BIP_RANGE(0.05),
 433          }
 434 };
 435
 436 /* analog input ranges for 6030, etc boards */
 437 static const struct comedi_lrange ai_ranges_6030 = {
 438         14,
 439         {
 440          BIP_RANGE(10),
 441          BIP_RANGE(5),
 442          BIP_RANGE(2),
 443          BIP_RANGE(1),
 444          BIP_RANGE(0.5),
 445          BIP_RANGE(0.2),
 446          BIP_RANGE(0.1),
 447          UNI_RANGE(10),
 448          UNI_RANGE(5),
 449          UNI_RANGE(2),
 450          UNI_RANGE(1),
 451          UNI_RANGE(0.5),
 452          UNI_RANGE(0.2),
 453          UNI_RANGE(0.1),
 454          }
 455 };
 456
 457 /* analog input ranges for 6052, etc boards */
 458 static const struct comedi_lrange ai_ranges_6052 = {
 459         15,
 460         {
 461          BIP_RANGE(10),
 462          BIP_RANGE(5),
 463          BIP_RANGE(2.5),
 464          BIP_RANGE(1),
 465          BIP_RANGE(0.5),
 466          BIP_RANGE(0.25),
 467          BIP_RANGE(0.1),
 468          BIP_RANGE(0.05),
 469          UNI_RANGE(10),
 470          UNI_RANGE(5),
 471          UNI_RANGE(2),
 472          UNI_RANGE(1),
 473          UNI_RANGE(0.5),
 474          UNI_RANGE(0.2),
 475          UNI_RANGE(0.1),
 476          }
 477 };
 478
 479 /* analog input ranges for 4020 board */
 480 static const struct comedi_lrange ai_ranges_4020 = {
 481         2,
 482         {
 483          BIP_RANGE(5),
 484          BIP_RANGE(1),
 485          }
 486 };
 487
 488 /* analog output ranges */
 489 static const struct comedi_lrange ao_ranges_64xx = {
 490         4,
 491         {
 492          BIP_RANGE(5),
 493          BIP_RANGE(10),
 494          UNI_RANGE(5),
 495          UNI_RANGE(10),
 496          }
 497 };
 498
 499 static const int ao_range_code_64xx[] = {
 500         0x0,
 501         0x1,
 502         0x2,
 503         0x3,
 504 };
 505
 506 static const struct comedi_lrange ao_ranges_60xx = {
 507         1,
 508         {
 509          BIP_RANGE(10),
 510          }
 511 };
 512
 513 static const int ao_range_code_60xx[] = {
 514         0x0,
 515 };
 516
 517 static const struct comedi_lrange ao_ranges_6030 = {
 518         2,
 519         {
 520          BIP_RANGE(10),
 521          UNI_RANGE(10),
 522          }
 523 };
 524
 525 static const int ao_range_code_6030[] = {
 526         0x0,
 527         0x2,
 528 };
 529
 530 static const struct comedi_lrange ao_ranges_4020 = {
 531         2,
 532         {
 533          BIP_RANGE(5),
 534          BIP_RANGE(10),
 535          }
 536 };
 537
 538 static const int ao_range_code_4020[] = {
 539         0x1,
 540         0x0,
 541 };
 542
 543 enum register_layout {
 544         LAYOUT_60XX,
 545         LAYOUT_64XX,
 546         LAYOUT_4020,
 547 };
 548
 549 struct hw_fifo_info {
 550         unsigned int num_segments;
 551         unsigned int max_segment_length;
 552         unsigned int sample_packing_ratio;
 553         uint16_t fifo_size_reg_mask;
 554 };
 555
 556 struct pcidas64_board {
 557         const char *name;
 558         int device_id;          /*  pci device id */
 559         int ai_se_chans;        /*  number of ai inputs in single-ended mode */
 560         int ai_bits;            /*  analog input resolution */
 561         int ai_speed;           /*  fastest conversion period in ns */
 562         const struct comedi_lrange *ai_range_table;
 563         int ao_nchan;           /*  number of analog out channels */
 564         int ao_bits;            /*  analog output resolution */
 565         int ao_scan_speed;      /*  analog output speed (for a scan, not conversion) */
 566         const struct comedi_lrange *ao_range_table;
 567         const int *ao_range_code;
 568         const struct hw_fifo_info *const ai_fifo;
 569         enum register_layout layout;    /*  different board families have slightly different registers */
 570         unsigned has_8255:1;
 571 };
 572
 573 static const struct hw_fifo_info ai_fifo_4020 = {
 574         .num_segments = 2,
 575         .max_segment_length = 0x8000,
 576         .sample_packing_ratio = 2,
 577         .fifo_size_reg_mask = 0x7f,
 578 };
 579
 580 static const struct hw_fifo_info ai_fifo_64xx = {
 581         .num_segments = 4,
 582         .max_segment_length = 0x800,
 583         .sample_packing_ratio = 1,
 584         .fifo_size_reg_mask = 0x3f,
 585 };
 586
 587 static const struct hw_fifo_info ai_fifo_60xx = {
 588         .num_segments = 4,
 589         .max_segment_length = 0x800,
 590         .sample_packing_ratio = 1,
 591         .fifo_size_reg_mask = 0x7f,
 592 };
 593
 594 /* maximum number of dma transfers we will chain together into a ring
 595  * (and the maximum number of dma buffers we maintain) */
 596 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
 597 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 598 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 599 static inline unsigned int ai_dma_ring_count(struct pcidas64_board *board)
 600 {
 601         if (board->layout == LAYOUT_4020)
 602                 return MAX_AI_DMA_RING_COUNT;
 603         else
 604                 return MIN_AI_DMA_RING_COUNT;
 605 }
 606
 607 static const int bytes_in_sample = 2;
 608
 609 static const struct pcidas64_board pcidas64_boards[] = {
 610         {
 611          .name = "pci-das6402/16",
 612          .device_id = 0x1d,
 613          .ai_se_chans = 64,
 614          .ai_bits = 16,
 615          .ai_speed = 5000,
 616          .ao_nchan = 2,
 617          .ao_bits = 16,
 618          .ao_scan_speed = 10000,
 619          .layout = LAYOUT_64XX,
 620          .ai_range_table = &ai_ranges_64xx,
 621          .ao_range_table = &ao_ranges_64xx,
 622          .ao_range_code = ao_range_code_64xx,
 623          .ai_fifo = &ai_fifo_64xx,
 624          .has_8255 = 1,
 625          },
 626         {
 627          .name = "pci-das6402/12",      /*  XXX check */
 628          .device_id = 0x1e,
 629          .ai_se_chans = 64,
 630          .ai_bits = 12,
 631          .ai_speed = 5000,
 632          .ao_nchan = 2,
 633          .ao_bits = 12,
 634          .ao_scan_speed = 10000,
 635          .layout = LAYOUT_64XX,
 636          .ai_range_table = &ai_ranges_64xx,
 637          .ao_range_table = &ao_ranges_64xx,
 638          .ao_range_code = ao_range_code_64xx,
 639          .ai_fifo = &ai_fifo_64xx,
 640          .has_8255 = 1,
 641          },
 642         {
 643          .name = "pci-das64/m1/16",
 644          .device_id = 0x35,
 645          .ai_se_chans = 64,
 646          .ai_bits = 16,
 647          .ai_speed = 1000,
 648          .ao_nchan = 2,
 649          .ao_bits = 16,
 650          .ao_scan_speed = 10000,
 651          .layout = LAYOUT_64XX,
 652          .ai_range_table = &ai_ranges_64xx,
 653          .ao_range_table = &ao_ranges_64xx,
 654          .ao_range_code = ao_range_code_64xx,
 655          .ai_fifo = &ai_fifo_64xx,
 656          .has_8255 = 1,
 657          },
 658         {
 659          .name = "pci-das64/m2/16",
 660          .device_id = 0x36,
 661          .ai_se_chans = 64,
 662          .ai_bits = 16,
 663          .ai_speed = 500,
 664          .ao_nchan = 2,
 665          .ao_bits = 16,
 666          .ao_scan_speed = 10000,
 667          .layout = LAYOUT_64XX,
 668          .ai_range_table = &ai_ranges_64xx,
 669          .ao_range_table = &ao_ranges_64xx,
 670          .ao_range_code = ao_range_code_64xx,
 671          .ai_fifo = &ai_fifo_64xx,
 672          .has_8255 = 1,
 673          },
 674         {
 675          .name = "pci-das64/m3/16",
 676          .device_id = 0x37,
 677          .ai_se_chans = 64,
 678          .ai_bits = 16,
 679          .ai_speed = 333,
 680          .ao_nchan = 2,
 681          .ao_bits = 16,
 682          .ao_scan_speed = 10000,
 683          .layout = LAYOUT_64XX,
 684          .ai_range_table = &ai_ranges_64xx,
 685          .ao_range_table = &ao_ranges_64xx,
 686          .ao_range_code = ao_range_code_64xx,
 687          .ai_fifo = &ai_fifo_64xx,
 688          .has_8255 = 1,
 689          },
 690         {
 691          .name = "pci-das6013",
 692          .device_id = 0x78,
 693          .ai_se_chans = 16,
 694          .ai_bits = 16,
 695          .ai_speed = 5000,
 696          .ao_nchan = 0,
 697          .ao_bits = 16,
 698          .layout = LAYOUT_60XX,
 699          .ai_range_table = &ai_ranges_60xx,
 700          .ao_range_table = &ao_ranges_60xx,
 701          .ao_range_code = ao_range_code_60xx,
 702          .ai_fifo = &ai_fifo_60xx,
 703          .has_8255 = 0,
 704          },
 705         {
 706          .name = "pci-das6014",
 707          .device_id = 0x79,
 708          .ai_se_chans = 16,
 709          .ai_bits = 16,
 710          .ai_speed = 5000,
 711          .ao_nchan = 2,
 712          .ao_bits = 16,
 713          .ao_scan_speed = 100000,
 714          .layout = LAYOUT_60XX,
 715          .ai_range_table = &ai_ranges_60xx,
 716          .ao_range_table = &ao_ranges_60xx,
 717          .ao_range_code = ao_range_code_60xx,
 718          .ai_fifo = &ai_fifo_60xx,
 719          .has_8255 = 0,
 720          },
 721         {
 722          .name = "pci-das6023",
 723          .device_id = 0x5d,
 724          .ai_se_chans = 16,
 725          .ai_bits = 12,
 726          .ai_speed = 5000,
 727          .ao_nchan = 0,
 728          .ao_scan_speed = 100000,
 729          .layout = LAYOUT_60XX,
 730          .ai_range_table = &ai_ranges_60xx,
 731          .ao_range_table = &ao_ranges_60xx,
 732          .ao_range_code = ao_range_code_60xx,
 733          .ai_fifo = &ai_fifo_60xx,
 734          .has_8255 = 1,
 735          },
 736         {
 737          .name = "pci-das6025",
 738          .device_id = 0x5e,
 739          .ai_se_chans = 16,
 740          .ai_bits = 12,
 741          .ai_speed = 5000,
 742          .ao_nchan = 2,
 743          .ao_bits = 12,
 744          .ao_scan_speed = 100000,
 745          .layout = LAYOUT_60XX,
 746          .ai_range_table = &ai_ranges_60xx,
 747          .ao_range_table = &ao_ranges_60xx,
 748          .ao_range_code = ao_range_code_60xx,
 749          .ai_fifo = &ai_fifo_60xx,
 750          .has_8255 = 1,
 751          },
 752         {
 753          .name = "pci-das6030",
 754          .device_id = 0x5f,
 755          .ai_se_chans = 16,
 756          .ai_bits = 16,
 757          .ai_speed = 10000,
 758          .ao_nchan = 2,
 759          .ao_bits = 16,
 760          .ao_scan_speed = 10000,
 761          .layout = LAYOUT_60XX,
 762          .ai_range_table = &ai_ranges_6030,
 763          .ao_range_table = &ao_ranges_6030,
 764          .ao_range_code = ao_range_code_6030,
 765          .ai_fifo = &ai_fifo_60xx,
 766          .has_8255 = 0,
 767          },
 768         {
 769          .name = "pci-das6031",
 770          .device_id = 0x60,
 771          .ai_se_chans = 64,
 772          .ai_bits = 16,
 773          .ai_speed = 10000,
 774          .ao_nchan = 2,
 775          .ao_bits = 16,
 776          .ao_scan_speed = 10000,
 777          .layout = LAYOUT_60XX,
 778          .ai_range_table = &ai_ranges_6030,
 779          .ao_range_table = &ao_ranges_6030,
 780          .ao_range_code = ao_range_code_6030,
 781          .ai_fifo = &ai_fifo_60xx,
 782          .has_8255 = 0,
 783          },
 784         {
 785          .name = "pci-das6032",
 786          .device_id = 0x61,
 787          .ai_se_chans = 16,
 788          .ai_bits = 16,
 789          .ai_speed = 10000,
 790          .ao_nchan = 0,
 791          .layout = LAYOUT_60XX,
 792          .ai_range_table = &ai_ranges_6030,
 793          .ai_fifo = &ai_fifo_60xx,
 794          .has_8255 = 0,
 795          },
 796         {
 797          .name = "pci-das6033",
 798          .device_id = 0x62,
 799          .ai_se_chans = 64,
 800          .ai_bits = 16,
 801          .ai_speed = 10000,
 802          .ao_nchan = 0,
 803          .layout = LAYOUT_60XX,
 804          .ai_range_table = &ai_ranges_6030,
 805          .ai_fifo = &ai_fifo_60xx,
 806          .has_8255 = 0,
 807          },
 808         {
 809          .name = "pci-das6034",
 810          .device_id = 0x63,
 811          .ai_se_chans = 16,
 812          .ai_bits = 16,
 813          .ai_speed = 5000,
 814          .ao_nchan = 0,
 815          .ao_scan_speed = 0,
 816          .layout = LAYOUT_60XX,
 817          .ai_range_table = &ai_ranges_60xx,
 818          .ai_fifo = &ai_fifo_60xx,
 819          .has_8255 = 0,
 820          },
 821         {
 822          .name = "pci-das6035",
 823          .device_id = 0x64,
 824          .ai_se_chans = 16,
 825          .ai_bits = 16,
 826          .ai_speed = 5000,
 827          .ao_nchan = 2,
 828          .ao_bits = 12,
 829          .ao_scan_speed = 100000,
 830          .layout = LAYOUT_60XX,
 831          .ai_range_table = &ai_ranges_60xx,
 832          .ao_range_table = &ao_ranges_60xx,
 833          .ao_range_code = ao_range_code_60xx,
 834          .ai_fifo = &ai_fifo_60xx,
 835          .has_8255 = 0,
 836          },
 837         {
 838          .name = "pci-das6036",
 839          .device_id = 0x6f,
 840          .ai_se_chans = 16,
 841          .ai_bits = 16,
 842          .ai_speed = 5000,
 843          .ao_nchan = 2,
 844          .ao_bits = 16,
 845          .ao_scan_speed = 100000,
 846          .layout = LAYOUT_60XX,
 847          .ai_range_table = &ai_ranges_60xx,
 848          .ao_range_table = &ao_ranges_60xx,
 849          .ao_range_code = ao_range_code_60xx,
 850          .ai_fifo = &ai_fifo_60xx,
 851          .has_8255 = 0,
 852          },
 853         {
 854          .name = "pci-das6040",
 855          .device_id = 0x65,
 856          .ai_se_chans = 16,
 857          .ai_bits = 12,
 858          .ai_speed = 2000,
 859          .ao_nchan = 2,
 860          .ao_bits = 12,
 861          .ao_scan_speed = 1000,
 862          .layout = LAYOUT_60XX,
 863          .ai_range_table = &ai_ranges_6052,
 864          .ao_range_table = &ao_ranges_6030,
 865          .ao_range_code = ao_range_code_6030,
 866          .ai_fifo = &ai_fifo_60xx,
 867          .has_8255 = 0,
 868          },
 869         {
 870          .name = "pci-das6052",
 871          .device_id = 0x66,
 872          .ai_se_chans = 16,
 873          .ai_bits = 16,
 874          .ai_speed = 3333,
 875          .ao_nchan = 2,
 876          .ao_bits = 16,
 877          .ao_scan_speed = 3333,
 878          .layout = LAYOUT_60XX,
 879          .ai_range_table = &ai_ranges_6052,
 880          .ao_range_table = &ao_ranges_6030,
 881          .ao_range_code = ao_range_code_6030,
 882          .ai_fifo = &ai_fifo_60xx,
 883          .has_8255 = 0,
 884          },
 885         {
 886          .name = "pci-das6070",
 887          .device_id = 0x67,
 888          .ai_se_chans = 16,
 889          .ai_bits = 12,
 890          .ai_speed = 800,
 891          .ao_nchan = 2,
 892          .ao_bits = 12,
 893          .ao_scan_speed = 1000,
 894          .layout = LAYOUT_60XX,
 895          .ai_range_table = &ai_ranges_6052,
 896          .ao_range_table = &ao_ranges_6030,
 897          .ao_range_code = ao_range_code_6030,
 898          .ai_fifo = &ai_fifo_60xx,
 899          .has_8255 = 0,
 900          },
 901         {
 902          .name = "pci-das6071",
 903          .device_id = 0x68,
 904          .ai_se_chans = 64,
 905          .ai_bits = 12,
 906          .ai_speed = 800,
 907          .ao_nchan = 2,
 908          .ao_bits = 12,
 909          .ao_scan_speed = 1000,
 910          .layout = LAYOUT_60XX,
 911          .ai_range_table = &ai_ranges_6052,
 912          .ao_range_table = &ao_ranges_6030,
 913          .ao_range_code = ao_range_code_6030,
 914          .ai_fifo = &ai_fifo_60xx,
 915          .has_8255 = 0,
 916          },
 917         {
 918          .name = "pci-das4020/12",
 919          .device_id = 0x52,
 920          .ai_se_chans = 4,
 921          .ai_bits = 12,
 922          .ai_speed = 50,
 923          .ao_bits = 12,
 924          .ao_nchan = 2,
 925          .ao_scan_speed = 0,    /*  no hardware pacing on ao */
 926          .layout = LAYOUT_4020,
 927          .ai_range_table = &ai_ranges_4020,
 928          .ao_range_table = &ao_ranges_4020,
 929          .ao_range_code = ao_range_code_4020,
 930          .ai_fifo = &ai_fifo_4020,
 931          .has_8255 = 1,
 932          },
 933 #if 0
 934         {
 935          .name = "pci-das6402/16/jr",
 936          .device_id = 0         /*  XXX, */
 937          .ai_se_chans = 64,
 938          .ai_bits = 16,
 939          .ai_speed = 5000,
 940          .ao_nchan = 0,
 941          .ao_scan_speed = 10000,
 942          .layout = LAYOUT_64XX,
 943          .ai_range_table = &ai_ranges_64xx,
 944          .ai_fifo = ai_fifo_64xx,
 945          .has_8255 = 1,
 946          },
 947         {
 948          .name = "pci-das64/m1/16/jr",
 949          .device_id = 0         /*  XXX, */
 950          .ai_se_chans = 64,
 951          .ai_bits = 16,
 952          .ai_speed = 1000,
 953          .ao_nchan = 0,
 954          .ao_scan_speed = 10000,
 955          .layout = LAYOUT_64XX,
 956          .ai_range_table = &ai_ranges_64xx,
 957          .ai_fifo = ai_fifo_64xx,
 958          .has_8255 = 1,
 959          },
 960         {
 961          .name = "pci-das64/m2/16/jr",
 962          .device_id = 0         /*  XXX, */
 963          .ai_se_chans = 64,
 964          .ai_bits = 16,
 965          .ai_speed = 500,
 966          .ao_nchan = 0,
 967          .ao_scan_speed = 10000,
 968          .layout = LAYOUT_64XX,
 969          .ai_range_table = &ai_ranges_64xx,
 970          .ai_fifo = ai_fifo_64xx,
 971          .has_8255 = 1,
 972          },
 973         {
 974          .name = "pci-das64/m3/16/jr",
 975          .device_id = 0         /*  XXX, */
 976          .ai_se_chans = 64,
 977          .ai_bits = 16,
 978          .ai_speed = 333,
 979          .ao_nchan = 0,
 980          .ao_scan_speed = 10000,
 981          .layout = LAYOUT_64XX,
 982          .ai_range_table = &ai_ranges_64xx,
 983          .ai_fifo = ai_fifo_64xx,
 984          .has_8255 = 1,
 985          },
 986         {
 987          .name = "pci-das64/m1/14",
 988          .device_id = 0,        /*  XXX */
 989          .ai_se_chans = 64,
 990          .ai_bits = 14,
 991          .ai_speed = 1000,
 992          .ao_nchan = 2,
 993          .ao_scan_speed = 10000,
 994          .layout = LAYOUT_64XX,
 995          .ai_range_table = &ai_ranges_64xx,
 996          .ai_fifo = ai_fifo_64xx,
 997          .has_8255 = 1,
 998          },
 999         {
1000          .name = "pci-das64/m2/14",
1001          .device_id = 0,        /*  XXX */
1002          .ai_se_chans = 64,
1003          .ai_bits = 14,
1004          .ai_speed = 500,
1005          .ao_nchan = 2,
1006          .ao_scan_speed = 10000,
1007          .layout = LAYOUT_64XX,
1008          .ai_range_table = &ai_ranges_64xx,
1009          .ai_fifo = ai_fifo_64xx,
1010          .has_8255 = 1,
1011          },
1012         {
1013          .name = "pci-das64/m3/14",
1014          .device_id = 0,        /*  XXX */
1015          .ai_se_chans = 64,
1016          .ai_bits = 14,
1017          .ai_speed = 333,
1018          .ao_nchan = 2,
1019          .ao_scan_speed = 10000,
1020          .layout = LAYOUT_64XX,
1021          .ai_range_table = &ai_ranges_64xx,
1022          .ai_fifo = ai_fifo_64xx,
1023          .has_8255 = 1,
1024          },
1025 #endif
1026 };
1027
1028 static inline struct pcidas64_board *board(const struct comedi_device *dev)
1029 {
1030         return (struct pcidas64_board *)dev->board_ptr;
1031 }
1032
1033 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1034                                               int use_differential)
1035 {
1036         if ((board(dev)->layout == LAYOUT_64XX && !use_differential) ||
1037             (board(dev)->layout == LAYOUT_60XX && use_differential))
1038                 return ADC_SE_DIFF_BIT;
1039         else
1040                 return 0;
1041 };
1042
1043 struct ext_clock_info {
1044         unsigned int divisor;   /*  master clock divisor to use for scans with external master clock */
1045         unsigned int chanspec;  /*  chanspec for master clock input when used as scan begin src */
1046 };
1047
1048 /* this structure is for data unique to this hardware driver. */
1049 struct pcidas64_private {
1050         /*  base addresses (physical) */
1051         resource_size_t plx9080_phys_iobase;
1052         resource_size_t main_phys_iobase;
1053         resource_size_t dio_counter_phys_iobase;
1054         /*  base addresses (ioremapped) */
1055         void __iomem *plx9080_iobase;
1056         void __iomem *main_iobase;
1057         void __iomem *dio_counter_iobase;
1058         /*  local address (used by dma controller) */
1059         uint32_t local0_iobase;
1060         uint32_t local1_iobase;
1061         volatile unsigned int ai_count; /*  number of analog input samples remaining */
1062         uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];     /*  dma buffers for analog input */
1063         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];   /*  physical addresses of ai dma buffers */
1064         struct plx_dma_desc *ai_dma_desc;       /*  array of ai dma descriptors read by plx9080, allocated to get proper alignment */
1065         dma_addr_t ai_dma_desc_bus_addr;        /*  physical address of ai dma descriptor array */
1066         volatile unsigned int ai_dma_index;     /*  index of the ai dma descriptor/buffer that is currently being used */
1067         uint16_t *ao_buffer[AO_DMA_RING_COUNT]; /*  dma buffers for analog output */
1068         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];       /*  physical addresses of ao dma buffers */
1069         struct plx_dma_desc *ao_dma_desc;
1070         dma_addr_t ao_dma_desc_bus_addr;
1071         volatile unsigned int ao_dma_index;     /*  keeps track of buffer where the next ao sample should go */
1072         volatile unsigned long ao_count;        /*  number of analog output samples remaining */
1073         volatile unsigned int ao_value[2];      /*  remember what the analog outputs are set to, to allow readback */
1074         unsigned int hw_revision;       /*  stc chip hardware revision number */
1075         volatile unsigned int intr_enable_bits; /*  last bits sent to INTR_ENABLE_REG register */
1076         volatile uint16_t adc_control1_bits;    /*  last bits sent to ADC_CONTROL1_REG register */
1077         volatile uint16_t fifo_size_bits;       /*  last bits sent to FIFO_SIZE_REG register */
1078         volatile uint16_t hw_config_bits;       /*  last bits sent to HW_CONFIG_REG register */
1079         volatile uint16_t dac_control1_bits;
1080         volatile uint32_t plx_control_bits;     /*  last bits written to plx9080 control register */
1081         volatile uint32_t plx_intcsr_bits;      /*  last bits written to plx interrupt control and status register */
1082         volatile int calibration_source;        /*  index of calibration source readable through ai ch0 */
1083         volatile uint8_t i2c_cal_range_bits;    /*  bits written to i2c calibration/range register */
1084         volatile unsigned int ext_trig_falling; /*  configure digital triggers to trigger on falling edge */
1085         /*  states of various devices stored to enable read-back */
1086         unsigned int ad8402_state[2];
1087         unsigned int caldac_state[8];
1088         volatile short ai_cmd_running;
1089         unsigned int ai_fifo_segment_length;
1090         struct ext_clock_info ext_clock;
1091         short ao_bounce_buffer[DAC_FIFO_SIZE];
1092 };
1093
1094 /* inline function that makes it easier to
1095  * access the private structure.
1096  */
1097 static inline struct pcidas64_private *priv(struct comedi_device *dev)
1098 {
1099         return dev->private;
1100 }
1101
1102 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1103                     struct comedi_insn *insn, unsigned int *data);
1104 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1105                           struct comedi_insn *insn, unsigned int *data);
1106 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1107                     struct comedi_insn *insn, unsigned int *data);
1108 static int ao_readback_insn(struct comedi_device *dev,
1109                             struct comedi_subdevice *s,
1110                             struct comedi_insn *insn, unsigned int *data);
1111 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
1112 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
1113                       struct comedi_cmd *cmd);
1114 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
1115 static int ao_inttrig(struct comedi_device *dev,
1116                       struct comedi_subdevice *subdev, unsigned int trig_num);
1117 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
1118                       struct comedi_cmd *cmd);
1119 static irqreturn_t handle_interrupt(int irq, void *d);
1120 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
1121 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
1122 static int dio_callback(int dir, int port, int data, unsigned long arg);
1123 static int dio_callback_4020(int dir, int port, int data, unsigned long arg);
1124 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
1125                     struct comedi_insn *insn, unsigned int *data);
1126 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
1127                     struct comedi_insn *insn, unsigned int *data);
1128 static int dio_60xx_config_insn(struct comedi_device *dev,
1129                                 struct comedi_subdevice *s,
1130                                 struct comedi_insn *insn, unsigned int *data);
1131 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
1132                           struct comedi_insn *insn, unsigned int *data);
1133 static int calib_read_insn(struct comedi_device *dev,
1134                            struct comedi_subdevice *s, struct comedi_insn *insn,
1135                            unsigned int *data);
1136 static int calib_write_insn(struct comedi_device *dev,
1137                             struct comedi_subdevice *s,
1138                             struct comedi_insn *insn, unsigned int *data);
1139 static int ad8402_read_insn(struct comedi_device *dev,
1140                             struct comedi_subdevice *s,
1141                             struct comedi_insn *insn, unsigned int *data);
1142 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
1143                          unsigned int value);
1144 static int ad8402_write_insn(struct comedi_device *dev,
1145                              struct comedi_subdevice *s,
1146                              struct comedi_insn *insn, unsigned int *data);
1147 static int eeprom_read_insn(struct comedi_device *dev,
1148                             struct comedi_subdevice *s,
1149                             struct comedi_insn *insn, unsigned int *data);
1150 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd);
1151 static unsigned int get_divisor(unsigned int ns, unsigned int flags);
1152 static void i2c_write(struct comedi_device *dev, unsigned int address,
1153                       const uint8_t *data, unsigned int length);
1154 static void caldac_write(struct comedi_device *dev, unsigned int channel,
1155                          unsigned int value);
1156 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
1157                              uint8_t value);
1158 /* static int dac_1590_write(struct comedi_device *dev, unsigned int dac_a, unsigned int dac_b); */
1159 static int caldac_i2c_write(struct comedi_device *dev,
1160                             unsigned int caldac_channel, unsigned int value);
1161 static void abort_dma(struct comedi_device *dev, unsigned int channel);
1162 static void disable_plx_interrupts(struct comedi_device *dev);
1163 static int set_ai_fifo_size(struct comedi_device *dev,
1164                             unsigned int num_samples);
1165 static unsigned int ai_fifo_size(struct comedi_device *dev);
1166 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1167                                       unsigned int num_entries);
1168 static void disable_ai_pacing(struct comedi_device *dev);
1169 static void disable_ai_interrupts(struct comedi_device *dev);
1170 static void enable_ai_interrupts(struct comedi_device *dev,
1171                                  const struct comedi_cmd *cmd);
1172 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags);
1173 static void load_ao_dma(struct comedi_device *dev,
1174                         const struct comedi_cmd *cmd);
1175
1176 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1177                                        unsigned int range_index)
1178 {
1179         const struct comedi_krange *range =
1180             &board(dev)->ai_range_table->range[range_index];
1181         unsigned int bits = 0;
1182
1183         switch (range->max) {
1184         case 10000000:
1185                 bits = 0x000;
1186                 break;
1187         case 5000000:
1188                 bits = 0x100;
1189                 break;
1190         case 2000000:
1191         case 2500000:
1192                 bits = 0x200;
1193                 break;
1194         case 1000000:
1195         case 1250000:
1196                 bits = 0x300;
1197                 break;
1198         case 500000:
1199                 bits = 0x400;
1200                 break;
1201         case 200000:
1202         case 250000:
1203                 bits = 0x500;
1204                 break;
1205         case 100000:
1206                 bits = 0x600;
1207                 break;
1208         case 50000:
1209                 bits = 0x700;
1210                 break;
1211         default:
1212                 comedi_error(dev, "bug! in ai_range_bits_6xxx");
1213                 break;
1214         }
1215         if (range->min == 0)
1216                 bits += 0x900;
1217         return bits;
1218 }
1219
1220 static unsigned int hw_revision(const struct comedi_device *dev,
1221                                 uint16_t hw_status_bits)
1222 {
1223         if (board(dev)->layout == LAYOUT_4020)
1224                 return (hw_status_bits >> 13) & 0x7;
1225
1226         return (hw_status_bits >> 12) & 0xf;
1227 }
1228
1229 static void set_dac_range_bits(struct comedi_device *dev,
1230                                volatile uint16_t *bits, unsigned int channel,
1231                                unsigned int range)
1232 {
1233         unsigned int code = board(dev)->ao_range_code[range];
1234
1235         if (channel > 1)
1236                 comedi_error(dev, "bug! bad channel?");
1237         if (code & ~0x3)
1238                 comedi_error(dev, "bug! bad range code?");
1239
1240         *bits &= ~(0x3 << (2 * channel));
1241         *bits |= code << (2 * channel);
1242 };
1243
1244 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1245 {
1246         return board->ao_nchan && board->layout != LAYOUT_4020;
1247 }
1248
1249 /* initialize plx9080 chip */
1250 static void init_plx9080(struct comedi_device *dev)
1251 {
1252         uint32_t bits;
1253         void __iomem *plx_iobase = priv(dev)->plx9080_iobase;
1254
1255         priv(dev)->plx_control_bits =
1256             readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG);
1257
1258         /*  plx9080 dump */
1259         DEBUG_PRINT(" plx interrupt status 0x%x\n",
1260                     readl(plx_iobase + PLX_INTRCS_REG));
1261         DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
1262         DEBUG_PRINT(" plx control reg 0x%x\n", priv(dev)->plx_control_bits);
1263         DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n",
1264                     readl(plx_iobase + PLX_MARB_REG));
1265         DEBUG_PRINT(" plx region0 reg 0x%x\n",
1266                     readl(plx_iobase + PLX_REGION0_REG));
1267         DEBUG_PRINT(" plx region1 reg 0x%x\n",
1268                     readl(plx_iobase + PLX_REGION1_REG));
1269
1270         DEBUG_PRINT(" plx revision 0x%x\n",
1271                     readl(plx_iobase + PLX_REVISION_REG));
1272         DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
1273                     readl(plx_iobase + PLX_DMA0_MODE_REG));
1274         DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
1275                     readl(plx_iobase + PLX_DMA1_MODE_REG));
1276         DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
1277                     readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
1278         DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
1279                     readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
1280         DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
1281                     readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
1282         DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
1283                     readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
1284         DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
1285                     readb(plx_iobase + PLX_DMA0_CS_REG));
1286         DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
1287                     readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
1288         DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
1289
1290 #ifdef __BIG_ENDIAN
1291         bits = BIGEND_DMA0 | BIGEND_DMA1;
1292 #else
1293         bits = 0;
1294 #endif
1295         writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
1296
1297         disable_plx_interrupts(dev);
1298
1299         abort_dma(dev, 0);
1300         abort_dma(dev, 1);
1301
1302         /*  configure dma0 mode */
1303         bits = 0;
1304         /*  enable ready input, not sure if this is necessary */
1305         bits |= PLX_DMA_EN_READYIN_BIT;
1306         /*  enable bterm, not sure if this is necessary */
1307         bits |= PLX_EN_BTERM_BIT;
1308         /*  enable dma chaining */
1309         bits |= PLX_EN_CHAIN_BIT;
1310         /*  enable interrupt on dma done (probably don't need this, since chain never finishes) */
1311         bits |= PLX_EN_DMA_DONE_INTR_BIT;
1312         /*  don't increment local address during transfers (we are transferring from a fixed fifo register) */
1313         bits |= PLX_LOCAL_ADDR_CONST_BIT;
1314         /*  route dma interrupt to pci bus */
1315         bits |= PLX_DMA_INTR_PCI_BIT;
1316         /*  enable demand mode */
1317         bits |= PLX_DEMAND_MODE_BIT;
1318         /*  enable local burst mode */
1319         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1320         /*  4020 uses 32 bit dma */
1321         if (board(dev)->layout == LAYOUT_4020) {
1322                 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1323         } else {                /*  localspace0 bus is 16 bits wide */
1324                 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1325         }
1326         writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1327         if (ao_cmd_is_supported(board(dev)))
1328                 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1329
1330         /*  enable interrupts on plx 9080 */
1331         priv(dev)->plx_intcsr_bits |=
1332             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1333             ICS_DMA0_E | ICS_DMA1_E;
1334         writel(priv(dev)->plx_intcsr_bits,
1335                priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1336 }
1337
1338 /* Allocate and initialize the subdevice structures.
1339  */
1340 static int setup_subdevices(struct comedi_device *dev)
1341 {
1342         struct comedi_subdevice *s;
1343         void __iomem *dio_8255_iobase;
1344         int i;
1345         int ret;
1346
1347         ret = comedi_alloc_subdevices(dev, 10);
1348         if (ret)
1349                 return ret;
1350
1351         s = dev->subdevices + 0;
1352         /* analog input subdevice */
1353         dev->read_subdev = s;
1354         s->type = COMEDI_SUBD_AI;
1355         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
1356         if (board(dev)->layout == LAYOUT_60XX)
1357                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
1358         else if (board(dev)->layout == LAYOUT_64XX)
1359                 s->subdev_flags |= SDF_DIFF;
1360         /* XXX Number of inputs in differential mode is ignored */
1361         s->n_chan = board(dev)->ai_se_chans;
1362         s->len_chanlist = 0x2000;
1363         s->maxdata = (1 << board(dev)->ai_bits) - 1;
1364         s->range_table = board(dev)->ai_range_table;
1365         s->insn_read = ai_rinsn;
1366         s->insn_config = ai_config_insn;
1367         s->do_cmd = ai_cmd;
1368         s->do_cmdtest = ai_cmdtest;
1369         s->cancel = ai_cancel;
1370         if (board(dev)->layout == LAYOUT_4020) {
1371                 uint8_t data;
1372                 /*  set adc to read from inputs (not internal calibration sources) */
1373                 priv(dev)->i2c_cal_range_bits = adc_src_4020_bits(4);
1374                 /*  set channels to +-5 volt input ranges */
1375                 for (i = 0; i < s->n_chan; i++)
1376                         priv(dev)->i2c_cal_range_bits |= attenuate_bit(i);
1377                 data = priv(dev)->i2c_cal_range_bits;
1378                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
1379         }
1380
1381         /* analog output subdevice */
1382         s = dev->subdevices + 1;
1383         if (board(dev)->ao_nchan) {
1384                 s->type = COMEDI_SUBD_AO;
1385                 s->subdev_flags =
1386                     SDF_READABLE | SDF_WRITABLE | SDF_GROUND | SDF_CMD_WRITE;
1387                 s->n_chan = board(dev)->ao_nchan;
1388                 s->maxdata = (1 << board(dev)->ao_bits) - 1;
1389                 s->range_table = board(dev)->ao_range_table;
1390                 s->insn_read = ao_readback_insn;
1391                 s->insn_write = ao_winsn;
1392                 if (ao_cmd_is_supported(board(dev))) {
1393                         dev->write_subdev = s;
1394                         s->do_cmdtest = ao_cmdtest;
1395                         s->do_cmd = ao_cmd;
1396                         s->len_chanlist = board(dev)->ao_nchan;
1397                         s->cancel = ao_cancel;
1398                 }
1399         } else {
1400                 s->type = COMEDI_SUBD_UNUSED;
1401         }
1402
1403         /*  digital input */
1404         s = dev->subdevices + 2;
1405         if (board(dev)->layout == LAYOUT_64XX) {
1406                 s->type = COMEDI_SUBD_DI;
1407                 s->subdev_flags = SDF_READABLE;
1408                 s->n_chan = 4;
1409                 s->maxdata = 1;
1410                 s->range_table = &range_digital;
1411                 s->insn_bits = di_rbits;
1412         } else
1413                 s->type = COMEDI_SUBD_UNUSED;
1414
1415         /*  digital output */
1416         if (board(dev)->layout == LAYOUT_64XX) {
1417                 s = dev->subdevices + 3;
1418                 s->type = COMEDI_SUBD_DO;
1419                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1420                 s->n_chan = 4;
1421                 s->maxdata = 1;
1422                 s->range_table = &range_digital;
1423                 s->insn_bits = do_wbits;
1424         } else
1425                 s->type = COMEDI_SUBD_UNUSED;
1426
1427         /* 8255 */
1428         s = dev->subdevices + 4;
1429         if (board(dev)->has_8255) {
1430                 if (board(dev)->layout == LAYOUT_4020) {
1431                         dio_8255_iobase =
1432                             priv(dev)->main_iobase + I8255_4020_REG;
1433                         subdev_8255_init(dev, s, dio_callback_4020,
1434                                          (unsigned long)dio_8255_iobase);
1435                 } else {
1436                         dio_8255_iobase =
1437                             priv(dev)->dio_counter_iobase + DIO_8255_OFFSET;
1438                         subdev_8255_init(dev, s, dio_callback,
1439                                          (unsigned long)dio_8255_iobase);
1440                 }
1441         } else
1442                 s->type = COMEDI_SUBD_UNUSED;
1443
1444         /*  8 channel dio for 60xx */
1445         s = dev->subdevices + 5;
1446         if (board(dev)->layout == LAYOUT_60XX) {
1447                 s->type = COMEDI_SUBD_DIO;
1448                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1449                 s->n_chan = 8;
1450                 s->maxdata = 1;
1451                 s->range_table = &range_digital;
1452                 s->insn_config = dio_60xx_config_insn;
1453                 s->insn_bits = dio_60xx_wbits;
1454         } else
1455                 s->type = COMEDI_SUBD_UNUSED;
1456
1457         /*  caldac */
1458         s = dev->subdevices + 6;
1459         s->type = COMEDI_SUBD_CALIB;
1460         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1461         s->n_chan = 8;
1462         if (board(dev)->layout == LAYOUT_4020)
1463                 s->maxdata = 0xfff;
1464         else
1465                 s->maxdata = 0xff;
1466         s->insn_read = calib_read_insn;
1467         s->insn_write = calib_write_insn;
1468         for (i = 0; i < s->n_chan; i++)
1469                 caldac_write(dev, i, s->maxdata / 2);
1470
1471         /*  2 channel ad8402 potentiometer */
1472         s = dev->subdevices + 7;
1473         if (board(dev)->layout == LAYOUT_64XX) {
1474                 s->type = COMEDI_SUBD_CALIB;
1475                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1476                 s->n_chan = 2;
1477                 s->insn_read = ad8402_read_insn;
1478                 s->insn_write = ad8402_write_insn;
1479                 s->maxdata = 0xff;
1480                 for (i = 0; i < s->n_chan; i++)
1481                         ad8402_write(dev, i, s->maxdata / 2);
1482         } else
1483                 s->type = COMEDI_SUBD_UNUSED;
1484
1485         /* serial EEPROM, if present */
1486         s = dev->subdevices + 8;
1487         if (readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
1488                 s->type = COMEDI_SUBD_MEMORY;
1489                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
1490                 s->n_chan = 128;
1491                 s->maxdata = 0xffff;
1492                 s->insn_read = eeprom_read_insn;
1493         } else
1494                 s->type = COMEDI_SUBD_UNUSED;
1495
1496         /*  user counter subd XXX */
1497         s = dev->subdevices + 9;
1498         s->type = COMEDI_SUBD_UNUSED;
1499
1500         return 0;
1501 }
1502
1503 static void disable_plx_interrupts(struct comedi_device *dev)
1504 {
1505         priv(dev)->plx_intcsr_bits = 0;
1506         writel(priv(dev)->plx_intcsr_bits,
1507                priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1508 }
1509
1510 static void init_stc_registers(struct comedi_device *dev)
1511 {
1512         uint16_t bits;
1513         unsigned long flags;
1514
1515         spin_lock_irqsave(&dev->spinlock, flags);
1516
1517         /*  bit should be set for 6025, although docs say boards with <= 16 chans should be cleared XXX */
1518         if (1)
1519                 priv(dev)->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1520         writew(priv(dev)->adc_control1_bits,
1521                priv(dev)->main_iobase + ADC_CONTROL1_REG);
1522
1523         /*  6402/16 manual says this register must be initialized to 0xff? */
1524         writew(0xff, priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1525
1526         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1527         if (board(dev)->layout == LAYOUT_4020)
1528                 bits |= INTERNAL_CLOCK_4020_BITS;
1529         priv(dev)->hw_config_bits |= bits;
1530         writew(priv(dev)->hw_config_bits,
1531                priv(dev)->main_iobase + HW_CONFIG_REG);
1532
1533         writew(0, priv(dev)->main_iobase + DAQ_SYNC_REG);
1534         writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
1535
1536         spin_unlock_irqrestore(&dev->spinlock, flags);
1537
1538         /*  set fifos to maximum size */
1539         priv(dev)->fifo_size_bits |= DAC_FIFO_BITS;
1540         set_ai_fifo_segment_length(dev,
1541                                    board(dev)->ai_fifo->max_segment_length);
1542
1543         priv(dev)->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1544         priv(dev)->intr_enable_bits =   /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1545             EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1546         writew(priv(dev)->intr_enable_bits,
1547                priv(dev)->main_iobase + INTR_ENABLE_REG);
1548
1549         disable_ai_pacing(dev);
1550 };
1551
1552 static int alloc_and_init_dma_members(struct comedi_device *dev)
1553 {
1554         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1555         int i;
1556
1557         /*  alocate pci dma buffers */
1558         for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1559                 priv(dev)->ai_buffer[i] =
1560                     pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1561                                          &priv(dev)->ai_buffer_bus_addr[i]);
1562                 if (priv(dev)->ai_buffer[i] == NULL)
1563                         return -ENOMEM;
1564
1565         }
1566         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1567                 if (ao_cmd_is_supported(board(dev))) {
1568                         priv(dev)->ao_buffer[i] =
1569                             pci_alloc_consistent(pcidev,
1570                                                  DMA_BUFFER_SIZE,
1571                                                  &priv(dev)->
1572                                                  ao_buffer_bus_addr[i]);
1573                         if (priv(dev)->ao_buffer[i] == NULL)
1574                                 return -ENOMEM;
1575
1576                 }
1577         }
1578         /*  allocate dma descriptors */
1579         priv(dev)->ai_dma_desc =
1580             pci_alloc_consistent(pcidev,
1581                                  sizeof(struct plx_dma_desc) *
1582                                  ai_dma_ring_count(board(dev)),
1583                                  &priv(dev)->ai_dma_desc_bus_addr);
1584         if (priv(dev)->ai_dma_desc == NULL)
1585                 return -ENOMEM;
1586
1587         DEBUG_PRINT("ai dma descriptors start at bus addr 0x%x\n",
1588                     priv(dev)->ai_dma_desc_bus_addr);
1589         if (ao_cmd_is_supported(board(dev))) {
1590                 priv(dev)->ao_dma_desc =
1591                     pci_alloc_consistent(pcidev,
1592                                          sizeof(struct plx_dma_desc) *
1593                                          AO_DMA_RING_COUNT,
1594                                          &priv(dev)->ao_dma_desc_bus_addr);
1595                 if (priv(dev)->ao_dma_desc == NULL)
1596                         return -ENOMEM;
1597
1598                 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%x\n",
1599                             priv(dev)->ao_dma_desc_bus_addr);
1600         }
1601         /*  initialize dma descriptors */
1602         for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1603                 priv(dev)->ai_dma_desc[i].pci_start_addr =
1604                     cpu_to_le32(priv(dev)->ai_buffer_bus_addr[i]);
1605                 if (board(dev)->layout == LAYOUT_4020)
1606                         priv(dev)->ai_dma_desc[i].local_start_addr =
1607                             cpu_to_le32(priv(dev)->local1_iobase +
1608                                         ADC_FIFO_REG);
1609                 else
1610                         priv(dev)->ai_dma_desc[i].local_start_addr =
1611                             cpu_to_le32(priv(dev)->local0_iobase +
1612                                         ADC_FIFO_REG);
1613                 priv(dev)->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1614                 priv(dev)->ai_dma_desc[i].next =
1615                     cpu_to_le32((priv(dev)->ai_dma_desc_bus_addr + ((i +
1616                                                                      1) %
1617                                                                     ai_dma_ring_count
1618                                                                     (board
1619                                                                      (dev))) *
1620                                  sizeof(priv(dev)->ai_dma_desc[0])) |
1621                                 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1622                                 PLX_XFER_LOCAL_TO_PCI);
1623         }
1624         if (ao_cmd_is_supported(board(dev))) {
1625                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1626                         priv(dev)->ao_dma_desc[i].pci_start_addr =
1627                             cpu_to_le32(priv(dev)->ao_buffer_bus_addr[i]);
1628                         priv(dev)->ao_dma_desc[i].local_start_addr =
1629                             cpu_to_le32(priv(dev)->local0_iobase +
1630                                         DAC_FIFO_REG);
1631                         priv(dev)->ao_dma_desc[i].transfer_size =
1632                             cpu_to_le32(0);
1633                         priv(dev)->ao_dma_desc[i].next =
1634                             cpu_to_le32((priv(dev)->ao_dma_desc_bus_addr +
1635                                          ((i + 1) % (AO_DMA_RING_COUNT)) *
1636                                          sizeof(priv(dev)->ao_dma_desc[0])) |
1637                                         PLX_DESC_IN_PCI_BIT |
1638                                         PLX_INTR_TERM_COUNT);
1639                 }
1640         }
1641         return 0;
1642 }
1643
1644 static inline void warn_external_queue(struct comedi_device *dev)
1645 {
1646         comedi_error(dev,
1647                      "AO command and AI external channel queue cannot be used simultaneously.");
1648         comedi_error(dev,
1649                      "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1650 }
1651
1652 static struct pci_dev *cb_pcidas64_find_pci_dev(struct comedi_device *dev,
1653                                                 struct comedi_devconfig *it)
1654 {
1655         struct pci_dev *pcidev = NULL;
1656         int bus = it->options[0];
1657         int slot = it->options[1];
1658         int i;
1659
1660         for_each_pci_dev(pcidev) {
1661                 if (bus || slot) {
1662                         if (bus != pcidev->bus->number ||
1663                             slot != PCI_SLOT(pcidev->devfn))
1664                                 continue;
1665                 }
1666                 if (pcidev->vendor != PCI_VENDOR_ID_COMPUTERBOARDS)
1667                         continue;
1668
1669                 for (i = 0; i < ARRAY_SIZE(pcidas64_boards); i++) {
1670                         if (pcidas64_boards[i].device_id != pcidev->device)
1671                                 continue;
1672                         dev->board_ptr = pcidas64_boards + i;
1673                         return pcidev;
1674                 }
1675         }
1676         dev_err(dev->class_dev,
1677                 "No supported board found! (req. bus %d, slot %d)\n",
1678                 bus, slot);
1679         return NULL;
1680 }
1681
1682 /*
1683  * Attach is called by the Comedi core to configure the driver
1684  * for a particular board.
1685  */
1686 static int attach(struct comedi_device *dev, struct comedi_devconfig *it)
1687 {
1688         struct pci_dev *pcidev;
1689         uint32_t local_range, local_decode;
1690         int retval;
1691
1692 /*
1693  * Allocate the private structure area.
1694  */
1695         if (alloc_private(dev, sizeof(struct pcidas64_private)) < 0)
1696                 return -ENOMEM;
1697
1698         pcidev = cb_pcidas64_find_pci_dev(dev, it);
1699         if (!pcidev)
1700                 return -EIO;
1701         comedi_set_hw_dev(dev, &pcidev->dev);
1702
1703         if (comedi_pci_enable(pcidev, dev->driver->driver_name)) {
1704                 dev_warn(dev->class_dev,
1705                          "failed to enable PCI device and request regions\n");
1706                 return -EIO;
1707         }
1708         pci_set_master(pcidev);
1709
1710         /* Initialize dev->board_name */
1711         dev->board_name = board(dev)->name;
1712
1713         dev->iobase = pci_resource_start(pcidev, MAIN_BADDRINDEX);
1714
1715         priv(dev)->plx9080_phys_iobase =
1716             pci_resource_start(pcidev, PLX9080_BADDRINDEX);
1717         priv(dev)->main_phys_iobase = dev->iobase;
1718         priv(dev)->dio_counter_phys_iobase =
1719             pci_resource_start(pcidev, DIO_COUNTER_BADDRINDEX);
1720
1721         /*  remap, won't work with 2.0 kernels but who cares */
1722         priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
1723                                             pci_resource_len(pcidev,
1724                                                              PLX9080_BADDRINDEX));
1725         priv(dev)->main_iobase =
1726             ioremap(priv(dev)->main_phys_iobase,
1727                     pci_resource_len(pcidev, MAIN_BADDRINDEX));
1728         priv(dev)->dio_counter_iobase =
1729             ioremap(priv(dev)->dio_counter_phys_iobase,
1730                     pci_resource_len(pcidev, DIO_COUNTER_BADDRINDEX));
1731
1732         if (!priv(dev)->plx9080_iobase || !priv(dev)->main_iobase
1733             || !priv(dev)->dio_counter_iobase) {
1734                 dev_warn(dev->class_dev, "failed to remap io memory\n");
1735                 return -ENOMEM;
1736         }
1737
1738         DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase);
1739         DEBUG_PRINT(" main remapped to 0x%p\n", priv(dev)->main_iobase);
1740         DEBUG_PRINT(" diocounter remapped to 0x%p\n",
1741                     priv(dev)->dio_counter_iobase);
1742
1743         /*  figure out what local addresses are */
1744         local_range =
1745             readl(priv(dev)->plx9080_iobase + PLX_LAS0RNG_REG) & LRNG_MEM_MASK;
1746         local_decode =
1747             readl(priv(dev)->plx9080_iobase +
1748                   PLX_LAS0MAP_REG) & local_range & LMAP_MEM_MASK;
1749         priv(dev)->local0_iobase =
1750             ((uint32_t) priv(dev)->main_phys_iobase & ~local_range) |
1751             local_decode;
1752         local_range =
1753             readl(priv(dev)->plx9080_iobase + PLX_LAS1RNG_REG) & LRNG_MEM_MASK;
1754         local_decode =
1755             readl(priv(dev)->plx9080_iobase +
1756                   PLX_LAS1MAP_REG) & local_range & LMAP_MEM_MASK;
1757         priv(dev)->local1_iobase =
1758             ((uint32_t) priv(dev)->dio_counter_phys_iobase & ~local_range) |
1759             local_decode;
1760
1761         DEBUG_PRINT(" local 0 io addr 0x%x\n", priv(dev)->local0_iobase);
1762         DEBUG_PRINT(" local 1 io addr 0x%x\n", priv(dev)->local1_iobase);
1763
1764         retval = alloc_and_init_dma_members(dev);
1765         if (retval < 0)
1766                 return retval;
1767
1768         priv(dev)->hw_revision =
1769             hw_revision(dev, readw(priv(dev)->main_iobase + HW_STATUS_REG));
1770         dev_dbg(dev->class_dev, "stc hardware revision %i\n",
1771                 priv(dev)->hw_revision);
1772         init_plx9080(dev);
1773         init_stc_registers(dev);
1774         /*  get irq */
1775         if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
1776                         "cb_pcidas64", dev)) {
1777                 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
1778                         pcidev->irq);
1779                 return -EINVAL;
1780         }
1781         dev->irq = pcidev->irq;
1782         dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
1783
1784         retval = setup_subdevices(dev);
1785         if (retval < 0)
1786                 return retval;
1787
1788
1789         return 0;
1790 }
1791
1792 static void detach(struct comedi_device *dev)
1793 {
1794         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1795         unsigned int i;
1796
1797         if (dev->irq)
1798                 free_irq(dev->irq, dev);
1799         if (priv(dev)) {
1800                 if (pcidev) {
1801                         if (priv(dev)->plx9080_iobase) {
1802                                 disable_plx_interrupts(dev);
1803                                 iounmap(priv(dev)->plx9080_iobase);
1804                         }
1805                         if (priv(dev)->main_iobase)
1806                                 iounmap(priv(dev)->main_iobase);
1807                         if (priv(dev)->dio_counter_iobase)
1808                                 iounmap(priv(dev)->dio_counter_iobase);
1809                         /*  free pci dma buffers */
1810                         for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1811                                 if (priv(dev)->ai_buffer[i])
1812                                         pci_free_consistent(pcidev,
1813                                                             DMA_BUFFER_SIZE,
1814                                                             priv(dev)->
1815                                                             ai_buffer[i],
1816                                                             priv
1817                                                             (dev)->ai_buffer_bus_addr
1818                                                             [i]);
1819                         }
1820                         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1821                                 if (priv(dev)->ao_buffer[i])
1822                                         pci_free_consistent(pcidev,
1823                                                             DMA_BUFFER_SIZE,
1824                                                             priv(dev)->
1825                                                             ao_buffer[i],
1826                                                             priv
1827                                                             (dev)->ao_buffer_bus_addr
1828                                                             [i]);
1829                         }
1830                         /*  free dma descriptors */
1831                         if (priv(dev)->ai_dma_desc)
1832                                 pci_free_consistent(pcidev,
1833                                                     sizeof(struct plx_dma_desc)
1834                                                     *
1835                                                     ai_dma_ring_count(board
1836                                                                       (dev)),
1837                                                     priv(dev)->ai_dma_desc,
1838                                                     priv(dev)->
1839                                                     ai_dma_desc_bus_addr);
1840                         if (priv(dev)->ao_dma_desc)
1841                                 pci_free_consistent(pcidev,
1842                                                     sizeof(struct plx_dma_desc)
1843                                                     * AO_DMA_RING_COUNT,
1844                                                     priv(dev)->ao_dma_desc,
1845                                                     priv(dev)->
1846                                                     ao_dma_desc_bus_addr);
1847                 }
1848         }
1849         if (dev->subdevices)
1850                 subdev_8255_cleanup(dev, dev->subdevices + 4);
1851         if (pcidev) {
1852                 if (dev->iobase)
1853                         comedi_pci_disable(pcidev);
1854
1855                 pci_dev_put(pcidev);
1856         }
1857 }
1858
1859 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1860                     struct comedi_insn *insn, unsigned int *data)
1861 {
1862         unsigned int bits = 0, n, i;
1863         unsigned int channel, range, aref;
1864         unsigned long flags;
1865         static const int timeout = 100;
1866
1867         DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec);
1868         channel = CR_CHAN(insn->chanspec);
1869         range = CR_RANGE(insn->chanspec);
1870         aref = CR_AREF(insn->chanspec);
1871
1872         /*  disable card's analog input interrupt sources and pacing */
1873         /*  4020 generates dac done interrupts even though they are disabled */
1874         disable_ai_pacing(dev);
1875
1876         spin_lock_irqsave(&dev->spinlock, flags);
1877         if (insn->chanspec & CR_ALT_FILTER)
1878                 priv(dev)->adc_control1_bits |= ADC_DITHER_BIT;
1879         else
1880                 priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT;
1881         writew(priv(dev)->adc_control1_bits,
1882                priv(dev)->main_iobase + ADC_CONTROL1_REG);
1883         spin_unlock_irqrestore(&dev->spinlock, flags);
1884
1885         if (board(dev)->layout != LAYOUT_4020) {
1886                 /*  use internal queue */
1887                 priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT;
1888                 writew(priv(dev)->hw_config_bits,
1889                        priv(dev)->main_iobase + HW_CONFIG_REG);
1890
1891                 /*  ALT_SOURCE is internal calibration reference */
1892                 if (insn->chanspec & CR_ALT_SOURCE) {
1893                         unsigned int cal_en_bit;
1894
1895                         DEBUG_PRINT("reading calibration source\n");
1896                         if (board(dev)->layout == LAYOUT_60XX)
1897                                 cal_en_bit = CAL_EN_60XX_BIT;
1898                         else
1899                                 cal_en_bit = CAL_EN_64XX_BIT;
1900                         /*  select internal reference source to connect to channel 0 */
1901                         writew(cal_en_bit |
1902                                adc_src_bits(priv(dev)->calibration_source),
1903                                priv(dev)->main_iobase + CALIBRATION_REG);
1904                 } else {
1905                         /*  make sure internal calibration source is turned off */
1906                         writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
1907                 }
1908                 /*  load internal queue */
1909                 bits = 0;
1910                 /*  set gain */
1911                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1912                 /*  set single-ended / differential */
1913                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1914                 if (aref == AREF_COMMON)
1915                         bits |= ADC_COMMON_BIT;
1916                 bits |= adc_chan_bits(channel);
1917                 /*  set stop channel */
1918                 writew(adc_chan_bits(channel),
1919                        priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG);
1920                 /*  set start channel, and rest of settings */
1921                 writew(bits, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
1922         } else {
1923                 uint8_t old_cal_range_bits = priv(dev)->i2c_cal_range_bits;
1924
1925                 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1926                 if (insn->chanspec & CR_ALT_SOURCE) {
1927                         DEBUG_PRINT("reading calibration source\n");
1928                         priv(dev)->i2c_cal_range_bits |=
1929                             adc_src_4020_bits(priv(dev)->calibration_source);
1930                 } else {        /* select BNC inputs */
1931                         priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4);
1932                 }
1933                 /*  select range */
1934                 if (range == 0)
1935                         priv(dev)->i2c_cal_range_bits |= attenuate_bit(channel);
1936                 else
1937                         priv(dev)->i2c_cal_range_bits &=
1938                             ~attenuate_bit(channel);
1939                 /*  update calibration/range i2c register only if necessary, as it is very slow */
1940                 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) {
1941                         uint8_t i2c_data = priv(dev)->i2c_cal_range_bits;
1942                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1943                                   sizeof(i2c_data));
1944                 }
1945
1946                 /* 4020 manual asks that sample interval register to be set before writing to convert register.
1947                  * Using somewhat arbitrary setting of 4 master clock ticks = 0.1 usec */
1948                 writew(0,
1949                        priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1950                 writew(2,
1951                        priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1952         }
1953
1954         for (n = 0; n < insn->n; n++) {
1955
1956                 /*  clear adc buffer (inside loop for 4020 sake) */
1957                 writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG);
1958
1959                 /* trigger conversion, bits sent only matter for 4020 */
1960                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1961                        priv(dev)->main_iobase + ADC_CONVERT_REG);
1962
1963                 /*  wait for data */
1964                 for (i = 0; i < timeout; i++) {
1965                         bits = readw(priv(dev)->main_iobase + HW_STATUS_REG);
1966                         DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits));
1967                         if (board(dev)->layout == LAYOUT_4020) {
1968                                 if (readw(priv(dev)->main_iobase +
1969                                           ADC_WRITE_PNTR_REG))
1970                                         break;
1971                         } else {
1972                                 if (pipe_full_bits(bits))
1973                                         break;
1974                         }
1975                         udelay(1);
1976                 }
1977                 DEBUG_PRINT(" looped %i times waiting for data\n", i);
1978                 if (i == timeout) {
1979                         comedi_error(dev, " analog input read insn timed out");
1980                         printk(" status 0x%x\n", bits);
1981                         return -ETIME;
1982                 }
1983                 if (board(dev)->layout == LAYOUT_4020)
1984                         data[n] =
1985                             readl(priv(dev)->dio_counter_iobase +
1986                                   ADC_FIFO_REG) & 0xffff;
1987                 else
1988                         data[n] =
1989                             readw(priv(dev)->main_iobase + PIPE1_READ_REG);
1990         }
1991
1992         return n;
1993 }
1994
1995 static int ai_config_calibration_source(struct comedi_device *dev,
1996                                         unsigned int *data)
1997 {
1998         unsigned int source = data[1];
1999         int num_calibration_sources;
2000
2001         if (board(dev)->layout == LAYOUT_60XX)
2002                 num_calibration_sources = 16;
2003         else
2004                 num_calibration_sources = 8;
2005         if (source >= num_calibration_sources) {
2006                 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
2007                         source);
2008                 return -EINVAL;
2009         }
2010
2011         DEBUG_PRINT("setting calibration source to %i\n", source);
2012         priv(dev)->calibration_source = source;
2013
2014         return 2;
2015 }
2016
2017 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
2018 {
2019         int fifo_size;
2020         const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
2021         unsigned int block_size, requested_block_size;
2022         int retval;
2023
2024         requested_block_size = data[1];
2025
2026         if (requested_block_size) {
2027                 fifo_size =
2028                     requested_block_size * fifo->num_segments / bytes_in_sample;
2029
2030                 retval = set_ai_fifo_size(dev, fifo_size);
2031                 if (retval < 0)
2032                         return retval;
2033
2034         }
2035
2036         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
2037
2038         data[1] = block_size;
2039
2040         return 2;
2041 }
2042
2043 static int ai_config_master_clock_4020(struct comedi_device *dev,
2044                                        unsigned int *data)
2045 {
2046         unsigned int divisor = data[4];
2047         int retval = 0;
2048
2049         if (divisor < 2) {
2050                 divisor = 2;
2051                 retval = -EAGAIN;
2052         }
2053
2054         switch (data[1]) {
2055         case COMEDI_EV_SCAN_BEGIN:
2056                 priv(dev)->ext_clock.divisor = divisor;
2057                 priv(dev)->ext_clock.chanspec = data[2];
2058                 break;
2059         default:
2060                 return -EINVAL;
2061                 break;
2062         }
2063
2064         data[4] = divisor;
2065
2066         return retval ? retval : 5;
2067 }
2068
2069 /* XXX could add support for 60xx series */
2070 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
2071 {
2072
2073         switch (board(dev)->layout) {
2074         case LAYOUT_4020:
2075                 return ai_config_master_clock_4020(dev, data);
2076                 break;
2077         default:
2078                 return -EINVAL;
2079                 break;
2080         }
2081
2082         return -EINVAL;
2083 }
2084
2085 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
2086                           struct comedi_insn *insn, unsigned int *data)
2087 {
2088         int id = data[0];
2089
2090         switch (id) {
2091         case INSN_CONFIG_ALT_SOURCE:
2092                 return ai_config_calibration_source(dev, data);
2093                 break;
2094         case INSN_CONFIG_BLOCK_SIZE:
2095                 return ai_config_block_size(dev, data);
2096                 break;
2097         case INSN_CONFIG_TIMER_1:
2098                 return ai_config_master_clock(dev, data);
2099                 break;
2100         default:
2101                 return -EINVAL;
2102                 break;
2103         }
2104         return -EINVAL;
2105 }
2106
2107 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2108                       struct comedi_cmd *cmd)
2109 {
2110         int err = 0;
2111         int tmp;
2112         unsigned int tmp_arg, tmp_arg2;
2113         int i;
2114         int aref;
2115         unsigned int triggers;
2116
2117         /* step 1: make sure trigger sources are trivially valid */
2118
2119         tmp = cmd->start_src;
2120         cmd->start_src &= TRIG_NOW | TRIG_EXT;
2121         if (!cmd->start_src || tmp != cmd->start_src)
2122                 err++;
2123
2124         tmp = cmd->scan_begin_src;
2125         triggers = TRIG_TIMER;
2126         if (board(dev)->layout == LAYOUT_4020)
2127                 triggers |= TRIG_OTHER;
2128         else
2129                 triggers |= TRIG_FOLLOW;
2130         cmd->scan_begin_src &= triggers;
2131         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
2132                 err++;
2133
2134         tmp = cmd->convert_src;
2135         triggers = TRIG_TIMER;
2136         if (board(dev)->layout == LAYOUT_4020)
2137                 triggers |= TRIG_NOW;
2138         else
2139                 triggers |= TRIG_EXT;
2140         cmd->convert_src &= triggers;
2141         if (!cmd->convert_src || tmp != cmd->convert_src)
2142                 err++;
2143
2144         tmp = cmd->scan_end_src;
2145         cmd->scan_end_src &= TRIG_COUNT;
2146         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
2147                 err++;
2148
2149         tmp = cmd->stop_src;
2150         cmd->stop_src &= TRIG_COUNT | TRIG_EXT | TRIG_NONE;
2151         if (!cmd->stop_src || tmp != cmd->stop_src)
2152                 err++;
2153
2154         if (err)
2155                 return 1;
2156
2157         /* step 2: make sure trigger sources are unique and mutually compatible */
2158
2159         /*  uniqueness check */
2160         if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
2161                 err++;
2162         if (cmd->scan_begin_src != TRIG_TIMER &&
2163             cmd->scan_begin_src != TRIG_OTHER &&
2164             cmd->scan_begin_src != TRIG_FOLLOW)
2165                 err++;
2166         if (cmd->convert_src != TRIG_TIMER &&
2167             cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
2168                 err++;
2169         if (cmd->stop_src != TRIG_COUNT &&
2170             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2171                 err++;
2172
2173         /*  compatibility check */
2174         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2175                 err++;
2176         if (cmd->stop_src != TRIG_COUNT &&
2177             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2178                 err++;
2179
2180         if (err)
2181                 return 2;
2182
2183         /* step 3: make sure arguments are trivially compatible */
2184
2185         if (cmd->convert_src == TRIG_TIMER) {
2186                 if (board(dev)->layout == LAYOUT_4020) {
2187                         if (cmd->convert_arg) {
2188                                 cmd->convert_arg = 0;
2189                                 err++;
2190                         }
2191                 } else {
2192                         if (cmd->convert_arg < board(dev)->ai_speed) {
2193                                 cmd->convert_arg = board(dev)->ai_speed;
2194                                 err++;
2195                         }
2196                         if (cmd->scan_begin_src == TRIG_TIMER) {
2197                                 /*  if scans are timed faster than conversion rate allows */
2198                                 if (cmd->convert_arg * cmd->chanlist_len >
2199                                     cmd->scan_begin_arg) {
2200                                         cmd->scan_begin_arg =
2201                                             cmd->convert_arg *
2202                                             cmd->chanlist_len;
2203                                         err++;
2204                                 }
2205                         }
2206                 }
2207         }
2208
2209         if (!cmd->chanlist_len) {
2210                 cmd->chanlist_len = 1;
2211                 err++;
2212         }
2213         if (cmd->scan_end_arg != cmd->chanlist_len) {
2214                 cmd->scan_end_arg = cmd->chanlist_len;
2215                 err++;
2216         }
2217
2218         switch (cmd->stop_src) {
2219         case TRIG_EXT:
2220                 break;
2221         case TRIG_COUNT:
2222                 if (!cmd->stop_arg) {
2223                         cmd->stop_arg = 1;
2224                         err++;
2225                 }
2226                 break;
2227         case TRIG_NONE:
2228                 if (cmd->stop_arg != 0) {
2229                         cmd->stop_arg = 0;
2230                         err++;
2231                 }
2232                 break;
2233         default:
2234                 break;
2235         }
2236
2237         if (err)
2238                 return 3;
2239
2240         /* step 4: fix up any arguments */
2241
2242         if (cmd->convert_src == TRIG_TIMER) {
2243                 tmp_arg = cmd->convert_arg;
2244                 tmp_arg2 = cmd->scan_begin_arg;
2245                 check_adc_timing(dev, cmd);
2246                 if (tmp_arg != cmd->convert_arg)
2247                         err++;
2248                 if (tmp_arg2 != cmd->scan_begin_arg)
2249                         err++;
2250         }
2251
2252         if (err)
2253                 return 4;
2254
2255         /*  make sure user is doesn't change analog reference mid chanlist */
2256         if (cmd->chanlist) {
2257                 aref = CR_AREF(cmd->chanlist[0]);
2258                 for (i = 1; i < cmd->chanlist_len; i++) {
2259                         if (aref != CR_AREF(cmd->chanlist[i])) {
2260                                 comedi_error(dev,
2261                                              "all elements in chanlist must use the same analog reference");
2262                                 err++;
2263                                 break;
2264                         }
2265                 }
2266                 /*  check 4020 chanlist */
2267                 if (board(dev)->layout == LAYOUT_4020) {
2268                         unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
2269                         for (i = 1; i < cmd->chanlist_len; i++) {
2270                                 if (CR_CHAN(cmd->chanlist[i]) !=
2271                                     first_channel + i) {
2272                                         comedi_error(dev,
2273                                                      "chanlist must use consecutive channels");
2274                                         err++;
2275                                         break;
2276                                 }
2277                         }
2278                         if (cmd->chanlist_len == 3) {
2279                                 comedi_error(dev,
2280                                              "chanlist cannot be 3 channels long, use 1, 2, or 4 channels");
2281                                 err++;
2282                         }
2283                 }
2284         }
2285
2286         if (err)
2287                 return 5;
2288
2289         return 0;
2290 }
2291
2292 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2293 {
2294 /* disable for now until I work out a race */
2295         return 0;
2296
2297         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2298                 return 1;
2299         else
2300                 return 0;
2301 }
2302
2303 static void setup_sample_counters(struct comedi_device *dev,
2304                                   struct comedi_cmd *cmd)
2305 {
2306         if (cmd->stop_src == TRIG_COUNT) {
2307                 /*  set software count */
2308                 priv(dev)->ai_count = cmd->stop_arg * cmd->chanlist_len;
2309         }
2310         /*  load hardware conversion counter */
2311         if (use_hw_sample_counter(cmd)) {
2312                 writew(cmd->stop_arg & 0xffff,
2313                        priv(dev)->main_iobase + ADC_COUNT_LOWER_REG);
2314                 writew((cmd->stop_arg >> 16) & 0xff,
2315                        priv(dev)->main_iobase + ADC_COUNT_UPPER_REG);
2316         } else {
2317                 writew(1, priv(dev)->main_iobase + ADC_COUNT_LOWER_REG);
2318         }
2319 }
2320
2321 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2322 {
2323         unsigned int num_samples;
2324
2325         num_samples =
2326             priv(dev)->ai_fifo_segment_length *
2327             board(dev)->ai_fifo->sample_packing_ratio;
2328         if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2329                 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2330
2331         return num_samples;
2332 }
2333
2334 static void disable_ai_pacing(struct comedi_device *dev)
2335 {
2336         unsigned long flags;
2337
2338         disable_ai_interrupts(dev);
2339
2340         spin_lock_irqsave(&dev->spinlock, flags);
2341         priv(dev)->adc_control1_bits &= ~ADC_SW_GATE_BIT;
2342         writew(priv(dev)->adc_control1_bits,
2343                priv(dev)->main_iobase + ADC_CONTROL1_REG);
2344         spin_unlock_irqrestore(&dev->spinlock, flags);
2345
2346         /* disable pacing, triggering, etc */
2347         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
2348                priv(dev)->main_iobase + ADC_CONTROL0_REG);
2349 }
2350
2351 static void disable_ai_interrupts(struct comedi_device *dev)
2352 {
2353         unsigned long flags;
2354
2355         spin_lock_irqsave(&dev->spinlock, flags);
2356         priv(dev)->intr_enable_bits &=
2357             ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
2358             ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
2359             ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
2360         writew(priv(dev)->intr_enable_bits,
2361                priv(dev)->main_iobase + INTR_ENABLE_REG);
2362         spin_unlock_irqrestore(&dev->spinlock, flags);
2363
2364         DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits);
2365 }
2366
2367 static void enable_ai_interrupts(struct comedi_device *dev,
2368                                  const struct comedi_cmd *cmd)
2369 {
2370         uint32_t bits;
2371         unsigned long flags;
2372
2373         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
2374             EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
2375         /*  Use pio transfer and interrupt on end of conversion if TRIG_WAKE_EOS flag is set. */
2376         if (cmd->flags & TRIG_WAKE_EOS) {
2377                 /*  4020 doesn't support pio transfers except for fifo dregs */
2378                 if (board(dev)->layout != LAYOUT_4020)
2379                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
2380         }
2381         spin_lock_irqsave(&dev->spinlock, flags);
2382         priv(dev)->intr_enable_bits |= bits;
2383         writew(priv(dev)->intr_enable_bits,
2384                priv(dev)->main_iobase + INTR_ENABLE_REG);
2385         DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits);
2386         spin_unlock_irqrestore(&dev->spinlock, flags);
2387 }
2388
2389 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2390                                         const struct comedi_cmd *cmd)
2391 {
2392         /*  supposed to load counter with desired divisor minus 3 */
2393         return cmd->convert_arg / TIMER_BASE - 3;
2394 }
2395
2396 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2397                                      struct comedi_cmd *cmd)
2398 {
2399         uint32_t count;
2400         /*  figure out how long we need to delay at end of scan */
2401         switch (cmd->scan_begin_src) {
2402         case TRIG_TIMER:
2403                 count = (cmd->scan_begin_arg -
2404                          (cmd->convert_arg * (cmd->chanlist_len - 1)))
2405                     / TIMER_BASE;
2406                 break;
2407         case TRIG_FOLLOW:
2408                 count = cmd->convert_arg / TIMER_BASE;
2409                 break;
2410         default:
2411                 return 0;
2412                 break;
2413         }
2414         return count - 3;
2415 }
2416
2417 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2418                                         struct comedi_cmd *cmd)
2419 {
2420         unsigned int divisor;
2421
2422         switch (cmd->scan_begin_src) {
2423         case TRIG_TIMER:
2424                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2425                 break;
2426         case TRIG_OTHER:
2427                 divisor = priv(dev)->ext_clock.divisor;
2428                 break;
2429         default:                /*  should never happen */
2430                 comedi_error(dev, "bug! failed to set ai pacing!");
2431                 divisor = 1000;
2432                 break;
2433         }
2434
2435         /*  supposed to load counter with desired divisor minus 2 for 4020 */
2436         return divisor - 2;
2437 }
2438
2439 static void select_master_clock_4020(struct comedi_device *dev,
2440                                      const struct comedi_cmd *cmd)
2441 {
2442         /*  select internal/external master clock */
2443         priv(dev)->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2444         if (cmd->scan_begin_src == TRIG_OTHER) {
2445                 int chanspec = priv(dev)->ext_clock.chanspec;
2446
2447                 if (CR_CHAN(chanspec))
2448                         priv(dev)->hw_config_bits |= BNC_CLOCK_4020_BITS;
2449                 else
2450                         priv(dev)->hw_config_bits |= EXT_CLOCK_4020_BITS;
2451         } else {
2452                 priv(dev)->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2453         }
2454         writew(priv(dev)->hw_config_bits,
2455                priv(dev)->main_iobase + HW_CONFIG_REG);
2456 }
2457
2458 static void select_master_clock(struct comedi_device *dev,
2459                                 const struct comedi_cmd *cmd)
2460 {
2461         switch (board(dev)->layout) {
2462         case LAYOUT_4020:
2463                 select_master_clock_4020(dev, cmd);
2464                 break;
2465         default:
2466                 break;
2467         }
2468 }
2469
2470 static inline void dma_start_sync(struct comedi_device *dev,
2471                                   unsigned int channel)
2472 {
2473         unsigned long flags;
2474
2475         /*  spinlock for plx dma control/status reg */
2476         spin_lock_irqsave(&dev->spinlock, flags);
2477         if (channel)
2478                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2479                        PLX_CLEAR_DMA_INTR_BIT,
2480                        priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2481         else
2482                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2483                        PLX_CLEAR_DMA_INTR_BIT,
2484                        priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
2485         spin_unlock_irqrestore(&dev->spinlock, flags);
2486 }
2487
2488 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2489 {
2490         uint32_t convert_counter = 0, scan_counter = 0;
2491
2492         check_adc_timing(dev, cmd);
2493
2494         select_master_clock(dev, cmd);
2495
2496         if (board(dev)->layout == LAYOUT_4020) {
2497                 convert_counter = ai_convert_counter_4020(dev, cmd);
2498         } else {
2499                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2500                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2501         }
2502
2503         /*  load lower 16 bits of convert interval */
2504         writew(convert_counter & 0xffff,
2505                priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2506         DEBUG_PRINT("convert counter 0x%x\n", convert_counter);
2507         /*  load upper 8 bits of convert interval */
2508         writew((convert_counter >> 16) & 0xff,
2509                priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2510         /*  load lower 16 bits of scan delay */
2511         writew(scan_counter & 0xffff,
2512                priv(dev)->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2513         /*  load upper 8 bits of scan delay */
2514         writew((scan_counter >> 16) & 0xff,
2515                priv(dev)->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2516         DEBUG_PRINT("scan counter 0x%x\n", scan_counter);
2517 }
2518
2519 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2520 {
2521         int i;
2522         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2523                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2524                     CR_CHAN(cmd->chanlist[i]) + 1)
2525                         return 0;
2526                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2527                     CR_RANGE(cmd->chanlist[i]))
2528                         return 0;
2529                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2530                         return 0;
2531         }
2532         return 1;
2533 }
2534
2535 static int setup_channel_queue(struct comedi_device *dev,
2536                                const struct comedi_cmd *cmd)
2537 {
2538         unsigned short bits;
2539         int i;
2540
2541         if (board(dev)->layout != LAYOUT_4020) {
2542                 if (use_internal_queue_6xxx(cmd)) {
2543                         priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT;
2544                         writew(priv(dev)->hw_config_bits,
2545                                priv(dev)->main_iobase + HW_CONFIG_REG);
2546                         bits = 0;
2547                         /*  set channel */
2548                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2549                         /*  set gain */
2550                         bits |= ai_range_bits_6xxx(dev,
2551                                                    CR_RANGE(cmd->chanlist[0]));
2552                         /*  set single-ended / differential */
2553                         bits |= se_diff_bit_6xxx(dev,
2554                                                  CR_AREF(cmd->chanlist[0]) ==
2555                                                  AREF_DIFF);
2556                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2557                                 bits |= ADC_COMMON_BIT;
2558                         /*  set stop channel */
2559                         writew(adc_chan_bits
2560                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2561                                priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG);
2562                         /*  set start channel, and rest of settings */
2563                         writew(bits,
2564                                priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2565                 } else {
2566                         /*  use external queue */
2567                         if (dev->write_subdev && dev->write_subdev->busy) {
2568                                 warn_external_queue(dev);
2569                                 return -EBUSY;
2570                         }
2571                         priv(dev)->hw_config_bits |= EXT_QUEUE_BIT;
2572                         writew(priv(dev)->hw_config_bits,
2573                                priv(dev)->main_iobase + HW_CONFIG_REG);
2574                         /*  clear DAC buffer to prevent weird interactions */
2575                         writew(0,
2576                                priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG);
2577                         /*  clear queue pointer */
2578                         writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
2579                         /*  load external queue */
2580                         for (i = 0; i < cmd->chanlist_len; i++) {
2581                                 bits = 0;
2582                                 /*  set channel */
2583                                 bits |=
2584                                     adc_chan_bits(CR_CHAN(cmd->chanlist[i]));
2585                                 /*  set gain */
2586                                 bits |= ai_range_bits_6xxx(dev,
2587                                                            CR_RANGE(cmd->
2588                                                                     chanlist
2589                                                                     [i]));
2590                                 /*  set single-ended / differential */
2591                                 bits |= se_diff_bit_6xxx(dev,
2592                                                          CR_AREF(cmd->
2593                                                                  chanlist[i]) ==
2594                                                          AREF_DIFF);
2595                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2596                                         bits |= ADC_COMMON_BIT;
2597                                 /*  mark end of queue */
2598                                 if (i == cmd->chanlist_len - 1)
2599                                         bits |= QUEUE_EOSCAN_BIT |
2600                                             QUEUE_EOSEQ_BIT;
2601                                 writew(bits,
2602                                        priv(dev)->main_iobase +
2603                                        ADC_QUEUE_FIFO_REG);
2604                                 DEBUG_PRINT
2605                                     ("wrote 0x%x to external channel queue\n",
2606                                      bits);
2607                         }
2608                         /* doing a queue clear is not specified in board docs,
2609                          * but required for reliable operation */
2610                         writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
2611                         /*  prime queue holding register */
2612                         writew(0, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2613                 }
2614         } else {
2615                 unsigned short old_cal_range_bits =
2616                     priv(dev)->i2c_cal_range_bits;
2617
2618                 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2619                 /* select BNC inputs */
2620                 priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4);
2621                 /*  select ranges */
2622                 for (i = 0; i < cmd->chanlist_len; i++) {
2623                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2624                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2625
2626                         if (range == 0)
2627                                 priv(dev)->i2c_cal_range_bits |=
2628                                     attenuate_bit(channel);
2629                         else
2630                                 priv(dev)->i2c_cal_range_bits &=
2631                                     ~attenuate_bit(channel);
2632                 }
2633                 /*  update calibration/range i2c register only if necessary, as it is very slow */
2634                 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) {
2635                         uint8_t i2c_data = priv(dev)->i2c_cal_range_bits;
2636                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2637                                   sizeof(i2c_data));
2638                 }
2639         }
2640         return 0;
2641 }
2642
2643 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2644                                              unsigned int dma_channel,
2645                                              unsigned int descriptor_bits)
2646 {
2647         /* The transfer size, pci address, and local address registers
2648          * are supposedly unused during chained dma,
2649          * but I have found that left over values from last operation
2650          * occasionally cause problems with transfer of first dma
2651          * block.  Initializing them to zero seems to fix the problem. */
2652         if (dma_channel) {
2653                 writel(0,
2654                        priv(dev)->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2655                 writel(0, priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2656                 writel(0,
2657                        priv(dev)->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2658                 writel(descriptor_bits,
2659                        priv(dev)->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2660         } else {
2661                 writel(0,
2662                        priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2663                 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2664                 writel(0,
2665                        priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2666                 writel(descriptor_bits,
2667                        priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2668         }
2669 }
2670
2671 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2672 {
2673         struct comedi_async *async = s->async;
2674         struct comedi_cmd *cmd = &async->cmd;
2675         uint32_t bits;
2676         unsigned int i;
2677         unsigned long flags;
2678         int retval;
2679
2680         disable_ai_pacing(dev);
2681         abort_dma(dev, 1);
2682
2683         retval = setup_channel_queue(dev, cmd);
2684         if (retval < 0)
2685                 return retval;
2686
2687         /*  make sure internal calibration source is turned off */
2688         writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
2689
2690         set_ai_pacing(dev, cmd);
2691
2692         setup_sample_counters(dev, cmd);
2693
2694         enable_ai_interrupts(dev, cmd);
2695
2696         spin_lock_irqsave(&dev->spinlock, flags);
2697         /* set mode, allow conversions through software gate */
2698         priv(dev)->adc_control1_bits |= ADC_SW_GATE_BIT;
2699         priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT;
2700         if (board(dev)->layout != LAYOUT_4020) {
2701                 priv(dev)->adc_control1_bits &= ~ADC_MODE_MASK;
2702                 if (cmd->convert_src == TRIG_EXT)
2703                         priv(dev)->adc_control1_bits |= adc_mode_bits(13);      /*  good old mode 13 */
2704                 else
2705                         priv(dev)->adc_control1_bits |= adc_mode_bits(8);       /*  mode 8.  What else could you need? */
2706         } else {
2707                 priv(dev)->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2708                 if (cmd->chanlist_len == 4)
2709                         priv(dev)->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2710                 else if (cmd->chanlist_len == 2)
2711                         priv(dev)->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2712                 priv(dev)->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2713                 priv(dev)->adc_control1_bits |=
2714                     adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2715                 priv(dev)->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2716                 priv(dev)->adc_control1_bits |=
2717                     adc_hi_chan_4020_bits(CR_CHAN
2718                                           (cmd->
2719                                            chanlist[cmd->chanlist_len - 1]));
2720         }
2721         writew(priv(dev)->adc_control1_bits,
2722                priv(dev)->main_iobase + ADC_CONTROL1_REG);
2723         DEBUG_PRINT("control1 bits 0x%x\n", priv(dev)->adc_control1_bits);
2724         spin_unlock_irqrestore(&dev->spinlock, flags);
2725
2726         /*  clear adc buffer */
2727         writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG);
2728
2729         if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2730             board(dev)->layout == LAYOUT_4020) {
2731                 priv(dev)->ai_dma_index = 0;
2732
2733                 /*  set dma transfer size */
2734                 for (i = 0; i < ai_dma_ring_count(board(dev)); i++)
2735                         priv(dev)->ai_dma_desc[i].transfer_size =
2736                             cpu_to_le32(dma_transfer_size(dev) *
2737                                         sizeof(uint16_t));
2738
2739                 /*  give location of first dma descriptor */
2740                 load_first_dma_descriptor(dev, 1,
2741                                           priv(dev)->ai_dma_desc_bus_addr |
2742                                           PLX_DESC_IN_PCI_BIT |
2743                                           PLX_INTR_TERM_COUNT |
2744                                           PLX_XFER_LOCAL_TO_PCI);
2745
2746                 dma_start_sync(dev, 1);
2747         }
2748
2749         if (board(dev)->layout == LAYOUT_4020) {
2750                 /* set source for external triggers */
2751                 bits = 0;
2752                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2753                         bits |= EXT_START_TRIG_BNC_BIT;
2754                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2755                         bits |= EXT_STOP_TRIG_BNC_BIT;
2756                 writew(bits, priv(dev)->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2757         }
2758
2759         spin_lock_irqsave(&dev->spinlock, flags);
2760
2761         /* enable pacing, triggering, etc */
2762         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2763         if (cmd->flags & TRIG_WAKE_EOS)
2764                 bits |= ADC_DMA_DISABLE_BIT;
2765         /*  set start trigger */
2766         if (cmd->start_src == TRIG_EXT) {
2767                 bits |= ADC_START_TRIG_EXT_BITS;
2768                 if (cmd->start_arg & CR_INVERT)
2769                         bits |= ADC_START_TRIG_FALLING_BIT;
2770         } else if (cmd->start_src == TRIG_NOW)
2771                 bits |= ADC_START_TRIG_SOFT_BITS;
2772         if (use_hw_sample_counter(cmd))
2773                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2774         writew(bits, priv(dev)->main_iobase + ADC_CONTROL0_REG);
2775         DEBUG_PRINT("control0 bits 0x%x\n", bits);
2776
2777         priv(dev)->ai_cmd_running = 1;
2778
2779         spin_unlock_irqrestore(&dev->spinlock, flags);
2780
2781         /*  start acquisition */
2782         if (cmd->start_src == TRIG_NOW) {
2783                 writew(0, priv(dev)->main_iobase + ADC_START_REG);
2784                 DEBUG_PRINT("soft trig\n");
2785         }
2786
2787         return 0;
2788 }
2789
2790 /* read num_samples from 16 bit wide ai fifo */
2791 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2792 {
2793         struct comedi_subdevice *s = dev->read_subdev;
2794         struct comedi_async *async = s->async;
2795         struct comedi_cmd *cmd = &async->cmd;
2796         unsigned int i;
2797         uint16_t prepost_bits;
2798         int read_segment, read_index, write_segment, write_index;
2799         int num_samples;
2800
2801         do {
2802                 /*  get least significant 15 bits */
2803                 read_index =
2804                     readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2805                 write_index =
2806                     readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2807                 /* Get most significant bits (grey code).  Different boards use different code
2808                  * so use a scheme that doesn't depend on encoding.  This read must
2809                  * occur after reading least significant 15 bits to avoid race
2810                  * with fifo switching to next segment. */
2811                 prepost_bits = readw(priv(dev)->main_iobase + PREPOST_REG);
2812
2813                 /* if read and write pointers are not on the same fifo segment, read to the
2814                  * end of the read segment */
2815                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2816                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2817
2818                 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n",
2819                             read_segment, write_segment, read_index,
2820                             write_index);
2821
2822                 if (read_segment != write_segment)
2823                         num_samples =
2824                             priv(dev)->ai_fifo_segment_length - read_index;
2825                 else
2826                         num_samples = write_index - read_index;
2827
2828                 if (cmd->stop_src == TRIG_COUNT) {
2829                         if (priv(dev)->ai_count == 0)
2830                                 break;
2831                         if (num_samples > priv(dev)->ai_count)
2832                                 num_samples = priv(dev)->ai_count;
2833
2834                         priv(dev)->ai_count -= num_samples;
2835                 }
2836
2837                 if (num_samples < 0) {
2838                         dev_err(dev->class_dev,
2839                                 "cb_pcidas64: bug! num_samples < 0\n");
2840                         break;
2841                 }
2842
2843                 DEBUG_PRINT(" read %i samples from fifo\n", num_samples);
2844
2845                 for (i = 0; i < num_samples; i++) {
2846                         cfc_write_to_buffer(s,
2847                                             readw(priv(dev)->main_iobase +
2848                                                   ADC_FIFO_REG));
2849                 }
2850
2851         } while (read_segment != write_segment);
2852 }
2853
2854 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of pointers.
2855  * The pci-4020 hardware only supports
2856  * dma transfers (it only supports the use of pio for draining the last remaining
2857  * points from the fifo when a data acquisition operation has completed).
2858  */
2859 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2860 {
2861         struct comedi_subdevice *s = dev->read_subdev;
2862         struct comedi_async *async = s->async;
2863         struct comedi_cmd *cmd = &async->cmd;
2864         unsigned int i;
2865         unsigned int max_transfer = 100000;
2866         uint32_t fifo_data;
2867         int write_code =
2868             readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2869         int read_code =
2870             readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2871
2872         if (cmd->stop_src == TRIG_COUNT) {
2873                 if (max_transfer > priv(dev)->ai_count)
2874                         max_transfer = priv(dev)->ai_count;
2875
2876         }
2877         for (i = 0; read_code != write_code && i < max_transfer;) {
2878                 fifo_data = readl(priv(dev)->dio_counter_iobase + ADC_FIFO_REG);
2879                 cfc_write_to_buffer(s, fifo_data & 0xffff);
2880                 i++;
2881                 if (i < max_transfer) {
2882                         cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2883                         i++;
2884                 }
2885                 read_code =
2886                     readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2887         }
2888         priv(dev)->ai_count -= i;
2889 }
2890
2891 /* empty fifo */
2892 static void pio_drain_ai_fifo(struct comedi_device *dev)
2893 {
2894         if (board(dev)->layout == LAYOUT_4020)
2895                 pio_drain_ai_fifo_32(dev);
2896         else
2897                 pio_drain_ai_fifo_16(dev);
2898 }
2899
2900 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2901 {
2902         struct comedi_async *async = dev->read_subdev->async;
2903         uint32_t next_transfer_addr;
2904         int j;
2905         int num_samples = 0;
2906         void __iomem *pci_addr_reg;
2907
2908         if (channel)
2909                 pci_addr_reg =
2910                     priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2911         else
2912                 pci_addr_reg =
2913                     priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2914
2915         /*  loop until we have read all the full buffers */
2916         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2917              (next_transfer_addr <
2918               priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index]
2919               || next_transfer_addr >=
2920               priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index] +
2921               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board(dev)); j++) {
2922                 /*  transfer data from dma buffer to comedi buffer */
2923                 num_samples = dma_transfer_size(dev);
2924                 if (async->cmd.stop_src == TRIG_COUNT) {
2925                         if (num_samples > priv(dev)->ai_count)
2926                                 num_samples = priv(dev)->ai_count;
2927                         priv(dev)->ai_count -= num_samples;
2928                 }
2929                 cfc_write_array_to_buffer(dev->read_subdev,
2930                                           priv(dev)->ai_buffer[priv(dev)->
2931                                                                ai_dma_index],
2932                                           num_samples * sizeof(uint16_t));
2933                 priv(dev)->ai_dma_index =
2934                     (priv(dev)->ai_dma_index +
2935                      1) % ai_dma_ring_count(board(dev));
2936
2937                 DEBUG_PRINT("next buffer addr 0x%lx\n",
2938                             (unsigned long)priv(dev)->
2939                             ai_buffer_bus_addr[priv(dev)->ai_dma_index]);
2940                 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
2941         }
2942         /* XXX check for dma ring buffer overrun (use end-of-chain bit to mark last
2943          * unused buffer) */
2944 }
2945
2946 static void handle_ai_interrupt(struct comedi_device *dev,
2947                                 unsigned short status,
2948                                 unsigned int plx_status)
2949 {
2950         struct comedi_subdevice *s = dev->read_subdev;
2951         struct comedi_async *async = s->async;
2952         struct comedi_cmd *cmd = &async->cmd;
2953         uint8_t dma1_status;
2954         unsigned long flags;
2955
2956         /*  check for fifo overrun */
2957         if (status & ADC_OVERRUN_BIT) {
2958                 comedi_error(dev, "fifo overrun");
2959                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2960         }
2961         /*  spin lock makes sure no one else changes plx dma control reg */
2962         spin_lock_irqsave(&dev->spinlock, flags);
2963         dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2964         if (plx_status & ICS_DMA1_A) {  /*  dma chan 1 interrupt */
2965                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2966                        priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2967                 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
2968
2969                 if (dma1_status & PLX_DMA_EN_BIT)
2970                         drain_dma_buffers(dev, 1);
2971
2972                 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
2973         }
2974         spin_unlock_irqrestore(&dev->spinlock, flags);
2975
2976         if (status & ADC_DONE_BIT)
2977                 DEBUG_PRINT("adc done interrupt\n");
2978
2979         /*  drain fifo with pio */
2980         if ((status & ADC_DONE_BIT) ||
2981             ((cmd->flags & TRIG_WAKE_EOS) &&
2982              (status & ADC_INTR_PENDING_BIT) &&
2983              (board(dev)->layout != LAYOUT_4020))) {
2984                 DEBUG_PRINT("pio fifo drain\n");
2985                 spin_lock_irqsave(&dev->spinlock, flags);
2986                 if (priv(dev)->ai_cmd_running) {
2987                         spin_unlock_irqrestore(&dev->spinlock, flags);
2988                         pio_drain_ai_fifo(dev);
2989                 } else
2990                         spin_unlock_irqrestore(&dev->spinlock, flags);
2991         }
2992         /*  if we are have all the data, then quit */
2993         if ((cmd->stop_src == TRIG_COUNT && (int)priv(dev)->ai_count <= 0) ||
2994             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
2995                 async->events |= COMEDI_CB_EOA;
2996         }
2997
2998         cfc_handle_events(dev, s);
2999 }
3000
3001 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
3002 {
3003         unsigned int buffer_index;
3004
3005         if (priv(dev)->ao_dma_index == 0)
3006                 buffer_index = AO_DMA_RING_COUNT - 1;
3007         else
3008                 buffer_index = priv(dev)->ao_dma_index - 1;
3009         return buffer_index;
3010 }
3011
3012 static int last_ao_dma_load_completed(struct comedi_device *dev)
3013 {
3014         unsigned int buffer_index;
3015         unsigned int transfer_address;
3016         unsigned short dma_status;
3017
3018         buffer_index = prev_ao_dma_index(dev);
3019         dma_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3020         if ((dma_status & PLX_DMA_DONE_BIT) == 0)
3021                 return 0;
3022
3023         transfer_address =
3024             readl(priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
3025         if (transfer_address != priv(dev)->ao_buffer_bus_addr[buffer_index])
3026                 return 0;
3027
3028         return 1;
3029 }
3030
3031 static int ao_stopped_by_error(struct comedi_device *dev,
3032                                const struct comedi_cmd *cmd)
3033 {
3034         if (cmd->stop_src == TRIG_NONE)
3035                 return 1;
3036         if (cmd->stop_src == TRIG_COUNT) {
3037                 if (priv(dev)->ao_count)
3038                         return 1;
3039                 if (last_ao_dma_load_completed(dev) == 0)
3040                         return 1;
3041         }
3042         return 0;
3043 }
3044
3045 static inline int ao_dma_needs_restart(struct comedi_device *dev,
3046                                        unsigned short dma_status)
3047 {
3048         if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
3049             (dma_status & PLX_DMA_EN_BIT) == 0)
3050                 return 0;
3051         if (last_ao_dma_load_completed(dev))
3052                 return 0;
3053
3054         return 1;
3055 }
3056
3057 static void restart_ao_dma(struct comedi_device *dev)
3058 {
3059         unsigned int dma_desc_bits;
3060
3061         dma_desc_bits =
3062             readl(priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
3063         dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
3064         DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits);
3065         load_first_dma_descriptor(dev, 0, dma_desc_bits);
3066
3067         dma_start_sync(dev, 0);
3068 }
3069
3070 static void handle_ao_interrupt(struct comedi_device *dev,
3071                                 unsigned short status, unsigned int plx_status)
3072 {
3073         struct comedi_subdevice *s = dev->write_subdev;
3074         struct comedi_async *async;
3075         struct comedi_cmd *cmd;
3076         uint8_t dma0_status;
3077         unsigned long flags;
3078
3079         /* board might not support ao, in which case write_subdev is NULL */
3080         if (s == NULL)
3081                 return;
3082         async = s->async;
3083         cmd = &async->cmd;
3084
3085         /*  spin lock makes sure no one else changes plx dma control reg */
3086         spin_lock_irqsave(&dev->spinlock, flags);
3087         dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3088         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
3089                 if ((dma0_status & PLX_DMA_EN_BIT)
3090                     && !(dma0_status & PLX_DMA_DONE_BIT))
3091                         writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3092                                priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3093                 else
3094                         writeb(PLX_CLEAR_DMA_INTR_BIT,
3095                                priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3096                 spin_unlock_irqrestore(&dev->spinlock, flags);
3097                 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
3098                 if (dma0_status & PLX_DMA_EN_BIT) {
3099                         load_ao_dma(dev, cmd);
3100                         /* try to recover from dma end-of-chain event */
3101                         if (ao_dma_needs_restart(dev, dma0_status))
3102                                 restart_ao_dma(dev);
3103                 }
3104                 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
3105         } else
3106                 spin_unlock_irqrestore(&dev->spinlock, flags);
3107
3108         if ((status & DAC_DONE_BIT)) {
3109                 async->events |= COMEDI_CB_EOA;
3110                 if (ao_stopped_by_error(dev, cmd))
3111                         async->events |= COMEDI_CB_ERROR;
3112                 DEBUG_PRINT("plx dma0 desc reg 0x%x\n",
3113                             readl(priv(dev)->plx9080_iobase +
3114                                   PLX_DMA0_DESCRIPTOR_REG));
3115                 DEBUG_PRINT("plx dma0 address reg 0x%x\n",
3116                             readl(priv(dev)->plx9080_iobase +
3117                                   PLX_DMA0_PCI_ADDRESS_REG));
3118         }
3119         cfc_handle_events(dev, s);
3120 }
3121
3122 static irqreturn_t handle_interrupt(int irq, void *d)
3123 {
3124         struct comedi_device *dev = d;
3125         unsigned short status;
3126         uint32_t plx_status;
3127         uint32_t plx_bits;
3128
3129         plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
3130         status = readw(priv(dev)->main_iobase + HW_STATUS_REG);
3131
3132         DEBUG_PRINT("cb_pcidas64: hw status 0x%x ", status);
3133         DEBUG_PRINT("plx status 0x%x\n", plx_status);
3134
3135         /* an interrupt before all the postconfig stuff gets done could
3136          * cause a NULL dereference if we continue through the
3137          * interrupt handler */
3138         if (dev->attached == 0) {
3139                 DEBUG_PRINT("cb_pcidas64: premature interrupt, ignoring",
3140                             status);
3141                 return IRQ_HANDLED;
3142         }
3143         handle_ai_interrupt(dev, status, plx_status);
3144         handle_ao_interrupt(dev, status, plx_status);
3145
3146         /*  clear possible plx9080 interrupt sources */
3147         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
3148                 plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
3149                 writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
3150                 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
3151         }
3152
3153         DEBUG_PRINT("exiting handler\n");
3154
3155         return IRQ_HANDLED;
3156 }
3157
3158 static void abort_dma(struct comedi_device *dev, unsigned int channel)
3159 {
3160         unsigned long flags;
3161
3162         /*  spinlock for plx dma control/status reg */
3163         spin_lock_irqsave(&dev->spinlock, flags);
3164
3165         plx9080_abort_dma(priv(dev)->plx9080_iobase, channel);
3166
3167         spin_unlock_irqrestore(&dev->spinlock, flags);
3168 }
3169
3170 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3171 {
3172         unsigned long flags;
3173
3174         spin_lock_irqsave(&dev->spinlock, flags);
3175         if (priv(dev)->ai_cmd_running == 0) {
3176                 spin_unlock_irqrestore(&dev->spinlock, flags);
3177                 return 0;
3178         }
3179         priv(dev)->ai_cmd_running = 0;
3180         spin_unlock_irqrestore(&dev->spinlock, flags);
3181
3182         disable_ai_pacing(dev);
3183
3184         abort_dma(dev, 1);
3185
3186         DEBUG_PRINT("ai canceled\n");
3187         return 0;
3188 }
3189
3190 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3191                     struct comedi_insn *insn, unsigned int *data)
3192 {
3193         int chan = CR_CHAN(insn->chanspec);
3194         int range = CR_RANGE(insn->chanspec);
3195
3196         /*  do some initializing */
3197         writew(0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3198
3199         /*  set range */
3200         set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, chan, range);
3201         writew(priv(dev)->dac_control1_bits,
3202                priv(dev)->main_iobase + DAC_CONTROL1_REG);
3203
3204         /*  write to channel */
3205         if (board(dev)->layout == LAYOUT_4020) {
3206                 writew(data[0] & 0xff,
3207                        priv(dev)->main_iobase + dac_lsb_4020_reg(chan));
3208                 writew((data[0] >> 8) & 0xf,
3209                        priv(dev)->main_iobase + dac_msb_4020_reg(chan));
3210         } else {
3211                 writew(data[0], priv(dev)->main_iobase + dac_convert_reg(chan));
3212         }
3213
3214         /*  remember output value */
3215         priv(dev)->ao_value[chan] = data[0];
3216
3217         return 1;
3218 }
3219
3220 static int ao_readback_insn(struct comedi_device *dev,
3221                             struct comedi_subdevice *s,
3222                             struct comedi_insn *insn, unsigned int *data)
3223 {
3224         data[0] = priv(dev)->ao_value[CR_CHAN(insn->chanspec)];
3225
3226         return 1;
3227 }
3228
3229 static void set_dac_control0_reg(struct comedi_device *dev,
3230                                  const struct comedi_cmd *cmd)
3231 {
3232         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3233             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3234
3235         if (cmd->start_src == TRIG_EXT) {
3236                 bits |= WAVEFORM_TRIG_EXT_BITS;
3237                 if (cmd->start_arg & CR_INVERT)
3238                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3239         } else {
3240                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3241         }
3242         if (cmd->scan_begin_src == TRIG_EXT) {
3243                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3244                 if (cmd->scan_begin_arg & CR_INVERT)
3245                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3246         }
3247         writew(bits, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3248 }
3249
3250 static void set_dac_control1_reg(struct comedi_device *dev,
3251                                  const struct comedi_cmd *cmd)
3252 {
3253         int i;
3254
3255         for (i = 0; i < cmd->chanlist_len; i++) {
3256                 int channel, range;
3257
3258                 channel = CR_CHAN(cmd->chanlist[i]);
3259                 range = CR_RANGE(cmd->chanlist[i]);
3260                 set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, channel,
3261                                    range);
3262         }
3263         priv(dev)->dac_control1_bits |= DAC_SW_GATE_BIT;
3264         writew(priv(dev)->dac_control1_bits,
3265                priv(dev)->main_iobase + DAC_CONTROL1_REG);
3266 }
3267
3268 static void set_dac_select_reg(struct comedi_device *dev,
3269                                const struct comedi_cmd *cmd)
3270 {
3271         uint16_t bits;
3272         unsigned int first_channel, last_channel;
3273
3274         first_channel = CR_CHAN(cmd->chanlist[0]);
3275         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3276         if (last_channel < first_channel)
3277                 comedi_error(dev, "bug! last ao channel < first ao channel");
3278
3279         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3280
3281         writew(bits, priv(dev)->main_iobase + DAC_SELECT_REG);
3282 }
3283
3284 static void set_dac_interval_regs(struct comedi_device *dev,
3285                                   const struct comedi_cmd *cmd)
3286 {
3287         unsigned int divisor;
3288
3289         if (cmd->scan_begin_src != TRIG_TIMER)
3290                 return;
3291
3292         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3293         if (divisor > max_counter_value) {
3294                 comedi_error(dev, "bug! ao divisor too big");
3295                 divisor = max_counter_value;
3296         }
3297         writew(divisor & 0xffff,
3298                priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3299         writew((divisor >> 16) & 0xff,
3300                priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3301 }
3302
3303 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
3304                                        const struct comedi_cmd *cmd)
3305 {
3306         unsigned int num_bytes, buffer_index, prev_buffer_index;
3307         unsigned int next_bits;
3308
3309         buffer_index = priv(dev)->ao_dma_index;
3310         prev_buffer_index = prev_ao_dma_index(dev);
3311
3312         DEBUG_PRINT("attempting to load ao buffer %i (0x%x)\n", buffer_index,
3313                     priv(dev)->ao_buffer_bus_addr[buffer_index]);
3314
3315         num_bytes = comedi_buf_read_n_available(dev->write_subdev->async);
3316         if (num_bytes > DMA_BUFFER_SIZE)
3317                 num_bytes = DMA_BUFFER_SIZE;
3318         if (cmd->stop_src == TRIG_COUNT && num_bytes > priv(dev)->ao_count)
3319                 num_bytes = priv(dev)->ao_count;
3320         num_bytes -= num_bytes % bytes_in_sample;
3321
3322         if (num_bytes == 0)
3323                 return 0;
3324
3325         DEBUG_PRINT("loading %i bytes\n", num_bytes);
3326
3327         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3328                                                priv(dev)->
3329                                                ao_buffer[buffer_index],
3330                                                num_bytes);
3331         priv(dev)->ao_dma_desc[buffer_index].transfer_size =
3332             cpu_to_le32(num_bytes);
3333         /* set end of chain bit so we catch underruns */
3334         next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[buffer_index].next);
3335         next_bits |= PLX_END_OF_CHAIN_BIT;
3336         priv(dev)->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
3337         /* clear end of chain bit on previous buffer now that we have set it
3338          * for the last buffer */
3339         next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[prev_buffer_index].next);
3340         next_bits &= ~PLX_END_OF_CHAIN_BIT;
3341         priv(dev)->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
3342
3343         priv(dev)->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
3344         priv(dev)->ao_count -= num_bytes;
3345
3346         return num_bytes;
3347 }
3348
3349 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3350 {
3351         unsigned int num_bytes;
3352         unsigned int next_transfer_addr;
3353         void __iomem *pci_addr_reg =
3354             priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
3355         unsigned int buffer_index;
3356
3357         do {
3358                 buffer_index = priv(dev)->ao_dma_index;
3359                 /* don't overwrite data that hasn't been transferred yet */
3360                 next_transfer_addr = readl(pci_addr_reg);
3361                 if (next_transfer_addr >=
3362                     priv(dev)->ao_buffer_bus_addr[buffer_index]
3363                     && next_transfer_addr <
3364                     priv(dev)->ao_buffer_bus_addr[buffer_index] +
3365                     DMA_BUFFER_SIZE)
3366                         return;
3367                 num_bytes = load_ao_dma_buffer(dev, cmd);
3368         } while (num_bytes >= DMA_BUFFER_SIZE);
3369 }
3370
3371 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3372 {
3373         unsigned int num_bytes;
3374         int i;
3375
3376         /* clear queue pointer too, since external queue has
3377          * weird interactions with ao fifo */
3378         writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
3379         writew(0, priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG);
3380
3381         num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3382         if (cmd->stop_src == TRIG_COUNT &&
3383             num_bytes / bytes_in_sample > priv(dev)->ao_count)
3384                 num_bytes = priv(dev)->ao_count * bytes_in_sample;
3385         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3386                                                priv(dev)->ao_bounce_buffer,
3387                                                num_bytes);
3388         for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3389                 writew(priv(dev)->ao_bounce_buffer[i],
3390                        priv(dev)->main_iobase + DAC_FIFO_REG);
3391         }
3392         priv(dev)->ao_count -= num_bytes / bytes_in_sample;
3393         if (cmd->stop_src == TRIG_COUNT && priv(dev)->ao_count == 0)
3394                 return 0;
3395         num_bytes = load_ao_dma_buffer(dev, cmd);
3396         if (num_bytes == 0)
3397                 return -1;
3398         if (num_bytes >= DMA_BUFFER_SIZE) ;
3399         load_ao_dma(dev, cmd);
3400
3401         dma_start_sync(dev, 0);
3402
3403         return 0;
3404 }
3405
3406 static inline int external_ai_queue_in_use(struct comedi_device *dev)
3407 {
3408         if (dev->read_subdev->busy)
3409                 return 0;
3410         if (board(dev)->layout == LAYOUT_4020)
3411                 return 0;
3412         else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd))
3413                 return 0;
3414         return 1;
3415 }
3416
3417 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3418 {
3419         struct comedi_cmd *cmd = &s->async->cmd;
3420
3421         if (external_ai_queue_in_use(dev)) {
3422                 warn_external_queue(dev);
3423                 return -EBUSY;
3424         }
3425         /* disable analog output system during setup */
3426         writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3427
3428         priv(dev)->ao_dma_index = 0;
3429         priv(dev)->ao_count = cmd->stop_arg * cmd->chanlist_len;
3430
3431         set_dac_select_reg(dev, cmd);
3432         set_dac_interval_regs(dev, cmd);
3433         load_first_dma_descriptor(dev, 0, priv(dev)->ao_dma_desc_bus_addr |
3434                                   PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3435
3436         set_dac_control1_reg(dev, cmd);
3437         s->async->inttrig = ao_inttrig;
3438
3439         return 0;
3440 }
3441
3442 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3443                       unsigned int trig_num)
3444 {
3445         struct comedi_cmd *cmd = &s->async->cmd;
3446         int retval;
3447
3448         if (trig_num != 0)
3449                 return -EINVAL;
3450
3451         retval = prep_ao_dma(dev, cmd);
3452         if (retval < 0)
3453                 return -EPIPE;
3454
3455         set_dac_control0_reg(dev, cmd);
3456
3457         if (cmd->start_src == TRIG_INT)
3458                 writew(0, priv(dev)->main_iobase + DAC_START_REG);
3459
3460         s->async->inttrig = NULL;
3461
3462         return 0;
3463 }
3464
3465 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3466                       struct comedi_cmd *cmd)
3467 {
3468         int err = 0;
3469         int tmp;
3470         unsigned int tmp_arg;
3471         int i;
3472
3473         /* step 1: make sure trigger sources are trivially valid */
3474
3475         tmp = cmd->start_src;
3476         cmd->start_src &= TRIG_INT | TRIG_EXT;
3477         if (!cmd->start_src || tmp != cmd->start_src)
3478                 err++;
3479
3480         tmp = cmd->scan_begin_src;
3481         cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
3482         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3483                 err++;
3484
3485         tmp = cmd->convert_src;
3486         cmd->convert_src &= TRIG_NOW;
3487         if (!cmd->convert_src || tmp != cmd->convert_src)
3488                 err++;
3489
3490         tmp = cmd->scan_end_src;
3491         cmd->scan_end_src &= TRIG_COUNT;
3492         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3493                 err++;
3494
3495         tmp = cmd->stop_src;
3496         cmd->stop_src &= TRIG_NONE;
3497         if (!cmd->stop_src || tmp != cmd->stop_src)
3498                 err++;
3499
3500         if (err)
3501                 return 1;
3502
3503         /* step 2: make sure trigger sources are unique and mutually compatible */
3504
3505         /*  uniqueness check */
3506         if (cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT)
3507                 err++;
3508         if (cmd->scan_begin_src != TRIG_TIMER &&
3509             cmd->scan_begin_src != TRIG_EXT)
3510                 err++;
3511
3512         /*  compatibility check */
3513         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3514                 err++;
3515         if (cmd->stop_src != TRIG_COUNT &&
3516             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3517                 err++;
3518
3519         if (err)
3520                 return 2;
3521
3522         /* step 3: make sure arguments are trivially compatible */
3523
3524         if (cmd->scan_begin_src == TRIG_TIMER) {
3525                 if (cmd->scan_begin_arg < board(dev)->ao_scan_speed) {
3526                         cmd->scan_begin_arg = board(dev)->ao_scan_speed;
3527                         err++;
3528                 }
3529                 if (get_ao_divisor(cmd->scan_begin_arg,
3530                                    cmd->flags) > max_counter_value) {
3531                         cmd->scan_begin_arg =
3532                             (max_counter_value + 2) * TIMER_BASE;
3533                         err++;
3534                 }
3535         }
3536
3537         if (!cmd->chanlist_len) {
3538                 cmd->chanlist_len = 1;
3539                 err++;
3540         }
3541         if (cmd->scan_end_arg != cmd->chanlist_len) {
3542                 cmd->scan_end_arg = cmd->chanlist_len;
3543                 err++;
3544         }
3545
3546         if (err)
3547                 return 3;
3548
3549         /* step 4: fix up any arguments */
3550
3551         if (cmd->scan_begin_src == TRIG_TIMER) {
3552                 tmp_arg = cmd->scan_begin_arg;
3553                 cmd->scan_begin_arg =
3554                     get_divisor(cmd->scan_begin_arg, cmd->flags) * TIMER_BASE;
3555                 if (tmp_arg != cmd->scan_begin_arg)
3556                         err++;
3557         }
3558
3559         if (err)
3560                 return 4;
3561
3562         if (cmd->chanlist) {
3563                 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
3564                 for (i = 1; i < cmd->chanlist_len; i++) {
3565                         if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) {
3566                                 comedi_error(dev,
3567                                              "chanlist must use consecutive channels");
3568                                 err++;
3569                                 break;
3570                         }
3571                 }
3572         }
3573
3574         if (err)
3575                 return 5;
3576
3577         return 0;
3578 }
3579
3580 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3581 {
3582         writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3583         abort_dma(dev, 0);
3584         return 0;
3585 }
3586
3587 static int dio_callback(int dir, int port, int data, unsigned long arg)
3588 {
3589         void __iomem *iobase = (void __iomem *)arg;
3590         if (dir) {
3591                 writeb(data, iobase + port);
3592                 DEBUG_PRINT("wrote 0x%x to port %i\n", data, port);
3593                 return 0;
3594         } else {
3595                 return readb(iobase + port);
3596         }
3597 }
3598
3599 static int dio_callback_4020(int dir, int port, int data, unsigned long arg)
3600 {
3601         void __iomem *iobase = (void __iomem *)arg;
3602         if (dir) {
3603                 writew(data, iobase + 2 * port);
3604                 return 0;
3605         } else {
3606                 return readw(iobase + 2 * port);
3607         }
3608 }
3609
3610 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3611                     struct comedi_insn *insn, unsigned int *data)
3612 {
3613         unsigned int bits;
3614
3615         bits = readb(priv(dev)->dio_counter_iobase + DI_REG);
3616         bits &= 0xf;
3617         data[1] = bits;
3618         data[0] = 0;
3619
3620         return insn->n;
3621 }
3622
3623 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3624                     struct comedi_insn *insn, unsigned int *data)
3625 {
3626         data[0] &= 0xf;
3627         /*  zero bits we are going to change */
3628         s->state &= ~data[0];
3629         /*  set new bits */
3630         s->state |= data[0] & data[1];
3631
3632         writeb(s->state, priv(dev)->dio_counter_iobase + DO_REG);
3633
3634         data[1] = s->state;
3635
3636         return insn->n;
3637 }
3638
3639 static int dio_60xx_config_insn(struct comedi_device *dev,
3640                                 struct comedi_subdevice *s,
3641                                 struct comedi_insn *insn, unsigned int *data)
3642 {
3643         unsigned int mask;
3644
3645         mask = 1 << CR_CHAN(insn->chanspec);
3646
3647         switch (data[0]) {
3648         case INSN_CONFIG_DIO_INPUT:
3649                 s->io_bits &= ~mask;
3650                 break;
3651         case INSN_CONFIG_DIO_OUTPUT:
3652                 s->io_bits |= mask;
3653                 break;
3654         case INSN_CONFIG_DIO_QUERY:
3655                 data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT;
3656                 return 2;
3657         default:
3658                 return -EINVAL;
3659         }
3660
3661         writeb(s->io_bits,
3662                priv(dev)->dio_counter_iobase + DIO_DIRECTION_60XX_REG);
3663
3664         return 1;
3665 }
3666
3667 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3668                           struct comedi_insn *insn, unsigned int *data)
3669 {
3670         if (data[0]) {
3671                 s->state &= ~data[0];
3672                 s->state |= (data[0] & data[1]);
3673                 writeb(s->state,
3674                        priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG);
3675         }
3676
3677         data[1] = readb(priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG);
3678
3679         return insn->n;
3680 }
3681
3682 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3683                          unsigned int value)
3684 {
3685         priv(dev)->caldac_state[channel] = value;
3686
3687         switch (board(dev)->layout) {
3688         case LAYOUT_60XX:
3689         case LAYOUT_64XX:
3690                 caldac_8800_write(dev, channel, value);
3691                 break;
3692         case LAYOUT_4020:
3693                 caldac_i2c_write(dev, channel, value);
3694                 break;
3695         default:
3696                 break;
3697         }
3698 }
3699
3700 static int calib_write_insn(struct comedi_device *dev,
3701                             struct comedi_subdevice *s,
3702                             struct comedi_insn *insn, unsigned int *data)
3703 {
3704         int channel = CR_CHAN(insn->chanspec);
3705
3706         /* return immediately if setting hasn't changed, since
3707          * programming these things is slow */
3708         if (priv(dev)->caldac_state[channel] == data[0])
3709                 return 1;
3710
3711         caldac_write(dev, channel, data[0]);
3712
3713         return 1;
3714 }
3715
3716 static int calib_read_insn(struct comedi_device *dev,
3717                            struct comedi_subdevice *s, struct comedi_insn *insn,
3718                            unsigned int *data)
3719 {
3720         unsigned int channel = CR_CHAN(insn->chanspec);
3721
3722         data[0] = priv(dev)->caldac_state[channel];
3723
3724         return 1;
3725 }
3726
3727 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3728                          unsigned int value)
3729 {
3730         static const int bitstream_length = 10;
3731         unsigned int bit, register_bits;
3732         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3733         static const int ad8402_udelay = 1;
3734
3735         priv(dev)->ad8402_state[channel] = value;
3736
3737         register_bits = SELECT_8402_64XX_BIT;
3738         udelay(ad8402_udelay);
3739         writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3740
3741         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3742                 if (bitstream & bit)
3743                         register_bits |= SERIAL_DATA_IN_BIT;
3744                 else
3745                         register_bits &= ~SERIAL_DATA_IN_BIT;
3746                 udelay(ad8402_udelay);
3747                 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3748                 udelay(ad8402_udelay);
3749                 writew(register_bits | SERIAL_CLOCK_BIT,
3750                        priv(dev)->main_iobase + CALIBRATION_REG);
3751         }
3752
3753         udelay(ad8402_udelay);
3754         writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
3755 }
3756
3757 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3758 static int ad8402_write_insn(struct comedi_device *dev,
3759                              struct comedi_subdevice *s,
3760                              struct comedi_insn *insn, unsigned int *data)
3761 {
3762         int channel = CR_CHAN(insn->chanspec);
3763
3764         /* return immediately if setting hasn't changed, since
3765          * programming these things is slow */
3766         if (priv(dev)->ad8402_state[channel] == data[0])
3767                 return 1;
3768
3769         priv(dev)->ad8402_state[channel] = data[0];
3770
3771         ad8402_write(dev, channel, data[0]);
3772
3773         return 1;
3774 }
3775
3776 static int ad8402_read_insn(struct comedi_device *dev,
3777                             struct comedi_subdevice *s,
3778                             struct comedi_insn *insn, unsigned int *data)
3779 {
3780         unsigned int channel = CR_CHAN(insn->chanspec);
3781
3782         data[0] = priv(dev)->ad8402_state[channel];
3783
3784         return 1;
3785 }
3786
3787 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3788 {
3789         static const int bitstream_length = 11;
3790         static const int read_command = 0x6;
3791         unsigned int bitstream = (read_command << 8) | address;
3792         unsigned int bit;
3793         void __iomem * const plx_control_addr =
3794             priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
3795         uint16_t value;
3796         static const int value_length = 16;
3797         static const int eeprom_udelay = 1;
3798
3799         udelay(eeprom_udelay);
3800         priv(dev)->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3801         /*  make sure we don't send anything to the i2c bus on 4020 */
3802         priv(dev)->plx_control_bits |= CTL_USERO;
3803         writel(priv(dev)->plx_control_bits, plx_control_addr);
3804         /*  activate serial eeprom */
3805         udelay(eeprom_udelay);
3806         priv(dev)->plx_control_bits |= CTL_EE_CS;
3807         writel(priv(dev)->plx_control_bits, plx_control_addr);
3808
3809         /*  write read command and desired memory address */
3810         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3811                 /*  set bit to be written */
3812                 udelay(eeprom_udelay);
3813                 if (bitstream & bit)
3814                         priv(dev)->plx_control_bits |= CTL_EE_W;
3815                 else
3816                         priv(dev)->plx_control_bits &= ~CTL_EE_W;
3817                 writel(priv(dev)->plx_control_bits, plx_control_addr);
3818                 /*  clock in bit */
3819                 udelay(eeprom_udelay);
3820                 priv(dev)->plx_control_bits |= CTL_EE_CLK;
3821                 writel(priv(dev)->plx_control_bits, plx_control_addr);
3822                 udelay(eeprom_udelay);
3823                 priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
3824                 writel(priv(dev)->plx_control_bits, plx_control_addr);
3825         }
3826         /*  read back value from eeprom memory location */
3827         value = 0;
3828         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3829                 /*  clock out bit */
3830                 udelay(eeprom_udelay);
3831                 priv(dev)->plx_control_bits |= CTL_EE_CLK;
3832                 writel(priv(dev)->plx_control_bits, plx_control_addr);
3833                 udelay(eeprom_udelay);
3834                 priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
3835                 writel(priv(dev)->plx_control_bits, plx_control_addr);
3836                 udelay(eeprom_udelay);
3837                 if (readl(plx_control_addr) & CTL_EE_R)
3838                         value |= bit;
3839         }
3840
3841         /*  deactivate eeprom serial input */
3842         udelay(eeprom_udelay);
3843         priv(dev)->plx_control_bits &= ~CTL_EE_CS;
3844         writel(priv(dev)->plx_control_bits, plx_control_addr);
3845
3846         return value;
3847 }
3848
3849 static int eeprom_read_insn(struct comedi_device *dev,
3850                             struct comedi_subdevice *s,
3851                             struct comedi_insn *insn, unsigned int *data)
3852 {
3853         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3854
3855         return 1;
3856 }
3857
3858 /* utility function that rounds desired timing to an achievable time, and
3859  * sets cmd members appropriately.
3860  * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
3861  */
3862 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
3863 {
3864         unsigned int convert_divisor = 0, scan_divisor;
3865         static const int min_convert_divisor = 3;
3866         static const int max_convert_divisor =
3867             max_counter_value + min_convert_divisor;
3868         static const int min_scan_divisor_4020 = 2;
3869         unsigned long long max_scan_divisor, min_scan_divisor;
3870
3871         if (cmd->convert_src == TRIG_TIMER) {
3872                 if (board(dev)->layout == LAYOUT_4020) {
3873                         cmd->convert_arg = 0;
3874                 } else {
3875                         convert_divisor =
3876                             get_divisor(cmd->convert_arg, cmd->flags);
3877                         if (convert_divisor > max_convert_divisor)
3878                                 convert_divisor = max_convert_divisor;
3879                         if (convert_divisor < min_convert_divisor)
3880                                 convert_divisor = min_convert_divisor;
3881                         cmd->convert_arg = convert_divisor * TIMER_BASE;
3882                 }
3883         } else if (cmd->convert_src == TRIG_NOW)
3884                 cmd->convert_arg = 0;
3885
3886         if (cmd->scan_begin_src == TRIG_TIMER) {
3887                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
3888                 if (cmd->convert_src == TRIG_TIMER) {
3889                         /*  XXX check for integer overflows */
3890                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
3891                         max_scan_divisor =
3892                             (convert_divisor * cmd->chanlist_len - 1) +
3893                             max_counter_value;
3894                 } else {
3895                         min_scan_divisor = min_scan_divisor_4020;
3896                         max_scan_divisor = max_counter_value + min_scan_divisor;
3897                 }
3898                 if (scan_divisor > max_scan_divisor)
3899                         scan_divisor = max_scan_divisor;
3900                 if (scan_divisor < min_scan_divisor)
3901                         scan_divisor = min_scan_divisor;
3902                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
3903         }
3904
3905         return;
3906 }
3907
3908 /* Gets nearest achievable timing given master clock speed, does not
3909  * take into account possible minimum/maximum divisor values.  Used
3910  * by other timing checking functions. */
3911 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
3912 {
3913         unsigned int divisor;
3914
3915         switch (flags & TRIG_ROUND_MASK) {
3916         case TRIG_ROUND_UP:
3917                 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
3918                 break;
3919         case TRIG_ROUND_DOWN:
3920                 divisor = ns / TIMER_BASE;
3921                 break;
3922         case TRIG_ROUND_NEAREST:
3923         default:
3924                 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
3925                 break;
3926         }
3927         return divisor;
3928 }
3929
3930 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3931 {
3932         return get_divisor(ns, flags) - 2;
3933 }
3934
3935 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
3936 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
3937 {
3938         unsigned int num_fifo_entries;
3939         int retval;
3940         const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
3941
3942         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
3943
3944         retval = set_ai_fifo_segment_length(dev,
3945                                             num_fifo_entries /
3946                                             fifo->num_segments);
3947         if (retval < 0)
3948                 return retval;
3949
3950         num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
3951
3952         DEBUG_PRINT("set hardware fifo size to %i\n", num_samples);
3953
3954         return num_samples;
3955 }
3956
3957 /* query length of fifo */
3958 static unsigned int ai_fifo_size(struct comedi_device *dev)
3959 {
3960         return priv(dev)->ai_fifo_segment_length *
3961             board(dev)->ai_fifo->num_segments *
3962             board(dev)->ai_fifo->sample_packing_ratio;
3963 }
3964
3965 static int set_ai_fifo_segment_length(struct comedi_device *dev,
3966                                       unsigned int num_entries)
3967 {
3968         static const int increment_size = 0x100;
3969         const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
3970         unsigned int num_increments;
3971         uint16_t bits;
3972
3973         if (num_entries < increment_size)
3974                 num_entries = increment_size;
3975         if (num_entries > fifo->max_segment_length)
3976                 num_entries = fifo->max_segment_length;
3977
3978         /*  1 == 256 entries, 2 == 512 entries, etc */
3979         num_increments = (num_entries + increment_size / 2) / increment_size;
3980
3981         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
3982         priv(dev)->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
3983         priv(dev)->fifo_size_bits |= bits;
3984         writew(priv(dev)->fifo_size_bits,
3985                priv(dev)->main_iobase + FIFO_SIZE_REG);
3986
3987         priv(dev)->ai_fifo_segment_length = num_increments * increment_size;
3988
3989         DEBUG_PRINT("set hardware fifo segment length to %i\n",
3990                     priv(dev)->ai_fifo_segment_length);
3991
3992         return priv(dev)->ai_fifo_segment_length;
3993 }
3994
3995 /* pci-6025 8800 caldac:
3996  * address 0 == dac channel 0 offset
3997  * address 1 == dac channel 0 gain
3998  * address 2 == dac channel 1 offset
3999  * address 3 == dac channel 1 gain
4000  * address 4 == fine adc offset
4001  * address 5 == coarse adc offset
4002  * address 6 == coarse adc gain
4003  * address 7 == fine adc gain
4004  */
4005 /* pci-6402/16 uses all 8 channels for dac:
4006  * address 0 == dac channel 0 fine gain
4007  * address 1 == dac channel 0 coarse gain
4008  * address 2 == dac channel 0 coarse offset
4009  * address 3 == dac channel 1 coarse offset
4010  * address 4 == dac channel 1 fine gain
4011  * address 5 == dac channel 1 coarse gain
4012  * address 6 == dac channel 0 fine offset
4013  * address 7 == dac channel 1 fine offset
4014 */
4015
4016 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
4017                              uint8_t value)
4018 {
4019         static const int num_caldac_channels = 8;
4020         static const int bitstream_length = 11;
4021         unsigned int bitstream = ((address & 0x7) << 8) | value;
4022         unsigned int bit, register_bits;
4023         static const int caldac_8800_udelay = 1;
4024
4025         if (address >= num_caldac_channels) {
4026                 comedi_error(dev, "illegal caldac channel");
4027                 return -1;
4028         }
4029         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
4030                 register_bits = 0;
4031                 if (bitstream & bit)
4032                         register_bits |= SERIAL_DATA_IN_BIT;
4033                 udelay(caldac_8800_udelay);
4034                 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
4035                 register_bits |= SERIAL_CLOCK_BIT;
4036                 udelay(caldac_8800_udelay);
4037                 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
4038         }
4039         udelay(caldac_8800_udelay);
4040         writew(SELECT_8800_BIT, priv(dev)->main_iobase + CALIBRATION_REG);
4041         udelay(caldac_8800_udelay);
4042         writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
4043         udelay(caldac_8800_udelay);
4044         return 0;
4045 }
4046
4047 /* 4020 caldacs */
4048 static int caldac_i2c_write(struct comedi_device *dev,
4049                             unsigned int caldac_channel, unsigned int value)
4050 {
4051         uint8_t serial_bytes[3];
4052         uint8_t i2c_addr;
4053         enum pointer_bits {
4054                 /*  manual has gain and offset bits switched */
4055                 OFFSET_0_2 = 0x1,
4056                 GAIN_0_2 = 0x2,
4057                 OFFSET_1_3 = 0x4,
4058                 GAIN_1_3 = 0x8,
4059         };
4060         enum data_bits {
4061                 NOT_CLEAR_REGISTERS = 0x20,
4062         };
4063
4064         switch (caldac_channel) {
4065         case 0:         /*  chan 0 offset */
4066                 i2c_addr = CALDAC0_I2C_ADDR;
4067                 serial_bytes[0] = OFFSET_0_2;
4068                 break;
4069         case 1:         /*  chan 1 offset */
4070                 i2c_addr = CALDAC0_I2C_ADDR;
4071                 serial_bytes[0] = OFFSET_1_3;
4072                 break;
4073         case 2:         /*  chan 2 offset */
4074                 i2c_addr = CALDAC1_I2C_ADDR;
4075                 serial_bytes[0] = OFFSET_0_2;
4076                 break;
4077         case 3:         /*  chan 3 offset */
4078                 i2c_addr = CALDAC1_I2C_ADDR;
4079                 serial_bytes[0] = OFFSET_1_3;
4080                 break;
4081         case 4:         /*  chan 0 gain */
4082                 i2c_addr = CALDAC0_I2C_ADDR;
4083                 serial_bytes[0] = GAIN_0_2;
4084                 break;
4085         case 5:         /*  chan 1 gain */
4086                 i2c_addr = CALDAC0_I2C_ADDR;
4087                 serial_bytes[0] = GAIN_1_3;
4088                 break;
4089         case 6:         /*  chan 2 gain */
4090                 i2c_addr = CALDAC1_I2C_ADDR;
4091                 serial_bytes[0] = GAIN_0_2;
4092                 break;
4093         case 7:         /*  chan 3 gain */
4094                 i2c_addr = CALDAC1_I2C_ADDR;
4095                 serial_bytes[0] = GAIN_1_3;
4096                 break;
4097         default:
4098                 comedi_error(dev, "invalid caldac channel\n");
4099                 return -1;
4100                 break;
4101         }
4102         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
4103         serial_bytes[2] = value & 0xff;
4104         i2c_write(dev, i2c_addr, serial_bytes, 3);
4105         return 0;
4106 }
4107
4108 /* Their i2c requires a huge delay on setting clock or data high for some reason */
4109 static const int i2c_high_udelay = 1000;
4110 static const int i2c_low_udelay = 10;
4111
4112 /* set i2c data line high or low */
4113 static void i2c_set_sda(struct comedi_device *dev, int state)
4114 {
4115         static const int data_bit = CTL_EE_W;
4116         void __iomem *plx_control_addr = priv(dev)->plx9080_iobase +
4117                                          PLX_CONTROL_REG;
4118
4119         if (state) {
4120                 /*  set data line high */
4121                 priv(dev)->plx_control_bits &= ~data_bit;
4122                 writel(priv(dev)->plx_control_bits, plx_control_addr);
4123                 udelay(i2c_high_udelay);
4124         } else {                /*  set data line low */
4125
4126                 priv(dev)->plx_control_bits |= data_bit;
4127                 writel(priv(dev)->plx_control_bits, plx_control_addr);
4128                 udelay(i2c_low_udelay);
4129         }
4130 }
4131
4132 /* set i2c clock line high or low */
4133 static void i2c_set_scl(struct comedi_device *dev, int state)
4134 {
4135         static const int clock_bit = CTL_USERO;
4136         void __iomem *plx_control_addr = priv(dev)->plx9080_iobase +
4137                                          PLX_CONTROL_REG;
4138
4139         if (state) {
4140                 /*  set clock line high */
4141                 priv(dev)->plx_control_bits &= ~clock_bit;
4142                 writel(priv(dev)->plx_control_bits, plx_control_addr);
4143                 udelay(i2c_high_udelay);
4144         } else {                /*  set clock line low */
4145
4146                 priv(dev)->plx_control_bits |= clock_bit;
4147                 writel(priv(dev)->plx_control_bits, plx_control_addr);
4148                 udelay(i2c_low_udelay);
4149         }
4150 }
4151
4152 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
4153 {
4154         uint8_t bit;
4155         unsigned int num_bits = 8;
4156
4157         DEBUG_PRINT("writing to i2c byte 0x%x\n", byte);
4158
4159         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
4160                 i2c_set_scl(dev, 0);
4161                 if ((byte & bit))
4162                         i2c_set_sda(dev, 1);
4163                 else
4164                         i2c_set_sda(dev, 0);
4165                 i2c_set_scl(dev, 1);
4166         }
4167 }
4168
4169 /* we can't really read the lines, so fake it */
4170 static int i2c_read_ack(struct comedi_device *dev)
4171 {
4172         i2c_set_scl(dev, 0);
4173         i2c_set_sda(dev, 1);
4174         i2c_set_scl(dev, 1);
4175
4176         return 0;               /*  return fake acknowledge bit */
4177 }
4178
4179 /* send start bit */
4180 static void i2c_start(struct comedi_device *dev)
4181 {
4182         i2c_set_scl(dev, 1);
4183         i2c_set_sda(dev, 1);
4184         i2c_set_sda(dev, 0);
4185 }
4186
4187 /* send stop bit */
4188 static void i2c_stop(struct comedi_device *dev)
4189 {
4190         i2c_set_scl(dev, 0);
4191         i2c_set_sda(dev, 0);
4192         i2c_set_scl(dev, 1);
4193         i2c_set_sda(dev, 1);
4194 }
4195
4196 static void i2c_write(struct comedi_device *dev, unsigned int address,
4197                       const uint8_t *data, unsigned int length)
4198 {
4199         unsigned int i;
4200         uint8_t bitstream;
4201         static const int read_bit = 0x1;
4202
4203 /* XXX need mutex to prevent simultaneous attempts to access eeprom and i2c bus */
4204
4205         /*  make sure we dont send anything to eeprom */
4206         priv(dev)->plx_control_bits &= ~CTL_EE_CS;
4207
4208         i2c_stop(dev);
4209         i2c_start(dev);
4210
4211         /*  send address and write bit */
4212         bitstream = (address << 1) & ~read_bit;
4213         i2c_write_byte(dev, bitstream);
4214
4215         /*  get acknowledge */
4216         if (i2c_read_ack(dev) != 0) {
4217                 comedi_error(dev, "i2c write failed: no acknowledge");
4218                 i2c_stop(dev);
4219                 return;
4220         }
4221         /*  write data bytes */
4222         for (i = 0; i < length; i++) {
4223                 i2c_write_byte(dev, data[i]);
4224                 if (i2c_read_ack(dev) != 0) {
4225                         comedi_error(dev, "i2c write failed: no acknowledge");
4226                         i2c_stop(dev);
4227                         return;
4228                 }
4229         }
4230         i2c_stop(dev);
4231 }
4232
4233 static struct comedi_driver cb_pcidas64_driver = {
4234         .driver_name    = "cb_pcidas64",
4235         .module         = THIS_MODULE,
4236         .attach         = attach,
4237         .detach         = detach,
4238 };
4239
4240 static int __devinit cb_pcidas64_pci_probe(struct pci_dev *dev,
4241                                            const struct pci_device_id *ent)
4242 {
4243         return comedi_pci_auto_config(dev, &cb_pcidas64_driver);
4244 }
4245
4246 static void __devexit cb_pcidas64_pci_remove(struct pci_dev *dev)
4247 {
4248         comedi_pci_auto_unconfig(dev);
4249 }
4250
4251 static DEFINE_PCI_DEVICE_TABLE(cb_pcidas64_pci_table) = {
4252         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x001d) },
4253         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x001e) },
4254         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0035) },
4255         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0036) },
4256         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0037) },
4257         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0052) },
4258         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005d) },
4259         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005e) },
4260         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005f) },
4261         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0061) },
4262         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0062) },
4263         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0063) },
4264         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0064) },
4265         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0066) },
4266         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0067) },
4267         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0068) },
4268         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x006f) },
4269         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0078) },
4270         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0079) },
4271         { 0 }
4272 };
4273 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4274
4275 static struct pci_driver cb_pcidas64_pci_driver = {
4276         .name           = "cb_pcidas64",
4277         .id_table       = cb_pcidas64_pci_table,
4278         .probe          = cb_pcidas64_pci_probe,
4279         .remove         = __devexit_p(cb_pcidas64_pci_remove),
4280 };
4281 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4282
4283 MODULE_AUTHOR("Comedi http://www.comedi.org");
4284 MODULE_DESCRIPTION("Comedi low-level driver");
4285 MODULE_LICENSE("GPL");