drivers/staging/comedi/drivers/cb_pcidas64.c

   1 /*
   2     comedi/drivers/cb_pcidas64.c
   3     This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
   4     64xx, 60xx, and 4020 cards.
   5
   6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7     Copyright (C) 2001, 2002 Frank Mori Hess
   8
   9     Thanks also go to the following people:
  10
  11     Steve Rosenbluth, for providing the source code for
  12     his pci-das6402 driver, and source code for working QNX pci-6402
  13     drivers by Greg Laird and Mariusz Bogacz.  None of the code was
  14     used directly here, but it was useful as an additional source of
  15     documentation on how to program the boards.
  16
  17     John Sims, for much testing and feedback on pcidas-4020 support.
  18
  19     COMEDI - Linux Control and Measurement Device Interface
  20     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  21
  22     This program is free software; you can redistribute it and/or modify
  23     it under the terms of the GNU General Public License as published by
  24     the Free Software Foundation; either version 2 of the License, or
  25     (at your option) any later version.
  26
  27     This program is distributed in the hope that it will be useful,
  28     but WITHOUT ANY WARRANTY; without even the implied warranty of
  29     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30     GNU General Public License for more details.
  31
  32     You should have received a copy of the GNU General Public License
  33     along with this program; if not, write to the Free Software
  34     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  35
  36 ************************************************************************/
  37
  38 /*
  39
  40 Driver: cb_pcidas64
  41 Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series with the PLX 9080 PCI controller
  42 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  43 Status: works
  44 Updated: 2002-10-09
  45 Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
  46   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
  47   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
  48   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
  49   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
  50   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
  51   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
  52   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
  53   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
  54
  55 Configuration options:
  56    [0] - PCI bus of device (optional)
  57    [1] - PCI slot of device (optional)
  58
  59 These boards may be autocalibrated with the comedi_calibrate utility.
  60
  61 To select the bnc trigger input on the 4020 (instead of the dio input),
  62 specify a nonzero channel in the chanspec.  If you wish to use an external
  63 master clock on the 4020, you may do so by setting the scan_begin_src
  64 to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
  65 to configure the divisor to use for the external clock.
  66
  67 Some devices are not identified because the PCI device IDs are not yet
  68 known. If you have such a board, please file a bug report at
  69 https://bugs.comedi.org.
  70
  71 */
  72
  73 /*
  74
  75 TODO:
  76         make it return error if user attempts an ai command that uses the
  77                 external queue, and an ao command simultaneously
  78         user counter subdevice
  79         there are a number of boards this driver will support when they are
  80                 fully released, but does not yet since the pci device id numbers
  81                 are not yet available.
  82         support prescaled 100khz clock for slow pacing (not available on 6000 series?)
  83         make ao fifo size adjustable like ai fifo
  84 */
  85
  86 #include "../comedidev.h"
  87 #include <linux/delay.h>
  88 #include <linux/interrupt.h>
  89
  90 #include "comedi_pci.h"
  91 #include "8253.h"
  92 #include "8255.h"
  93 #include "plx9080.h"
  94 #include "comedi_fc.h"
  95
  96 #undef PCIDAS64_DEBUG           /*  disable debugging code */
  97 /* #define PCIDAS64_DEBUG         enable debugging code */
  98
  99 #ifdef PCIDAS64_DEBUG
 100 #define DEBUG_PRINT(format, args...)  printk(format , ## args)
 101 #else
 102 #define DEBUG_PRINT(format, args...)
 103 #endif
 104
 105 #define TIMER_BASE 25           /*  40MHz master clock */
 106 #define PRESCALED_TIMER_BASE    10000   /*  100kHz 'prescaled' clock for slow acquisition, maybe I'll support this someday */
 107 #define DMA_BUFFER_SIZE 0x1000
 108
 109 #define PCI_VENDOR_ID_COMPUTERBOARDS    0x1307
 110
 111 /* maximum value that can be loaded into board's 24-bit counters*/
 112 static const int max_counter_value = 0xffffff;
 113
 114 /* PCI-DAS64xxx base addresses */
 115
 116 /* indices of base address regions */
 117 enum base_address_regions {
 118         PLX9080_BADDRINDEX = 0,
 119         MAIN_BADDRINDEX = 2,
 120         DIO_COUNTER_BADDRINDEX = 3,
 121 };
 122
 123 /* priv(dev)->main_iobase registers */
 124 enum write_only_registers {
 125         INTR_ENABLE_REG = 0x0,  /*  interrupt enable register */
 126         HW_CONFIG_REG = 0x2,    /*  hardware config register */
 127         DAQ_SYNC_REG = 0xc,
 128         DAQ_ATRIG_LOW_4020_REG = 0xc,
 129         ADC_CONTROL0_REG = 0x10,        /*  adc control register 0 */
 130         ADC_CONTROL1_REG = 0x12,        /*  adc control register 1 */
 131         CALIBRATION_REG = 0x14,
 132         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,   /*  lower 16 bits of adc sample interval counter */
 133         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,   /*  upper 8 bits of adc sample interval counter */
 134         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,    /*  lower 16 bits of delay interval counter */
 135         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,    /*  upper 8 bits of delay interval counter */
 136         ADC_COUNT_LOWER_REG = 0x1e,     /*  lower 16 bits of hardware conversion/scan counter */
 137         ADC_COUNT_UPPER_REG = 0x20,     /*  upper 8 bits of hardware conversion/scan counter */
 138         ADC_START_REG = 0x22,   /*  software trigger to start acquisition */
 139         ADC_CONVERT_REG = 0x24, /*  initiates single conversion */
 140         ADC_QUEUE_CLEAR_REG = 0x26,     /*  clears adc queue */
 141         ADC_QUEUE_LOAD_REG = 0x28,      /*  loads adc queue */
 142         ADC_BUFFER_CLEAR_REG = 0x2a,
 143         ADC_QUEUE_HIGH_REG = 0x2c,      /*  high channel for internal queue, use adc_chan_bits() inline above */
 144         DAC_CONTROL0_REG = 0x50,        /*  dac control register 0 */
 145         DAC_CONTROL1_REG = 0x52,        /*  dac control register 0 */
 146         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,   /*  lower 16 bits of dac sample interval counter */
 147         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,   /*  upper 8 bits of dac sample interval counter */
 148         DAC_SELECT_REG = 0x60,
 149         DAC_START_REG = 0x64,
 150         DAC_BUFFER_CLEAR_REG = 0x66,    /*  clear dac buffer */
 151 };
 152 static inline unsigned int dac_convert_reg(unsigned int channel)
 153 {
 154         return 0x70 + (2 * (channel & 0x1));
 155 }
 156
 157 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
 158 {
 159         return 0x70 + (4 * (channel & 0x1));
 160 }
 161
 162 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
 163 {
 164         return 0x72 + (4 * (channel & 0x1));
 165 }
 166
 167 enum read_only_registers {
 168         HW_STATUS_REG = 0x0,    /*  hardware status register, reading this apparently clears pending interrupts as well */
 169         PIPE1_READ_REG = 0x4,
 170         ADC_READ_PNTR_REG = 0x8,
 171         LOWER_XFER_REG = 0x10,
 172         ADC_WRITE_PNTR_REG = 0xc,
 173         PREPOST_REG = 0x14,
 174 };
 175
 176 enum read_write_registers {
 177         I8255_4020_REG = 0x48,  /*  8255 offset, for 4020 only */
 178         ADC_QUEUE_FIFO_REG = 0x100,     /*  external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
 179         ADC_FIFO_REG = 0x200,   /* adc data fifo */
 180         DAC_FIFO_REG = 0x300,   /* dac data fifo, has weird interactions with external channel queue */
 181 };
 182
 183 /* priv(dev)->dio_counter_iobase registers */
 184 enum dio_counter_registers {
 185         DIO_8255_OFFSET = 0x0,
 186         DO_REG = 0x20,
 187         DI_REG = 0x28,
 188         DIO_DIRECTION_60XX_REG = 0x40,
 189         DIO_DATA_60XX_REG = 0x48,
 190 };
 191
 192 /* bit definitions for write-only registers */
 193
 194 enum intr_enable_contents {
 195         ADC_INTR_SRC_MASK = 0x3,        /*  bits that set adc interrupt source */
 196         ADC_INTR_QFULL_BITS = 0x0,      /*  interrupt fifo quater full */
 197         ADC_INTR_EOC_BITS = 0x1,        /*  interrupt end of conversion */
 198         ADC_INTR_EOSCAN_BITS = 0x2,     /*  interrupt end of scan */
 199         ADC_INTR_EOSEQ_BITS = 0x3,      /*  interrupt end of sequence (probably wont use this it's pretty fancy) */
 200         EN_ADC_INTR_SRC_BIT = 0x4,      /*  enable adc interrupt source */
 201         EN_ADC_DONE_INTR_BIT = 0x8,     /*  enable adc acquisition done interrupt */
 202         DAC_INTR_SRC_MASK = 0x30,
 203         DAC_INTR_QEMPTY_BITS = 0x0,
 204         DAC_INTR_HIGH_CHAN_BITS = 0x10,
 205         EN_DAC_INTR_SRC_BIT = 0x40,     /*  enable dac interrupt source */
 206         EN_DAC_DONE_INTR_BIT = 0x80,
 207         EN_ADC_ACTIVE_INTR_BIT = 0x200, /*  enable adc active interrupt */
 208         EN_ADC_STOP_INTR_BIT = 0x400,   /*  enable adc stop trigger interrupt */
 209         EN_DAC_ACTIVE_INTR_BIT = 0x800, /*  enable dac active interrupt */
 210         EN_DAC_UNDERRUN_BIT = 0x4000,   /*  enable dac underrun status bit */
 211         EN_ADC_OVERRUN_BIT = 0x8000,    /*  enable adc overrun status bit */
 212 };
 213
 214 enum hw_config_contents {
 215         MASTER_CLOCK_4020_MASK = 0x3,   /*  bits that specify master clock source for 4020 */
 216         INTERNAL_CLOCK_4020_BITS = 0x1, /*  use 40 MHz internal master clock for 4020 */
 217         BNC_CLOCK_4020_BITS = 0x2,      /*  use BNC input for master clock */
 218         EXT_CLOCK_4020_BITS = 0x3,      /*  use dio input for master clock */
 219         EXT_QUEUE_BIT = 0x200,  /*  use external channel/gain queue (more versatile than internal queue) */
 220         SLOW_DAC_BIT = 0x400,   /*  use 225 nanosec strobe when loading dac instead of 50 nanosec */
 221         HW_CONFIG_DUMMY_BITS = 0x2000,  /*  bit with unknown function yet given as default value in pci-das64 manual */
 222         DMA_CH_SELECT_BIT = 0x8000,     /*  bit selects channels 1/0 for analog input/output, otherwise 0/1 */
 223         FIFO_SIZE_REG = 0x4,    /*  allows adjustment of fifo sizes */
 224         DAC_FIFO_SIZE_MASK = 0xff00,    /*  bits that set dac fifo size */
 225         DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */
 226 };
 227 #define DAC_FIFO_SIZE 0x2000
 228
 229 enum daq_atrig_low_4020_contents {
 230         EXT_AGATE_BNC_BIT = 0x8000,     /*  use trig/ext clk bnc input for analog gate signal */
 231         EXT_STOP_TRIG_BNC_BIT = 0x4000, /*  use trig/ext clk bnc input for external stop trigger signal */
 232         EXT_START_TRIG_BNC_BIT = 0x2000,        /*  use trig/ext clk bnc input for external start trigger signal */
 233 };
 234 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
 235 {
 236         return threshold & 0xfff;
 237 }
 238
 239 enum adc_control0_contents {
 240         ADC_GATE_SRC_MASK = 0x3,        /*  bits that select gate */
 241         ADC_SOFT_GATE_BITS = 0x1,       /*  software gate */
 242         ADC_EXT_GATE_BITS = 0x2,        /*  external digital gate */
 243         ADC_ANALOG_GATE_BITS = 0x3,     /*  analog level gate */
 244         ADC_GATE_LEVEL_BIT = 0x4,       /*  level-sensitive gate (for digital) */
 245         ADC_GATE_POLARITY_BIT = 0x8,    /*  gate active low */
 246         ADC_START_TRIG_SOFT_BITS = 0x10,
 247         ADC_START_TRIG_EXT_BITS = 0x20,
 248         ADC_START_TRIG_ANALOG_BITS = 0x30,
 249         ADC_START_TRIG_MASK = 0x30,
 250         ADC_START_TRIG_FALLING_BIT = 0x40,      /*  trig 1 uses falling edge */
 251         ADC_EXT_CONV_FALLING_BIT = 0x800,       /*  external pacing uses falling edge */
 252         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,     /*  enable hardware scan counter */
 253         ADC_DMA_DISABLE_BIT = 0x4000,   /*  disables dma */
 254         ADC_ENABLE_BIT = 0x8000,        /*  master adc enable */
 255 };
 256
 257 enum adc_control1_contents {
 258         ADC_QUEUE_CONFIG_BIT = 0x1,     /*  should be set for boards with > 16 channels */
 259         CONVERT_POLARITY_BIT = 0x10,
 260         EOC_POLARITY_BIT = 0x20,
 261         ADC_SW_GATE_BIT = 0x40, /*  software gate of adc */
 262         ADC_DITHER_BIT = 0x200, /*  turn on extra noise for dithering */
 263         RETRIGGER_BIT = 0x800,
 264         ADC_LO_CHANNEL_4020_MASK = 0x300,
 265         ADC_HI_CHANNEL_4020_MASK = 0xc00,
 266         TWO_CHANNEL_4020_BITS = 0x1000, /*  two channel mode for 4020 */
 267         FOUR_CHANNEL_4020_BITS = 0x2000,        /*  four channel mode for 4020 */
 268         CHANNEL_MODE_4020_MASK = 0x3000,
 269         ADC_MODE_MASK = 0xf000,
 270 };
 271 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
 272 {
 273         return (channel & 0x3) << 8;
 274 };
 275
 276 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
 277 {
 278         return (channel & 0x3) << 10;
 279 };
 280
 281 static inline uint16_t adc_mode_bits(unsigned int mode)
 282 {
 283         return (mode & 0xf) << 12;
 284 };
 285
 286 enum calibration_contents {
 287         SELECT_8800_BIT = 0x1,
 288         SELECT_8402_64XX_BIT = 0x2,
 289         SELECT_1590_60XX_BIT = 0x2,
 290         CAL_EN_64XX_BIT = 0x40, /*  calibration enable for 64xx series */
 291         SERIAL_DATA_IN_BIT = 0x80,
 292         SERIAL_CLOCK_BIT = 0x100,
 293         CAL_EN_60XX_BIT = 0x200,        /*  calibration enable for 60xx series */
 294         CAL_GAIN_BIT = 0x800,
 295 };
 296 /* calibration sources for 6025 are:
 297  *  0 : ground
 298  *  1 : 10V
 299  *  2 : 5V
 300  *  3 : 0.5V
 301  *  4 : 0.05V
 302  *  5 : ground
 303  *  6 : dac channel 0
 304  *  7 : dac channel 1
 305  */
 306 static inline uint16_t adc_src_bits(unsigned int source)
 307 {
 308         return (source & 0xf) << 3;
 309 };
 310
 311 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
 312 {
 313         return (channel & 0x3) << 8;
 314 };
 315
 316 enum adc_queue_load_contents {
 317         UNIP_BIT = 0x800,       /*  unipolar/bipolar bit */
 318         ADC_SE_DIFF_BIT = 0x1000,       /*  single-ended/ differential bit */
 319         ADC_COMMON_BIT = 0x2000,        /*  non-referenced single-ended (common-mode input) */
 320         QUEUE_EOSEQ_BIT = 0x4000,       /*  queue end of sequence */
 321         QUEUE_EOSCAN_BIT = 0x8000,      /*  queue end of scan */
 322 };
 323 static inline uint16_t adc_chan_bits(unsigned int channel)
 324 {
 325         return channel & 0x3f;
 326 };
 327
 328 enum dac_control0_contents {
 329         DAC_ENABLE_BIT = 0x8000,        /*  dac controller enable bit */
 330         DAC_CYCLIC_STOP_BIT = 0x4000,
 331         DAC_WAVEFORM_MODE_BIT = 0x100,
 332         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
 333         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
 334         WAVEFORM_TRIG_MASK = 0x30,
 335         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
 336         WAVEFORM_TRIG_SOFT_BITS = 0x10,
 337         WAVEFORM_TRIG_EXT_BITS = 0x20,
 338         WAVEFORM_TRIG_ADC1_BITS = 0x30,
 339         WAVEFORM_TRIG_FALLING_BIT = 0x8,
 340         WAVEFORM_GATE_LEVEL_BIT = 0x4,
 341         WAVEFORM_GATE_ENABLE_BIT = 0x2,
 342         WAVEFORM_GATE_SELECT_BIT = 0x1,
 343 };
 344
 345 enum dac_control1_contents {
 346         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
 347         DAC1_EXT_REF_BIT = 0x200,
 348         DAC0_EXT_REF_BIT = 0x100,
 349         DAC_OUTPUT_ENABLE_BIT = 0x80,   /*  dac output enable bit */
 350         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
 351         DAC_SW_GATE_BIT = 0x20,
 352         DAC1_UNIPOLAR_BIT = 0x8,
 353         DAC0_UNIPOLAR_BIT = 0x2,
 354 };
 355
 356 /* bit definitions for read-only registers */
 357 enum hw_status_contents {
 358         DAC_UNDERRUN_BIT = 0x1,
 359         ADC_OVERRUN_BIT = 0x2,
 360         DAC_ACTIVE_BIT = 0x4,
 361         ADC_ACTIVE_BIT = 0x8,
 362         DAC_INTR_PENDING_BIT = 0x10,
 363         ADC_INTR_PENDING_BIT = 0x20,
 364         DAC_DONE_BIT = 0x40,
 365         ADC_DONE_BIT = 0x80,
 366         EXT_INTR_PENDING_BIT = 0x100,
 367         ADC_STOP_BIT = 0x200,
 368 };
 369 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
 370 {
 371         return (hw_status_bits >> 10) & 0x3;
 372 };
 373
 374 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
 375 {
 376         return (prepost_bits >> 6) & 0x3;
 377 }
 378
 379 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
 380 {
 381         return (prepost_bits >> 12) & 0x3;
 382 }
 383
 384 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
 385 {
 386         return (prepost_bits >> 14) & 0x3;
 387 }
 388
 389 /* I2C addresses for 4020 */
 390 enum i2c_addresses {
 391         RANGE_CAL_I2C_ADDR = 0x20,
 392         CALDAC0_I2C_ADDR = 0xc,
 393         CALDAC1_I2C_ADDR = 0xd,
 394 };
 395
 396 enum range_cal_i2c_contents {
 397         ADC_SRC_4020_MASK = 0x70,       /*  bits that set what source the adc converter measures */
 398         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,       /*  make bnc trig/ext clock threshold 0V instead of 2.5V */
 399 };
 400 static inline uint8_t adc_src_4020_bits(unsigned int source)
 401 {
 402         return (source << 4) & ADC_SRC_4020_MASK;
 403 };
 404
 405 static inline uint8_t attenuate_bit(unsigned int channel)
 406 {
 407         /*  attenuate channel (+-5V input range) */
 408         return 1 << (channel & 0x3);
 409 };
 410
 411 /* analog input ranges for 64xx boards */
 412 static const struct comedi_lrange ai_ranges_64xx = {
 413         8,
 414         {
 415          BIP_RANGE(10),
 416          BIP_RANGE(5),
 417          BIP_RANGE(2.5),
 418          BIP_RANGE(1.25),
 419          UNI_RANGE(10),
 420          UNI_RANGE(5),
 421          UNI_RANGE(2.5),
 422          UNI_RANGE(1.25)
 423          }
 424 };
 425
 426 /* analog input ranges for 60xx boards */
 427 static const struct comedi_lrange ai_ranges_60xx = {
 428         4,
 429         {
 430          BIP_RANGE(10),
 431          BIP_RANGE(5),
 432          BIP_RANGE(0.5),
 433          BIP_RANGE(0.05),
 434          }
 435 };
 436
 437 /* analog input ranges for 6030, etc boards */
 438 static const struct comedi_lrange ai_ranges_6030 = {
 439         14,
 440         {
 441          BIP_RANGE(10),
 442          BIP_RANGE(5),
 443          BIP_RANGE(2),
 444          BIP_RANGE(1),
 445          BIP_RANGE(0.5),
 446          BIP_RANGE(0.2),
 447          BIP_RANGE(0.1),
 448          UNI_RANGE(10),
 449          UNI_RANGE(5),
 450          UNI_RANGE(2),
 451          UNI_RANGE(1),
 452          UNI_RANGE(0.5),
 453          UNI_RANGE(0.2),
 454          UNI_RANGE(0.1),
 455          }
 456 };
 457
 458 /* analog input ranges for 6052, etc boards */
 459 static const struct comedi_lrange ai_ranges_6052 = {
 460         15,
 461         {
 462          BIP_RANGE(10),
 463          BIP_RANGE(5),
 464          BIP_RANGE(2.5),
 465          BIP_RANGE(1),
 466          BIP_RANGE(0.5),
 467          BIP_RANGE(0.25),
 468          BIP_RANGE(0.1),
 469          BIP_RANGE(0.05),
 470          UNI_RANGE(10),
 471          UNI_RANGE(5),
 472          UNI_RANGE(2),
 473          UNI_RANGE(1),
 474          UNI_RANGE(0.5),
 475          UNI_RANGE(0.2),
 476          UNI_RANGE(0.1),
 477          }
 478 };
 479
 480 /* analog input ranges for 4020 board */
 481 static const struct comedi_lrange ai_ranges_4020 = {
 482         2,
 483         {
 484          BIP_RANGE(5),
 485          BIP_RANGE(1),
 486          }
 487 };
 488
 489 /* analog output ranges */
 490 static const struct comedi_lrange ao_ranges_64xx = {
 491         4,
 492         {
 493          BIP_RANGE(5),
 494          BIP_RANGE(10),
 495          UNI_RANGE(5),
 496          UNI_RANGE(10),
 497          }
 498 };
 499
 500 static const int ao_range_code_64xx[] = {
 501         0x0,
 502         0x1,
 503         0x2,
 504         0x3,
 505 };
 506
 507 static const struct comedi_lrange ao_ranges_60xx = {
 508         1,
 509         {
 510          BIP_RANGE(10),
 511          }
 512 };
 513
 514 static const int ao_range_code_60xx[] = {
 515         0x0,
 516 };
 517
 518 static const struct comedi_lrange ao_ranges_6030 = {
 519         2,
 520         {
 521          BIP_RANGE(10),
 522          UNI_RANGE(10),
 523          }
 524 };
 525
 526 static const int ao_range_code_6030[] = {
 527         0x0,
 528         0x2,
 529 };
 530
 531 static const struct comedi_lrange ao_ranges_4020 = {
 532         2,
 533         {
 534          BIP_RANGE(5),
 535          BIP_RANGE(10),
 536          }
 537 };
 538
 539 static const int ao_range_code_4020[] = {
 540         0x1,
 541         0x0,
 542 };
 543
 544 enum register_layout {
 545         LAYOUT_60XX,
 546         LAYOUT_64XX,
 547         LAYOUT_4020,
 548 };
 549
 550 struct hw_fifo_info {
 551         unsigned int num_segments;
 552         unsigned int max_segment_length;
 553         unsigned int sample_packing_ratio;
 554         uint16_t fifo_size_reg_mask;
 555 };
 556
 557 struct pcidas64_board {
 558         const char *name;
 559         int device_id;          /*  pci device id */
 560         int ai_se_chans;        /*  number of ai inputs in single-ended mode */
 561         int ai_bits;            /*  analog input resolution */
 562         int ai_speed;           /*  fastest conversion period in ns */
 563         const struct comedi_lrange *ai_range_table;
 564         int ao_nchan;           /*  number of analog out channels */
 565         int ao_bits;            /*  analog output resolution */
 566         int ao_scan_speed;      /*  analog output speed (for a scan, not conversion) */
 567         const struct comedi_lrange *ao_range_table;
 568         const int *ao_range_code;
 569         const struct hw_fifo_info *const ai_fifo;
 570         enum register_layout layout;    /*  different board families have slightly different registers */
 571         unsigned has_8255:1;
 572 };
 573
 574 static const struct hw_fifo_info ai_fifo_4020 = {
 575         .num_segments = 2,
 576         .max_segment_length = 0x8000,
 577         .sample_packing_ratio = 2,
 578         .fifo_size_reg_mask = 0x7f,
 579 };
 580
 581 static const struct hw_fifo_info ai_fifo_64xx = {
 582         .num_segments = 4,
 583         .max_segment_length = 0x800,
 584         .sample_packing_ratio = 1,
 585         .fifo_size_reg_mask = 0x3f,
 586 };
 587
 588 static const struct hw_fifo_info ai_fifo_60xx = {
 589         .num_segments = 4,
 590         .max_segment_length = 0x800,
 591         .sample_packing_ratio = 1,
 592         .fifo_size_reg_mask = 0x7f,
 593 };
 594
 595 /* maximum number of dma transfers we will chain together into a ring
 596  * (and the maximum number of dma buffers we maintain) */
 597 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
 598 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 599 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 600 static inline unsigned int ai_dma_ring_count(struct pcidas64_board *board)
 601 {
 602         if (board->layout == LAYOUT_4020)
 603                 return MAX_AI_DMA_RING_COUNT;
 604         else
 605                 return MIN_AI_DMA_RING_COUNT;
 606 }
 607
 608 static const int bytes_in_sample = 2;
 609
 610 static const struct pcidas64_board pcidas64_boards[] = {
 611         {
 612          .name = "pci-das6402/16",
 613          .device_id = 0x1d,
 614          .ai_se_chans = 64,
 615          .ai_bits = 16,
 616          .ai_speed = 5000,
 617          .ao_nchan = 2,
 618          .ao_bits = 16,
 619          .ao_scan_speed = 10000,
 620          .layout = LAYOUT_64XX,
 621          .ai_range_table = &ai_ranges_64xx,
 622          .ao_range_table = &ao_ranges_64xx,
 623          .ao_range_code = ao_range_code_64xx,
 624          .ai_fifo = &ai_fifo_64xx,
 625          .has_8255 = 1,
 626          },
 627         {
 628          .name = "pci-das6402/12",      /*  XXX check */
 629          .device_id = 0x1e,
 630          .ai_se_chans = 64,
 631          .ai_bits = 12,
 632          .ai_speed = 5000,
 633          .ao_nchan = 2,
 634          .ao_bits = 12,
 635          .ao_scan_speed = 10000,
 636          .layout = LAYOUT_64XX,
 637          .ai_range_table = &ai_ranges_64xx,
 638          .ao_range_table = &ao_ranges_64xx,
 639          .ao_range_code = ao_range_code_64xx,
 640          .ai_fifo = &ai_fifo_64xx,
 641          .has_8255 = 1,
 642          },
 643         {
 644          .name = "pci-das64/m1/16",
 645          .device_id = 0x35,
 646          .ai_se_chans = 64,
 647          .ai_bits = 16,
 648          .ai_speed = 1000,
 649          .ao_nchan = 2,
 650          .ao_bits = 16,
 651          .ao_scan_speed = 10000,
 652          .layout = LAYOUT_64XX,
 653          .ai_range_table = &ai_ranges_64xx,
 654          .ao_range_table = &ao_ranges_64xx,
 655          .ao_range_code = ao_range_code_64xx,
 656          .ai_fifo = &ai_fifo_64xx,
 657          .has_8255 = 1,
 658          },
 659         {
 660          .name = "pci-das64/m2/16",
 661          .device_id = 0x36,
 662          .ai_se_chans = 64,
 663          .ai_bits = 16,
 664          .ai_speed = 500,
 665          .ao_nchan = 2,
 666          .ao_bits = 16,
 667          .ao_scan_speed = 10000,
 668          .layout = LAYOUT_64XX,
 669          .ai_range_table = &ai_ranges_64xx,
 670          .ao_range_table = &ao_ranges_64xx,
 671          .ao_range_code = ao_range_code_64xx,
 672          .ai_fifo = &ai_fifo_64xx,
 673          .has_8255 = 1,
 674          },
 675         {
 676          .name = "pci-das64/m3/16",
 677          .device_id = 0x37,
 678          .ai_se_chans = 64,
 679          .ai_bits = 16,
 680          .ai_speed = 333,
 681          .ao_nchan = 2,
 682          .ao_bits = 16,
 683          .ao_scan_speed = 10000,
 684          .layout = LAYOUT_64XX,
 685          .ai_range_table = &ai_ranges_64xx,
 686          .ao_range_table = &ao_ranges_64xx,
 687          .ao_range_code = ao_range_code_64xx,
 688          .ai_fifo = &ai_fifo_64xx,
 689          .has_8255 = 1,
 690          },
 691         {
 692          .name = "pci-das6013",
 693          .device_id = 0x78,
 694          .ai_se_chans = 16,
 695          .ai_bits = 16,
 696          .ai_speed = 5000,
 697          .ao_nchan = 0,
 698          .ao_bits = 16,
 699          .layout = LAYOUT_60XX,
 700          .ai_range_table = &ai_ranges_60xx,
 701          .ao_range_table = &ao_ranges_60xx,
 702          .ao_range_code = ao_range_code_60xx,
 703          .ai_fifo = &ai_fifo_60xx,
 704          .has_8255 = 0,
 705          },
 706         {
 707          .name = "pci-das6014",
 708          .device_id = 0x79,
 709          .ai_se_chans = 16,
 710          .ai_bits = 16,
 711          .ai_speed = 5000,
 712          .ao_nchan = 2,
 713          .ao_bits = 16,
 714          .ao_scan_speed = 100000,
 715          .layout = LAYOUT_60XX,
 716          .ai_range_table = &ai_ranges_60xx,
 717          .ao_range_table = &ao_ranges_60xx,
 718          .ao_range_code = ao_range_code_60xx,
 719          .ai_fifo = &ai_fifo_60xx,
 720          .has_8255 = 0,
 721          },
 722         {
 723          .name = "pci-das6023",
 724          .device_id = 0x5d,
 725          .ai_se_chans = 16,
 726          .ai_bits = 12,
 727          .ai_speed = 5000,
 728          .ao_nchan = 0,
 729          .ao_scan_speed = 100000,
 730          .layout = LAYOUT_60XX,
 731          .ai_range_table = &ai_ranges_60xx,
 732          .ao_range_table = &ao_ranges_60xx,
 733          .ao_range_code = ao_range_code_60xx,
 734          .ai_fifo = &ai_fifo_60xx,
 735          .has_8255 = 1,
 736          },
 737         {
 738          .name = "pci-das6025",
 739          .device_id = 0x5e,
 740          .ai_se_chans = 16,
 741          .ai_bits = 12,
 742          .ai_speed = 5000,
 743          .ao_nchan = 2,
 744          .ao_bits = 12,
 745          .ao_scan_speed = 100000,
 746          .layout = LAYOUT_60XX,
 747          .ai_range_table = &ai_ranges_60xx,
 748          .ao_range_table = &ao_ranges_60xx,
 749          .ao_range_code = ao_range_code_60xx,
 750          .ai_fifo = &ai_fifo_60xx,
 751          .has_8255 = 1,
 752          },
 753         {
 754          .name = "pci-das6030",
 755          .device_id = 0x5f,
 756          .ai_se_chans = 16,
 757          .ai_bits = 16,
 758          .ai_speed = 10000,
 759          .ao_nchan = 2,
 760          .ao_bits = 16,
 761          .ao_scan_speed = 10000,
 762          .layout = LAYOUT_60XX,
 763          .ai_range_table = &ai_ranges_6030,
 764          .ao_range_table = &ao_ranges_6030,
 765          .ao_range_code = ao_range_code_6030,
 766          .ai_fifo = &ai_fifo_60xx,
 767          .has_8255 = 0,
 768          },
 769         {
 770          .name = "pci-das6031",
 771          .device_id = 0x60,
 772          .ai_se_chans = 64,
 773          .ai_bits = 16,
 774          .ai_speed = 10000,
 775          .ao_nchan = 2,
 776          .ao_bits = 16,
 777          .ao_scan_speed = 10000,
 778          .layout = LAYOUT_60XX,
 779          .ai_range_table = &ai_ranges_6030,
 780          .ao_range_table = &ao_ranges_6030,
 781          .ao_range_code = ao_range_code_6030,
 782          .ai_fifo = &ai_fifo_60xx,
 783          .has_8255 = 0,
 784          },
 785         {
 786          .name = "pci-das6032",
 787          .device_id = 0x61,
 788          .ai_se_chans = 16,
 789          .ai_bits = 16,
 790          .ai_speed = 10000,
 791          .ao_nchan = 0,
 792          .layout = LAYOUT_60XX,
 793          .ai_range_table = &ai_ranges_6030,
 794          .ai_fifo = &ai_fifo_60xx,
 795          .has_8255 = 0,
 796          },
 797         {
 798          .name = "pci-das6033",
 799          .device_id = 0x62,
 800          .ai_se_chans = 64,
 801          .ai_bits = 16,
 802          .ai_speed = 10000,
 803          .ao_nchan = 0,
 804          .layout = LAYOUT_60XX,
 805          .ai_range_table = &ai_ranges_6030,
 806          .ai_fifo = &ai_fifo_60xx,
 807          .has_8255 = 0,
 808          },
 809         {
 810          .name = "pci-das6034",
 811          .device_id = 0x63,
 812          .ai_se_chans = 16,
 813          .ai_bits = 16,
 814          .ai_speed = 5000,
 815          .ao_nchan = 0,
 816          .ao_scan_speed = 0,
 817          .layout = LAYOUT_60XX,
 818          .ai_range_table = &ai_ranges_60xx,
 819          .ai_fifo = &ai_fifo_60xx,
 820          .has_8255 = 0,
 821          },
 822         {
 823          .name = "pci-das6035",
 824          .device_id = 0x64,
 825          .ai_se_chans = 16,
 826          .ai_bits = 16,
 827          .ai_speed = 5000,
 828          .ao_nchan = 2,
 829          .ao_bits = 12,
 830          .ao_scan_speed = 100000,
 831          .layout = LAYOUT_60XX,
 832          .ai_range_table = &ai_ranges_60xx,
 833          .ao_range_table = &ao_ranges_60xx,
 834          .ao_range_code = ao_range_code_60xx,
 835          .ai_fifo = &ai_fifo_60xx,
 836          .has_8255 = 0,
 837          },
 838         {
 839          .name = "pci-das6036",
 840          .device_id = 0x6f,
 841          .ai_se_chans = 16,
 842          .ai_bits = 16,
 843          .ai_speed = 5000,
 844          .ao_nchan = 2,
 845          .ao_bits = 16,
 846          .ao_scan_speed = 100000,
 847          .layout = LAYOUT_60XX,
 848          .ai_range_table = &ai_ranges_60xx,
 849          .ao_range_table = &ao_ranges_60xx,
 850          .ao_range_code = ao_range_code_60xx,
 851          .ai_fifo = &ai_fifo_60xx,
 852          .has_8255 = 0,
 853          },
 854         {
 855          .name = "pci-das6040",
 856          .device_id = 0x65,
 857          .ai_se_chans = 16,
 858          .ai_bits = 12,
 859          .ai_speed = 2000,
 860          .ao_nchan = 2,
 861          .ao_bits = 12,
 862          .ao_scan_speed = 1000,
 863          .layout = LAYOUT_60XX,
 864          .ai_range_table = &ai_ranges_6052,
 865          .ao_range_table = &ao_ranges_6030,
 866          .ao_range_code = ao_range_code_6030,
 867          .ai_fifo = &ai_fifo_60xx,
 868          .has_8255 = 0,
 869          },
 870         {
 871          .name = "pci-das6052",
 872          .device_id = 0x66,
 873          .ai_se_chans = 16,
 874          .ai_bits = 16,
 875          .ai_speed = 3333,
 876          .ao_nchan = 2,
 877          .ao_bits = 16,
 878          .ao_scan_speed = 3333,
 879          .layout = LAYOUT_60XX,
 880          .ai_range_table = &ai_ranges_6052,
 881          .ao_range_table = &ao_ranges_6030,
 882          .ao_range_code = ao_range_code_6030,
 883          .ai_fifo = &ai_fifo_60xx,
 884          .has_8255 = 0,
 885          },
 886         {
 887          .name = "pci-das6070",
 888          .device_id = 0x67,
 889          .ai_se_chans = 16,
 890          .ai_bits = 12,
 891          .ai_speed = 800,
 892          .ao_nchan = 2,
 893          .ao_bits = 12,
 894          .ao_scan_speed = 1000,
 895          .layout = LAYOUT_60XX,
 896          .ai_range_table = &ai_ranges_6052,
 897          .ao_range_table = &ao_ranges_6030,
 898          .ao_range_code = ao_range_code_6030,
 899          .ai_fifo = &ai_fifo_60xx,
 900          .has_8255 = 0,
 901          },
 902         {
 903          .name = "pci-das6071",
 904          .device_id = 0x68,
 905          .ai_se_chans = 64,
 906          .ai_bits = 12,
 907          .ai_speed = 800,
 908          .ao_nchan = 2,
 909          .ao_bits = 12,
 910          .ao_scan_speed = 1000,
 911          .layout = LAYOUT_60XX,
 912          .ai_range_table = &ai_ranges_6052,
 913          .ao_range_table = &ao_ranges_6030,
 914          .ao_range_code = ao_range_code_6030,
 915          .ai_fifo = &ai_fifo_60xx,
 916          .has_8255 = 0,
 917          },
 918         {
 919          .name = "pci-das4020/12",
 920          .device_id = 0x52,
 921          .ai_se_chans = 4,
 922          .ai_bits = 12,
 923          .ai_speed = 50,
 924          .ao_bits = 12,
 925          .ao_nchan = 2,
 926          .ao_scan_speed = 0,    /*  no hardware pacing on ao */
 927          .layout = LAYOUT_4020,
 928          .ai_range_table = &ai_ranges_4020,
 929          .ao_range_table = &ao_ranges_4020,
 930          .ao_range_code = ao_range_code_4020,
 931          .ai_fifo = &ai_fifo_4020,
 932          .has_8255 = 1,
 933          },
 934 #if 0
 935         {
 936          .name = "pci-das6402/16/jr",
 937          .device_id = 0         /*  XXX, */
 938          .ai_se_chans = 64,
 939          .ai_bits = 16,
 940          .ai_speed = 5000,
 941          .ao_nchan = 0,
 942          .ao_scan_speed = 10000,
 943          .layout = LAYOUT_64XX,
 944          .ai_range_table = &ai_ranges_64xx,
 945          .ai_fifo = ai_fifo_64xx,
 946          .has_8255 = 1,
 947          },
 948         {
 949          .name = "pci-das64/m1/16/jr",
 950          .device_id = 0         /*  XXX, */
 951          .ai_se_chans = 64,
 952          .ai_bits = 16,
 953          .ai_speed = 1000,
 954          .ao_nchan = 0,
 955          .ao_scan_speed = 10000,
 956          .layout = LAYOUT_64XX,
 957          .ai_range_table = &ai_ranges_64xx,
 958          .ai_fifo = ai_fifo_64xx,
 959          .has_8255 = 1,
 960          },
 961         {
 962          .name = "pci-das64/m2/16/jr",
 963          .device_id = 0         /*  XXX, */
 964          .ai_se_chans = 64,
 965          .ai_bits = 16,
 966          .ai_speed = 500,
 967          .ao_nchan = 0,
 968          .ao_scan_speed = 10000,
 969          .layout = LAYOUT_64XX,
 970          .ai_range_table = &ai_ranges_64xx,
 971          .ai_fifo = ai_fifo_64xx,
 972          .has_8255 = 1,
 973          },
 974         {
 975          .name = "pci-das64/m3/16/jr",
 976          .device_id = 0         /*  XXX, */
 977          .ai_se_chans = 64,
 978          .ai_bits = 16,
 979          .ai_speed = 333,
 980          .ao_nchan = 0,
 981          .ao_scan_speed = 10000,
 982          .layout = LAYOUT_64XX,
 983          .ai_range_table = &ai_ranges_64xx,
 984          .ai_fifo = ai_fifo_64xx,
 985          .has_8255 = 1,
 986          },
 987         {
 988          .name = "pci-das64/m1/14",
 989          .device_id = 0,        /*  XXX */
 990          .ai_se_chans = 64,
 991          .ai_bits = 14,
 992          .ai_speed = 1000,
 993          .ao_nchan = 2,
 994          .ao_scan_speed = 10000,
 995          .layout = LAYOUT_64XX,
 996          .ai_range_table = &ai_ranges_64xx,
 997          .ai_fifo = ai_fifo_64xx,
 998          .has_8255 = 1,
 999          },
1000         {
1001          .name = "pci-das64/m2/14",
1002          .device_id = 0,        /*  XXX */
1003          .ai_se_chans = 64,
1004          .ai_bits = 14,
1005          .ai_speed = 500,
1006          .ao_nchan = 2,
1007          .ao_scan_speed = 10000,
1008          .layout = LAYOUT_64XX,
1009          .ai_range_table = &ai_ranges_64xx,
1010          .ai_fifo = ai_fifo_64xx,
1011          .has_8255 = 1,
1012          },
1013         {
1014          .name = "pci-das64/m3/14",
1015          .device_id = 0,        /*  XXX */
1016          .ai_se_chans = 64,
1017          .ai_bits = 14,
1018          .ai_speed = 333,
1019          .ao_nchan = 2,
1020          .ao_scan_speed = 10000,
1021          .layout = LAYOUT_64XX,
1022          .ai_range_table = &ai_ranges_64xx,
1023          .ai_fifo = ai_fifo_64xx,
1024          .has_8255 = 1,
1025          },
1026 #endif
1027 };
1028
1029 static inline struct pcidas64_board *board(const struct comedi_device *dev)
1030 {
1031         return (struct pcidas64_board *)dev->board_ptr;
1032 }
1033
1034 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1035                                               int use_differential)
1036 {
1037         if ((board(dev)->layout == LAYOUT_64XX && !use_differential) ||
1038             (board(dev)->layout == LAYOUT_60XX && use_differential))
1039                 return ADC_SE_DIFF_BIT;
1040         else
1041                 return 0;
1042 };
1043
1044 struct ext_clock_info {
1045         unsigned int divisor;   /*  master clock divisor to use for scans with external master clock */
1046         unsigned int chanspec;  /*  chanspec for master clock input when used as scan begin src */
1047 };
1048
1049 /* this structure is for data unique to this hardware driver. */
1050 struct pcidas64_private {
1051
1052         struct pci_dev *hw_dev; /*  pointer to board's pci_dev struct */
1053         /*  base addresses (physical) */
1054         resource_size_t plx9080_phys_iobase;
1055         resource_size_t main_phys_iobase;
1056         resource_size_t dio_counter_phys_iobase;
1057         /*  base addresses (ioremapped) */
1058         void __iomem *plx9080_iobase;
1059         void __iomem *main_iobase;
1060         void __iomem *dio_counter_iobase;
1061         /*  local address (used by dma controller) */
1062         uint32_t local0_iobase;
1063         uint32_t local1_iobase;
1064         volatile unsigned int ai_count; /*  number of analog input samples remaining */
1065         uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];     /*  dma buffers for analog input */
1066         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];   /*  physical addresses of ai dma buffers */
1067         struct plx_dma_desc *ai_dma_desc;       /*  array of ai dma descriptors read by plx9080, allocated to get proper alignment */
1068         dma_addr_t ai_dma_desc_bus_addr;        /*  physical address of ai dma descriptor array */
1069         volatile unsigned int ai_dma_index;     /*  index of the ai dma descriptor/buffer that is currently being used */
1070         uint16_t *ao_buffer[AO_DMA_RING_COUNT]; /*  dma buffers for analog output */
1071         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];       /*  physical addresses of ao dma buffers */
1072         struct plx_dma_desc *ao_dma_desc;
1073         dma_addr_t ao_dma_desc_bus_addr;
1074         volatile unsigned int ao_dma_index;     /*  keeps track of buffer where the next ao sample should go */
1075         volatile unsigned long ao_count;        /*  number of analog output samples remaining */
1076         volatile unsigned int ao_value[2];      /*  remember what the analog outputs are set to, to allow readback */
1077         unsigned int hw_revision;       /*  stc chip hardware revision number */
1078         volatile unsigned int intr_enable_bits; /*  last bits sent to INTR_ENABLE_REG register */
1079         volatile uint16_t adc_control1_bits;    /*  last bits sent to ADC_CONTROL1_REG register */
1080         volatile uint16_t fifo_size_bits;       /*  last bits sent to FIFO_SIZE_REG register */
1081         volatile uint16_t hw_config_bits;       /*  last bits sent to HW_CONFIG_REG register */
1082         volatile uint16_t dac_control1_bits;
1083         volatile uint32_t plx_control_bits;     /*  last bits written to plx9080 control register */
1084         volatile uint32_t plx_intcsr_bits;      /*  last bits written to plx interrupt control and status register */
1085         volatile int calibration_source;        /*  index of calibration source readable through ai ch0 */
1086         volatile uint8_t i2c_cal_range_bits;    /*  bits written to i2c calibration/range register */
1087         volatile unsigned int ext_trig_falling; /*  configure digital triggers to trigger on falling edge */
1088         /*  states of various devices stored to enable read-back */
1089         unsigned int ad8402_state[2];
1090         unsigned int caldac_state[8];
1091         volatile short ai_cmd_running;
1092         unsigned int ai_fifo_segment_length;
1093         struct ext_clock_info ext_clock;
1094         short ao_bounce_buffer[DAC_FIFO_SIZE];
1095 };
1096
1097 /* inline function that makes it easier to
1098  * access the private structure.
1099  */
1100 static inline struct pcidas64_private *priv(struct comedi_device *dev)
1101 {
1102         return dev->private;
1103 }
1104
1105 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1106                     struct comedi_insn *insn, unsigned int *data);
1107 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1108                           struct comedi_insn *insn, unsigned int *data);
1109 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1110                     struct comedi_insn *insn, unsigned int *data);
1111 static int ao_readback_insn(struct comedi_device *dev,
1112                             struct comedi_subdevice *s,
1113                             struct comedi_insn *insn, unsigned int *data);
1114 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
1115 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
1116                       struct comedi_cmd *cmd);
1117 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
1118 static int ao_inttrig(struct comedi_device *dev,
1119                       struct comedi_subdevice *subdev, unsigned int trig_num);
1120 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
1121                       struct comedi_cmd *cmd);
1122 static irqreturn_t handle_interrupt(int irq, void *d);
1123 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
1124 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
1125 static int dio_callback(int dir, int port, int data, unsigned long arg);
1126 static int dio_callback_4020(int dir, int port, int data, unsigned long arg);
1127 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
1128                     struct comedi_insn *insn, unsigned int *data);
1129 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
1130                     struct comedi_insn *insn, unsigned int *data);
1131 static int dio_60xx_config_insn(struct comedi_device *dev,
1132                                 struct comedi_subdevice *s,
1133                                 struct comedi_insn *insn, unsigned int *data);
1134 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
1135                           struct comedi_insn *insn, unsigned int *data);
1136 static int calib_read_insn(struct comedi_device *dev,
1137                            struct comedi_subdevice *s, struct comedi_insn *insn,
1138                            unsigned int *data);
1139 static int calib_write_insn(struct comedi_device *dev,
1140                             struct comedi_subdevice *s,
1141                             struct comedi_insn *insn, unsigned int *data);
1142 static int ad8402_read_insn(struct comedi_device *dev,
1143                             struct comedi_subdevice *s,
1144                             struct comedi_insn *insn, unsigned int *data);
1145 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
1146                          unsigned int value);
1147 static int ad8402_write_insn(struct comedi_device *dev,
1148                              struct comedi_subdevice *s,
1149                              struct comedi_insn *insn, unsigned int *data);
1150 static int eeprom_read_insn(struct comedi_device *dev,
1151                             struct comedi_subdevice *s,
1152                             struct comedi_insn *insn, unsigned int *data);
1153 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd);
1154 static unsigned int get_divisor(unsigned int ns, unsigned int flags);
1155 static void i2c_write(struct comedi_device *dev, unsigned int address,
1156                       const uint8_t * data, unsigned int length);
1157 static void caldac_write(struct comedi_device *dev, unsigned int channel,
1158                          unsigned int value);
1159 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
1160                              uint8_t value);
1161 /* static int dac_1590_write(struct comedi_device *dev, unsigned int dac_a, unsigned int dac_b); */
1162 static int caldac_i2c_write(struct comedi_device *dev,
1163                             unsigned int caldac_channel, unsigned int value);
1164 static void abort_dma(struct comedi_device *dev, unsigned int channel);
1165 static void disable_plx_interrupts(struct comedi_device *dev);
1166 static int set_ai_fifo_size(struct comedi_device *dev,
1167                             unsigned int num_samples);
1168 static unsigned int ai_fifo_size(struct comedi_device *dev);
1169 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1170                                       unsigned int num_entries);
1171 static void disable_ai_pacing(struct comedi_device *dev);
1172 static void disable_ai_interrupts(struct comedi_device *dev);
1173 static void enable_ai_interrupts(struct comedi_device *dev,
1174                                  const struct comedi_cmd *cmd);
1175 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags);
1176 static void load_ao_dma(struct comedi_device *dev,
1177                         const struct comedi_cmd *cmd);
1178
1179 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1180                                        unsigned int range_index)
1181 {
1182         const struct comedi_krange *range =
1183             &board(dev)->ai_range_table->range[range_index];
1184         unsigned int bits = 0;
1185
1186         switch (range->max) {
1187         case 10000000:
1188                 bits = 0x000;
1189                 break;
1190         case 5000000:
1191                 bits = 0x100;
1192                 break;
1193         case 2000000:
1194         case 2500000:
1195                 bits = 0x200;
1196                 break;
1197         case 1000000:
1198         case 1250000:
1199                 bits = 0x300;
1200                 break;
1201         case 500000:
1202                 bits = 0x400;
1203                 break;
1204         case 200000:
1205         case 250000:
1206                 bits = 0x500;
1207                 break;
1208         case 100000:
1209                 bits = 0x600;
1210                 break;
1211         case 50000:
1212                 bits = 0x700;
1213                 break;
1214         default:
1215                 comedi_error(dev, "bug! in ai_range_bits_6xxx");
1216                 break;
1217         }
1218         if (range->min == 0)
1219                 bits += 0x900;
1220         return bits;
1221 }
1222
1223 static unsigned int hw_revision(const struct comedi_device *dev,
1224                                 uint16_t hw_status_bits)
1225 {
1226         if (board(dev)->layout == LAYOUT_4020)
1227                 return (hw_status_bits >> 13) & 0x7;
1228
1229         return (hw_status_bits >> 12) & 0xf;
1230 }
1231
1232 static void set_dac_range_bits(struct comedi_device *dev,
1233                                volatile uint16_t * bits, unsigned int channel,
1234                                unsigned int range)
1235 {
1236         unsigned int code = board(dev)->ao_range_code[range];
1237
1238         if (channel > 1)
1239                 comedi_error(dev, "bug! bad channel?");
1240         if (code & ~0x3)
1241                 comedi_error(dev, "bug! bad range code?");
1242
1243         *bits &= ~(0x3 << (2 * channel));
1244         *bits |= code << (2 * channel);
1245 };
1246
1247 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1248 {
1249         return board->ao_nchan && board->layout != LAYOUT_4020;
1250 }
1251
1252 /* initialize plx9080 chip */
1253 static void init_plx9080(struct comedi_device *dev)
1254 {
1255         uint32_t bits;
1256         void __iomem *plx_iobase = priv(dev)->plx9080_iobase;
1257
1258         priv(dev)->plx_control_bits =
1259             readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG);
1260
1261         /*  plx9080 dump */
1262         DEBUG_PRINT(" plx interrupt status 0x%x\n",
1263                     readl(plx_iobase + PLX_INTRCS_REG));
1264         DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
1265         DEBUG_PRINT(" plx control reg 0x%x\n", priv(dev)->plx_control_bits);
1266         DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n",
1267                     readl(plx_iobase + PLX_MARB_REG));
1268         DEBUG_PRINT(" plx region0 reg 0x%x\n",
1269                     readl(plx_iobase + PLX_REGION0_REG));
1270         DEBUG_PRINT(" plx region1 reg 0x%x\n",
1271                     readl(plx_iobase + PLX_REGION1_REG));
1272
1273         DEBUG_PRINT(" plx revision 0x%x\n",
1274                     readl(plx_iobase + PLX_REVISION_REG));
1275         DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
1276                     readl(plx_iobase + PLX_DMA0_MODE_REG));
1277         DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
1278                     readl(plx_iobase + PLX_DMA1_MODE_REG));
1279         DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
1280                     readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
1281         DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
1282                     readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
1283         DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
1284                     readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
1285         DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
1286                     readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
1287         DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
1288                     readb(plx_iobase + PLX_DMA0_CS_REG));
1289         DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
1290                     readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
1291         DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
1292
1293 #ifdef __BIG_ENDIAN
1294         bits = BIGEND_DMA0 | BIGEND_DMA1;
1295 #else
1296         bits = 0;
1297 #endif
1298         writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
1299
1300         disable_plx_interrupts(dev);
1301
1302         abort_dma(dev, 0);
1303         abort_dma(dev, 1);
1304
1305         /*  configure dma0 mode */
1306         bits = 0;
1307         /*  enable ready input, not sure if this is necessary */
1308         bits |= PLX_DMA_EN_READYIN_BIT;
1309         /*  enable bterm, not sure if this is necessary */
1310         bits |= PLX_EN_BTERM_BIT;
1311         /*  enable dma chaining */
1312         bits |= PLX_EN_CHAIN_BIT;
1313         /*  enable interrupt on dma done (probably don't need this, since chain never finishes) */
1314         bits |= PLX_EN_DMA_DONE_INTR_BIT;
1315         /*  don't increment local address during transfers (we are transferring from a fixed fifo register) */
1316         bits |= PLX_LOCAL_ADDR_CONST_BIT;
1317         /*  route dma interrupt to pci bus */
1318         bits |= PLX_DMA_INTR_PCI_BIT;
1319         /*  enable demand mode */
1320         bits |= PLX_DEMAND_MODE_BIT;
1321         /*  enable local burst mode */
1322         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1323         /*  4020 uses 32 bit dma */
1324         if (board(dev)->layout == LAYOUT_4020) {
1325                 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1326         } else {                /*  localspace0 bus is 16 bits wide */
1327                 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1328         }
1329         writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1330         if (ao_cmd_is_supported(board(dev)))
1331                 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1332
1333         /*  enable interrupts on plx 9080 */
1334         priv(dev)->plx_intcsr_bits |=
1335             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1336             ICS_DMA0_E | ICS_DMA1_E;
1337         writel(priv(dev)->plx_intcsr_bits,
1338                priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1339 }
1340
1341 /* Allocate and initialize the subdevice structures.
1342  */
1343 static int setup_subdevices(struct comedi_device *dev)
1344 {
1345         struct comedi_subdevice *s;
1346         void __iomem *dio_8255_iobase;
1347         int i;
1348
1349         if (alloc_subdevices(dev, 10) < 0)
1350                 return -ENOMEM;
1351
1352         s = dev->subdevices + 0;
1353         /* analog input subdevice */
1354         dev->read_subdev = s;
1355         s->type = COMEDI_SUBD_AI;
1356         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
1357         if (board(dev)->layout == LAYOUT_60XX)
1358                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
1359         else if (board(dev)->layout == LAYOUT_64XX)
1360                 s->subdev_flags |= SDF_DIFF;
1361         /* XXX Number of inputs in differential mode is ignored */
1362         s->n_chan = board(dev)->ai_se_chans;
1363         s->len_chanlist = 0x2000;
1364         s->maxdata = (1 << board(dev)->ai_bits) - 1;
1365         s->range_table = board(dev)->ai_range_table;
1366         s->insn_read = ai_rinsn;
1367         s->insn_config = ai_config_insn;
1368         s->do_cmd = ai_cmd;
1369         s->do_cmdtest = ai_cmdtest;
1370         s->cancel = ai_cancel;
1371         if (board(dev)->layout == LAYOUT_4020) {
1372                 uint8_t data;
1373                 /*  set adc to read from inputs (not internal calibration sources) */
1374                 priv(dev)->i2c_cal_range_bits = adc_src_4020_bits(4);
1375                 /*  set channels to +-5 volt input ranges */
1376                 for (i = 0; i < s->n_chan; i++)
1377                         priv(dev)->i2c_cal_range_bits |= attenuate_bit(i);
1378                 data = priv(dev)->i2c_cal_range_bits;
1379                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
1380         }
1381
1382         /* analog output subdevice */
1383         s = dev->subdevices + 1;
1384         if (board(dev)->ao_nchan) {
1385                 s->type = COMEDI_SUBD_AO;
1386                 s->subdev_flags =
1387                     SDF_READABLE | SDF_WRITABLE | SDF_GROUND | SDF_CMD_WRITE;
1388                 s->n_chan = board(dev)->ao_nchan;
1389                 s->maxdata = (1 << board(dev)->ao_bits) - 1;
1390                 s->range_table = board(dev)->ao_range_table;
1391                 s->insn_read = ao_readback_insn;
1392                 s->insn_write = ao_winsn;
1393                 if (ao_cmd_is_supported(board(dev))) {
1394                         dev->write_subdev = s;
1395                         s->do_cmdtest = ao_cmdtest;
1396                         s->do_cmd = ao_cmd;
1397                         s->len_chanlist = board(dev)->ao_nchan;
1398                         s->cancel = ao_cancel;
1399                 }
1400         } else {
1401                 s->type = COMEDI_SUBD_UNUSED;
1402         }
1403
1404         /*  digital input */
1405         s = dev->subdevices + 2;
1406         if (board(dev)->layout == LAYOUT_64XX) {
1407                 s->type = COMEDI_SUBD_DI;
1408                 s->subdev_flags = SDF_READABLE;
1409                 s->n_chan = 4;
1410                 s->maxdata = 1;
1411                 s->range_table = &range_digital;
1412                 s->insn_bits = di_rbits;
1413         } else
1414                 s->type = COMEDI_SUBD_UNUSED;
1415
1416         /*  digital output */
1417         if (board(dev)->layout == LAYOUT_64XX) {
1418                 s = dev->subdevices + 3;
1419                 s->type = COMEDI_SUBD_DO;
1420                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1421                 s->n_chan = 4;
1422                 s->maxdata = 1;
1423                 s->range_table = &range_digital;
1424                 s->insn_bits = do_wbits;
1425         } else
1426                 s->type = COMEDI_SUBD_UNUSED;
1427
1428         /* 8255 */
1429         s = dev->subdevices + 4;
1430         if (board(dev)->has_8255) {
1431                 if (board(dev)->layout == LAYOUT_4020) {
1432                         dio_8255_iobase =
1433                             priv(dev)->main_iobase + I8255_4020_REG;
1434                         subdev_8255_init(dev, s, dio_callback_4020,
1435                                          (unsigned long)dio_8255_iobase);
1436                 } else {
1437                         dio_8255_iobase =
1438                             priv(dev)->dio_counter_iobase + DIO_8255_OFFSET;
1439                         subdev_8255_init(dev, s, dio_callback,
1440                                          (unsigned long)dio_8255_iobase);
1441                 }
1442         } else
1443                 s->type = COMEDI_SUBD_UNUSED;
1444
1445         /*  8 channel dio for 60xx */
1446         s = dev->subdevices + 5;
1447         if (board(dev)->layout == LAYOUT_60XX) {
1448                 s->type = COMEDI_SUBD_DIO;
1449                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1450                 s->n_chan = 8;
1451                 s->maxdata = 1;
1452                 s->range_table = &range_digital;
1453                 s->insn_config = dio_60xx_config_insn;
1454                 s->insn_bits = dio_60xx_wbits;
1455         } else
1456                 s->type = COMEDI_SUBD_UNUSED;
1457
1458         /*  caldac */
1459         s = dev->subdevices + 6;
1460         s->type = COMEDI_SUBD_CALIB;
1461         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1462         s->n_chan = 8;
1463         if (board(dev)->layout == LAYOUT_4020)
1464                 s->maxdata = 0xfff;
1465         else
1466                 s->maxdata = 0xff;
1467         s->insn_read = calib_read_insn;
1468         s->insn_write = calib_write_insn;
1469         for (i = 0; i < s->n_chan; i++)
1470                 caldac_write(dev, i, s->maxdata / 2);
1471
1472         /*  2 channel ad8402 potentiometer */
1473         s = dev->subdevices + 7;
1474         if (board(dev)->layout == LAYOUT_64XX) {
1475                 s->type = COMEDI_SUBD_CALIB;
1476                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1477                 s->n_chan = 2;
1478                 s->insn_read = ad8402_read_insn;
1479                 s->insn_write = ad8402_write_insn;
1480                 s->maxdata = 0xff;
1481                 for (i = 0; i < s->n_chan; i++)
1482                         ad8402_write(dev, i, s->maxdata / 2);
1483         } else
1484                 s->type = COMEDI_SUBD_UNUSED;
1485
1486         /* serial EEPROM, if present */
1487         s = dev->subdevices + 8;
1488         if (readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
1489                 s->type = COMEDI_SUBD_MEMORY;
1490                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
1491                 s->n_chan = 128;
1492                 s->maxdata = 0xffff;
1493                 s->insn_read = eeprom_read_insn;
1494         } else
1495                 s->type = COMEDI_SUBD_UNUSED;
1496
1497         /*  user counter subd XXX */
1498         s = dev->subdevices + 9;
1499         s->type = COMEDI_SUBD_UNUSED;
1500
1501         return 0;
1502 }
1503
1504 static void disable_plx_interrupts(struct comedi_device *dev)
1505 {
1506         priv(dev)->plx_intcsr_bits = 0;
1507         writel(priv(dev)->plx_intcsr_bits,
1508                priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1509 }
1510
1511 static void init_stc_registers(struct comedi_device *dev)
1512 {
1513         uint16_t bits;
1514         unsigned long flags;
1515
1516         spin_lock_irqsave(&dev->spinlock, flags);
1517
1518         /*  bit should be set for 6025, although docs say boards with <= 16 chans should be cleared XXX */
1519         if (1)
1520                 priv(dev)->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1521         writew(priv(dev)->adc_control1_bits,
1522                priv(dev)->main_iobase + ADC_CONTROL1_REG);
1523
1524         /*  6402/16 manual says this register must be initialized to 0xff? */
1525         writew(0xff, priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1526
1527         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1528         if (board(dev)->layout == LAYOUT_4020)
1529                 bits |= INTERNAL_CLOCK_4020_BITS;
1530         priv(dev)->hw_config_bits |= bits;
1531         writew(priv(dev)->hw_config_bits,
1532                priv(dev)->main_iobase + HW_CONFIG_REG);
1533
1534         writew(0, priv(dev)->main_iobase + DAQ_SYNC_REG);
1535         writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
1536
1537         spin_unlock_irqrestore(&dev->spinlock, flags);
1538
1539         /*  set fifos to maximum size */
1540         priv(dev)->fifo_size_bits |= DAC_FIFO_BITS;
1541         set_ai_fifo_segment_length(dev,
1542                                    board(dev)->ai_fifo->max_segment_length);
1543
1544         priv(dev)->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1545         priv(dev)->intr_enable_bits =   /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1546             EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1547         writew(priv(dev)->intr_enable_bits,
1548                priv(dev)->main_iobase + INTR_ENABLE_REG);
1549
1550         disable_ai_pacing(dev);
1551 };
1552
1553 static int alloc_and_init_dma_members(struct comedi_device *dev)
1554 {
1555         int i;
1556
1557         /*  alocate pci dma buffers */
1558         for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1559                 priv(dev)->ai_buffer[i] =
1560                     pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE,
1561                                          &priv(dev)->ai_buffer_bus_addr[i]);
1562                 if (priv(dev)->ai_buffer[i] == NULL)
1563                         return -ENOMEM;
1564
1565         }
1566         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1567                 if (ao_cmd_is_supported(board(dev))) {
1568                         priv(dev)->ao_buffer[i] =
1569                             pci_alloc_consistent(priv(dev)->hw_dev,
1570                                                  DMA_BUFFER_SIZE,
1571                                                  &priv(dev)->
1572                                                  ao_buffer_bus_addr[i]);
1573                         if (priv(dev)->ao_buffer[i] == NULL)
1574                                 return -ENOMEM;
1575
1576                 }
1577         }
1578         /*  allocate dma descriptors */
1579         priv(dev)->ai_dma_desc =
1580             pci_alloc_consistent(priv(dev)->hw_dev,
1581                                  sizeof(struct plx_dma_desc) *
1582                                  ai_dma_ring_count(board(dev)),
1583                                  &priv(dev)->ai_dma_desc_bus_addr);
1584         if (priv(dev)->ai_dma_desc == NULL)
1585                 return -ENOMEM;
1586
1587         DEBUG_PRINT("ai dma descriptors start at bus addr 0x%x\n",
1588                     priv(dev)->ai_dma_desc_bus_addr);
1589         if (ao_cmd_is_supported(board(dev))) {
1590                 priv(dev)->ao_dma_desc =
1591                     pci_alloc_consistent(priv(dev)->hw_dev,
1592                                          sizeof(struct plx_dma_desc) *
1593                                          AO_DMA_RING_COUNT,
1594                                          &priv(dev)->ao_dma_desc_bus_addr);
1595                 if (priv(dev)->ao_dma_desc == NULL)
1596                         return -ENOMEM;
1597
1598                 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%x\n",
1599                             priv(dev)->ao_dma_desc_bus_addr);
1600         }
1601         /*  initialize dma descriptors */
1602         for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1603                 priv(dev)->ai_dma_desc[i].pci_start_addr =
1604                     cpu_to_le32(priv(dev)->ai_buffer_bus_addr[i]);
1605                 if (board(dev)->layout == LAYOUT_4020)
1606                         priv(dev)->ai_dma_desc[i].local_start_addr =
1607                             cpu_to_le32(priv(dev)->local1_iobase +
1608                                         ADC_FIFO_REG);
1609                 else
1610                         priv(dev)->ai_dma_desc[i].local_start_addr =
1611                             cpu_to_le32(priv(dev)->local0_iobase +
1612                                         ADC_FIFO_REG);
1613                 priv(dev)->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1614                 priv(dev)->ai_dma_desc[i].next =
1615                     cpu_to_le32((priv(dev)->ai_dma_desc_bus_addr + ((i +
1616                                                                      1) %
1617                                                                     ai_dma_ring_count
1618                                                                     (board
1619                                                                      (dev))) *
1620                                  sizeof(priv(dev)->ai_dma_desc[0])) |
1621                                 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1622                                 PLX_XFER_LOCAL_TO_PCI);
1623         }
1624         if (ao_cmd_is_supported(board(dev))) {
1625                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1626                         priv(dev)->ao_dma_desc[i].pci_start_addr =
1627                             cpu_to_le32(priv(dev)->ao_buffer_bus_addr[i]);
1628                         priv(dev)->ao_dma_desc[i].local_start_addr =
1629                             cpu_to_le32(priv(dev)->local0_iobase +
1630                                         DAC_FIFO_REG);
1631                         priv(dev)->ao_dma_desc[i].transfer_size =
1632                             cpu_to_le32(0);
1633                         priv(dev)->ao_dma_desc[i].next =
1634                             cpu_to_le32((priv(dev)->ao_dma_desc_bus_addr +
1635                                          ((i + 1) % (AO_DMA_RING_COUNT)) *
1636                                          sizeof(priv(dev)->ao_dma_desc[0])) |
1637                                         PLX_DESC_IN_PCI_BIT |
1638                                         PLX_INTR_TERM_COUNT);
1639                 }
1640         }
1641         return 0;
1642 }
1643
1644 static inline void warn_external_queue(struct comedi_device *dev)
1645 {
1646         comedi_error(dev,
1647                      "AO command and AI external channel queue cannot be used simultaneously.");
1648         comedi_error(dev,
1649                      "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1650 }
1651
1652 /*
1653  * Attach is called by the Comedi core to configure the driver
1654  * for a particular board.
1655  */
1656 static int attach(struct comedi_device *dev, struct comedi_devconfig *it)
1657 {
1658         struct pci_dev *pcidev = NULL;
1659         int index;
1660         uint32_t local_range, local_decode;
1661         int retval;
1662
1663 /*
1664  * Allocate the private structure area.
1665  */
1666         if (alloc_private(dev, sizeof(struct pcidas64_private)) < 0)
1667                 return -ENOMEM;
1668
1669 /*
1670  * Probe the device to determine what device in the series it is.
1671  */
1672
1673         for_each_pci_dev(pcidev) {
1674                 /*  is it not a computer boards card? */
1675                 if (pcidev->vendor != PCI_VENDOR_ID_COMPUTERBOARDS)
1676                         continue;
1677                 /*  loop through cards supported by this driver */
1678                 for (index = 0; index < ARRAY_SIZE(pcidas64_boards); index++) {
1679                         if (pcidas64_boards[index].device_id != pcidev->device)
1680                                 continue;
1681                         /*  was a particular bus/slot requested? */
1682                         if (it->options[0] || it->options[1]) {
1683                                 /*  are we on the wrong bus/slot? */
1684                                 if (pcidev->bus->number != it->options[0] ||
1685                                     PCI_SLOT(pcidev->devfn) != it->options[1]) {
1686                                         continue;
1687                                 }
1688                         }
1689                         priv(dev)->hw_dev = pcidev;
1690                         dev->board_ptr = pcidas64_boards + index;
1691                         break;
1692                 }
1693                 if (dev->board_ptr)
1694                         break;
1695         }
1696
1697         if (dev->board_ptr == NULL) {
1698                 printk
1699                     ("No supported ComputerBoards/MeasurementComputing card found\n");
1700                 return -EIO;
1701         }
1702
1703         dev_dbg(dev->hw_dev, "Found %s on bus %i, slot %i\n", board(dev)->name,
1704                 pcidev->bus->number, PCI_SLOT(pcidev->devfn));
1705
1706         if (comedi_pci_enable(pcidev, dev->driver->driver_name)) {
1707                 dev_warn(dev->hw_dev, "failed to enable PCI device and request regions\n");
1708                 return -EIO;
1709         }
1710         pci_set_master(pcidev);
1711
1712         /* Initialize dev->board_name */
1713         dev->board_name = board(dev)->name;
1714
1715         priv(dev)->plx9080_phys_iobase =
1716             pci_resource_start(pcidev, PLX9080_BADDRINDEX);
1717         priv(dev)->main_phys_iobase =
1718             pci_resource_start(pcidev, MAIN_BADDRINDEX);
1719         priv(dev)->dio_counter_phys_iobase =
1720             pci_resource_start(pcidev, DIO_COUNTER_BADDRINDEX);
1721
1722         /*  remap, won't work with 2.0 kernels but who cares */
1723         priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
1724                                             pci_resource_len(pcidev,
1725                                                              PLX9080_BADDRINDEX));
1726         priv(dev)->main_iobase =
1727             ioremap(priv(dev)->main_phys_iobase,
1728                     pci_resource_len(pcidev, MAIN_BADDRINDEX));
1729         priv(dev)->dio_counter_iobase =
1730             ioremap(priv(dev)->dio_counter_phys_iobase,
1731                     pci_resource_len(pcidev, DIO_COUNTER_BADDRINDEX));
1732
1733         if (!priv(dev)->plx9080_iobase || !priv(dev)->main_iobase
1734             || !priv(dev)->dio_counter_iobase) {
1735                 dev_warn(dev->hw_dev, "failed to remap io memory\n");
1736                 return -ENOMEM;
1737         }
1738
1739         DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase);
1740         DEBUG_PRINT(" main remapped to 0x%p\n", priv(dev)->main_iobase);
1741         DEBUG_PRINT(" diocounter remapped to 0x%p\n",
1742                     priv(dev)->dio_counter_iobase);
1743
1744         /*  figure out what local addresses are */
1745         local_range =
1746             readl(priv(dev)->plx9080_iobase + PLX_LAS0RNG_REG) & LRNG_MEM_MASK;
1747         local_decode =
1748             readl(priv(dev)->plx9080_iobase +
1749                   PLX_LAS0MAP_REG) & local_range & LMAP_MEM_MASK;
1750         priv(dev)->local0_iobase =
1751             ((uint32_t) priv(dev)->main_phys_iobase & ~local_range) |
1752             local_decode;
1753         local_range =
1754             readl(priv(dev)->plx9080_iobase + PLX_LAS1RNG_REG) & LRNG_MEM_MASK;
1755         local_decode =
1756             readl(priv(dev)->plx9080_iobase +
1757                   PLX_LAS1MAP_REG) & local_range & LMAP_MEM_MASK;
1758         priv(dev)->local1_iobase =
1759             ((uint32_t) priv(dev)->dio_counter_phys_iobase & ~local_range) |
1760             local_decode;
1761
1762         DEBUG_PRINT(" local 0 io addr 0x%x\n", priv(dev)->local0_iobase);
1763         DEBUG_PRINT(" local 1 io addr 0x%x\n", priv(dev)->local1_iobase);
1764
1765         retval = alloc_and_init_dma_members(dev);
1766         if (retval < 0)
1767                 return retval;
1768
1769         priv(dev)->hw_revision =
1770             hw_revision(dev, readw(priv(dev)->main_iobase + HW_STATUS_REG));
1771         dev_dbg(dev->hw_dev, "stc hardware revision %i\n",
1772                 priv(dev)->hw_revision);
1773         init_plx9080(dev);
1774         init_stc_registers(dev);
1775         /*  get irq */
1776         if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
1777                         "cb_pcidas64", dev)) {
1778                 dev_dbg(dev->hw_dev, "unable to allocate irq %u\n",
1779                         pcidev->irq);
1780                 return -EINVAL;
1781         }
1782         dev->irq = pcidev->irq;
1783         dev_dbg(dev->hw_dev, "irq %u\n", dev->irq);
1784
1785         retval = setup_subdevices(dev);
1786         if (retval < 0)
1787                 return retval;
1788
1789
1790         return 0;
1791 }
1792
1793 static void detach(struct comedi_device *dev)
1794 {
1795         unsigned int i;
1796
1797         if (dev->irq)
1798                 free_irq(dev->irq, dev);
1799         if (priv(dev)) {
1800                 if (priv(dev)->hw_dev) {
1801                         if (priv(dev)->plx9080_iobase) {
1802                                 disable_plx_interrupts(dev);
1803                                 iounmap(priv(dev)->plx9080_iobase);
1804                         }
1805                         if (priv(dev)->main_iobase)
1806                                 iounmap(priv(dev)->main_iobase);
1807                         if (priv(dev)->dio_counter_iobase)
1808                                 iounmap(priv(dev)->dio_counter_iobase);
1809                         /*  free pci dma buffers */
1810                         for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1811                                 if (priv(dev)->ai_buffer[i])
1812                                         pci_free_consistent(priv(dev)->hw_dev,
1813                                                             DMA_BUFFER_SIZE,
1814                                                             priv(dev)->
1815                                                             ai_buffer[i],
1816                                                             priv
1817                                                             (dev)->ai_buffer_bus_addr
1818                                                             [i]);
1819                         }
1820                         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1821                                 if (priv(dev)->ao_buffer[i])
1822                                         pci_free_consistent(priv(dev)->hw_dev,
1823                                                             DMA_BUFFER_SIZE,
1824                                                             priv(dev)->
1825                                                             ao_buffer[i],
1826                                                             priv
1827                                                             (dev)->ao_buffer_bus_addr
1828                                                             [i]);
1829                         }
1830                         /*  free dma descriptors */
1831                         if (priv(dev)->ai_dma_desc)
1832                                 pci_free_consistent(priv(dev)->hw_dev,
1833                                                     sizeof(struct plx_dma_desc)
1834                                                     *
1835                                                     ai_dma_ring_count(board
1836                                                                       (dev)),
1837                                                     priv(dev)->ai_dma_desc,
1838                                                     priv(dev)->
1839                                                     ai_dma_desc_bus_addr);
1840                         if (priv(dev)->ao_dma_desc)
1841                                 pci_free_consistent(priv(dev)->hw_dev,
1842                                                     sizeof(struct plx_dma_desc)
1843                                                     * AO_DMA_RING_COUNT,
1844                                                     priv(dev)->ao_dma_desc,
1845                                                     priv(dev)->
1846                                                     ao_dma_desc_bus_addr);
1847                         if (priv(dev)->main_phys_iobase)
1848                                 comedi_pci_disable(priv(dev)->hw_dev);
1849
1850                         pci_dev_put(priv(dev)->hw_dev);
1851                 }
1852         }
1853         if (dev->subdevices)
1854                 subdev_8255_cleanup(dev, dev->subdevices + 4);
1855 }
1856
1857 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1858                     struct comedi_insn *insn, unsigned int *data)
1859 {
1860         unsigned int bits = 0, n, i;
1861         unsigned int channel, range, aref;
1862         unsigned long flags;
1863         static const int timeout = 100;
1864
1865         DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec);
1866         channel = CR_CHAN(insn->chanspec);
1867         range = CR_RANGE(insn->chanspec);
1868         aref = CR_AREF(insn->chanspec);
1869
1870         /*  disable card's analog input interrupt sources and pacing */
1871         /*  4020 generates dac done interrupts even though they are disabled */
1872         disable_ai_pacing(dev);
1873
1874         spin_lock_irqsave(&dev->spinlock, flags);
1875         if (insn->chanspec & CR_ALT_FILTER)
1876                 priv(dev)->adc_control1_bits |= ADC_DITHER_BIT;
1877         else
1878                 priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT;
1879         writew(priv(dev)->adc_control1_bits,
1880                priv(dev)->main_iobase + ADC_CONTROL1_REG);
1881         spin_unlock_irqrestore(&dev->spinlock, flags);
1882
1883         if (board(dev)->layout != LAYOUT_4020) {
1884                 /*  use internal queue */
1885                 priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT;
1886                 writew(priv(dev)->hw_config_bits,
1887                        priv(dev)->main_iobase + HW_CONFIG_REG);
1888
1889                 /*  ALT_SOURCE is internal calibration reference */
1890                 if (insn->chanspec & CR_ALT_SOURCE) {
1891                         unsigned int cal_en_bit;
1892
1893                         DEBUG_PRINT("reading calibration source\n");
1894                         if (board(dev)->layout == LAYOUT_60XX)
1895                                 cal_en_bit = CAL_EN_60XX_BIT;
1896                         else
1897                                 cal_en_bit = CAL_EN_64XX_BIT;
1898                         /*  select internal reference source to connect to channel 0 */
1899                         writew(cal_en_bit |
1900                                adc_src_bits(priv(dev)->calibration_source),
1901                                priv(dev)->main_iobase + CALIBRATION_REG);
1902                 } else {
1903                         /*  make sure internal calibration source is turned off */
1904                         writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
1905                 }
1906                 /*  load internal queue */
1907                 bits = 0;
1908                 /*  set gain */
1909                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1910                 /*  set single-ended / differential */
1911                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1912                 if (aref == AREF_COMMON)
1913                         bits |= ADC_COMMON_BIT;
1914                 bits |= adc_chan_bits(channel);
1915                 /*  set stop channel */
1916                 writew(adc_chan_bits(channel),
1917                        priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG);
1918                 /*  set start channel, and rest of settings */
1919                 writew(bits, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
1920         } else {
1921                 uint8_t old_cal_range_bits = priv(dev)->i2c_cal_range_bits;
1922
1923                 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1924                 if (insn->chanspec & CR_ALT_SOURCE) {
1925                         DEBUG_PRINT("reading calibration source\n");
1926                         priv(dev)->i2c_cal_range_bits |=
1927                             adc_src_4020_bits(priv(dev)->calibration_source);
1928                 } else {        /* select BNC inputs */
1929                         priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4);
1930                 }
1931                 /*  select range */
1932                 if (range == 0)
1933                         priv(dev)->i2c_cal_range_bits |= attenuate_bit(channel);
1934                 else
1935                         priv(dev)->i2c_cal_range_bits &=
1936                             ~attenuate_bit(channel);
1937                 /*  update calibration/range i2c register only if necessary, as it is very slow */
1938                 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) {
1939                         uint8_t i2c_data = priv(dev)->i2c_cal_range_bits;
1940                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1941                                   sizeof(i2c_data));
1942                 }
1943
1944                 /* 4020 manual asks that sample interval register to be set before writing to convert register.
1945                  * Using somewhat arbitrary setting of 4 master clock ticks = 0.1 usec */
1946                 writew(0,
1947                        priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1948                 writew(2,
1949                        priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1950         }
1951
1952         for (n = 0; n < insn->n; n++) {
1953
1954                 /*  clear adc buffer (inside loop for 4020 sake) */
1955                 writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG);
1956
1957                 /* trigger conversion, bits sent only matter for 4020 */
1958                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1959                        priv(dev)->main_iobase + ADC_CONVERT_REG);
1960
1961                 /*  wait for data */
1962                 for (i = 0; i < timeout; i++) {
1963                         bits = readw(priv(dev)->main_iobase + HW_STATUS_REG);
1964                         DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits));
1965                         if (board(dev)->layout == LAYOUT_4020) {
1966                                 if (readw(priv(dev)->main_iobase +
1967                                           ADC_WRITE_PNTR_REG))
1968                                         break;
1969                         } else {
1970                                 if (pipe_full_bits(bits))
1971                                         break;
1972                         }
1973                         udelay(1);
1974                 }
1975                 DEBUG_PRINT(" looped %i times waiting for data\n", i);
1976                 if (i == timeout) {
1977                         comedi_error(dev, " analog input read insn timed out");
1978                         printk(" status 0x%x\n", bits);
1979                         return -ETIME;
1980                 }
1981                 if (board(dev)->layout == LAYOUT_4020)
1982                         data[n] =
1983                             readl(priv(dev)->dio_counter_iobase +
1984                                   ADC_FIFO_REG) & 0xffff;
1985                 else
1986                         data[n] =
1987                             readw(priv(dev)->main_iobase + PIPE1_READ_REG);
1988         }
1989
1990         return n;
1991 }
1992
1993 static int ai_config_calibration_source(struct comedi_device *dev,
1994                                         unsigned int *data)
1995 {
1996         unsigned int source = data[1];
1997         int num_calibration_sources;
1998
1999         if (board(dev)->layout == LAYOUT_60XX)
2000                 num_calibration_sources = 16;
2001         else
2002                 num_calibration_sources = 8;
2003         if (source >= num_calibration_sources) {
2004                 dev_dbg(dev->hw_dev, "invalid calibration source: %i\n",
2005                         source);
2006                 return -EINVAL;
2007         }
2008
2009         DEBUG_PRINT("setting calibration source to %i\n", source);
2010         priv(dev)->calibration_source = source;
2011
2012         return 2;
2013 }
2014
2015 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
2016 {
2017         int fifo_size;
2018         const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
2019         unsigned int block_size, requested_block_size;
2020         int retval;
2021
2022         requested_block_size = data[1];
2023
2024         if (requested_block_size) {
2025                 fifo_size =
2026                     requested_block_size * fifo->num_segments / bytes_in_sample;
2027
2028                 retval = set_ai_fifo_size(dev, fifo_size);
2029                 if (retval < 0)
2030                         return retval;
2031
2032         }
2033
2034         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
2035
2036         data[1] = block_size;
2037
2038         return 2;
2039 }
2040
2041 static int ai_config_master_clock_4020(struct comedi_device *dev,
2042                                        unsigned int *data)
2043 {
2044         unsigned int divisor = data[4];
2045         int retval = 0;
2046
2047         if (divisor < 2) {
2048                 divisor = 2;
2049                 retval = -EAGAIN;
2050         }
2051
2052         switch (data[1]) {
2053         case COMEDI_EV_SCAN_BEGIN:
2054                 priv(dev)->ext_clock.divisor = divisor;
2055                 priv(dev)->ext_clock.chanspec = data[2];
2056                 break;
2057         default:
2058                 return -EINVAL;
2059                 break;
2060         }
2061
2062         data[4] = divisor;
2063
2064         return retval ? retval : 5;
2065 }
2066
2067 /* XXX could add support for 60xx series */
2068 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
2069 {
2070
2071         switch (board(dev)->layout) {
2072         case LAYOUT_4020:
2073                 return ai_config_master_clock_4020(dev, data);
2074                 break;
2075         default:
2076                 return -EINVAL;
2077                 break;
2078         }
2079
2080         return -EINVAL;
2081 }
2082
2083 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
2084                           struct comedi_insn *insn, unsigned int *data)
2085 {
2086         int id = data[0];
2087
2088         switch (id) {
2089         case INSN_CONFIG_ALT_SOURCE:
2090                 return ai_config_calibration_source(dev, data);
2091                 break;
2092         case INSN_CONFIG_BLOCK_SIZE:
2093                 return ai_config_block_size(dev, data);
2094                 break;
2095         case INSN_CONFIG_TIMER_1:
2096                 return ai_config_master_clock(dev, data);
2097                 break;
2098         default:
2099                 return -EINVAL;
2100                 break;
2101         }
2102         return -EINVAL;
2103 }
2104
2105 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2106                       struct comedi_cmd *cmd)
2107 {
2108         int err = 0;
2109         int tmp;
2110         unsigned int tmp_arg, tmp_arg2;
2111         int i;
2112         int aref;
2113         unsigned int triggers;
2114
2115         /* step 1: make sure trigger sources are trivially valid */
2116
2117         tmp = cmd->start_src;
2118         cmd->start_src &= TRIG_NOW | TRIG_EXT;
2119         if (!cmd->start_src || tmp != cmd->start_src)
2120                 err++;
2121
2122         tmp = cmd->scan_begin_src;
2123         triggers = TRIG_TIMER;
2124         if (board(dev)->layout == LAYOUT_4020)
2125                 triggers |= TRIG_OTHER;
2126         else
2127                 triggers |= TRIG_FOLLOW;
2128         cmd->scan_begin_src &= triggers;
2129         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
2130                 err++;
2131
2132         tmp = cmd->convert_src;
2133         triggers = TRIG_TIMER;
2134         if (board(dev)->layout == LAYOUT_4020)
2135                 triggers |= TRIG_NOW;
2136         else
2137                 triggers |= TRIG_EXT;
2138         cmd->convert_src &= triggers;
2139         if (!cmd->convert_src || tmp != cmd->convert_src)
2140                 err++;
2141
2142         tmp = cmd->scan_end_src;
2143         cmd->scan_end_src &= TRIG_COUNT;
2144         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
2145                 err++;
2146
2147         tmp = cmd->stop_src;
2148         cmd->stop_src &= TRIG_COUNT | TRIG_EXT | TRIG_NONE;
2149         if (!cmd->stop_src || tmp != cmd->stop_src)
2150                 err++;
2151
2152         if (err)
2153                 return 1;
2154
2155         /* step 2: make sure trigger sources are unique and mutually compatible */
2156
2157         /*  uniqueness check */
2158         if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
2159                 err++;
2160         if (cmd->scan_begin_src != TRIG_TIMER &&
2161             cmd->scan_begin_src != TRIG_OTHER &&
2162             cmd->scan_begin_src != TRIG_FOLLOW)
2163                 err++;
2164         if (cmd->convert_src != TRIG_TIMER &&
2165             cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
2166                 err++;
2167         if (cmd->stop_src != TRIG_COUNT &&
2168             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2169                 err++;
2170
2171         /*  compatibility check */
2172         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2173                 err++;
2174         if (cmd->stop_src != TRIG_COUNT &&
2175             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2176                 err++;
2177
2178         if (err)
2179                 return 2;
2180
2181         /* step 3: make sure arguments are trivially compatible */
2182
2183         if (cmd->convert_src == TRIG_TIMER) {
2184                 if (board(dev)->layout == LAYOUT_4020) {
2185                         if (cmd->convert_arg) {
2186                                 cmd->convert_arg = 0;
2187                                 err++;
2188                         }
2189                 } else {
2190                         if (cmd->convert_arg < board(dev)->ai_speed) {
2191                                 cmd->convert_arg = board(dev)->ai_speed;
2192                                 err++;
2193                         }
2194                         if (cmd->scan_begin_src == TRIG_TIMER) {
2195                                 /*  if scans are timed faster than conversion rate allows */
2196                                 if (cmd->convert_arg * cmd->chanlist_len >
2197                                     cmd->scan_begin_arg) {
2198                                         cmd->scan_begin_arg =
2199                                             cmd->convert_arg *
2200                                             cmd->chanlist_len;
2201                                         err++;
2202                                 }
2203                         }
2204                 }
2205         }
2206
2207         if (!cmd->chanlist_len) {
2208                 cmd->chanlist_len = 1;
2209                 err++;
2210         }
2211         if (cmd->scan_end_arg != cmd->chanlist_len) {
2212                 cmd->scan_end_arg = cmd->chanlist_len;
2213                 err++;
2214         }
2215
2216         switch (cmd->stop_src) {
2217         case TRIG_EXT:
2218                 break;
2219         case TRIG_COUNT:
2220                 if (!cmd->stop_arg) {
2221                         cmd->stop_arg = 1;
2222                         err++;
2223                 }
2224                 break;
2225         case TRIG_NONE:
2226                 if (cmd->stop_arg != 0) {
2227                         cmd->stop_arg = 0;
2228                         err++;
2229                 }
2230                 break;
2231         default:
2232                 break;
2233         }
2234
2235         if (err)
2236                 return 3;
2237
2238         /* step 4: fix up any arguments */
2239
2240         if (cmd->convert_src == TRIG_TIMER) {
2241                 tmp_arg = cmd->convert_arg;
2242                 tmp_arg2 = cmd->scan_begin_arg;
2243                 check_adc_timing(dev, cmd);
2244                 if (tmp_arg != cmd->convert_arg)
2245                         err++;
2246                 if (tmp_arg2 != cmd->scan_begin_arg)
2247                         err++;
2248         }
2249
2250         if (err)
2251                 return 4;
2252
2253         /*  make sure user is doesn't change analog reference mid chanlist */
2254         if (cmd->chanlist) {
2255                 aref = CR_AREF(cmd->chanlist[0]);
2256                 for (i = 1; i < cmd->chanlist_len; i++) {
2257                         if (aref != CR_AREF(cmd->chanlist[i])) {
2258                                 comedi_error(dev,
2259                                              "all elements in chanlist must use the same analog reference");
2260                                 err++;
2261                                 break;
2262                         }
2263                 }
2264                 /*  check 4020 chanlist */
2265                 if (board(dev)->layout == LAYOUT_4020) {
2266                         unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
2267                         for (i = 1; i < cmd->chanlist_len; i++) {
2268                                 if (CR_CHAN(cmd->chanlist[i]) !=
2269                                     first_channel + i) {
2270                                         comedi_error(dev,
2271                                                      "chanlist must use consecutive channels");
2272                                         err++;
2273                                         break;
2274                                 }
2275                         }
2276                         if (cmd->chanlist_len == 3) {
2277                                 comedi_error(dev,
2278                                              "chanlist cannot be 3 channels long, use 1, 2, or 4 channels");
2279                                 err++;
2280                         }
2281                 }
2282         }
2283
2284         if (err)
2285                 return 5;
2286
2287         return 0;
2288 }
2289
2290 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2291 {
2292 /* disable for now until I work out a race */
2293         return 0;
2294
2295         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2296                 return 1;
2297         else
2298                 return 0;
2299 }
2300
2301 static void setup_sample_counters(struct comedi_device *dev,
2302                                   struct comedi_cmd *cmd)
2303 {
2304         if (cmd->stop_src == TRIG_COUNT) {
2305                 /*  set software count */
2306                 priv(dev)->ai_count = cmd->stop_arg * cmd->chanlist_len;
2307         }
2308         /*  load hardware conversion counter */
2309         if (use_hw_sample_counter(cmd)) {
2310                 writew(cmd->stop_arg & 0xffff,
2311                        priv(dev)->main_iobase + ADC_COUNT_LOWER_REG);
2312                 writew((cmd->stop_arg >> 16) & 0xff,
2313                        priv(dev)->main_iobase + ADC_COUNT_UPPER_REG);
2314         } else {
2315                 writew(1, priv(dev)->main_iobase + ADC_COUNT_LOWER_REG);
2316         }
2317 }
2318
2319 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2320 {
2321         unsigned int num_samples;
2322
2323         num_samples =
2324             priv(dev)->ai_fifo_segment_length *
2325             board(dev)->ai_fifo->sample_packing_ratio;
2326         if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2327                 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2328
2329         return num_samples;
2330 }
2331
2332 static void disable_ai_pacing(struct comedi_device *dev)
2333 {
2334         unsigned long flags;
2335
2336         disable_ai_interrupts(dev);
2337
2338         spin_lock_irqsave(&dev->spinlock, flags);
2339         priv(dev)->adc_control1_bits &= ~ADC_SW_GATE_BIT;
2340         writew(priv(dev)->adc_control1_bits,
2341                priv(dev)->main_iobase + ADC_CONTROL1_REG);
2342         spin_unlock_irqrestore(&dev->spinlock, flags);
2343
2344         /* disable pacing, triggering, etc */
2345         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
2346                priv(dev)->main_iobase + ADC_CONTROL0_REG);
2347 }
2348
2349 static void disable_ai_interrupts(struct comedi_device *dev)
2350 {
2351         unsigned long flags;
2352
2353         spin_lock_irqsave(&dev->spinlock, flags);
2354         priv(dev)->intr_enable_bits &=
2355             ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
2356             ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
2357             ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
2358         writew(priv(dev)->intr_enable_bits,
2359                priv(dev)->main_iobase + INTR_ENABLE_REG);
2360         spin_unlock_irqrestore(&dev->spinlock, flags);
2361
2362         DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits);
2363 }
2364
2365 static void enable_ai_interrupts(struct comedi_device *dev,
2366                                  const struct comedi_cmd *cmd)
2367 {
2368         uint32_t bits;
2369         unsigned long flags;
2370
2371         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
2372             EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
2373         /*  Use pio transfer and interrupt on end of conversion if TRIG_WAKE_EOS flag is set. */
2374         if (cmd->flags & TRIG_WAKE_EOS) {
2375                 /*  4020 doesn't support pio transfers except for fifo dregs */
2376                 if (board(dev)->layout != LAYOUT_4020)
2377                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
2378         }
2379         spin_lock_irqsave(&dev->spinlock, flags);
2380         priv(dev)->intr_enable_bits |= bits;
2381         writew(priv(dev)->intr_enable_bits,
2382                priv(dev)->main_iobase + INTR_ENABLE_REG);
2383         DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits);
2384         spin_unlock_irqrestore(&dev->spinlock, flags);
2385 }
2386
2387 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2388                                         const struct comedi_cmd *cmd)
2389 {
2390         /*  supposed to load counter with desired divisor minus 3 */
2391         return cmd->convert_arg / TIMER_BASE - 3;
2392 }
2393
2394 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2395                                      struct comedi_cmd *cmd)
2396 {
2397         uint32_t count;
2398         /*  figure out how long we need to delay at end of scan */
2399         switch (cmd->scan_begin_src) {
2400         case TRIG_TIMER:
2401                 count = (cmd->scan_begin_arg -
2402                          (cmd->convert_arg * (cmd->chanlist_len - 1)))
2403                     / TIMER_BASE;
2404                 break;
2405         case TRIG_FOLLOW:
2406                 count = cmd->convert_arg / TIMER_BASE;
2407                 break;
2408         default:
2409                 return 0;
2410                 break;
2411         }
2412         return count - 3;
2413 }
2414
2415 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2416                                         struct comedi_cmd *cmd)
2417 {
2418         unsigned int divisor;
2419
2420         switch (cmd->scan_begin_src) {
2421         case TRIG_TIMER:
2422                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2423                 break;
2424         case TRIG_OTHER:
2425                 divisor = priv(dev)->ext_clock.divisor;
2426                 break;
2427         default:                /*  should never happen */
2428                 comedi_error(dev, "bug! failed to set ai pacing!");
2429                 divisor = 1000;
2430                 break;
2431         }
2432
2433         /*  supposed to load counter with desired divisor minus 2 for 4020 */
2434         return divisor - 2;
2435 }
2436
2437 static void select_master_clock_4020(struct comedi_device *dev,
2438                                      const struct comedi_cmd *cmd)
2439 {
2440         /*  select internal/external master clock */
2441         priv(dev)->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2442         if (cmd->scan_begin_src == TRIG_OTHER) {
2443                 int chanspec = priv(dev)->ext_clock.chanspec;
2444
2445                 if (CR_CHAN(chanspec))
2446                         priv(dev)->hw_config_bits |= BNC_CLOCK_4020_BITS;
2447                 else
2448                         priv(dev)->hw_config_bits |= EXT_CLOCK_4020_BITS;
2449         } else {
2450                 priv(dev)->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2451         }
2452         writew(priv(dev)->hw_config_bits,
2453                priv(dev)->main_iobase + HW_CONFIG_REG);
2454 }
2455
2456 static void select_master_clock(struct comedi_device *dev,
2457                                 const struct comedi_cmd *cmd)
2458 {
2459         switch (board(dev)->layout) {
2460         case LAYOUT_4020:
2461                 select_master_clock_4020(dev, cmd);
2462                 break;
2463         default:
2464                 break;
2465         }
2466 }
2467
2468 static inline void dma_start_sync(struct comedi_device *dev,
2469                                   unsigned int channel)
2470 {
2471         unsigned long flags;
2472
2473         /*  spinlock for plx dma control/status reg */
2474         spin_lock_irqsave(&dev->spinlock, flags);
2475         if (channel)
2476                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2477                        PLX_CLEAR_DMA_INTR_BIT,
2478                        priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2479         else
2480                 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2481                        PLX_CLEAR_DMA_INTR_BIT,
2482                        priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
2483         spin_unlock_irqrestore(&dev->spinlock, flags);
2484 }
2485
2486 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2487 {
2488         uint32_t convert_counter = 0, scan_counter = 0;
2489
2490         check_adc_timing(dev, cmd);
2491
2492         select_master_clock(dev, cmd);
2493
2494         if (board(dev)->layout == LAYOUT_4020) {
2495                 convert_counter = ai_convert_counter_4020(dev, cmd);
2496         } else {
2497                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2498                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2499         }
2500
2501         /*  load lower 16 bits of convert interval */
2502         writew(convert_counter & 0xffff,
2503                priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2504         DEBUG_PRINT("convert counter 0x%x\n", convert_counter);
2505         /*  load upper 8 bits of convert interval */
2506         writew((convert_counter >> 16) & 0xff,
2507                priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2508         /*  load lower 16 bits of scan delay */
2509         writew(scan_counter & 0xffff,
2510                priv(dev)->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2511         /*  load upper 8 bits of scan delay */
2512         writew((scan_counter >> 16) & 0xff,
2513                priv(dev)->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2514         DEBUG_PRINT("scan counter 0x%x\n", scan_counter);
2515 }
2516
2517 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2518 {
2519         int i;
2520         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2521                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2522                     CR_CHAN(cmd->chanlist[i]) + 1)
2523                         return 0;
2524                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2525                     CR_RANGE(cmd->chanlist[i]))
2526                         return 0;
2527                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2528                         return 0;
2529         }
2530         return 1;
2531 }
2532
2533 static int setup_channel_queue(struct comedi_device *dev,
2534                                const struct comedi_cmd *cmd)
2535 {
2536         unsigned short bits;
2537         int i;
2538
2539         if (board(dev)->layout != LAYOUT_4020) {
2540                 if (use_internal_queue_6xxx(cmd)) {
2541                         priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT;
2542                         writew(priv(dev)->hw_config_bits,
2543                                priv(dev)->main_iobase + HW_CONFIG_REG);
2544                         bits = 0;
2545                         /*  set channel */
2546                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2547                         /*  set gain */
2548                         bits |= ai_range_bits_6xxx(dev,
2549                                                    CR_RANGE(cmd->chanlist[0]));
2550                         /*  set single-ended / differential */
2551                         bits |= se_diff_bit_6xxx(dev,
2552                                                  CR_AREF(cmd->chanlist[0]) ==
2553                                                  AREF_DIFF);
2554                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2555                                 bits |= ADC_COMMON_BIT;
2556                         /*  set stop channel */
2557                         writew(adc_chan_bits
2558                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2559                                priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG);
2560                         /*  set start channel, and rest of settings */
2561                         writew(bits,
2562                                priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2563                 } else {
2564                         /*  use external queue */
2565                         if (dev->write_subdev && dev->write_subdev->busy) {
2566                                 warn_external_queue(dev);
2567                                 return -EBUSY;
2568                         }
2569                         priv(dev)->hw_config_bits |= EXT_QUEUE_BIT;
2570                         writew(priv(dev)->hw_config_bits,
2571                                priv(dev)->main_iobase + HW_CONFIG_REG);
2572                         /*  clear DAC buffer to prevent weird interactions */
2573                         writew(0,
2574                                priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG);
2575                         /*  clear queue pointer */
2576                         writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
2577                         /*  load external queue */
2578                         for (i = 0; i < cmd->chanlist_len; i++) {
2579                                 bits = 0;
2580                                 /*  set channel */
2581                                 bits |=
2582                                     adc_chan_bits(CR_CHAN(cmd->chanlist[i]));
2583                                 /*  set gain */
2584                                 bits |= ai_range_bits_6xxx(dev,
2585                                                            CR_RANGE(cmd->
2586                                                                     chanlist
2587                                                                     [i]));
2588                                 /*  set single-ended / differential */
2589                                 bits |= se_diff_bit_6xxx(dev,
2590                                                          CR_AREF(cmd->
2591                                                                  chanlist[i]) ==
2592                                                          AREF_DIFF);
2593                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2594                                         bits |= ADC_COMMON_BIT;
2595                                 /*  mark end of queue */
2596                                 if (i == cmd->chanlist_len - 1)
2597                                         bits |= QUEUE_EOSCAN_BIT |
2598                                             QUEUE_EOSEQ_BIT;
2599                                 writew(bits,
2600                                        priv(dev)->main_iobase +
2601                                        ADC_QUEUE_FIFO_REG);
2602                                 DEBUG_PRINT
2603                                     ("wrote 0x%x to external channel queue\n",
2604                                      bits);
2605                         }
2606                         /* doing a queue clear is not specified in board docs,
2607                          * but required for reliable operation */
2608                         writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
2609                         /*  prime queue holding register */
2610                         writew(0, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2611                 }
2612         } else {
2613                 unsigned short old_cal_range_bits =
2614                     priv(dev)->i2c_cal_range_bits;
2615
2616                 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2617                 /* select BNC inputs */
2618                 priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4);
2619                 /*  select ranges */
2620                 for (i = 0; i < cmd->chanlist_len; i++) {
2621                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2622                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2623
2624                         if (range == 0)
2625                                 priv(dev)->i2c_cal_range_bits |=
2626                                     attenuate_bit(channel);
2627                         else
2628                                 priv(dev)->i2c_cal_range_bits &=
2629                                     ~attenuate_bit(channel);
2630                 }
2631                 /*  update calibration/range i2c register only if necessary, as it is very slow */
2632                 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) {
2633                         uint8_t i2c_data = priv(dev)->i2c_cal_range_bits;
2634                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2635                                   sizeof(i2c_data));
2636                 }
2637         }
2638         return 0;
2639 }
2640
2641 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2642                                              unsigned int dma_channel,
2643                                              unsigned int descriptor_bits)
2644 {
2645         /* The transfer size, pci address, and local address registers
2646          * are supposedly unused during chained dma,
2647          * but I have found that left over values from last operation
2648          * occasionally cause problems with transfer of first dma
2649          * block.  Initializing them to zero seems to fix the problem. */
2650         if (dma_channel) {
2651                 writel(0,
2652                        priv(dev)->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2653                 writel(0, priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2654                 writel(0,
2655                        priv(dev)->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2656                 writel(descriptor_bits,
2657                        priv(dev)->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2658         } else {
2659                 writel(0,
2660                        priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2661                 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2662                 writel(0,
2663                        priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2664                 writel(descriptor_bits,
2665                        priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2666         }
2667 }
2668
2669 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2670 {
2671         struct comedi_async *async = s->async;
2672         struct comedi_cmd *cmd = &async->cmd;
2673         uint32_t bits;
2674         unsigned int i;
2675         unsigned long flags;
2676         int retval;
2677
2678         disable_ai_pacing(dev);
2679         abort_dma(dev, 1);
2680
2681         retval = setup_channel_queue(dev, cmd);
2682         if (retval < 0)
2683                 return retval;
2684
2685         /*  make sure internal calibration source is turned off */
2686         writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
2687
2688         set_ai_pacing(dev, cmd);
2689
2690         setup_sample_counters(dev, cmd);
2691
2692         enable_ai_interrupts(dev, cmd);
2693
2694         spin_lock_irqsave(&dev->spinlock, flags);
2695         /* set mode, allow conversions through software gate */
2696         priv(dev)->adc_control1_bits |= ADC_SW_GATE_BIT;
2697         priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT;
2698         if (board(dev)->layout != LAYOUT_4020) {
2699                 priv(dev)->adc_control1_bits &= ~ADC_MODE_MASK;
2700                 if (cmd->convert_src == TRIG_EXT)
2701                         priv(dev)->adc_control1_bits |= adc_mode_bits(13);      /*  good old mode 13 */
2702                 else
2703                         priv(dev)->adc_control1_bits |= adc_mode_bits(8);       /*  mode 8.  What else could you need? */
2704         } else {
2705                 priv(dev)->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2706                 if (cmd->chanlist_len == 4)
2707                         priv(dev)->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2708                 else if (cmd->chanlist_len == 2)
2709                         priv(dev)->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2710                 priv(dev)->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2711                 priv(dev)->adc_control1_bits |=
2712                     adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2713                 priv(dev)->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2714                 priv(dev)->adc_control1_bits |=
2715                     adc_hi_chan_4020_bits(CR_CHAN
2716                                           (cmd->
2717                                            chanlist[cmd->chanlist_len - 1]));
2718         }
2719         writew(priv(dev)->adc_control1_bits,
2720                priv(dev)->main_iobase + ADC_CONTROL1_REG);
2721         DEBUG_PRINT("control1 bits 0x%x\n", priv(dev)->adc_control1_bits);
2722         spin_unlock_irqrestore(&dev->spinlock, flags);
2723
2724         /*  clear adc buffer */
2725         writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG);
2726
2727         if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2728             board(dev)->layout == LAYOUT_4020) {
2729                 priv(dev)->ai_dma_index = 0;
2730
2731                 /*  set dma transfer size */
2732                 for (i = 0; i < ai_dma_ring_count(board(dev)); i++)
2733                         priv(dev)->ai_dma_desc[i].transfer_size =
2734                             cpu_to_le32(dma_transfer_size(dev) *
2735                                         sizeof(uint16_t));
2736
2737                 /*  give location of first dma descriptor */
2738                 load_first_dma_descriptor(dev, 1,
2739                                           priv(dev)->ai_dma_desc_bus_addr |
2740                                           PLX_DESC_IN_PCI_BIT |
2741                                           PLX_INTR_TERM_COUNT |
2742                                           PLX_XFER_LOCAL_TO_PCI);
2743
2744                 dma_start_sync(dev, 1);
2745         }
2746
2747         if (board(dev)->layout == LAYOUT_4020) {
2748                 /* set source for external triggers */
2749                 bits = 0;
2750                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2751                         bits |= EXT_START_TRIG_BNC_BIT;
2752                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2753                         bits |= EXT_STOP_TRIG_BNC_BIT;
2754                 writew(bits, priv(dev)->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2755         }
2756
2757         spin_lock_irqsave(&dev->spinlock, flags);
2758
2759         /* enable pacing, triggering, etc */
2760         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2761         if (cmd->flags & TRIG_WAKE_EOS)
2762                 bits |= ADC_DMA_DISABLE_BIT;
2763         /*  set start trigger */
2764         if (cmd->start_src == TRIG_EXT) {
2765                 bits |= ADC_START_TRIG_EXT_BITS;
2766                 if (cmd->start_arg & CR_INVERT)
2767                         bits |= ADC_START_TRIG_FALLING_BIT;
2768         } else if (cmd->start_src == TRIG_NOW)
2769                 bits |= ADC_START_TRIG_SOFT_BITS;
2770         if (use_hw_sample_counter(cmd))
2771                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2772         writew(bits, priv(dev)->main_iobase + ADC_CONTROL0_REG);
2773         DEBUG_PRINT("control0 bits 0x%x\n", bits);
2774
2775         priv(dev)->ai_cmd_running = 1;
2776
2777         spin_unlock_irqrestore(&dev->spinlock, flags);
2778
2779         /*  start acquisition */
2780         if (cmd->start_src == TRIG_NOW) {
2781                 writew(0, priv(dev)->main_iobase + ADC_START_REG);
2782                 DEBUG_PRINT("soft trig\n");
2783         }
2784
2785         return 0;
2786 }
2787
2788 /* read num_samples from 16 bit wide ai fifo */
2789 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2790 {
2791         struct comedi_subdevice *s = dev->read_subdev;
2792         struct comedi_async *async = s->async;
2793         struct comedi_cmd *cmd = &async->cmd;
2794         unsigned int i;
2795         uint16_t prepost_bits;
2796         int read_segment, read_index, write_segment, write_index;
2797         int num_samples;
2798
2799         do {
2800                 /*  get least significant 15 bits */
2801                 read_index =
2802                     readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2803                 write_index =
2804                     readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2805                 /* Get most significant bits (grey code).  Different boards use different code
2806                  * so use a scheme that doesn't depend on encoding.  This read must
2807                  * occur after reading least significant 15 bits to avoid race
2808                  * with fifo switching to next segment. */
2809                 prepost_bits = readw(priv(dev)->main_iobase + PREPOST_REG);
2810
2811                 /* if read and write pointers are not on the same fifo segment, read to the
2812                  * end of the read segment */
2813                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2814                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2815
2816                 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n",
2817                             read_segment, write_segment, read_index,
2818                             write_index);
2819
2820                 if (read_segment != write_segment)
2821                         num_samples =
2822                             priv(dev)->ai_fifo_segment_length - read_index;
2823                 else
2824                         num_samples = write_index - read_index;
2825
2826                 if (cmd->stop_src == TRIG_COUNT) {
2827                         if (priv(dev)->ai_count == 0)
2828                                 break;
2829                         if (num_samples > priv(dev)->ai_count)
2830                                 num_samples = priv(dev)->ai_count;
2831
2832                         priv(dev)->ai_count -= num_samples;
2833                 }
2834
2835                 if (num_samples < 0) {
2836                         dev_err(dev->hw_dev, "cb_pcidas64: bug! num_samples < 0\n");
2837                         break;
2838                 }
2839
2840                 DEBUG_PRINT(" read %i samples from fifo\n", num_samples);
2841
2842                 for (i = 0; i < num_samples; i++) {
2843                         cfc_write_to_buffer(s,
2844                                             readw(priv(dev)->main_iobase +
2845                                                   ADC_FIFO_REG));
2846                 }
2847
2848         } while (read_segment != write_segment);
2849 }
2850
2851 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of pointers.
2852  * The pci-4020 hardware only supports
2853  * dma transfers (it only supports the use of pio for draining the last remaining
2854  * points from the fifo when a data acquisition operation has completed).
2855  */
2856 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2857 {
2858         struct comedi_subdevice *s = dev->read_subdev;
2859         struct comedi_async *async = s->async;
2860         struct comedi_cmd *cmd = &async->cmd;
2861         unsigned int i;
2862         unsigned int max_transfer = 100000;
2863         uint32_t fifo_data;
2864         int write_code =
2865             readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2866         int read_code =
2867             readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2868
2869         if (cmd->stop_src == TRIG_COUNT) {
2870                 if (max_transfer > priv(dev)->ai_count)
2871                         max_transfer = priv(dev)->ai_count;
2872
2873         }
2874         for (i = 0; read_code != write_code && i < max_transfer;) {
2875                 fifo_data = readl(priv(dev)->dio_counter_iobase + ADC_FIFO_REG);
2876                 cfc_write_to_buffer(s, fifo_data & 0xffff);
2877                 i++;
2878                 if (i < max_transfer) {
2879                         cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2880                         i++;
2881                 }
2882                 read_code =
2883                     readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2884         }
2885         priv(dev)->ai_count -= i;
2886 }
2887
2888 /* empty fifo */
2889 static void pio_drain_ai_fifo(struct comedi_device *dev)
2890 {
2891         if (board(dev)->layout == LAYOUT_4020)
2892                 pio_drain_ai_fifo_32(dev);
2893         else
2894                 pio_drain_ai_fifo_16(dev);
2895 }
2896
2897 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2898 {
2899         struct comedi_async *async = dev->read_subdev->async;
2900         uint32_t next_transfer_addr;
2901         int j;
2902         int num_samples = 0;
2903         void __iomem *pci_addr_reg;
2904
2905         if (channel)
2906                 pci_addr_reg =
2907                     priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2908         else
2909                 pci_addr_reg =
2910                     priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2911
2912         /*  loop until we have read all the full buffers */
2913         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2914              (next_transfer_addr <
2915               priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index]
2916               || next_transfer_addr >=
2917               priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index] +
2918               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board(dev)); j++) {
2919                 /*  transfer data from dma buffer to comedi buffer */
2920                 num_samples = dma_transfer_size(dev);
2921                 if (async->cmd.stop_src == TRIG_COUNT) {
2922                         if (num_samples > priv(dev)->ai_count)
2923                                 num_samples = priv(dev)->ai_count;
2924                         priv(dev)->ai_count -= num_samples;
2925                 }
2926                 cfc_write_array_to_buffer(dev->read_subdev,
2927                                           priv(dev)->ai_buffer[priv(dev)->
2928                                                                ai_dma_index],
2929                                           num_samples * sizeof(uint16_t));
2930                 priv(dev)->ai_dma_index =
2931                     (priv(dev)->ai_dma_index +
2932                      1) % ai_dma_ring_count(board(dev));
2933
2934                 DEBUG_PRINT("next buffer addr 0x%lx\n",
2935                             (unsigned long)priv(dev)->
2936                             ai_buffer_bus_addr[priv(dev)->ai_dma_index]);
2937                 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
2938         }
2939         /* XXX check for dma ring buffer overrun (use end-of-chain bit to mark last
2940          * unused buffer) */
2941 }
2942
2943 static void handle_ai_interrupt(struct comedi_device *dev,
2944                                 unsigned short status,
2945                                 unsigned int plx_status)
2946 {
2947         struct comedi_subdevice *s = dev->read_subdev;
2948         struct comedi_async *async = s->async;
2949         struct comedi_cmd *cmd = &async->cmd;
2950         uint8_t dma1_status;
2951         unsigned long flags;
2952
2953         /*  check for fifo overrun */
2954         if (status & ADC_OVERRUN_BIT) {
2955                 comedi_error(dev, "fifo overrun");
2956                 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2957         }
2958         /*  spin lock makes sure no one else changes plx dma control reg */
2959         spin_lock_irqsave(&dev->spinlock, flags);
2960         dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2961         if (plx_status & ICS_DMA1_A) {  /*  dma chan 1 interrupt */
2962                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2963                        priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2964                 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
2965
2966                 if (dma1_status & PLX_DMA_EN_BIT)
2967                         drain_dma_buffers(dev, 1);
2968
2969                 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
2970         }
2971         spin_unlock_irqrestore(&dev->spinlock, flags);
2972
2973         if (status & ADC_DONE_BIT)
2974                 DEBUG_PRINT("adc done interrupt\n");
2975
2976         /*  drain fifo with pio */
2977         if ((status & ADC_DONE_BIT) ||
2978             ((cmd->flags & TRIG_WAKE_EOS) &&
2979              (status & ADC_INTR_PENDING_BIT) &&
2980              (board(dev)->layout != LAYOUT_4020))) {
2981                 DEBUG_PRINT("pio fifo drain\n");
2982                 spin_lock_irqsave(&dev->spinlock, flags);
2983                 if (priv(dev)->ai_cmd_running) {
2984                         spin_unlock_irqrestore(&dev->spinlock, flags);
2985                         pio_drain_ai_fifo(dev);
2986                 } else
2987                         spin_unlock_irqrestore(&dev->spinlock, flags);
2988         }
2989         /*  if we are have all the data, then quit */
2990         if ((cmd->stop_src == TRIG_COUNT && (int)priv(dev)->ai_count <= 0) ||
2991             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
2992                 async->events |= COMEDI_CB_EOA;
2993         }
2994
2995         cfc_handle_events(dev, s);
2996 }
2997
2998 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2999 {
3000         unsigned int buffer_index;
3001
3002         if (priv(dev)->ao_dma_index == 0)
3003                 buffer_index = AO_DMA_RING_COUNT - 1;
3004         else
3005                 buffer_index = priv(dev)->ao_dma_index - 1;
3006         return buffer_index;
3007 }
3008
3009 static int last_ao_dma_load_completed(struct comedi_device *dev)
3010 {
3011         unsigned int buffer_index;
3012         unsigned int transfer_address;
3013         unsigned short dma_status;
3014
3015         buffer_index = prev_ao_dma_index(dev);
3016         dma_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3017         if ((dma_status & PLX_DMA_DONE_BIT) == 0)
3018                 return 0;
3019
3020         transfer_address =
3021             readl(priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
3022         if (transfer_address != priv(dev)->ao_buffer_bus_addr[buffer_index])
3023                 return 0;
3024
3025         return 1;
3026 }
3027
3028 static int ao_stopped_by_error(struct comedi_device *dev,
3029                                const struct comedi_cmd *cmd)
3030 {
3031         if (cmd->stop_src == TRIG_NONE)
3032                 return 1;
3033         if (cmd->stop_src == TRIG_COUNT) {
3034                 if (priv(dev)->ao_count)
3035                         return 1;
3036                 if (last_ao_dma_load_completed(dev) == 0)
3037                         return 1;
3038         }
3039         return 0;
3040 }
3041
3042 static inline int ao_dma_needs_restart(struct comedi_device *dev,
3043                                        unsigned short dma_status)
3044 {
3045         if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
3046             (dma_status & PLX_DMA_EN_BIT) == 0)
3047                 return 0;
3048         if (last_ao_dma_load_completed(dev))
3049                 return 0;
3050
3051         return 1;
3052 }
3053
3054 static void restart_ao_dma(struct comedi_device *dev)
3055 {
3056         unsigned int dma_desc_bits;
3057
3058         dma_desc_bits =
3059             readl(priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
3060         dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
3061         DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits);
3062         load_first_dma_descriptor(dev, 0, dma_desc_bits);
3063
3064         dma_start_sync(dev, 0);
3065 }
3066
3067 static void handle_ao_interrupt(struct comedi_device *dev,
3068                                 unsigned short status, unsigned int plx_status)
3069 {
3070         struct comedi_subdevice *s = dev->write_subdev;
3071         struct comedi_async *async;
3072         struct comedi_cmd *cmd;
3073         uint8_t dma0_status;
3074         unsigned long flags;
3075
3076         /* board might not support ao, in which case write_subdev is NULL */
3077         if (s == NULL)
3078                 return;
3079         async = s->async;
3080         cmd = &async->cmd;
3081
3082         /*  spin lock makes sure no one else changes plx dma control reg */
3083         spin_lock_irqsave(&dev->spinlock, flags);
3084         dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3085         if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
3086                 if ((dma0_status & PLX_DMA_EN_BIT)
3087                     && !(dma0_status & PLX_DMA_DONE_BIT))
3088                         writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3089                                priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3090                 else
3091                         writeb(PLX_CLEAR_DMA_INTR_BIT,
3092                                priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3093                 spin_unlock_irqrestore(&dev->spinlock, flags);
3094                 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
3095                 if (dma0_status & PLX_DMA_EN_BIT) {
3096                         load_ao_dma(dev, cmd);
3097                         /* try to recover from dma end-of-chain event */
3098                         if (ao_dma_needs_restart(dev, dma0_status))
3099                                 restart_ao_dma(dev);
3100                 }
3101                 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
3102         } else
3103                 spin_unlock_irqrestore(&dev->spinlock, flags);
3104
3105         if ((status & DAC_DONE_BIT)) {
3106                 async->events |= COMEDI_CB_EOA;
3107                 if (ao_stopped_by_error(dev, cmd))
3108                         async->events |= COMEDI_CB_ERROR;
3109                 DEBUG_PRINT("plx dma0 desc reg 0x%x\n",
3110                             readl(priv(dev)->plx9080_iobase +
3111                                   PLX_DMA0_DESCRIPTOR_REG));
3112                 DEBUG_PRINT("plx dma0 address reg 0x%x\n",
3113                             readl(priv(dev)->plx9080_iobase +
3114                                   PLX_DMA0_PCI_ADDRESS_REG));
3115         }
3116         cfc_handle_events(dev, s);
3117 }
3118
3119 static irqreturn_t handle_interrupt(int irq, void *d)
3120 {
3121         struct comedi_device *dev = d;
3122         unsigned short status;
3123         uint32_t plx_status;
3124         uint32_t plx_bits;
3125
3126         plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
3127         status = readw(priv(dev)->main_iobase + HW_STATUS_REG);
3128
3129         DEBUG_PRINT("cb_pcidas64: hw status 0x%x ", status);
3130         DEBUG_PRINT("plx status 0x%x\n", plx_status);
3131
3132         /* an interrupt before all the postconfig stuff gets done could
3133          * cause a NULL dereference if we continue through the
3134          * interrupt handler */
3135         if (dev->attached == 0) {
3136                 DEBUG_PRINT("cb_pcidas64: premature interrupt, ignoring",
3137                             status);
3138                 return IRQ_HANDLED;
3139         }
3140         handle_ai_interrupt(dev, status, plx_status);
3141         handle_ao_interrupt(dev, status, plx_status);
3142
3143         /*  clear possible plx9080 interrupt sources */
3144         if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
3145                 plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
3146                 writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
3147                 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
3148         }
3149
3150         DEBUG_PRINT("exiting handler\n");
3151
3152         return IRQ_HANDLED;
3153 }
3154
3155 static void abort_dma(struct comedi_device *dev, unsigned int channel)
3156 {
3157         unsigned long flags;
3158
3159         /*  spinlock for plx dma control/status reg */
3160         spin_lock_irqsave(&dev->spinlock, flags);
3161
3162         plx9080_abort_dma(priv(dev)->plx9080_iobase, channel);
3163
3164         spin_unlock_irqrestore(&dev->spinlock, flags);
3165 }
3166
3167 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3168 {
3169         unsigned long flags;
3170
3171         spin_lock_irqsave(&dev->spinlock, flags);
3172         if (priv(dev)->ai_cmd_running == 0) {
3173                 spin_unlock_irqrestore(&dev->spinlock, flags);
3174                 return 0;
3175         }
3176         priv(dev)->ai_cmd_running = 0;
3177         spin_unlock_irqrestore(&dev->spinlock, flags);
3178
3179         disable_ai_pacing(dev);
3180
3181         abort_dma(dev, 1);
3182
3183         DEBUG_PRINT("ai canceled\n");
3184         return 0;
3185 }
3186
3187 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3188                     struct comedi_insn *insn, unsigned int *data)
3189 {
3190         int chan = CR_CHAN(insn->chanspec);
3191         int range = CR_RANGE(insn->chanspec);
3192
3193         /*  do some initializing */
3194         writew(0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3195
3196         /*  set range */
3197         set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, chan, range);
3198         writew(priv(dev)->dac_control1_bits,
3199                priv(dev)->main_iobase + DAC_CONTROL1_REG);
3200
3201         /*  write to channel */
3202         if (board(dev)->layout == LAYOUT_4020) {
3203                 writew(data[0] & 0xff,
3204                        priv(dev)->main_iobase + dac_lsb_4020_reg(chan));
3205                 writew((data[0] >> 8) & 0xf,
3206                        priv(dev)->main_iobase + dac_msb_4020_reg(chan));
3207         } else {
3208                 writew(data[0], priv(dev)->main_iobase + dac_convert_reg(chan));
3209         }
3210
3211         /*  remember output value */
3212         priv(dev)->ao_value[chan] = data[0];
3213
3214         return 1;
3215 }
3216
3217 static int ao_readback_insn(struct comedi_device *dev,
3218                             struct comedi_subdevice *s,
3219                             struct comedi_insn *insn, unsigned int *data)
3220 {
3221         data[0] = priv(dev)->ao_value[CR_CHAN(insn->chanspec)];
3222
3223         return 1;
3224 }
3225
3226 static void set_dac_control0_reg(struct comedi_device *dev,
3227                                  const struct comedi_cmd *cmd)
3228 {
3229         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3230             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3231
3232         if (cmd->start_src == TRIG_EXT) {
3233                 bits |= WAVEFORM_TRIG_EXT_BITS;
3234                 if (cmd->start_arg & CR_INVERT)
3235                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3236         } else {
3237                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3238         }
3239         if (cmd->scan_begin_src == TRIG_EXT) {
3240                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3241                 if (cmd->scan_begin_arg & CR_INVERT)
3242                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3243         }
3244         writew(bits, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3245 }
3246
3247 static void set_dac_control1_reg(struct comedi_device *dev,
3248                                  const struct comedi_cmd *cmd)
3249 {
3250         int i;
3251
3252         for (i = 0; i < cmd->chanlist_len; i++) {
3253                 int channel, range;
3254
3255                 channel = CR_CHAN(cmd->chanlist[i]);
3256                 range = CR_RANGE(cmd->chanlist[i]);
3257                 set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, channel,
3258                                    range);
3259         }
3260         priv(dev)->dac_control1_bits |= DAC_SW_GATE_BIT;
3261         writew(priv(dev)->dac_control1_bits,
3262                priv(dev)->main_iobase + DAC_CONTROL1_REG);
3263 }
3264
3265 static void set_dac_select_reg(struct comedi_device *dev,
3266                                const struct comedi_cmd *cmd)
3267 {
3268         uint16_t bits;
3269         unsigned int first_channel, last_channel;
3270
3271         first_channel = CR_CHAN(cmd->chanlist[0]);
3272         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3273         if (last_channel < first_channel)
3274                 comedi_error(dev, "bug! last ao channel < first ao channel");
3275
3276         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3277
3278         writew(bits, priv(dev)->main_iobase + DAC_SELECT_REG);
3279 }
3280
3281 static void set_dac_interval_regs(struct comedi_device *dev,
3282                                   const struct comedi_cmd *cmd)
3283 {
3284         unsigned int divisor;
3285
3286         if (cmd->scan_begin_src != TRIG_TIMER)
3287                 return;
3288
3289         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3290         if (divisor > max_counter_value) {
3291                 comedi_error(dev, "bug! ao divisor too big");
3292                 divisor = max_counter_value;
3293         }
3294         writew(divisor & 0xffff,
3295                priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3296         writew((divisor >> 16) & 0xff,
3297                priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3298 }
3299
3300 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
3301                                        const struct comedi_cmd *cmd)
3302 {
3303         unsigned int num_bytes, buffer_index, prev_buffer_index;
3304         unsigned int next_bits;
3305
3306         buffer_index = priv(dev)->ao_dma_index;
3307         prev_buffer_index = prev_ao_dma_index(dev);
3308
3309         DEBUG_PRINT("attempting to load ao buffer %i (0x%x)\n", buffer_index,
3310                     priv(dev)->ao_buffer_bus_addr[buffer_index]);
3311
3312         num_bytes = comedi_buf_read_n_available(dev->write_subdev->async);
3313         if (num_bytes > DMA_BUFFER_SIZE)
3314                 num_bytes = DMA_BUFFER_SIZE;
3315         if (cmd->stop_src == TRIG_COUNT && num_bytes > priv(dev)->ao_count)
3316                 num_bytes = priv(dev)->ao_count;
3317         num_bytes -= num_bytes % bytes_in_sample;
3318
3319         if (num_bytes == 0)
3320                 return 0;
3321
3322         DEBUG_PRINT("loading %i bytes\n", num_bytes);
3323
3324         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3325                                                priv(dev)->
3326                                                ao_buffer[buffer_index],
3327                                                num_bytes);
3328         priv(dev)->ao_dma_desc[buffer_index].transfer_size =
3329             cpu_to_le32(num_bytes);
3330         /* set end of chain bit so we catch underruns */
3331         next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[buffer_index].next);
3332         next_bits |= PLX_END_OF_CHAIN_BIT;
3333         priv(dev)->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
3334         /* clear end of chain bit on previous buffer now that we have set it
3335          * for the last buffer */
3336         next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[prev_buffer_index].next);
3337         next_bits &= ~PLX_END_OF_CHAIN_BIT;
3338         priv(dev)->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
3339
3340         priv(dev)->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
3341         priv(dev)->ao_count -= num_bytes;
3342
3343         return num_bytes;
3344 }
3345
3346 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3347 {
3348         unsigned int num_bytes;
3349         unsigned int next_transfer_addr;
3350         void __iomem *pci_addr_reg =
3351             priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
3352         unsigned int buffer_index;
3353
3354         do {
3355                 buffer_index = priv(dev)->ao_dma_index;
3356                 /* don't overwrite data that hasn't been transferred yet */
3357                 next_transfer_addr = readl(pci_addr_reg);
3358                 if (next_transfer_addr >=
3359                     priv(dev)->ao_buffer_bus_addr[buffer_index]
3360                     && next_transfer_addr <
3361                     priv(dev)->ao_buffer_bus_addr[buffer_index] +
3362                     DMA_BUFFER_SIZE)
3363                         return;
3364                 num_bytes = load_ao_dma_buffer(dev, cmd);
3365         } while (num_bytes >= DMA_BUFFER_SIZE);
3366 }
3367
3368 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3369 {
3370         unsigned int num_bytes;
3371         int i;
3372
3373         /* clear queue pointer too, since external queue has
3374          * weird interactions with ao fifo */
3375         writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
3376         writew(0, priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG);
3377
3378         num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3379         if (cmd->stop_src == TRIG_COUNT &&
3380             num_bytes / bytes_in_sample > priv(dev)->ao_count)
3381                 num_bytes = priv(dev)->ao_count * bytes_in_sample;
3382         num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3383                                                priv(dev)->ao_bounce_buffer,
3384                                                num_bytes);
3385         for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3386                 writew(priv(dev)->ao_bounce_buffer[i],
3387                        priv(dev)->main_iobase + DAC_FIFO_REG);
3388         }
3389         priv(dev)->ao_count -= num_bytes / bytes_in_sample;
3390         if (cmd->stop_src == TRIG_COUNT && priv(dev)->ao_count == 0)
3391                 return 0;
3392         num_bytes = load_ao_dma_buffer(dev, cmd);
3393         if (num_bytes == 0)
3394                 return -1;
3395         if (num_bytes >= DMA_BUFFER_SIZE) ;
3396         load_ao_dma(dev, cmd);
3397
3398         dma_start_sync(dev, 0);
3399
3400         return 0;
3401 }
3402
3403 static inline int external_ai_queue_in_use(struct comedi_device *dev)
3404 {
3405         if (dev->read_subdev->busy)
3406                 return 0;
3407         if (board(dev)->layout == LAYOUT_4020)
3408                 return 0;
3409         else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd))
3410                 return 0;
3411         return 1;
3412 }
3413
3414 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3415 {
3416         struct comedi_cmd *cmd = &s->async->cmd;
3417
3418         if (external_ai_queue_in_use(dev)) {
3419                 warn_external_queue(dev);
3420                 return -EBUSY;
3421         }
3422         /* disable analog output system during setup */
3423         writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3424
3425         priv(dev)->ao_dma_index = 0;
3426         priv(dev)->ao_count = cmd->stop_arg * cmd->chanlist_len;
3427
3428         set_dac_select_reg(dev, cmd);
3429         set_dac_interval_regs(dev, cmd);
3430         load_first_dma_descriptor(dev, 0, priv(dev)->ao_dma_desc_bus_addr |
3431                                   PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3432
3433         set_dac_control1_reg(dev, cmd);
3434         s->async->inttrig = ao_inttrig;
3435
3436         return 0;
3437 }
3438
3439 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3440                       unsigned int trig_num)
3441 {
3442         struct comedi_cmd *cmd = &s->async->cmd;
3443         int retval;
3444
3445         if (trig_num != 0)
3446                 return -EINVAL;
3447
3448         retval = prep_ao_dma(dev, cmd);
3449         if (retval < 0)
3450                 return -EPIPE;
3451
3452         set_dac_control0_reg(dev, cmd);
3453
3454         if (cmd->start_src == TRIG_INT)
3455                 writew(0, priv(dev)->main_iobase + DAC_START_REG);
3456
3457         s->async->inttrig = NULL;
3458
3459         return 0;
3460 }
3461
3462 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3463                       struct comedi_cmd *cmd)
3464 {
3465         int err = 0;
3466         int tmp;
3467         unsigned int tmp_arg;
3468         int i;
3469
3470         /* step 1: make sure trigger sources are trivially valid */
3471
3472         tmp = cmd->start_src;
3473         cmd->start_src &= TRIG_INT | TRIG_EXT;
3474         if (!cmd->start_src || tmp != cmd->start_src)
3475                 err++;
3476
3477         tmp = cmd->scan_begin_src;
3478         cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
3479         if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3480                 err++;
3481
3482         tmp = cmd->convert_src;
3483         cmd->convert_src &= TRIG_NOW;
3484         if (!cmd->convert_src || tmp != cmd->convert_src)
3485                 err++;
3486
3487         tmp = cmd->scan_end_src;
3488         cmd->scan_end_src &= TRIG_COUNT;
3489         if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3490                 err++;
3491
3492         tmp = cmd->stop_src;
3493         cmd->stop_src &= TRIG_NONE;
3494         if (!cmd->stop_src || tmp != cmd->stop_src)
3495                 err++;
3496
3497         if (err)
3498                 return 1;
3499
3500         /* step 2: make sure trigger sources are unique and mutually compatible */
3501
3502         /*  uniqueness check */
3503         if (cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT)
3504                 err++;
3505         if (cmd->scan_begin_src != TRIG_TIMER &&
3506             cmd->scan_begin_src != TRIG_EXT)
3507                 err++;
3508
3509         /*  compatibility check */
3510         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3511                 err++;
3512         if (cmd->stop_src != TRIG_COUNT &&
3513             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3514                 err++;
3515
3516         if (err)
3517                 return 2;
3518
3519         /* step 3: make sure arguments are trivially compatible */
3520
3521         if (cmd->scan_begin_src == TRIG_TIMER) {
3522                 if (cmd->scan_begin_arg < board(dev)->ao_scan_speed) {
3523                         cmd->scan_begin_arg = board(dev)->ao_scan_speed;
3524                         err++;
3525                 }
3526                 if (get_ao_divisor(cmd->scan_begin_arg,
3527                                    cmd->flags) > max_counter_value) {
3528                         cmd->scan_begin_arg =
3529                             (max_counter_value + 2) * TIMER_BASE;
3530                         err++;
3531                 }
3532         }
3533
3534         if (!cmd->chanlist_len) {
3535                 cmd->chanlist_len = 1;
3536                 err++;
3537         }
3538         if (cmd->scan_end_arg != cmd->chanlist_len) {
3539                 cmd->scan_end_arg = cmd->chanlist_len;
3540                 err++;
3541         }
3542
3543         if (err)
3544                 return 3;
3545
3546         /* step 4: fix up any arguments */
3547
3548         if (cmd->scan_begin_src == TRIG_TIMER) {
3549                 tmp_arg = cmd->scan_begin_arg;
3550                 cmd->scan_begin_arg =
3551                     get_divisor(cmd->scan_begin_arg, cmd->flags) * TIMER_BASE;
3552                 if (tmp_arg != cmd->scan_begin_arg)
3553                         err++;
3554         }
3555
3556         if (err)
3557                 return 4;
3558
3559         if (cmd->chanlist) {
3560                 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
3561                 for (i = 1; i < cmd->chanlist_len; i++) {
3562                         if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) {
3563                                 comedi_error(dev,
3564                                              "chanlist must use consecutive channels");
3565                                 err++;
3566                                 break;
3567                         }
3568                 }
3569         }
3570
3571         if (err)
3572                 return 5;
3573
3574         return 0;
3575 }
3576
3577 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3578 {
3579         writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3580         abort_dma(dev, 0);
3581         return 0;
3582 }
3583
3584 static int dio_callback(int dir, int port, int data, unsigned long arg)
3585 {
3586         void __iomem *iobase = (void __iomem *)arg;
3587         if (dir) {
3588                 writeb(data, iobase + port);
3589                 DEBUG_PRINT("wrote 0x%x to port %i\n", data, port);
3590                 return 0;
3591         } else {
3592                 return readb(iobase + port);
3593         }
3594 }
3595
3596 static int dio_callback_4020(int dir, int port, int data, unsigned long arg)
3597 {
3598         void __iomem *iobase = (void __iomem *)arg;
3599         if (dir) {
3600                 writew(data, iobase + 2 * port);
3601                 return 0;
3602         } else {
3603                 return readw(iobase + 2 * port);
3604         }
3605 }
3606
3607 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3608                     struct comedi_insn *insn, unsigned int *data)
3609 {
3610         unsigned int bits;
3611
3612         bits = readb(priv(dev)->dio_counter_iobase + DI_REG);
3613         bits &= 0xf;
3614         data[1] = bits;
3615         data[0] = 0;
3616
3617         return 2;
3618 }
3619
3620 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3621                     struct comedi_insn *insn, unsigned int *data)
3622 {
3623         data[0] &= 0xf;
3624         /*  zero bits we are going to change */
3625         s->state &= ~data[0];
3626         /*  set new bits */
3627         s->state |= data[0] & data[1];
3628
3629         writeb(s->state, priv(dev)->dio_counter_iobase + DO_REG);
3630
3631         data[1] = s->state;
3632
3633         return 2;
3634 }
3635
3636 static int dio_60xx_config_insn(struct comedi_device *dev,
3637                                 struct comedi_subdevice *s,
3638                                 struct comedi_insn *insn, unsigned int *data)
3639 {
3640         unsigned int mask;
3641
3642         mask = 1 << CR_CHAN(insn->chanspec);
3643
3644         switch (data[0]) {
3645         case INSN_CONFIG_DIO_INPUT:
3646                 s->io_bits &= ~mask;
3647                 break;
3648         case INSN_CONFIG_DIO_OUTPUT:
3649                 s->io_bits |= mask;
3650                 break;
3651         case INSN_CONFIG_DIO_QUERY:
3652                 data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT;
3653                 return 2;
3654         default:
3655                 return -EINVAL;
3656         }
3657
3658         writeb(s->io_bits,
3659                priv(dev)->dio_counter_iobase + DIO_DIRECTION_60XX_REG);
3660
3661         return 1;
3662 }
3663
3664 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3665                           struct comedi_insn *insn, unsigned int *data)
3666 {
3667         if (data[0]) {
3668                 s->state &= ~data[0];
3669                 s->state |= (data[0] & data[1]);
3670                 writeb(s->state,
3671                        priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG);
3672         }
3673
3674         data[1] = readb(priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG);
3675
3676         return 2;
3677 }
3678
3679 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3680                          unsigned int value)
3681 {
3682         priv(dev)->caldac_state[channel] = value;
3683
3684         switch (board(dev)->layout) {
3685         case LAYOUT_60XX:
3686         case LAYOUT_64XX:
3687                 caldac_8800_write(dev, channel, value);
3688                 break;
3689         case LAYOUT_4020:
3690                 caldac_i2c_write(dev, channel, value);
3691                 break;
3692         default:
3693                 break;
3694         }
3695 }
3696
3697 static int calib_write_insn(struct comedi_device *dev,
3698                             struct comedi_subdevice *s,
3699                             struct comedi_insn *insn, unsigned int *data)
3700 {
3701         int channel = CR_CHAN(insn->chanspec);
3702
3703         /* return immediately if setting hasn't changed, since
3704          * programming these things is slow */
3705         if (priv(dev)->caldac_state[channel] == data[0])
3706                 return 1;
3707
3708         caldac_write(dev, channel, data[0]);
3709
3710         return 1;
3711 }
3712
3713 static int calib_read_insn(struct comedi_device *dev,
3714                            struct comedi_subdevice *s, struct comedi_insn *insn,
3715                            unsigned int *data)
3716 {
3717         unsigned int channel = CR_CHAN(insn->chanspec);
3718
3719         data[0] = priv(dev)->caldac_state[channel];
3720
3721         return 1;
3722 }
3723
3724 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3725                          unsigned int value)
3726 {
3727         static const int bitstream_length = 10;
3728         unsigned int bit, register_bits;
3729         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3730         static const int ad8402_udelay = 1;
3731
3732         priv(dev)->ad8402_state[channel] = value;
3733
3734         register_bits = SELECT_8402_64XX_BIT;
3735         udelay(ad8402_udelay);
3736         writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3737
3738         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3739                 if (bitstream & bit)
3740                         register_bits |= SERIAL_DATA_IN_BIT;
3741                 else
3742                         register_bits &= ~SERIAL_DATA_IN_BIT;
3743                 udelay(ad8402_udelay);
3744                 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3745                 udelay(ad8402_udelay);
3746                 writew(register_bits | SERIAL_CLOCK_BIT,
3747                        priv(dev)->main_iobase + CALIBRATION_REG);
3748         }
3749
3750         udelay(ad8402_udelay);
3751         writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
3752 }
3753
3754 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3755 static int ad8402_write_insn(struct comedi_device *dev,
3756                              struct comedi_subdevice *s,
3757                              struct comedi_insn *insn, unsigned int *data)
3758 {
3759         int channel = CR_CHAN(insn->chanspec);
3760
3761         /* return immediately if setting hasn't changed, since
3762          * programming these things is slow */
3763         if (priv(dev)->ad8402_state[channel] == data[0])
3764                 return 1;
3765
3766         priv(dev)->ad8402_state[channel] = data[0];
3767
3768         ad8402_write(dev, channel, data[0]);
3769
3770         return 1;
3771 }
3772
3773 static int ad8402_read_insn(struct comedi_device *dev,
3774                             struct comedi_subdevice *s,
3775                             struct comedi_insn *insn, unsigned int *data)
3776 {
3777         unsigned int channel = CR_CHAN(insn->chanspec);
3778
3779         data[0] = priv(dev)->ad8402_state[channel];
3780
3781         return 1;
3782 }
3783
3784 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3785 {
3786         static const int bitstream_length = 11;
3787         static const int read_command = 0x6;
3788         unsigned int bitstream = (read_command << 8) | address;
3789         unsigned int bit;
3790         void __iomem * const plx_control_addr =
3791             priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
3792         uint16_t value;
3793         static const int value_length = 16;
3794         static const int eeprom_udelay = 1;
3795
3796         udelay(eeprom_udelay);
3797         priv(dev)->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3798         /*  make sure we don't send anything to the i2c bus on 4020 */
3799         priv(dev)->plx_control_bits |= CTL_USERO;
3800         writel(priv(dev)->plx_control_bits, plx_control_addr);
3801         /*  activate serial eeprom */
3802         udelay(eeprom_udelay);
3803         priv(dev)->plx_control_bits |= CTL_EE_CS;
3804         writel(priv(dev)->plx_control_bits, plx_control_addr);
3805
3806         /*  write read command and desired memory address */
3807         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3808                 /*  set bit to be written */
3809                 udelay(eeprom_udelay);
3810                 if (bitstream & bit)
3811                         priv(dev)->plx_control_bits |= CTL_EE_W;
3812                 else
3813                         priv(dev)->plx_control_bits &= ~CTL_EE_W;
3814                 writel(priv(dev)->plx_control_bits, plx_control_addr);
3815                 /*  clock in bit */
3816                 udelay(eeprom_udelay);
3817                 priv(dev)->plx_control_bits |= CTL_EE_CLK;
3818                 writel(priv(dev)->plx_control_bits, plx_control_addr);
3819                 udelay(eeprom_udelay);
3820                 priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
3821                 writel(priv(dev)->plx_control_bits, plx_control_addr);
3822         }
3823         /*  read back value from eeprom memory location */
3824         value = 0;
3825         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3826                 /*  clock out bit */
3827                 udelay(eeprom_udelay);
3828                 priv(dev)->plx_control_bits |= CTL_EE_CLK;
3829                 writel(priv(dev)->plx_control_bits, plx_control_addr);
3830                 udelay(eeprom_udelay);
3831                 priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
3832                 writel(priv(dev)->plx_control_bits, plx_control_addr);
3833                 udelay(eeprom_udelay);
3834                 if (readl(plx_control_addr) & CTL_EE_R)
3835                         value |= bit;
3836         }
3837
3838         /*  deactivate eeprom serial input */
3839         udelay(eeprom_udelay);
3840         priv(dev)->plx_control_bits &= ~CTL_EE_CS;
3841         writel(priv(dev)->plx_control_bits, plx_control_addr);
3842
3843         return value;
3844 }
3845
3846 static int eeprom_read_insn(struct comedi_device *dev,
3847                             struct comedi_subdevice *s,
3848                             struct comedi_insn *insn, unsigned int *data)
3849 {
3850         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3851
3852         return 1;
3853 }
3854
3855 /* utility function that rounds desired timing to an achievable time, and
3856  * sets cmd members appropriately.
3857  * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
3858  */
3859 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
3860 {
3861         unsigned int convert_divisor = 0, scan_divisor;
3862         static const int min_convert_divisor = 3;
3863         static const int max_convert_divisor =
3864             max_counter_value + min_convert_divisor;
3865         static const int min_scan_divisor_4020 = 2;
3866         unsigned long long max_scan_divisor, min_scan_divisor;
3867
3868         if (cmd->convert_src == TRIG_TIMER) {
3869                 if (board(dev)->layout == LAYOUT_4020) {
3870                         cmd->convert_arg = 0;
3871                 } else {
3872                         convert_divisor =
3873                             get_divisor(cmd->convert_arg, cmd->flags);
3874                         if (convert_divisor > max_convert_divisor)
3875                                 convert_divisor = max_convert_divisor;
3876                         if (convert_divisor < min_convert_divisor)
3877                                 convert_divisor = min_convert_divisor;
3878                         cmd->convert_arg = convert_divisor * TIMER_BASE;
3879                 }
3880         } else if (cmd->convert_src == TRIG_NOW)
3881                 cmd->convert_arg = 0;
3882
3883         if (cmd->scan_begin_src == TRIG_TIMER) {
3884                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
3885                 if (cmd->convert_src == TRIG_TIMER) {
3886                         /*  XXX check for integer overflows */
3887                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
3888                         max_scan_divisor =
3889                             (convert_divisor * cmd->chanlist_len - 1) +
3890                             max_counter_value;
3891                 } else {
3892                         min_scan_divisor = min_scan_divisor_4020;
3893                         max_scan_divisor = max_counter_value + min_scan_divisor;
3894                 }
3895                 if (scan_divisor > max_scan_divisor)
3896                         scan_divisor = max_scan_divisor;
3897                 if (scan_divisor < min_scan_divisor)
3898                         scan_divisor = min_scan_divisor;
3899                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
3900         }
3901
3902         return;
3903 }
3904
3905 /* Gets nearest achievable timing given master clock speed, does not
3906  * take into account possible minimum/maximum divisor values.  Used
3907  * by other timing checking functions. */
3908 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
3909 {
3910         unsigned int divisor;
3911
3912         switch (flags & TRIG_ROUND_MASK) {
3913         case TRIG_ROUND_UP:
3914                 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
3915                 break;
3916         case TRIG_ROUND_DOWN:
3917                 divisor = ns / TIMER_BASE;
3918                 break;
3919         case TRIG_ROUND_NEAREST:
3920         default:
3921                 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
3922                 break;
3923         }
3924         return divisor;
3925 }
3926
3927 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3928 {
3929         return get_divisor(ns, flags) - 2;
3930 }
3931
3932 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
3933 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
3934 {
3935         unsigned int num_fifo_entries;
3936         int retval;
3937         const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
3938
3939         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
3940
3941         retval = set_ai_fifo_segment_length(dev,
3942                                             num_fifo_entries /
3943                                             fifo->num_segments);
3944         if (retval < 0)
3945                 return retval;
3946
3947         num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
3948
3949         DEBUG_PRINT("set hardware fifo size to %i\n", num_samples);
3950
3951         return num_samples;
3952 }
3953
3954 /* query length of fifo */
3955 static unsigned int ai_fifo_size(struct comedi_device *dev)
3956 {
3957         return priv(dev)->ai_fifo_segment_length *
3958             board(dev)->ai_fifo->num_segments *
3959             board(dev)->ai_fifo->sample_packing_ratio;
3960 }
3961
3962 static int set_ai_fifo_segment_length(struct comedi_device *dev,
3963                                       unsigned int num_entries)
3964 {
3965         static const int increment_size = 0x100;
3966         const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
3967         unsigned int num_increments;
3968         uint16_t bits;
3969
3970         if (num_entries < increment_size)
3971                 num_entries = increment_size;
3972         if (num_entries > fifo->max_segment_length)
3973                 num_entries = fifo->max_segment_length;
3974
3975         /*  1 == 256 entries, 2 == 512 entries, etc */
3976         num_increments = (num_entries + increment_size / 2) / increment_size;
3977
3978         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
3979         priv(dev)->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
3980         priv(dev)->fifo_size_bits |= bits;
3981         writew(priv(dev)->fifo_size_bits,
3982                priv(dev)->main_iobase + FIFO_SIZE_REG);
3983
3984         priv(dev)->ai_fifo_segment_length = num_increments * increment_size;
3985
3986         DEBUG_PRINT("set hardware fifo segment length to %i\n",
3987                     priv(dev)->ai_fifo_segment_length);
3988
3989         return priv(dev)->ai_fifo_segment_length;
3990 }
3991
3992 /* pci-6025 8800 caldac:
3993  * address 0 == dac channel 0 offset
3994  * address 1 == dac channel 0 gain
3995  * address 2 == dac channel 1 offset
3996  * address 3 == dac channel 1 gain
3997  * address 4 == fine adc offset
3998  * address 5 == coarse adc offset
3999  * address 6 == coarse adc gain
4000  * address 7 == fine adc gain
4001  */
4002 /* pci-6402/16 uses all 8 channels for dac:
4003  * address 0 == dac channel 0 fine gain
4004  * address 1 == dac channel 0 coarse gain
4005  * address 2 == dac channel 0 coarse offset
4006  * address 3 == dac channel 1 coarse offset
4007  * address 4 == dac channel 1 fine gain
4008  * address 5 == dac channel 1 coarse gain
4009  * address 6 == dac channel 0 fine offset
4010  * address 7 == dac channel 1 fine offset
4011 */
4012
4013 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
4014                              uint8_t value)
4015 {
4016         static const int num_caldac_channels = 8;
4017         static const int bitstream_length = 11;
4018         unsigned int bitstream = ((address & 0x7) << 8) | value;
4019         unsigned int bit, register_bits;
4020         static const int caldac_8800_udelay = 1;
4021
4022         if (address >= num_caldac_channels) {
4023                 comedi_error(dev, "illegal caldac channel");
4024                 return -1;
4025         }
4026         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
4027                 register_bits = 0;
4028                 if (bitstream & bit)
4029                         register_bits |= SERIAL_DATA_IN_BIT;
4030                 udelay(caldac_8800_udelay);
4031                 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
4032                 register_bits |= SERIAL_CLOCK_BIT;
4033                 udelay(caldac_8800_udelay);
4034                 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
4035         }
4036         udelay(caldac_8800_udelay);
4037         writew(SELECT_8800_BIT, priv(dev)->main_iobase + CALIBRATION_REG);
4038         udelay(caldac_8800_udelay);
4039         writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
4040         udelay(caldac_8800_udelay);
4041         return 0;
4042 }
4043
4044 /* 4020 caldacs */
4045 static int caldac_i2c_write(struct comedi_device *dev,
4046                             unsigned int caldac_channel, unsigned int value)
4047 {
4048         uint8_t serial_bytes[3];
4049         uint8_t i2c_addr;
4050         enum pointer_bits {
4051                 /*  manual has gain and offset bits switched */
4052                 OFFSET_0_2 = 0x1,
4053                 GAIN_0_2 = 0x2,
4054                 OFFSET_1_3 = 0x4,
4055                 GAIN_1_3 = 0x8,
4056         };
4057         enum data_bits {
4058                 NOT_CLEAR_REGISTERS = 0x20,
4059         };
4060
4061         switch (caldac_channel) {
4062         case 0:         /*  chan 0 offset */
4063                 i2c_addr = CALDAC0_I2C_ADDR;
4064                 serial_bytes[0] = OFFSET_0_2;
4065                 break;
4066         case 1:         /*  chan 1 offset */
4067                 i2c_addr = CALDAC0_I2C_ADDR;
4068                 serial_bytes[0] = OFFSET_1_3;
4069                 break;
4070         case 2:         /*  chan 2 offset */
4071                 i2c_addr = CALDAC1_I2C_ADDR;
4072                 serial_bytes[0] = OFFSET_0_2;
4073                 break;
4074         case 3:         /*  chan 3 offset */
4075                 i2c_addr = CALDAC1_I2C_ADDR;
4076                 serial_bytes[0] = OFFSET_1_3;
4077                 break;
4078         case 4:         /*  chan 0 gain */
4079                 i2c_addr = CALDAC0_I2C_ADDR;
4080                 serial_bytes[0] = GAIN_0_2;
4081                 break;
4082         case 5:         /*  chan 1 gain */
4083                 i2c_addr = CALDAC0_I2C_ADDR;
4084                 serial_bytes[0] = GAIN_1_3;
4085                 break;
4086         case 6:         /*  chan 2 gain */
4087                 i2c_addr = CALDAC1_I2C_ADDR;
4088                 serial_bytes[0] = GAIN_0_2;
4089                 break;
4090         case 7:         /*  chan 3 gain */
4091                 i2c_addr = CALDAC1_I2C_ADDR;
4092                 serial_bytes[0] = GAIN_1_3;
4093                 break;
4094         default:
4095                 comedi_error(dev, "invalid caldac channel\n");
4096                 return -1;
4097                 break;
4098         }
4099         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
4100         serial_bytes[2] = value & 0xff;
4101         i2c_write(dev, i2c_addr, serial_bytes, 3);
4102         return 0;
4103 }
4104
4105 /* Their i2c requires a huge delay on setting clock or data high for some reason */
4106 static const int i2c_high_udelay = 1000;
4107 static const int i2c_low_udelay = 10;
4108
4109 /* set i2c data line high or low */
4110 static void i2c_set_sda(struct comedi_device *dev, int state)
4111 {
4112         static const int data_bit = CTL_EE_W;
4113         void __iomem *plx_control_addr = priv(dev)->plx9080_iobase +
4114                                          PLX_CONTROL_REG;
4115
4116         if (state) {
4117                 /*  set data line high */
4118                 priv(dev)->plx_control_bits &= ~data_bit;
4119                 writel(priv(dev)->plx_control_bits, plx_control_addr);
4120                 udelay(i2c_high_udelay);
4121         } else {                /*  set data line low */
4122
4123                 priv(dev)->plx_control_bits |= data_bit;
4124                 writel(priv(dev)->plx_control_bits, plx_control_addr);
4125                 udelay(i2c_low_udelay);
4126         }
4127 }
4128
4129 /* set i2c clock line high or low */
4130 static void i2c_set_scl(struct comedi_device *dev, int state)
4131 {
4132         static const int clock_bit = CTL_USERO;
4133         void __iomem *plx_control_addr = priv(dev)->plx9080_iobase +
4134                                          PLX_CONTROL_REG;
4135
4136         if (state) {
4137                 /*  set clock line high */
4138                 priv(dev)->plx_control_bits &= ~clock_bit;
4139                 writel(priv(dev)->plx_control_bits, plx_control_addr);
4140                 udelay(i2c_high_udelay);
4141         } else {                /*  set clock line low */
4142
4143                 priv(dev)->plx_control_bits |= clock_bit;
4144                 writel(priv(dev)->plx_control_bits, plx_control_addr);
4145                 udelay(i2c_low_udelay);
4146         }
4147 }
4148
4149 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
4150 {
4151         uint8_t bit;
4152         unsigned int num_bits = 8;
4153
4154         DEBUG_PRINT("writing to i2c byte 0x%x\n", byte);
4155
4156         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
4157                 i2c_set_scl(dev, 0);
4158                 if ((byte & bit))
4159                         i2c_set_sda(dev, 1);
4160                 else
4161                         i2c_set_sda(dev, 0);
4162                 i2c_set_scl(dev, 1);
4163         }
4164 }
4165
4166 /* we can't really read the lines, so fake it */
4167 static int i2c_read_ack(struct comedi_device *dev)
4168 {
4169         i2c_set_scl(dev, 0);
4170         i2c_set_sda(dev, 1);
4171         i2c_set_scl(dev, 1);
4172
4173         return 0;               /*  return fake acknowledge bit */
4174 }
4175
4176 /* send start bit */
4177 static void i2c_start(struct comedi_device *dev)
4178 {
4179         i2c_set_scl(dev, 1);
4180         i2c_set_sda(dev, 1);
4181         i2c_set_sda(dev, 0);
4182 }
4183
4184 /* send stop bit */
4185 static void i2c_stop(struct comedi_device *dev)
4186 {
4187         i2c_set_scl(dev, 0);
4188         i2c_set_sda(dev, 0);
4189         i2c_set_scl(dev, 1);
4190         i2c_set_sda(dev, 1);
4191 }
4192
4193 static void i2c_write(struct comedi_device *dev, unsigned int address,
4194                       const uint8_t * data, unsigned int length)
4195 {
4196         unsigned int i;
4197         uint8_t bitstream;
4198         static const int read_bit = 0x1;
4199
4200 /* XXX need mutex to prevent simultaneous attempts to access eeprom and i2c bus */
4201
4202         /*  make sure we dont send anything to eeprom */
4203         priv(dev)->plx_control_bits &= ~CTL_EE_CS;
4204
4205         i2c_stop(dev);
4206         i2c_start(dev);
4207
4208         /*  send address and write bit */
4209         bitstream = (address << 1) & ~read_bit;
4210         i2c_write_byte(dev, bitstream);
4211
4212         /*  get acknowledge */
4213         if (i2c_read_ack(dev) != 0) {
4214                 comedi_error(dev, "i2c write failed: no acknowledge");
4215                 i2c_stop(dev);
4216                 return;
4217         }
4218         /*  write data bytes */
4219         for (i = 0; i < length; i++) {
4220                 i2c_write_byte(dev, data[i]);
4221                 if (i2c_read_ack(dev) != 0) {
4222                         comedi_error(dev, "i2c write failed: no acknowledge");
4223                         i2c_stop(dev);
4224                         return;
4225                 }
4226         }
4227         i2c_stop(dev);
4228 }
4229
4230 static struct comedi_driver cb_pcidas64_driver = {
4231         .driver_name    = "cb_pcidas64",
4232         .module         = THIS_MODULE,
4233         .attach         = attach,
4234         .detach         = detach,
4235 };
4236
4237 static int __devinit cb_pcidas64_pci_probe(struct pci_dev *dev,
4238                                            const struct pci_device_id *ent)
4239 {
4240         return comedi_pci_auto_config(dev, &cb_pcidas64_driver);
4241 }
4242
4243 static void __devexit cb_pcidas64_pci_remove(struct pci_dev *dev)
4244 {
4245         comedi_pci_auto_unconfig(dev);
4246 }
4247
4248 static DEFINE_PCI_DEVICE_TABLE(cb_pcidas64_pci_table) = {
4249         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x001d) },
4250         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x001e) },
4251         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0035) },
4252         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0036) },
4253         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0037) },
4254         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0052) },
4255         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005d) },
4256         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005e) },
4257         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005f) },
4258         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0061) },
4259         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0062) },
4260         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0063) },
4261         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0064) },
4262         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0066) },
4263         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0067) },
4264         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0068) },
4265         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x006f) },
4266         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0078) },
4267         { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0079) },
4268         { 0 }
4269 };
4270 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4271
4272 static struct pci_driver cb_pcidas64_pci_driver = {
4273         .name           = "cb_pcidas64",
4274         .id_table       = cb_pcidas64_pci_table,
4275         .probe          = cb_pcidas64_pci_probe,
4276         .remove         = __devexit_p(cb_pcidas64_pci_remove),
4277 };
4278 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4279
4280 MODULE_AUTHOR("Comedi http://www.comedi.org");
4281 MODULE_DESCRIPTION("Comedi low-level driver");
4282 MODULE_LICENSE("GPL");