3 * Comedi driver the General Standards Corporation
4 * High Speed Parallel Digital Interface rs485 boards.
6 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 * Copyright (C) 2003 Coherent Imaging Systems
9 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
25 * Description: General Standards Corporation High
26 * Speed Parallel Digital Interface rs485 boards
27 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
28 * Status: only receive mode works, transmit not supported
29 * Updated: Thu, 01 Nov 2012 16:17:38 +0000
30 * Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
33 * Configuration options:
36 * Manual configuration of supported devices is not supported; they are
37 * configured automatically.
39 * There are some additional hpdi models available from GSC for which
40 * support could be added to this driver.
43 #include <linux/module.h>
44 #include <linux/pci.h>
45 #include <linux/delay.h>
46 #include <linux/interrupt.h>
48 #include "../comedidev.h"
51 #include "comedi_fc.h"
54 * PCI BAR2 Register map (dev->mmio)
56 #define FIRMWARE_REV_REG 0x00
57 #define FEATURES_REG_PRESENT_BIT (1 << 15)
58 #define BOARD_CONTROL_REG 0x04
59 #define BOARD_RESET_BIT (1 << 0)
60 #define TX_FIFO_RESET_BIT (1 << 1)
61 #define RX_FIFO_RESET_BIT (1 << 2)
62 #define TX_ENABLE_BIT (1 << 4)
63 #define RX_ENABLE_BIT (1 << 5)
64 #define DEMAND_DMA_DIRECTION_TX_BIT (1 << 6) /* ch 0 only */
65 #define LINE_VALID_ON_STATUS_VALID_BIT (1 << 7)
66 #define START_TX_BIT (1 << 8)
67 #define CABLE_THROTTLE_ENABLE_BIT (1 << 9)
68 #define TEST_MODE_ENABLE_BIT (1 << 31)
69 #define BOARD_STATUS_REG 0x08
70 #define COMMAND_LINE_STATUS_MASK (0x7f << 0)
71 #define TX_IN_PROGRESS_BIT (1 << 7)
72 #define TX_NOT_EMPTY_BIT (1 << 8)
73 #define TX_NOT_ALMOST_EMPTY_BIT (1 << 9)
74 #define TX_NOT_ALMOST_FULL_BIT (1 << 10)
75 #define TX_NOT_FULL_BIT (1 << 11)
76 #define RX_NOT_EMPTY_BIT (1 << 12)
77 #define RX_NOT_ALMOST_EMPTY_BIT (1 << 13)
78 #define RX_NOT_ALMOST_FULL_BIT (1 << 14)
79 #define RX_NOT_FULL_BIT (1 << 15)
80 #define BOARD_JUMPER0_INSTALLED_BIT (1 << 16)
81 #define BOARD_JUMPER1_INSTALLED_BIT (1 << 17)
82 #define TX_OVERRUN_BIT (1 << 21)
83 #define RX_UNDERRUN_BIT (1 << 22)
84 #define RX_OVERRUN_BIT (1 << 23)
85 #define TX_PROG_ALMOST_REG 0x0c
86 #define RX_PROG_ALMOST_REG 0x10
87 #define ALMOST_EMPTY_BITS(x) (((x) & 0xffff) << 0)
88 #define ALMOST_FULL_BITS(x) (((x) & 0xff) << 16)
89 #define FEATURES_REG 0x14
90 #define FIFO_SIZE_PRESENT_BIT (1 << 0)
91 #define FIFO_WORDS_PRESENT_BIT (1 << 1)
92 #define LEVEL_EDGE_INTERRUPTS_PRESENT_BIT (1 << 2)
93 #define GPIO_SUPPORTED_BIT (1 << 3)
94 #define PLX_DMA_CH1_SUPPORTED_BIT (1 << 4)
95 #define OVERRUN_UNDERRUN_SUPPORTED_BIT (1 << 5)
97 #define TX_STATUS_COUNT_REG 0x1c
98 #define TX_LINE_VALID_COUNT_REG 0x20,
99 #define TX_LINE_INVALID_COUNT_REG 0x24
100 #define RX_STATUS_COUNT_REG 0x28
101 #define RX_LINE_COUNT_REG 0x2c
102 #define INTERRUPT_CONTROL_REG 0x30
103 #define FRAME_VALID_START_INTR (1 << 0)
104 #define FRAME_VALID_END_INTR (1 << 1)
105 #define TX_FIFO_EMPTY_INTR (1 << 8)
106 #define TX_FIFO_ALMOST_EMPTY_INTR (1 << 9)
107 #define TX_FIFO_ALMOST_FULL_INTR (1 << 10)
108 #define TX_FIFO_FULL_INTR (1 << 11)
109 #define RX_EMPTY_INTR (1 << 12)
110 #define RX_ALMOST_EMPTY_INTR (1 << 13)
111 #define RX_ALMOST_FULL_INTR (1 << 14)
112 #define RX_FULL_INTR (1 << 15)
113 #define INTERRUPT_STATUS_REG 0x34
114 #define TX_CLOCK_DIVIDER_REG 0x38
115 #define TX_FIFO_SIZE_REG 0x40
116 #define RX_FIFO_SIZE_REG 0x44
117 #define FIFO_SIZE_MASK (0xfffff << 0)
118 #define TX_FIFO_WORDS_REG 0x48
119 #define RX_FIFO_WORDS_REG 0x4c
120 #define INTERRUPT_EDGE_LEVEL_REG 0x50
121 #define INTERRUPT_POLARITY_REG 0x54
123 #define TIMER_BASE 50 /* 20MHz master clock */
124 #define DMA_BUFFER_SIZE 0x10000
125 #define NUM_DMA_BUFFERS 4
126 #define NUM_DMA_DESCRIPTORS 256
134 static const struct hpdi_board hpdi_boards[] = {
136 .name = "pci-hpdi32",
137 .device_id = PCI_DEVICE_ID_PLX_9080,
138 .subdevice_id = 0x2400,
142 .name = "pxi-hpdi32",
144 .subdevice_id = 0x2705,
149 struct hpdi_private {
150 void __iomem *plx9080_mmio;
151 uint32_t *dio_buffer[NUM_DMA_BUFFERS]; /* dma buffers */
152 /* physical addresses of dma buffers */
153 dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
154 /* array of dma descriptors read by plx9080, allocated to get proper
156 struct plx_dma_desc *dma_desc;
157 /* physical address of dma descriptor array */
158 dma_addr_t dma_desc_phys_addr;
159 unsigned int num_dma_descriptors;
160 /* pointer to start of buffers indexed by descriptor */
161 uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
162 /* index of the dma descriptor that is currently being used */
163 unsigned int dma_desc_index;
164 unsigned int tx_fifo_size;
165 unsigned int rx_fifo_size;
166 unsigned long dio_count;
167 /* number of bytes at which to generate COMEDI_CB_BLOCK events */
168 unsigned int block_size;
171 static void gsc_hpdi_drain_dma(struct comedi_device *dev, unsigned int channel)
173 struct hpdi_private *devpriv = dev->private;
174 struct comedi_subdevice *s = dev->read_subdev;
175 struct comedi_cmd *cmd = &s->async->cmd;
183 next = readl(devpriv->plx9080_mmio + PLX_DMA1_PCI_ADDRESS_REG);
185 next = readl(devpriv->plx9080_mmio + PLX_DMA0_PCI_ADDRESS_REG);
187 idx = devpriv->dma_desc_index;
188 start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr);
189 /* loop until we have read all the full buffers */
190 for (desc = 0; (next < start || next >= start + devpriv->block_size) &&
191 desc < devpriv->num_dma_descriptors; desc++) {
192 /* transfer data from dma buffer to comedi buffer */
193 size = devpriv->block_size / sizeof(uint32_t);
194 if (cmd->stop_src == TRIG_COUNT) {
195 if (size > devpriv->dio_count)
196 size = devpriv->dio_count;
197 devpriv->dio_count -= size;
199 comedi_buf_write_samples(s, devpriv->desc_dio_buffer[idx],
202 idx %= devpriv->num_dma_descriptors;
203 start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr);
205 devpriv->dma_desc_index = idx;
207 /* XXX check for buffer overrun somehow */
210 static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
212 struct comedi_device *dev = d;
213 struct hpdi_private *devpriv = dev->private;
214 struct comedi_subdevice *s = dev->read_subdev;
215 struct comedi_async *async = s->async;
216 uint32_t hpdi_intr_status, hpdi_board_status;
219 uint8_t dma0_status, dma1_status;
225 plx_status = readl(devpriv->plx9080_mmio + PLX_INTRCS_REG);
226 if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
229 hpdi_intr_status = readl(dev->mmio + INTERRUPT_STATUS_REG);
230 hpdi_board_status = readl(dev->mmio + BOARD_STATUS_REG);
232 if (hpdi_intr_status)
233 writel(hpdi_intr_status, dev->mmio + INTERRUPT_STATUS_REG);
235 /* spin lock makes sure no one else changes plx dma control reg */
236 spin_lock_irqsave(&dev->spinlock, flags);
237 dma0_status = readb(devpriv->plx9080_mmio + PLX_DMA0_CS_REG);
238 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
239 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
240 devpriv->plx9080_mmio + PLX_DMA0_CS_REG);
242 if (dma0_status & PLX_DMA_EN_BIT)
243 gsc_hpdi_drain_dma(dev, 0);
245 spin_unlock_irqrestore(&dev->spinlock, flags);
247 /* spin lock makes sure no one else changes plx dma control reg */
248 spin_lock_irqsave(&dev->spinlock, flags);
249 dma1_status = readb(devpriv->plx9080_mmio + PLX_DMA1_CS_REG);
250 if (plx_status & ICS_DMA1_A) { /* XXX *//* dma chan 1 interrupt */
251 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
252 devpriv->plx9080_mmio + PLX_DMA1_CS_REG);
254 spin_unlock_irqrestore(&dev->spinlock, flags);
256 /* clear possible plx9080 interrupt sources */
257 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
258 plx_bits = readl(devpriv->plx9080_mmio + PLX_DBR_OUT_REG);
259 writel(plx_bits, devpriv->plx9080_mmio + PLX_DBR_OUT_REG);
262 if (hpdi_board_status & RX_OVERRUN_BIT) {
263 dev_err(dev->class_dev, "rx fifo overrun\n");
264 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
267 if (hpdi_board_status & RX_UNDERRUN_BIT) {
268 dev_err(dev->class_dev, "rx fifo underrun\n");
269 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
272 if (devpriv->dio_count == 0)
273 async->events |= COMEDI_CB_EOA;
275 comedi_handle_events(dev, s);
280 static void gsc_hpdi_abort_dma(struct comedi_device *dev, unsigned int channel)
282 struct hpdi_private *devpriv = dev->private;
285 /* spinlock for plx dma control/status reg */
286 spin_lock_irqsave(&dev->spinlock, flags);
288 plx9080_abort_dma(devpriv->plx9080_mmio, channel);
290 spin_unlock_irqrestore(&dev->spinlock, flags);
293 static int gsc_hpdi_cancel(struct comedi_device *dev,
294 struct comedi_subdevice *s)
296 writel(0, dev->mmio + BOARD_CONTROL_REG);
297 writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
299 gsc_hpdi_abort_dma(dev, 0);
304 static int gsc_hpdi_cmd(struct comedi_device *dev,
305 struct comedi_subdevice *s)
307 struct hpdi_private *devpriv = dev->private;
308 struct comedi_async *async = s->async;
309 struct comedi_cmd *cmd = &async->cmd;
316 writel(RX_FIFO_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
318 gsc_hpdi_abort_dma(dev, 0);
320 devpriv->dma_desc_index = 0;
323 * These register are supposedly unused during chained dma,
324 * but I have found that left over values from last operation
325 * occasionally cause problems with transfer of first dma
326 * block. Initializing them to zero seems to fix the problem.
328 writel(0, devpriv->plx9080_mmio + PLX_DMA0_TRANSFER_SIZE_REG);
329 writel(0, devpriv->plx9080_mmio + PLX_DMA0_PCI_ADDRESS_REG);
330 writel(0, devpriv->plx9080_mmio + PLX_DMA0_LOCAL_ADDRESS_REG);
332 /* give location of first dma descriptor */
333 bits = devpriv->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
334 PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
335 writel(bits, devpriv->plx9080_mmio + PLX_DMA0_DESCRIPTOR_REG);
337 /* enable dma transfer */
338 spin_lock_irqsave(&dev->spinlock, flags);
339 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
340 devpriv->plx9080_mmio + PLX_DMA0_CS_REG);
341 spin_unlock_irqrestore(&dev->spinlock, flags);
343 if (cmd->stop_src == TRIG_COUNT)
344 devpriv->dio_count = cmd->stop_arg;
346 devpriv->dio_count = 1;
348 /* clear over/under run status flags */
349 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT, dev->mmio + BOARD_STATUS_REG);
351 /* enable interrupts */
352 writel(RX_FULL_INTR, dev->mmio + INTERRUPT_CONTROL_REG);
354 writel(RX_ENABLE_BIT, dev->mmio + BOARD_CONTROL_REG);
359 static int gsc_hpdi_check_chanlist(struct comedi_device *dev,
360 struct comedi_subdevice *s,
361 struct comedi_cmd *cmd)
365 for (i = 0; i < cmd->chanlist_len; i++) {
366 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
369 dev_dbg(dev->class_dev,
370 "chanlist must be ch 0 to 31 in order\n");
378 static int gsc_hpdi_cmd_test(struct comedi_device *dev,
379 struct comedi_subdevice *s,
380 struct comedi_cmd *cmd)
387 /* Step 1 : check if triggers are trivially valid */
389 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
390 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
391 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
392 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
393 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
398 /* Step 2a : make sure trigger sources are unique */
400 err |= cfc_check_trigger_is_unique(cmd->stop_src);
402 /* Step 2b : and mutually compatible */
407 /* Step 3: check if arguments are trivially valid */
409 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
411 if (!cmd->chanlist_len || !cmd->chanlist) {
412 cmd->chanlist_len = 32;
415 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
417 if (cmd->stop_src == TRIG_COUNT)
418 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
420 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
425 /* Step 4: fix up any arguments */
427 /* Step 5: check channel list if it exists */
429 if (cmd->chanlist && cmd->chanlist_len > 0)
430 err |= gsc_hpdi_check_chanlist(dev, s, cmd);
439 /* setup dma descriptors so a link completes every 'len' bytes */
440 static int gsc_hpdi_setup_dma_descriptors(struct comedi_device *dev,
443 struct hpdi_private *devpriv = dev->private;
444 dma_addr_t phys_addr = devpriv->dma_desc_phys_addr;
445 uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
446 PLX_XFER_LOCAL_TO_PCI;
447 unsigned int offset = 0;
448 unsigned int idx = 0;
451 if (len > DMA_BUFFER_SIZE)
452 len = DMA_BUFFER_SIZE;
453 len -= len % sizeof(uint32_t);
457 for (i = 0; i < NUM_DMA_DESCRIPTORS && idx < NUM_DMA_BUFFERS; i++) {
458 devpriv->dma_desc[i].pci_start_addr =
459 cpu_to_le32(devpriv->dio_buffer_phys_addr[idx] + offset);
460 devpriv->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
461 devpriv->dma_desc[i].transfer_size = cpu_to_le32(len);
462 devpriv->dma_desc[i].next = cpu_to_le32((phys_addr +
463 (i + 1) * sizeof(devpriv->dma_desc[0])) | next_bits);
465 devpriv->desc_dio_buffer[i] = devpriv->dio_buffer[idx] +
466 (offset / sizeof(uint32_t));
469 if (len + offset > DMA_BUFFER_SIZE) {
474 devpriv->num_dma_descriptors = i;
475 /* fix last descriptor to point back to first */
476 devpriv->dma_desc[i - 1].next = cpu_to_le32(phys_addr | next_bits);
478 devpriv->block_size = len;
483 static int gsc_hpdi_dio_insn_config(struct comedi_device *dev,
484 struct comedi_subdevice *s,
485 struct comedi_insn *insn,
491 case INSN_CONFIG_BLOCK_SIZE:
492 ret = gsc_hpdi_setup_dma_descriptors(dev, data[1]);
499 ret = comedi_dio_insn_config(dev, s, insn, data, 0xffffffff);
508 static void gsc_hpdi_free_dma(struct comedi_device *dev)
510 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
511 struct hpdi_private *devpriv = dev->private;
517 /* free pci dma buffers */
518 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
519 if (devpriv->dio_buffer[i])
520 pci_free_consistent(pcidev,
522 devpriv->dio_buffer[i],
523 devpriv->dio_buffer_phys_addr[i]);
525 /* free dma descriptors */
526 if (devpriv->dma_desc)
527 pci_free_consistent(pcidev,
528 sizeof(struct plx_dma_desc) *
531 devpriv->dma_desc_phys_addr);
534 static int gsc_hpdi_init(struct comedi_device *dev)
536 struct hpdi_private *devpriv = dev->private;
537 uint32_t plx_intcsr_bits;
539 /* wait 10usec after reset before accessing fifos */
540 writel(BOARD_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
543 writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
544 dev->mmio + RX_PROG_ALMOST_REG);
545 writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
546 dev->mmio + TX_PROG_ALMOST_REG);
548 devpriv->tx_fifo_size = readl(dev->mmio + TX_FIFO_SIZE_REG) &
550 devpriv->rx_fifo_size = readl(dev->mmio + RX_FIFO_SIZE_REG) &
553 writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
555 /* enable interrupts */
557 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
559 writel(plx_intcsr_bits, devpriv->plx9080_mmio + PLX_INTRCS_REG);
564 static void gsc_hpdi_init_plx9080(struct comedi_device *dev)
566 struct hpdi_private *devpriv = dev->private;
568 void __iomem *plx_iobase = devpriv->plx9080_mmio;
571 bits = BIGEND_DMA0 | BIGEND_DMA1;
575 writel(bits, devpriv->plx9080_mmio + PLX_BIGEND_REG);
577 writel(0, devpriv->plx9080_mmio + PLX_INTRCS_REG);
579 gsc_hpdi_abort_dma(dev, 0);
580 gsc_hpdi_abort_dma(dev, 1);
582 /* configure dma0 mode */
584 /* enable ready input */
585 bits |= PLX_DMA_EN_READYIN_BIT;
586 /* enable dma chaining */
587 bits |= PLX_EN_CHAIN_BIT;
588 /* enable interrupt on dma done
589 * (probably don't need this, since chain never finishes) */
590 bits |= PLX_EN_DMA_DONE_INTR_BIT;
591 /* don't increment local address during transfers
592 * (we are transferring from a fixed fifo register) */
593 bits |= PLX_LOCAL_ADDR_CONST_BIT;
594 /* route dma interrupt to pci bus */
595 bits |= PLX_DMA_INTR_PCI_BIT;
596 /* enable demand mode */
597 bits |= PLX_DEMAND_MODE_BIT;
598 /* enable local burst mode */
599 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
600 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
601 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
604 static const struct hpdi_board *gsc_hpdi_find_board(struct pci_dev *pcidev)
608 for (i = 0; i < ARRAY_SIZE(hpdi_boards); i++)
609 if (pcidev->device == hpdi_boards[i].device_id &&
610 pcidev->subsystem_device == hpdi_boards[i].subdevice_id)
611 return &hpdi_boards[i];
615 static int gsc_hpdi_auto_attach(struct comedi_device *dev,
616 unsigned long context_unused)
618 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
619 const struct hpdi_board *thisboard;
620 struct hpdi_private *devpriv;
621 struct comedi_subdevice *s;
625 thisboard = gsc_hpdi_find_board(pcidev);
627 dev_err(dev->class_dev, "gsc_hpdi: pci %s not supported\n",
631 dev->board_ptr = thisboard;
632 dev->board_name = thisboard->name;
634 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
638 retval = comedi_pci_enable(dev);
641 pci_set_master(pcidev);
643 devpriv->plx9080_mmio = pci_ioremap_bar(pcidev, 0);
644 dev->mmio = pci_ioremap_bar(pcidev, 2);
645 if (!devpriv->plx9080_mmio || !dev->mmio) {
646 dev_warn(dev->class_dev, "failed to remap io memory\n");
650 gsc_hpdi_init_plx9080(dev);
653 if (request_irq(pcidev->irq, gsc_hpdi_interrupt, IRQF_SHARED,
654 dev->board_name, dev)) {
655 dev_warn(dev->class_dev,
656 "unable to allocate irq %u\n", pcidev->irq);
659 dev->irq = pcidev->irq;
661 dev_dbg(dev->class_dev, " irq %u\n", dev->irq);
663 /* allocate pci dma buffers */
664 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
665 devpriv->dio_buffer[i] =
666 pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
667 &devpriv->dio_buffer_phys_addr[i]);
669 /* allocate dma descriptors */
670 devpriv->dma_desc = pci_alloc_consistent(pcidev,
671 sizeof(struct plx_dma_desc) *
673 &devpriv->dma_desc_phys_addr);
674 if (devpriv->dma_desc_phys_addr & 0xf) {
675 dev_warn(dev->class_dev,
676 " dma descriptors not quad-word aligned (bug)\n");
680 retval = gsc_hpdi_setup_dma_descriptors(dev, 0x1000);
684 retval = comedi_alloc_subdevices(dev, 1);
688 /* Digital I/O subdevice */
689 s = &dev->subdevices[0];
690 dev->read_subdev = s;
691 s->type = COMEDI_SUBD_DIO;
692 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
695 s->len_chanlist = 32;
697 s->range_table = &range_digital;
698 s->insn_config = gsc_hpdi_dio_insn_config;
699 s->do_cmd = gsc_hpdi_cmd;
700 s->do_cmdtest = gsc_hpdi_cmd_test;
701 s->cancel = gsc_hpdi_cancel;
703 return gsc_hpdi_init(dev);
706 static void gsc_hpdi_detach(struct comedi_device *dev)
708 struct hpdi_private *devpriv = dev->private;
711 free_irq(dev->irq, dev);
713 if (devpriv->plx9080_mmio) {
714 writel(0, devpriv->plx9080_mmio + PLX_INTRCS_REG);
715 iounmap(devpriv->plx9080_mmio);
720 comedi_pci_disable(dev);
721 gsc_hpdi_free_dma(dev);
724 static struct comedi_driver gsc_hpdi_driver = {
725 .driver_name = "gsc_hpdi",
726 .module = THIS_MODULE,
727 .auto_attach = gsc_hpdi_auto_attach,
728 .detach = gsc_hpdi_detach,
731 static int gsc_hpdi_pci_probe(struct pci_dev *dev,
732 const struct pci_device_id *id)
734 return comedi_pci_auto_config(dev, &gsc_hpdi_driver, id->driver_data);
737 static const struct pci_device_id gsc_hpdi_pci_table[] = {
738 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
742 MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table);
744 static struct pci_driver gsc_hpdi_pci_driver = {
746 .id_table = gsc_hpdi_pci_table,
747 .probe = gsc_hpdi_pci_probe,
748 .remove = comedi_pci_auto_unconfig,
750 module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver);
752 MODULE_AUTHOR("Comedi http://www.comedi.org");
753 MODULE_DESCRIPTION("Comedi low-level driver");
754 MODULE_LICENSE("GPL");