2 comedi/drivers/me4000.c
3 Source code for the Meilhaus ME-4000 board family.
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
20 Description: Meilhaus ME-4000 series boards
21 Devices: [Meilhaus] ME-4650 (me4000), ME-4670i, ME-4680, ME-4680i, ME-4680is
22 Author: gg (Guenter Gebhardt <g.gebhardt@meilhaus.com>)
23 Updated: Mon, 18 Mar 2002 15:34:01 -0800
24 Status: broken (no support for loading firmware)
33 Configuration Options: not applicable, uses PCI auto config
35 The firmware required by these boards is available in the
36 comedi_nonfree_firmware tarball available from
37 http://www.comedi.org. However, the driver's support for
38 loading the firmware through comedi_config is currently
43 #include <linux/module.h>
44 #include <linux/pci.h>
45 #include <linux/delay.h>
46 #include <linux/interrupt.h>
47 #include <linux/list.h>
48 #include <linux/spinlock.h>
50 #include "../comedidev.h"
52 #include "comedi_fc.h"
57 /* file removed due to GPL incompatibility */
58 #include "me4000_fw.h"
62 * ME4000 Register map and bit defines
64 #define ME4000_AO_CHAN(x) ((x) * 0x18)
66 #define ME4000_AO_CTRL_REG(x) (0x00 + ME4000_AO_CHAN(x))
67 #define ME4000_AO_CTRL_BIT_MODE_0 (1 << 0)
68 #define ME4000_AO_CTRL_BIT_MODE_1 (1 << 1)
69 #define ME4000_AO_CTRL_MASK_MODE (3 << 0)
70 #define ME4000_AO_CTRL_BIT_STOP (1 << 2)
71 #define ME4000_AO_CTRL_BIT_ENABLE_FIFO (1 << 3)
72 #define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG (1 << 4)
73 #define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE (1 << 5)
74 #define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP (1 << 7)
75 #define ME4000_AO_CTRL_BIT_ENABLE_DO (1 << 8)
76 #define ME4000_AO_CTRL_BIT_ENABLE_IRQ (1 << 9)
77 #define ME4000_AO_CTRL_BIT_RESET_IRQ (1 << 10)
78 #define ME4000_AO_STATUS_REG(x) (0x04 + ME4000_AO_CHAN(x))
79 #define ME4000_AO_STATUS_BIT_FSM (1 << 0)
80 #define ME4000_AO_STATUS_BIT_FF (1 << 1)
81 #define ME4000_AO_STATUS_BIT_HF (1 << 2)
82 #define ME4000_AO_STATUS_BIT_EF (1 << 3)
83 #define ME4000_AO_FIFO_REG(x) (0x08 + ME4000_AO_CHAN(x))
84 #define ME4000_AO_SINGLE_REG(x) (0x0c + ME4000_AO_CHAN(x))
85 #define ME4000_AO_TIMER_REG(x) (0x10 + ME4000_AO_CHAN(x))
86 #define ME4000_AI_CTRL_REG 0x74
87 #define ME4000_AI_STATUS_REG 0x74
88 #define ME4000_AI_CTRL_BIT_MODE_0 (1 << 0)
89 #define ME4000_AI_CTRL_BIT_MODE_1 (1 << 1)
90 #define ME4000_AI_CTRL_BIT_MODE_2 (1 << 2)
91 #define ME4000_AI_CTRL_BIT_SAMPLE_HOLD (1 << 3)
92 #define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP (1 << 4)
93 #define ME4000_AI_CTRL_BIT_STOP (1 << 5)
94 #define ME4000_AI_CTRL_BIT_CHANNEL_FIFO (1 << 6)
95 #define ME4000_AI_CTRL_BIT_DATA_FIFO (1 << 7)
96 #define ME4000_AI_CTRL_BIT_FULLSCALE (1 << 8)
97 #define ME4000_AI_CTRL_BIT_OFFSET (1 << 9)
98 #define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG (1 << 10)
99 #define ME4000_AI_CTRL_BIT_EX_TRIG (1 << 11)
100 #define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING (1 << 12)
101 #define ME4000_AI_CTRL_BIT_EX_IRQ (1 << 13)
102 #define ME4000_AI_CTRL_BIT_EX_IRQ_RESET (1 << 14)
103 #define ME4000_AI_CTRL_BIT_LE_IRQ (1 << 15)
104 #define ME4000_AI_CTRL_BIT_LE_IRQ_RESET (1 << 16)
105 #define ME4000_AI_CTRL_BIT_HF_IRQ (1 << 17)
106 #define ME4000_AI_CTRL_BIT_HF_IRQ_RESET (1 << 18)
107 #define ME4000_AI_CTRL_BIT_SC_IRQ (1 << 19)
108 #define ME4000_AI_CTRL_BIT_SC_IRQ_RESET (1 << 20)
109 #define ME4000_AI_CTRL_BIT_SC_RELOAD (1 << 21)
110 #define ME4000_AI_STATUS_BIT_EF_CHANNEL (1 << 22)
111 #define ME4000_AI_STATUS_BIT_HF_CHANNEL (1 << 23)
112 #define ME4000_AI_STATUS_BIT_FF_CHANNEL (1 << 24)
113 #define ME4000_AI_STATUS_BIT_EF_DATA (1 << 25)
114 #define ME4000_AI_STATUS_BIT_HF_DATA (1 << 26)
115 #define ME4000_AI_STATUS_BIT_FF_DATA (1 << 27)
116 #define ME4000_AI_STATUS_BIT_LE (1 << 28)
117 #define ME4000_AI_STATUS_BIT_FSM (1 << 29)
118 #define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH (1 << 31)
119 #define ME4000_AI_CHANNEL_LIST_REG 0x78
120 #define ME4000_AI_LIST_INPUT_SINGLE_ENDED (0 << 5)
121 #define ME4000_AI_LIST_INPUT_DIFFERENTIAL (1 << 5)
122 #define ME4000_AI_LIST_RANGE_BIPOLAR_10 (0 << 6)
123 #define ME4000_AI_LIST_RANGE_BIPOLAR_2_5 (1 << 6)
124 #define ME4000_AI_LIST_RANGE_UNIPOLAR_10 (2 << 6)
125 #define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5 (3 << 6)
126 #define ME4000_AI_LIST_LAST_ENTRY (1 << 8)
127 #define ME4000_AI_DATA_REG 0x7c
128 #define ME4000_AI_CHAN_TIMER_REG 0x80
129 #define ME4000_AI_CHAN_PRE_TIMER_REG 0x84
130 #define ME4000_AI_SCAN_TIMER_LOW_REG 0x88
131 #define ME4000_AI_SCAN_TIMER_HIGH_REG 0x8c
132 #define ME4000_AI_SCAN_PRE_TIMER_LOW_REG 0x90
133 #define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG 0x94
134 #define ME4000_AI_START_REG 0x98
135 #define ME4000_IRQ_STATUS_REG 0x9c
136 #define ME4000_IRQ_STATUS_BIT_EX (1 << 0)
137 #define ME4000_IRQ_STATUS_BIT_LE (1 << 1)
138 #define ME4000_IRQ_STATUS_BIT_AI_HF (1 << 2)
139 #define ME4000_IRQ_STATUS_BIT_AO_0_HF (1 << 3)
140 #define ME4000_IRQ_STATUS_BIT_AO_1_HF (1 << 4)
141 #define ME4000_IRQ_STATUS_BIT_AO_2_HF (1 << 5)
142 #define ME4000_IRQ_STATUS_BIT_AO_3_HF (1 << 6)
143 #define ME4000_IRQ_STATUS_BIT_SC (1 << 7)
144 #define ME4000_DIO_PORT_0_REG 0xa0
145 #define ME4000_DIO_PORT_1_REG 0xa4
146 #define ME4000_DIO_PORT_2_REG 0xa8
147 #define ME4000_DIO_PORT_3_REG 0xac
148 #define ME4000_DIO_DIR_REG 0xb0
149 #define ME4000_AO_LOADSETREG_XX 0xb4
150 #define ME4000_DIO_CTRL_REG 0xb8
151 #define ME4000_DIO_CTRL_BIT_MODE_0 (1 << 0)
152 #define ME4000_DIO_CTRL_BIT_MODE_1 (1 << 1)
153 #define ME4000_DIO_CTRL_BIT_MODE_2 (1 << 2)
154 #define ME4000_DIO_CTRL_BIT_MODE_3 (1 << 3)
155 #define ME4000_DIO_CTRL_BIT_MODE_4 (1 << 4)
156 #define ME4000_DIO_CTRL_BIT_MODE_5 (1 << 5)
157 #define ME4000_DIO_CTRL_BIT_MODE_6 (1 << 6)
158 #define ME4000_DIO_CTRL_BIT_MODE_7 (1 << 7)
159 #define ME4000_DIO_CTRL_BIT_FUNCTION_0 (1 << 8)
160 #define ME4000_DIO_CTRL_BIT_FUNCTION_1 (1 << 9)
161 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0 (1 << 10)
162 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1 (1 << 11)
163 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2 (1 << 12)
164 #define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3 (1 << 13)
165 #define ME4000_AO_DEMUX_ADJUST_REG 0xbc
166 #define ME4000_AO_DEMUX_ADJUST_VALUE 0x4c
167 #define ME4000_AI_SAMPLE_COUNTER_REG 0xc0
169 #define ME4000_AI_FIFO_COUNT 2048
171 #define ME4000_AI_MIN_TICKS 66
172 #define ME4000_AI_MIN_SAMPLE_TIME 2000
173 #define ME4000_AI_BASE_FREQUENCY (unsigned int) 33E6
175 #define ME4000_AI_CHANNEL_LIST_COUNT 1024
178 unsigned long plx_regbase;
179 unsigned long timer_regbase;
181 unsigned int ao_readback[4];
184 enum me4000_boardid {
200 struct me4000_board {
212 static const struct me4000_board me4000_boards[] = {
330 static const struct comedi_lrange me4000_ai_range = {
339 #define FIRMWARE_NOT_AVAILABLE 1
340 #if FIRMWARE_NOT_AVAILABLE
341 extern unsigned char *xilinx_firm;
344 static int xilinx_download(struct comedi_device *dev)
346 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
347 struct me4000_info *info = dev->private;
348 unsigned long xilinx_iobase = pci_resource_start(pcidev, 5);
350 wait_queue_head_t queue;
358 init_waitqueue_head(&queue);
361 * Set PLX local interrupt 2 polarity to high.
362 * Interrupt is thrown by init pin of xilinx.
364 outl(PLX9052_INTCSR_LI2POL, info->plx_regbase + PLX9052_INTCSR);
366 /* Set /CS and /WRITE of the Xilinx */
367 value = inl(info->plx_regbase + PLX9052_CNTRL);
368 value |= PLX9052_CNTRL_UIO2_DATA;
369 outl(value, info->plx_regbase + PLX9052_CNTRL);
371 /* Init Xilinx with CS1 */
372 inb(xilinx_iobase + 0xC8);
374 /* Wait until /INIT pin is set */
376 intcsr = inl(info->plx_regbase + PLX9052_INTCSR);
377 if (!(intcsr & PLX9052_INTCSR_LI2STAT)) {
378 dev_err(dev->class_dev, "Can't init Xilinx\n");
382 /* Reset /CS and /WRITE of the Xilinx */
383 value = inl(info->plx_regbase + PLX9052_CNTRL);
384 value &= ~PLX9052_CNTRL_UIO2_DATA;
385 outl(value, info->plx_regbase + PLX9052_CNTRL);
386 if (FIRMWARE_NOT_AVAILABLE) {
387 dev_err(dev->class_dev,
388 "xilinx firmware unavailable due to licensing, aborting");
391 /* Download Xilinx firmware */
392 size = (xilinx_firm[0] << 24) + (xilinx_firm[1] << 16) +
393 (xilinx_firm[2] << 8) + xilinx_firm[3];
396 for (idx = 0; idx < size; idx++) {
397 outb(xilinx_firm[16 + idx], xilinx_iobase);
400 /* Check if BUSY flag is low */
401 if (inl(info->plx_regbase + PLX9052_CNTRL) & PLX9052_CNTRL_UIO1_DATA) {
402 dev_err(dev->class_dev,
403 "Xilinx is still busy (idx = %d)\n",
410 /* If done flag is high download was successful */
411 if (inl(info->plx_regbase + PLX9052_CNTRL) & PLX9052_CNTRL_UIO0_DATA) {
413 dev_err(dev->class_dev, "DONE flag is not set\n");
414 dev_err(dev->class_dev, "Download not successful\n");
418 /* Set /CS and /WRITE */
419 value = inl(info->plx_regbase + PLX9052_CNTRL);
420 value |= PLX9052_CNTRL_UIO2_DATA;
421 outl(value, info->plx_regbase + PLX9052_CNTRL);
426 static void me4000_reset(struct comedi_device *dev)
428 struct me4000_info *info = dev->private;
432 /* Make a hardware reset */
433 val = inl(info->plx_regbase + PLX9052_CNTRL);
434 val |= PLX9052_CNTRL_PCI_RESET;
435 outl(val, info->plx_regbase + PLX9052_CNTRL);
436 val &= ~PLX9052_CNTRL_PCI_RESET;
437 outl(val , info->plx_regbase + PLX9052_CNTRL);
439 /* 0x8000 to the DACs means an output voltage of 0V */
440 for (chan = 0; chan < 4; chan++)
441 outl(0x8000, dev->iobase + ME4000_AO_SINGLE_REG(chan));
443 /* Set both stop bits in the analog input control register */
444 outl(ME4000_AI_CTRL_BIT_IMMEDIATE_STOP | ME4000_AI_CTRL_BIT_STOP,
445 dev->iobase + ME4000_AI_CTRL_REG);
447 /* Set both stop bits in the analog output control register */
448 val = ME4000_AO_CTRL_BIT_IMMEDIATE_STOP | ME4000_AO_CTRL_BIT_STOP;
449 for (chan = 0; chan < 4; chan++)
450 outl(val, dev->iobase + ME4000_AO_CTRL_REG(chan));
452 /* Enable interrupts on the PLX */
453 outl(PLX9052_INTCSR_LI1ENAB |
454 PLX9052_INTCSR_LI1POL |
455 PLX9052_INTCSR_PCIENAB, info->plx_regbase + PLX9052_INTCSR);
457 /* Set the adustment register for AO demux */
458 outl(ME4000_AO_DEMUX_ADJUST_VALUE,
459 dev->iobase + ME4000_AO_DEMUX_ADJUST_REG);
462 * Set digital I/O direction for port 0
463 * to output on isolated versions
465 if (!(inl(dev->iobase + ME4000_DIO_DIR_REG) & 0x1))
466 outl(0x1, dev->iobase + ME4000_DIO_CTRL_REG);
469 /*=============================================================================
471 ===========================================================================*/
473 static int me4000_ai_insn_read(struct comedi_device *dev,
474 struct comedi_subdevice *subdevice,
475 struct comedi_insn *insn, unsigned int *data)
477 const struct me4000_board *thisboard = comedi_board(dev);
478 int chan = CR_CHAN(insn->chanspec);
479 int rang = CR_RANGE(insn->chanspec);
480 int aref = CR_AREF(insn->chanspec);
482 unsigned int entry = 0;
488 } else if (insn->n > 1) {
489 dev_err(dev->class_dev, "Invalid instruction length %d\n",
496 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5;
499 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_10;
502 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_2_5;
505 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_10;
508 dev_err(dev->class_dev, "Invalid range specified\n");
515 if (chan >= thisboard->ai_nchan) {
516 dev_err(dev->class_dev,
517 "Analog input is not available\n");
520 entry |= ME4000_AI_LIST_INPUT_SINGLE_ENDED | chan;
524 if (rang == 0 || rang == 1) {
525 dev_err(dev->class_dev,
526 "Range must be bipolar when aref = diff\n");
530 if (chan >= thisboard->ai_diff_nchan) {
531 dev_err(dev->class_dev,
532 "Analog input is not available\n");
535 entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL | chan;
538 dev_err(dev->class_dev, "Invalid aref specified\n");
542 entry |= ME4000_AI_LIST_LAST_ENTRY;
544 /* Clear channel list, data fifo and both stop bits */
545 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
546 tmp &= ~(ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
547 ME4000_AI_CTRL_BIT_DATA_FIFO |
548 ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
549 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
551 /* Set the acquisition mode to single */
552 tmp &= ~(ME4000_AI_CTRL_BIT_MODE_0 | ME4000_AI_CTRL_BIT_MODE_1 |
553 ME4000_AI_CTRL_BIT_MODE_2);
554 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
556 /* Enable channel list and data fifo */
557 tmp |= ME4000_AI_CTRL_BIT_CHANNEL_FIFO | ME4000_AI_CTRL_BIT_DATA_FIFO;
558 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
560 /* Generate channel list entry */
561 outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
563 /* Set the timer to maximum sample rate */
564 outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
565 outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
567 /* Start conversion by dummy read */
568 inl(dev->iobase + ME4000_AI_START_REG);
570 /* Wait until ready */
572 if (!(inl(dev->iobase + ME4000_AI_STATUS_REG) &
573 ME4000_AI_STATUS_BIT_EF_DATA)) {
574 dev_err(dev->class_dev, "Value not available after wait\n");
578 /* Read value from data fifo */
579 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
580 data[0] = lval ^ 0x8000;
585 static int me4000_ai_cancel(struct comedi_device *dev,
586 struct comedi_subdevice *s)
590 /* Stop any running conversion */
591 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
592 tmp &= ~(ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
593 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
595 /* Clear the control register */
596 outl(0x0, dev->iobase + ME4000_AI_CTRL_REG);
601 static int ai_check_chanlist(struct comedi_device *dev,
602 struct comedi_subdevice *s, struct comedi_cmd *cmd)
604 const struct me4000_board *thisboard = comedi_board(dev);
608 /* Check whether a channel list is available */
609 if (!cmd->chanlist_len) {
610 dev_err(dev->class_dev, "No channel list available\n");
614 /* Check the channel list size */
615 if (cmd->chanlist_len > ME4000_AI_CHANNEL_LIST_COUNT) {
616 dev_err(dev->class_dev, "Channel list is to large\n");
620 /* Check the pointer */
621 if (!cmd->chanlist) {
622 dev_err(dev->class_dev, "NULL pointer to channel list\n");
626 /* Check whether aref is equal for all entries */
627 aref = CR_AREF(cmd->chanlist[0]);
628 for (i = 0; i < cmd->chanlist_len; i++) {
629 if (CR_AREF(cmd->chanlist[i]) != aref) {
630 dev_err(dev->class_dev,
631 "Mode is not equal for all entries\n");
636 /* Check whether channels are available for this ending */
637 if (aref == SDF_DIFF) {
638 for (i = 0; i < cmd->chanlist_len; i++) {
639 if (CR_CHAN(cmd->chanlist[i]) >=
640 thisboard->ai_diff_nchan) {
641 dev_err(dev->class_dev,
642 "Channel number to high\n");
647 for (i = 0; i < cmd->chanlist_len; i++) {
648 if (CR_CHAN(cmd->chanlist[i]) >= thisboard->ai_nchan) {
649 dev_err(dev->class_dev,
650 "Channel number to high\n");
656 /* Check if bipolar is set for all entries when in differential mode */
657 if (aref == SDF_DIFF) {
658 for (i = 0; i < cmd->chanlist_len; i++) {
659 if (CR_RANGE(cmd->chanlist[i]) != 1 &&
660 CR_RANGE(cmd->chanlist[i]) != 2) {
661 dev_err(dev->class_dev,
662 "Bipolar is not selected in differential mode\n");
671 static int ai_round_cmd_args(struct comedi_device *dev,
672 struct comedi_subdevice *s,
673 struct comedi_cmd *cmd,
674 unsigned int *init_ticks,
675 unsigned int *scan_ticks, unsigned int *chan_ticks)
684 if (cmd->start_arg) {
685 *init_ticks = (cmd->start_arg * 33) / 1000;
686 rest = (cmd->start_arg * 33) % 1000;
688 if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
691 } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
697 if (cmd->scan_begin_arg) {
698 *scan_ticks = (cmd->scan_begin_arg * 33) / 1000;
699 rest = (cmd->scan_begin_arg * 33) % 1000;
701 if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
704 } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
710 if (cmd->convert_arg) {
711 *chan_ticks = (cmd->convert_arg * 33) / 1000;
712 rest = (cmd->convert_arg * 33) % 1000;
714 if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_NEAREST) {
717 } else if ((cmd->flags & TRIG_ROUND_MASK) == TRIG_ROUND_UP) {
726 static void ai_write_timer(struct comedi_device *dev,
727 unsigned int init_ticks,
728 unsigned int scan_ticks, unsigned int chan_ticks)
730 outl(init_ticks - 1, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_LOW_REG);
731 outl(0x0, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_HIGH_REG);
734 outl(scan_ticks - 1, dev->iobase + ME4000_AI_SCAN_TIMER_LOW_REG);
735 outl(0x0, dev->iobase + ME4000_AI_SCAN_TIMER_HIGH_REG);
738 outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
739 outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
742 static int ai_write_chanlist(struct comedi_device *dev,
743 struct comedi_subdevice *s, struct comedi_cmd *cmd)
751 for (i = 0; i < cmd->chanlist_len; i++) {
752 chan = CR_CHAN(cmd->chanlist[i]);
753 rang = CR_RANGE(cmd->chanlist[i]);
754 aref = CR_AREF(cmd->chanlist[i]);
759 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_2_5;
761 entry |= ME4000_AI_LIST_RANGE_UNIPOLAR_10;
763 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_2_5;
765 entry |= ME4000_AI_LIST_RANGE_BIPOLAR_10;
767 if (aref == SDF_DIFF)
768 entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL;
770 entry |= ME4000_AI_LIST_INPUT_SINGLE_ENDED;
772 outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
778 static int ai_prepare(struct comedi_device *dev,
779 struct comedi_subdevice *s,
780 struct comedi_cmd *cmd,
781 unsigned int init_ticks,
782 unsigned int scan_ticks, unsigned int chan_ticks)
785 unsigned int tmp = 0;
787 /* Write timer arguments */
788 ai_write_timer(dev, init_ticks, scan_ticks, chan_ticks);
790 /* Reset control register */
791 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
794 if ((cmd->start_src == TRIG_EXT &&
795 cmd->scan_begin_src == TRIG_TIMER &&
796 cmd->convert_src == TRIG_TIMER) ||
797 (cmd->start_src == TRIG_EXT &&
798 cmd->scan_begin_src == TRIG_FOLLOW &&
799 cmd->convert_src == TRIG_TIMER)) {
800 tmp = ME4000_AI_CTRL_BIT_MODE_1 |
801 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
802 ME4000_AI_CTRL_BIT_DATA_FIFO;
803 } else if (cmd->start_src == TRIG_EXT &&
804 cmd->scan_begin_src == TRIG_EXT &&
805 cmd->convert_src == TRIG_TIMER) {
806 tmp = ME4000_AI_CTRL_BIT_MODE_2 |
807 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
808 ME4000_AI_CTRL_BIT_DATA_FIFO;
809 } else if (cmd->start_src == TRIG_EXT &&
810 cmd->scan_begin_src == TRIG_EXT &&
811 cmd->convert_src == TRIG_EXT) {
812 tmp = ME4000_AI_CTRL_BIT_MODE_0 |
813 ME4000_AI_CTRL_BIT_MODE_1 |
814 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
815 ME4000_AI_CTRL_BIT_DATA_FIFO;
817 tmp = ME4000_AI_CTRL_BIT_MODE_0 |
818 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
819 ME4000_AI_CTRL_BIT_DATA_FIFO;
823 if (cmd->stop_src == TRIG_COUNT) {
824 outl(cmd->chanlist_len * cmd->stop_arg,
825 dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
826 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
827 } else if (cmd->stop_src == TRIG_NONE &&
828 cmd->scan_end_src == TRIG_COUNT) {
829 outl(cmd->scan_end_arg,
830 dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
831 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
833 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ;
836 /* Write the setup to the control register */
837 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
839 /* Write the channel list */
840 ai_write_chanlist(dev, s, cmd);
845 static int me4000_ai_do_cmd(struct comedi_device *dev,
846 struct comedi_subdevice *s)
849 unsigned int init_ticks = 0;
850 unsigned int scan_ticks = 0;
851 unsigned int chan_ticks = 0;
852 struct comedi_cmd *cmd = &s->async->cmd;
854 /* Reset the analog input */
855 err = me4000_ai_cancel(dev, s);
859 /* Round the timer arguments */
860 err = ai_round_cmd_args(dev,
861 s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
865 /* Prepare the AI for acquisition */
866 err = ai_prepare(dev, s, cmd, init_ticks, scan_ticks, chan_ticks);
870 /* Start acquistion by dummy read */
871 inl(dev->iobase + ME4000_AI_START_REG);
876 static int me4000_ai_do_cmd_test(struct comedi_device *dev,
877 struct comedi_subdevice *s,
878 struct comedi_cmd *cmd)
881 unsigned int init_ticks;
882 unsigned int chan_ticks;
883 unsigned int scan_ticks;
886 /* Only rounding flags are implemented */
887 cmd->flags &= TRIG_ROUND_NEAREST | TRIG_ROUND_UP | TRIG_ROUND_DOWN;
889 /* Round the timer arguments */
890 ai_round_cmd_args(dev, s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
892 /* Step 1 : check if triggers are trivially valid */
894 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
895 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
896 TRIG_FOLLOW | TRIG_TIMER | TRIG_EXT);
897 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
898 err |= cfc_check_trigger_src(&cmd->scan_end_src,
899 TRIG_NONE | TRIG_COUNT);
900 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE | TRIG_COUNT);
905 /* Step 2a : make sure trigger sources are unique */
907 err |= cfc_check_trigger_is_unique(cmd->start_src);
908 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
909 err |= cfc_check_trigger_is_unique(cmd->convert_src);
910 err |= cfc_check_trigger_is_unique(cmd->scan_end_src);
911 err |= cfc_check_trigger_is_unique(cmd->stop_src);
913 /* Step 2b : and mutually compatible */
915 if (cmd->start_src == TRIG_NOW &&
916 cmd->scan_begin_src == TRIG_TIMER &&
917 cmd->convert_src == TRIG_TIMER) {
918 } else if (cmd->start_src == TRIG_NOW &&
919 cmd->scan_begin_src == TRIG_FOLLOW &&
920 cmd->convert_src == TRIG_TIMER) {
921 } else if (cmd->start_src == TRIG_EXT &&
922 cmd->scan_begin_src == TRIG_TIMER &&
923 cmd->convert_src == TRIG_TIMER) {
924 } else if (cmd->start_src == TRIG_EXT &&
925 cmd->scan_begin_src == TRIG_FOLLOW &&
926 cmd->convert_src == TRIG_TIMER) {
927 } else if (cmd->start_src == TRIG_EXT &&
928 cmd->scan_begin_src == TRIG_EXT &&
929 cmd->convert_src == TRIG_TIMER) {
930 } else if (cmd->start_src == TRIG_EXT &&
931 cmd->scan_begin_src == TRIG_EXT &&
932 cmd->convert_src == TRIG_EXT) {
937 if (cmd->stop_src == TRIG_NONE && cmd->scan_end_src == TRIG_NONE) {
938 } else if (cmd->stop_src == TRIG_COUNT &&
939 cmd->scan_end_src == TRIG_NONE) {
940 } else if (cmd->stop_src == TRIG_NONE &&
941 cmd->scan_end_src == TRIG_COUNT) {
942 } else if (cmd->stop_src == TRIG_COUNT &&
943 cmd->scan_end_src == TRIG_COUNT) {
951 /* Step 3: check if arguments are trivially valid */
953 if (cmd->chanlist_len < 1) {
954 cmd->chanlist_len = 1;
957 if (init_ticks < 66) {
958 cmd->start_arg = 2000;
961 if (scan_ticks && scan_ticks < 67) {
962 cmd->scan_begin_arg = 2031;
965 if (chan_ticks < 66) {
966 cmd->convert_arg = 2000;
974 * Stage 4. Check for argument conflicts.
976 if (cmd->start_src == TRIG_NOW &&
977 cmd->scan_begin_src == TRIG_TIMER &&
978 cmd->convert_src == TRIG_TIMER) {
980 /* Check timer arguments */
981 if (init_ticks < ME4000_AI_MIN_TICKS) {
982 dev_err(dev->class_dev, "Invalid start arg\n");
983 cmd->start_arg = 2000; /* 66 ticks at least */
986 if (chan_ticks < ME4000_AI_MIN_TICKS) {
987 dev_err(dev->class_dev, "Invalid convert arg\n");
988 cmd->convert_arg = 2000; /* 66 ticks at least */
991 if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
992 dev_err(dev->class_dev, "Invalid scan end arg\n");
994 /* At least one tick more */
995 cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
998 } else if (cmd->start_src == TRIG_NOW &&
999 cmd->scan_begin_src == TRIG_FOLLOW &&
1000 cmd->convert_src == TRIG_TIMER) {
1002 /* Check timer arguments */
1003 if (init_ticks < ME4000_AI_MIN_TICKS) {
1004 dev_err(dev->class_dev, "Invalid start arg\n");
1005 cmd->start_arg = 2000; /* 66 ticks at least */
1008 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1009 dev_err(dev->class_dev, "Invalid convert arg\n");
1010 cmd->convert_arg = 2000; /* 66 ticks at least */
1013 } else if (cmd->start_src == TRIG_EXT &&
1014 cmd->scan_begin_src == TRIG_TIMER &&
1015 cmd->convert_src == TRIG_TIMER) {
1017 /* Check timer arguments */
1018 if (init_ticks < ME4000_AI_MIN_TICKS) {
1019 dev_err(dev->class_dev, "Invalid start arg\n");
1020 cmd->start_arg = 2000; /* 66 ticks at least */
1023 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1024 dev_err(dev->class_dev, "Invalid convert arg\n");
1025 cmd->convert_arg = 2000; /* 66 ticks at least */
1028 if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
1029 dev_err(dev->class_dev, "Invalid scan end arg\n");
1031 /* At least one tick more */
1032 cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
1035 } else if (cmd->start_src == TRIG_EXT &&
1036 cmd->scan_begin_src == TRIG_FOLLOW &&
1037 cmd->convert_src == TRIG_TIMER) {
1039 /* Check timer arguments */
1040 if (init_ticks < ME4000_AI_MIN_TICKS) {
1041 dev_err(dev->class_dev, "Invalid start arg\n");
1042 cmd->start_arg = 2000; /* 66 ticks at least */
1045 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1046 dev_err(dev->class_dev, "Invalid convert arg\n");
1047 cmd->convert_arg = 2000; /* 66 ticks at least */
1050 } else if (cmd->start_src == TRIG_EXT &&
1051 cmd->scan_begin_src == TRIG_EXT &&
1052 cmd->convert_src == TRIG_TIMER) {
1054 /* Check timer arguments */
1055 if (init_ticks < ME4000_AI_MIN_TICKS) {
1056 dev_err(dev->class_dev, "Invalid start arg\n");
1057 cmd->start_arg = 2000; /* 66 ticks at least */
1060 if (chan_ticks < ME4000_AI_MIN_TICKS) {
1061 dev_err(dev->class_dev, "Invalid convert arg\n");
1062 cmd->convert_arg = 2000; /* 66 ticks at least */
1065 } else if (cmd->start_src == TRIG_EXT &&
1066 cmd->scan_begin_src == TRIG_EXT &&
1067 cmd->convert_src == TRIG_EXT) {
1069 /* Check timer arguments */
1070 if (init_ticks < ME4000_AI_MIN_TICKS) {
1071 dev_err(dev->class_dev, "Invalid start arg\n");
1072 cmd->start_arg = 2000; /* 66 ticks at least */
1076 if (cmd->stop_src == TRIG_COUNT) {
1077 if (cmd->stop_arg == 0) {
1078 dev_err(dev->class_dev, "Invalid stop arg\n");
1083 if (cmd->scan_end_src == TRIG_COUNT) {
1084 if (cmd->scan_end_arg == 0) {
1085 dev_err(dev->class_dev, "Invalid scan end arg\n");
1086 cmd->scan_end_arg = 1;
1095 * Stage 5. Check the channel list.
1097 if (ai_check_chanlist(dev, s, cmd))
1103 static irqreturn_t me4000_ai_isr(int irq, void *dev_id)
1106 struct comedi_device *dev = dev_id;
1107 struct comedi_subdevice *s = dev->read_subdev;
1115 if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
1116 ME4000_IRQ_STATUS_BIT_AI_HF) {
1117 /* Read status register to find out what happened */
1118 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
1120 if (!(tmp & ME4000_AI_STATUS_BIT_FF_DATA) &&
1121 !(tmp & ME4000_AI_STATUS_BIT_HF_DATA) &&
1122 (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
1123 c = ME4000_AI_FIFO_COUNT;
1126 * FIFO overflow, so stop conversion
1127 * and disable all interrupts
1129 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1130 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1131 ME4000_AI_CTRL_BIT_SC_IRQ);
1132 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1134 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1136 dev_err(dev->class_dev, "FIFO overflow\n");
1137 } else if ((tmp & ME4000_AI_STATUS_BIT_FF_DATA)
1138 && !(tmp & ME4000_AI_STATUS_BIT_HF_DATA)
1139 && (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
1140 s->async->events |= COMEDI_CB_BLOCK;
1142 c = ME4000_AI_FIFO_COUNT / 2;
1144 dev_err(dev->class_dev,
1145 "Can't determine state of fifo\n");
1149 * Undefined state, so stop conversion
1150 * and disable all interrupts
1152 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1153 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1154 ME4000_AI_CTRL_BIT_SC_IRQ);
1155 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1157 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1159 dev_err(dev->class_dev, "Undefined FIFO state\n");
1162 for (i = 0; i < c; i++) {
1163 /* Read value from data fifo */
1164 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
1167 if (!comedi_buf_put(s->async, lval)) {
1169 * Buffer overflow, so stop conversion
1170 * and disable all interrupts
1172 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1173 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
1174 ME4000_AI_CTRL_BIT_SC_IRQ);
1175 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1177 s->async->events |= COMEDI_CB_OVERFLOW;
1179 dev_err(dev->class_dev, "Buffer overflow\n");
1185 /* Work is done, so reset the interrupt */
1186 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
1187 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1188 tmp &= ~ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
1189 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1192 if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
1193 ME4000_IRQ_STATUS_BIT_SC) {
1194 s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOA;
1197 * Acquisition is complete, so stop
1198 * conversion and disable all interrupts
1200 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
1201 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1202 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ);
1203 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1205 /* Poll data until fifo empty */
1206 while (inl(dev->iobase + ME4000_AI_CTRL_REG) &
1207 ME4000_AI_STATUS_BIT_EF_DATA) {
1208 /* Read value from data fifo */
1209 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
1212 if (!comedi_buf_put(s->async, lval)) {
1213 dev_err(dev->class_dev, "Buffer overflow\n");
1214 s->async->events |= COMEDI_CB_OVERFLOW;
1219 /* Work is done, so reset the interrupt */
1220 tmp |= ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
1221 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1222 tmp &= ~ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
1223 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
1226 if (s->async->events)
1227 comedi_event(dev, s);
1232 /*=============================================================================
1233 Analog output section
1234 ===========================================================================*/
1236 static int me4000_ao_insn_write(struct comedi_device *dev,
1237 struct comedi_subdevice *s,
1238 struct comedi_insn *insn, unsigned int *data)
1240 const struct me4000_board *thisboard = comedi_board(dev);
1241 struct me4000_info *info = dev->private;
1242 int chan = CR_CHAN(insn->chanspec);
1243 int rang = CR_RANGE(insn->chanspec);
1244 int aref = CR_AREF(insn->chanspec);
1249 } else if (insn->n > 1) {
1250 dev_err(dev->class_dev, "Invalid instruction length %d\n",
1255 if (chan >= thisboard->ao_nchan) {
1256 dev_err(dev->class_dev, "Invalid channel %d\n", insn->n);
1261 dev_err(dev->class_dev, "Invalid range %d\n", insn->n);
1265 if (aref != AREF_GROUND && aref != AREF_COMMON) {
1266 dev_err(dev->class_dev, "Invalid aref %d\n", insn->n);
1270 /* Stop any running conversion */
1271 tmp = inl(dev->iobase + ME4000_AO_CTRL_REG(chan));
1272 tmp |= ME4000_AO_CTRL_BIT_IMMEDIATE_STOP;
1273 outl(tmp, dev->iobase + ME4000_AO_CTRL_REG(chan));
1275 /* Clear control register and set to single mode */
1276 outl(0x0, dev->iobase + ME4000_AO_CTRL_REG(chan));
1278 /* Write data value */
1279 outl(data[0], dev->iobase + ME4000_AO_SINGLE_REG(chan));
1281 /* Store in the mirror */
1282 info->ao_readback[chan] = data[0];
1287 static int me4000_ao_insn_read(struct comedi_device *dev,
1288 struct comedi_subdevice *s,
1289 struct comedi_insn *insn, unsigned int *data)
1291 struct me4000_info *info = dev->private;
1292 int chan = CR_CHAN(insn->chanspec);
1296 } else if (insn->n > 1) {
1297 dev_err(dev->class_dev, "Invalid instruction length\n");
1301 data[0] = info->ao_readback[chan];
1306 static int me4000_dio_insn_bits(struct comedi_device *dev,
1307 struct comedi_subdevice *s,
1308 struct comedi_insn *insn,
1311 if (comedi_dio_update_state(s, data)) {
1312 outl((s->state >> 0) & 0xFF,
1313 dev->iobase + ME4000_DIO_PORT_0_REG);
1314 outl((s->state >> 8) & 0xFF,
1315 dev->iobase + ME4000_DIO_PORT_1_REG);
1316 outl((s->state >> 16) & 0xFF,
1317 dev->iobase + ME4000_DIO_PORT_2_REG);
1318 outl((s->state >> 24) & 0xFF,
1319 dev->iobase + ME4000_DIO_PORT_3_REG);
1322 data[1] = ((inl(dev->iobase + ME4000_DIO_PORT_0_REG) & 0xFF) << 0) |
1323 ((inl(dev->iobase + ME4000_DIO_PORT_1_REG) & 0xFF) << 8) |
1324 ((inl(dev->iobase + ME4000_DIO_PORT_2_REG) & 0xFF) << 16) |
1325 ((inl(dev->iobase + ME4000_DIO_PORT_3_REG) & 0xFF) << 24);
1330 static int me4000_dio_insn_config(struct comedi_device *dev,
1331 struct comedi_subdevice *s,
1332 struct comedi_insn *insn,
1335 unsigned int chan = CR_CHAN(insn->chanspec);
1349 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
1353 tmp = inl(dev->iobase + ME4000_DIO_CTRL_REG);
1354 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_0 | ME4000_DIO_CTRL_BIT_MODE_1 |
1355 ME4000_DIO_CTRL_BIT_MODE_2 | ME4000_DIO_CTRL_BIT_MODE_3 |
1356 ME4000_DIO_CTRL_BIT_MODE_4 | ME4000_DIO_CTRL_BIT_MODE_5 |
1357 ME4000_DIO_CTRL_BIT_MODE_6 | ME4000_DIO_CTRL_BIT_MODE_7);
1358 if (s->io_bits & 0x000000ff)
1359 tmp |= ME4000_DIO_CTRL_BIT_MODE_0;
1360 if (s->io_bits & 0x0000ff00)
1361 tmp |= ME4000_DIO_CTRL_BIT_MODE_2;
1362 if (s->io_bits & 0x00ff0000)
1363 tmp |= ME4000_DIO_CTRL_BIT_MODE_4;
1364 if (s->io_bits & 0xff000000)
1365 tmp |= ME4000_DIO_CTRL_BIT_MODE_6;
1368 * Check for optoisolated ME-4000 version.
1369 * If one the first port is a fixed output
1370 * port and the second is a fixed input port.
1372 if (inl(dev->iobase + ME4000_DIO_DIR_REG)) {
1373 s->io_bits |= 0x000000ff;
1374 s->io_bits &= ~0x0000ff00;
1375 tmp |= ME4000_DIO_CTRL_BIT_MODE_0;
1376 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_2 |
1377 ME4000_DIO_CTRL_BIT_MODE_3);
1380 outl(tmp, dev->iobase + ME4000_DIO_CTRL_REG);
1385 /*=============================================================================
1387 ===========================================================================*/
1389 static int me4000_cnt_insn_config(struct comedi_device *dev,
1390 struct comedi_subdevice *s,
1391 struct comedi_insn *insn,
1394 struct me4000_info *info = dev->private;
1402 err = i8254_load(info->timer_regbase, 0, insn->chanspec, 0,
1403 I8254_MODE0 | I8254_BINARY);
1407 case GPCT_SET_OPERATION:
1411 err = i8254_set_mode(info->timer_regbase, 0, insn->chanspec,
1412 (data[1] << 1) | I8254_BINARY);
1423 static int me4000_cnt_insn_read(struct comedi_device *dev,
1424 struct comedi_subdevice *s,
1425 struct comedi_insn *insn, unsigned int *data)
1427 struct me4000_info *info = dev->private;
1433 dev_err(dev->class_dev, "Invalid instruction length %d\n",
1438 data[0] = i8254_read(info->timer_regbase, 0, insn->chanspec);
1443 static int me4000_cnt_insn_write(struct comedi_device *dev,
1444 struct comedi_subdevice *s,
1445 struct comedi_insn *insn, unsigned int *data)
1447 struct me4000_info *info = dev->private;
1451 } else if (insn->n > 1) {
1452 dev_err(dev->class_dev, "Invalid instruction length %d\n",
1457 i8254_write(info->timer_regbase, 0, insn->chanspec, data[0]);
1462 static int me4000_auto_attach(struct comedi_device *dev,
1463 unsigned long context)
1465 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1466 const struct me4000_board *thisboard = NULL;
1467 struct me4000_info *info;
1468 struct comedi_subdevice *s;
1471 if (context < ARRAY_SIZE(me4000_boards))
1472 thisboard = &me4000_boards[context];
1475 dev->board_ptr = thisboard;
1476 dev->board_name = thisboard->name;
1478 info = comedi_alloc_devpriv(dev, sizeof(*info));
1482 result = comedi_pci_enable(dev);
1486 info->plx_regbase = pci_resource_start(pcidev, 1);
1487 dev->iobase = pci_resource_start(pcidev, 2);
1488 info->timer_regbase = pci_resource_start(pcidev, 3);
1489 if (!info->plx_regbase || !dev->iobase || !info->timer_regbase)
1492 result = xilinx_download(dev);
1498 if (pcidev->irq > 0) {
1499 result = request_irq(pcidev->irq, me4000_ai_isr, IRQF_SHARED,
1500 dev->board_name, dev);
1502 dev->irq = pcidev->irq;
1505 result = comedi_alloc_subdevices(dev, 4);
1509 /*=========================================================================
1510 Analog input subdevice
1511 ========================================================================*/
1513 s = &dev->subdevices[0];
1515 if (thisboard->ai_nchan) {
1516 s->type = COMEDI_SUBD_AI;
1518 SDF_READABLE | SDF_COMMON | SDF_GROUND | SDF_DIFF;
1519 s->n_chan = thisboard->ai_nchan;
1520 s->maxdata = 0xFFFF; /* 16 bit ADC */
1521 s->len_chanlist = ME4000_AI_CHANNEL_LIST_COUNT;
1522 s->range_table = &me4000_ai_range;
1523 s->insn_read = me4000_ai_insn_read;
1526 dev->read_subdev = s;
1527 s->subdev_flags |= SDF_CMD_READ;
1528 s->cancel = me4000_ai_cancel;
1529 s->do_cmdtest = me4000_ai_do_cmd_test;
1530 s->do_cmd = me4000_ai_do_cmd;
1533 s->type = COMEDI_SUBD_UNUSED;
1536 /*=========================================================================
1537 Analog output subdevice
1538 ========================================================================*/
1540 s = &dev->subdevices[1];
1542 if (thisboard->ao_nchan) {
1543 s->type = COMEDI_SUBD_AO;
1544 s->subdev_flags = SDF_WRITEABLE | SDF_COMMON | SDF_GROUND;
1545 s->n_chan = thisboard->ao_nchan;
1546 s->maxdata = 0xFFFF; /* 16 bit DAC */
1547 s->range_table = &range_bipolar10;
1548 s->insn_write = me4000_ao_insn_write;
1549 s->insn_read = me4000_ao_insn_read;
1551 s->type = COMEDI_SUBD_UNUSED;
1554 /*=========================================================================
1555 Digital I/O subdevice
1556 ========================================================================*/
1558 s = &dev->subdevices[2];
1560 if (thisboard->dio_nchan) {
1561 s->type = COMEDI_SUBD_DIO;
1562 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1563 s->n_chan = thisboard->dio_nchan;
1565 s->range_table = &range_digital;
1566 s->insn_bits = me4000_dio_insn_bits;
1567 s->insn_config = me4000_dio_insn_config;
1569 s->type = COMEDI_SUBD_UNUSED;
1573 * Check for optoisolated ME-4000 version. If one the first
1574 * port is a fixed output port and the second is a fixed input port.
1576 if (!inl(dev->iobase + ME4000_DIO_DIR_REG)) {
1578 outl(ME4000_DIO_CTRL_BIT_MODE_0,
1579 dev->iobase + ME4000_DIO_DIR_REG);
1582 /*=========================================================================
1584 ========================================================================*/
1586 s = &dev->subdevices[3];
1588 if (thisboard->has_counter) {
1589 s->type = COMEDI_SUBD_COUNTER;
1590 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1592 s->maxdata = 0xFFFF; /* 16 bit counters */
1593 s->insn_read = me4000_cnt_insn_read;
1594 s->insn_write = me4000_cnt_insn_write;
1595 s->insn_config = me4000_cnt_insn_config;
1597 s->type = COMEDI_SUBD_UNUSED;
1603 static void me4000_detach(struct comedi_device *dev)
1606 free_irq(dev->irq, dev);
1609 comedi_pci_disable(dev);
1612 static struct comedi_driver me4000_driver = {
1613 .driver_name = "me4000",
1614 .module = THIS_MODULE,
1615 .auto_attach = me4000_auto_attach,
1616 .detach = me4000_detach,
1619 static int me4000_pci_probe(struct pci_dev *dev,
1620 const struct pci_device_id *id)
1622 return comedi_pci_auto_config(dev, &me4000_driver, id->driver_data);
1625 static const struct pci_device_id me4000_pci_table[] = {
1626 { PCI_VDEVICE(MEILHAUS, 0x4650), BOARD_ME4650 },
1627 { PCI_VDEVICE(MEILHAUS, 0x4660), BOARD_ME4660 },
1628 { PCI_VDEVICE(MEILHAUS, 0x4661), BOARD_ME4660I },
1629 { PCI_VDEVICE(MEILHAUS, 0x4662), BOARD_ME4660S },
1630 { PCI_VDEVICE(MEILHAUS, 0x4663), BOARD_ME4660IS },
1631 { PCI_VDEVICE(MEILHAUS, 0x4670), BOARD_ME4670 },
1632 { PCI_VDEVICE(MEILHAUS, 0x4671), BOARD_ME4670I },
1633 { PCI_VDEVICE(MEILHAUS, 0x4672), BOARD_ME4670S },
1634 { PCI_VDEVICE(MEILHAUS, 0x4673), BOARD_ME4670IS },
1635 { PCI_VDEVICE(MEILHAUS, 0x4680), BOARD_ME4680 },
1636 { PCI_VDEVICE(MEILHAUS, 0x4681), BOARD_ME4680I },
1637 { PCI_VDEVICE(MEILHAUS, 0x4682), BOARD_ME4680S },
1638 { PCI_VDEVICE(MEILHAUS, 0x4683), BOARD_ME4680IS },
1641 MODULE_DEVICE_TABLE(pci, me4000_pci_table);
1643 static struct pci_driver me4000_pci_driver = {
1645 .id_table = me4000_pci_table,
1646 .probe = me4000_pci_probe,
1647 .remove = comedi_pci_auto_unconfig,
1649 module_comedi_pci_driver(me4000_driver, me4000_pci_driver);
1651 MODULE_AUTHOR("Comedi http://www.comedi.org");
1652 MODULE_DESCRIPTION("Comedi low-level driver");
1653 MODULE_LICENSE("GPL");