2 comedi/drivers/ni_atmio16d.c
3 Hardware driver for National Instruments AT-MIO16D board
4 Copyright (C) 2000 Chris R. Baugher <baugher@enteract.com>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 Description: National Instruments AT-MIO-16D
24 Author: Chris R. Baugher <baugher@enteract.com>
26 Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d)
29 * I must give credit here to Michal Dobes <dobes@tesnet.cz> who
30 * wrote the driver for Advantec's pcl812 boards. I used the interrupt
31 * handling code from his driver as an example for this one.
38 #include <linux/interrupt.h>
39 #include "../comedidev.h"
41 #include <linux/ioport.h>
45 /* Configuration and Status Registers */
46 #define COM_REG_1 0x00 /* wo 16 */
47 #define STAT_REG 0x00 /* ro 16 */
48 #define COM_REG_2 0x02 /* wo 16 */
49 /* Event Strobe Registers */
50 #define START_CONVERT_REG 0x08 /* wo 16 */
51 #define START_DAQ_REG 0x0A /* wo 16 */
52 #define AD_CLEAR_REG 0x0C /* wo 16 */
53 #define EXT_STROBE_REG 0x0E /* wo 16 */
54 /* Analog Output Registers */
55 #define DAC0_REG 0x10 /* wo 16 */
56 #define DAC1_REG 0x12 /* wo 16 */
57 #define INT2CLR_REG 0x14 /* wo 16 */
58 /* Analog Input Registers */
59 #define MUX_CNTR_REG 0x04 /* wo 16 */
60 #define MUX_GAIN_REG 0x06 /* wo 16 */
61 #define AD_FIFO_REG 0x16 /* ro 16 */
62 #define DMA_TC_INT_CLR_REG 0x16 /* wo 16 */
63 /* AM9513A Counter/Timer Registers */
64 #define AM9513A_DATA_REG 0x18 /* rw 16 */
65 #define AM9513A_COM_REG 0x1A /* wo 16 */
66 #define AM9513A_STAT_REG 0x1A /* ro 16 */
67 /* MIO-16 Digital I/O Registers */
68 #define MIO_16_DIG_IN_REG 0x1C /* ro 16 */
69 #define MIO_16_DIG_OUT_REG 0x1C /* wo 16 */
70 /* RTSI Switch Registers */
71 #define RTSI_SW_SHIFT_REG 0x1E /* wo 8 */
72 #define RTSI_SW_STROBE_REG 0x1F /* wo 8 */
73 /* DIO-24 Registers */
74 #define DIO_24_PORTA_REG 0x00 /* rw 8 */
75 #define DIO_24_PORTB_REG 0x01 /* rw 8 */
76 #define DIO_24_PORTC_REG 0x02 /* rw 8 */
77 #define DIO_24_CNFG_REG 0x03 /* wo 8 */
79 /* Command Register bits */
80 #define COMREG1_2SCADC 0x0001
81 #define COMREG1_1632CNT 0x0002
82 #define COMREG1_SCANEN 0x0008
83 #define COMREG1_DAQEN 0x0010
84 #define COMREG1_DMAEN 0x0020
85 #define COMREG1_CONVINTEN 0x0080
86 #define COMREG2_SCN2 0x0010
87 #define COMREG2_INTEN 0x0080
88 #define COMREG2_DOUTEN0 0x0100
89 #define COMREG2_DOUTEN1 0x0200
90 /* Status Register bits */
91 #define STAT_AD_OVERRUN 0x0100
92 #define STAT_AD_OVERFLOW 0x0200
93 #define STAT_AD_DAQPROG 0x0800
94 #define STAT_AD_CONVAVAIL 0x2000
95 #define STAT_AD_DAQSTOPINT 0x4000
96 /* AM9513A Counter/Timer defines */
97 #define CLOCK_1_MHZ 0x8B25
98 #define CLOCK_100_KHZ 0x8C25
99 #define CLOCK_10_KHZ 0x8D25
100 #define CLOCK_1_KHZ 0x8E25
101 #define CLOCK_100_HZ 0x8F25
102 /* Other miscellaneous defines */
103 #define ATMIO16D_SIZE 32 /* bus address range */
104 #define devpriv ((struct atmio16d_private *)dev->private)
105 #define ATMIO16D_TIMEOUT 10
107 struct atmio16_board_t {
113 #define boardtype ((const struct atmio16_board_t *)dev->board_ptr)
116 static const struct comedi_lrange range_atmio16d_ai_10_bipolar = { 4, {
128 static const struct comedi_lrange range_atmio16d_ai_5_bipolar = { 4, {
140 static const struct comedi_lrange range_atmio16d_ai_unipolar = { 4, {
152 /* private data struct */
153 struct atmio16d_private {
154 enum { adc_diff, adc_singleended } adc_mux;
155 enum { adc_bipolar10, adc_bipolar5, adc_unipolar10 } adc_range;
156 enum { adc_2comp, adc_straight } adc_coding;
157 enum { dac_bipolar, dac_unipolar } dac0_range, dac1_range;
158 enum { dac_internal, dac_external } dac0_reference, dac1_reference;
159 enum { dac_2comp, dac_straight } dac0_coding, dac1_coding;
160 const struct comedi_lrange *ao_range_type_list[2];
161 unsigned int ao_readback[2];
162 unsigned int com_reg_1_state; /* current state of command register 1 */
163 unsigned int com_reg_2_state; /* current state of command register 2 */
166 static void reset_counters(struct comedi_device *dev)
169 outw(0xFFC2, dev->iobase + AM9513A_COM_REG);
170 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
171 outw(0x4, dev->iobase + AM9513A_DATA_REG);
172 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
173 outw(0x3, dev->iobase + AM9513A_DATA_REG);
174 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
175 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
177 outw(0xFFC4, dev->iobase + AM9513A_COM_REG);
178 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
179 outw(0x4, dev->iobase + AM9513A_DATA_REG);
180 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
181 outw(0x3, dev->iobase + AM9513A_DATA_REG);
182 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
183 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
185 outw(0xFFC8, dev->iobase + AM9513A_COM_REG);
186 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
187 outw(0x4, dev->iobase + AM9513A_DATA_REG);
188 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
189 outw(0x3, dev->iobase + AM9513A_DATA_REG);
190 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
191 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
193 outw(0xFFD0, dev->iobase + AM9513A_COM_REG);
194 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
195 outw(0x4, dev->iobase + AM9513A_DATA_REG);
196 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
197 outw(0x3, dev->iobase + AM9513A_DATA_REG);
198 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
199 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
201 outw(0, dev->iobase + AD_CLEAR_REG);
204 static void reset_atmio16d(struct comedi_device *dev)
208 /* now we need to initialize the board */
209 outw(0, dev->iobase + COM_REG_1);
210 outw(0, dev->iobase + COM_REG_2);
211 outw(0, dev->iobase + MUX_GAIN_REG);
212 /* init AM9513A timer */
213 outw(0xFFFF, dev->iobase + AM9513A_COM_REG);
214 outw(0xFFEF, dev->iobase + AM9513A_COM_REG);
215 outw(0xFF17, dev->iobase + AM9513A_COM_REG);
216 outw(0xF000, dev->iobase + AM9513A_DATA_REG);
217 for (i = 1; i <= 5; ++i) {
218 outw(0xFF00 + i, dev->iobase + AM9513A_COM_REG);
219 outw(0x0004, dev->iobase + AM9513A_DATA_REG);
220 outw(0xFF08 + i, dev->iobase + AM9513A_COM_REG);
221 outw(0x3, dev->iobase + AM9513A_DATA_REG);
223 outw(0xFF5F, dev->iobase + AM9513A_COM_REG);
224 /* timer init done */
225 outw(0, dev->iobase + AD_CLEAR_REG);
226 outw(0, dev->iobase + INT2CLR_REG);
227 /* select straight binary mode for Analog Input */
228 devpriv->com_reg_1_state |= 1;
229 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
230 devpriv->adc_coding = adc_straight;
231 /* zero the analog outputs */
232 outw(2048, dev->iobase + DAC0_REG);
233 outw(2048, dev->iobase + DAC1_REG);
236 static irqreturn_t atmio16d_interrupt(int irq, void *d)
238 struct comedi_device *dev = d;
239 struct comedi_subdevice *s = dev->subdevices + 0;
242 printk(KERN_DEBUG "atmio16d_interrupt!\n");
245 comedi_buf_put(s->async, inw(dev->iobase + AD_FIFO_REG));
247 comedi_event(dev, s);
251 static int atmio16d_ai_cmdtest(struct comedi_device *dev,
252 struct comedi_subdevice *s,
253 struct comedi_cmd *cmd)
257 printk(KERN_DEBUG "atmio16d_ai_cmdtest\n");
259 /* make sure triggers are valid */
260 tmp = cmd->start_src;
261 cmd->start_src &= TRIG_NOW;
262 if (!cmd->start_src || tmp != cmd->start_src)
265 tmp = cmd->scan_begin_src;
266 cmd->scan_begin_src &= TRIG_FOLLOW | TRIG_TIMER;
267 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
270 tmp = cmd->convert_src;
271 cmd->convert_src &= TRIG_TIMER;
272 if (!cmd->convert_src || tmp != cmd->convert_src)
275 tmp = cmd->scan_end_src;
276 cmd->scan_end_src &= TRIG_COUNT;
277 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
281 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
282 if (!cmd->stop_src || tmp != cmd->stop_src)
288 /* step 2: make sure trigger sources are unique & mutually compatible */
289 /* note that mutual compatibility is not an issue here */
290 if (cmd->scan_begin_src != TRIG_FOLLOW &&
291 cmd->scan_begin_src != TRIG_EXT &&
292 cmd->scan_begin_src != TRIG_TIMER)
294 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
300 /* step 3: make sure arguments are trivially compatible */
302 if (cmd->start_arg != 0) {
306 if (cmd->scan_begin_src == TRIG_FOLLOW) {
307 /* internal trigger */
308 if (cmd->scan_begin_arg != 0) {
309 cmd->scan_begin_arg = 0;
314 /* external trigger */
315 /* should be level/edge, hi/lo specification here */
316 if (cmd->scan_begin_arg != 0) {
317 cmd->scan_begin_arg = 0;
323 if (cmd->convert_arg < 10000) {
324 cmd->convert_arg = 10000;
328 if (cmd->convert_arg > SLOWEST_TIMER) {
329 cmd->convert_arg = SLOWEST_TIMER;
333 if (cmd->scan_end_arg != cmd->chanlist_len) {
334 cmd->scan_end_arg = cmd->chanlist_len;
337 if (cmd->stop_src == TRIG_COUNT) {
338 /* any count is allowed */
341 if (cmd->stop_arg != 0) {
353 static int atmio16d_ai_cmd(struct comedi_device *dev,
354 struct comedi_subdevice *s)
356 struct comedi_cmd *cmd = &s->async->cmd;
357 unsigned int timer, base_clock;
358 unsigned int sample_count, tmp, chan, gain;
361 printk(KERN_DEBUG "atmio16d_ai_cmd\n");
363 /* This is slowly becoming a working command interface. *
364 * It is still uber-experimental */
367 s->async->cur_chan = 0;
369 /* check if scanning multiple channels */
370 if (cmd->chanlist_len < 2) {
371 devpriv->com_reg_1_state &= ~COMREG1_SCANEN;
372 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
374 devpriv->com_reg_1_state |= COMREG1_SCANEN;
375 devpriv->com_reg_2_state |= COMREG2_SCN2;
376 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
377 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
380 /* Setup the Mux-Gain Counter */
381 for (i = 0; i < cmd->chanlist_len; ++i) {
382 chan = CR_CHAN(cmd->chanlist[i]);
383 gain = CR_RANGE(cmd->chanlist[i]);
384 outw(i, dev->iobase + MUX_CNTR_REG);
385 tmp = chan | (gain << 6);
386 if (i == cmd->scan_end_arg - 1)
387 tmp |= 0x0010; /* set LASTONE bit */
388 outw(tmp, dev->iobase + MUX_GAIN_REG);
391 /* Now program the sample interval timer */
392 /* Figure out which clock to use then get an
393 * appropriate timer value */
394 if (cmd->convert_arg < 65536000) {
395 base_clock = CLOCK_1_MHZ;
396 timer = cmd->convert_arg / 1000;
397 } else if (cmd->convert_arg < 655360000) {
398 base_clock = CLOCK_100_KHZ;
399 timer = cmd->convert_arg / 10000;
400 } else if (cmd->convert_arg <= 0xffffffff /* 6553600000 */) {
401 base_clock = CLOCK_10_KHZ;
402 timer = cmd->convert_arg / 100000;
403 } else if (cmd->convert_arg <= 0xffffffff /* 65536000000 */) {
404 base_clock = CLOCK_1_KHZ;
405 timer = cmd->convert_arg / 1000000;
407 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
408 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
409 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
410 outw(0x2, dev->iobase + AM9513A_DATA_REG);
411 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
412 outw(0xFFF3, dev->iobase + AM9513A_COM_REG);
413 outw(timer, dev->iobase + AM9513A_DATA_REG);
414 outw(0xFF24, dev->iobase + AM9513A_COM_REG);
416 /* Now figure out how many samples to get */
417 /* and program the sample counter */
418 sample_count = cmd->stop_arg * cmd->scan_end_arg;
419 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
420 outw(0x1025, dev->iobase + AM9513A_DATA_REG);
421 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
422 if (sample_count < 65536) {
423 /* use only Counter 4 */
424 outw(sample_count, dev->iobase + AM9513A_DATA_REG);
425 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
426 outw(0xFFF4, dev->iobase + AM9513A_COM_REG);
427 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
428 devpriv->com_reg_1_state &= ~COMREG1_1632CNT;
429 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
431 /* Counter 4 and 5 are needed */
433 tmp = sample_count & 0xFFFF;
435 outw(tmp - 1, dev->iobase + AM9513A_DATA_REG);
437 outw(0xFFFF, dev->iobase + AM9513A_DATA_REG);
439 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
440 outw(0, dev->iobase + AM9513A_DATA_REG);
441 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
442 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
443 outw(0x25, dev->iobase + AM9513A_DATA_REG);
444 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
445 tmp = sample_count & 0xFFFF;
446 if ((tmp == 0) || (tmp == 1)) {
447 outw((sample_count >> 16) & 0xFFFF,
448 dev->iobase + AM9513A_DATA_REG);
450 outw(((sample_count >> 16) & 0xFFFF) + 1,
451 dev->iobase + AM9513A_DATA_REG);
453 outw(0xFF70, dev->iobase + AM9513A_COM_REG);
454 devpriv->com_reg_1_state |= COMREG1_1632CNT;
455 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
458 /* Program the scan interval timer ONLY IF SCANNING IS ENABLED */
459 /* Figure out which clock to use then get an
460 * appropriate timer value */
461 if (cmd->chanlist_len > 1) {
462 if (cmd->scan_begin_arg < 65536000) {
463 base_clock = CLOCK_1_MHZ;
464 timer = cmd->scan_begin_arg / 1000;
465 } else if (cmd->scan_begin_arg < 655360000) {
466 base_clock = CLOCK_100_KHZ;
467 timer = cmd->scan_begin_arg / 10000;
468 } else if (cmd->scan_begin_arg < 0xffffffff /* 6553600000 */) {
469 base_clock = CLOCK_10_KHZ;
470 timer = cmd->scan_begin_arg / 100000;
471 } else if (cmd->scan_begin_arg < 0xffffffff /* 65536000000 */) {
472 base_clock = CLOCK_1_KHZ;
473 timer = cmd->scan_begin_arg / 1000000;
475 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
476 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
477 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
478 outw(0x2, dev->iobase + AM9513A_DATA_REG);
479 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
480 outw(0xFFF2, dev->iobase + AM9513A_COM_REG);
481 outw(timer, dev->iobase + AM9513A_DATA_REG);
482 outw(0xFF22, dev->iobase + AM9513A_COM_REG);
485 /* Clear the A/D FIFO and reset the MUX counter */
486 outw(0, dev->iobase + AD_CLEAR_REG);
487 outw(0, dev->iobase + MUX_CNTR_REG);
488 outw(0, dev->iobase + INT2CLR_REG);
489 /* enable this acquisition operation */
490 devpriv->com_reg_1_state |= COMREG1_DAQEN;
491 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
492 /* enable interrupts for conversion completion */
493 devpriv->com_reg_1_state |= COMREG1_CONVINTEN;
494 devpriv->com_reg_2_state |= COMREG2_INTEN;
495 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
496 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
497 /* apply a trigger. this starts the counters! */
498 outw(0, dev->iobase + START_DAQ_REG);
503 /* This will cancel a running acquisition operation */
504 static int atmio16d_ai_cancel(struct comedi_device *dev,
505 struct comedi_subdevice *s)
512 /* Mode 0 is used to get a single conversion on demand */
513 static int atmio16d_ai_insn_read(struct comedi_device *dev,
514 struct comedi_subdevice *s,
515 struct comedi_insn *insn, unsigned int *data)
523 printk(KERN_DEBUG "atmio16d_ai_insn_read\n");
525 chan = CR_CHAN(insn->chanspec);
526 gain = CR_RANGE(insn->chanspec);
528 /* reset the Analog input circuitry */
529 /* outw( 0, dev->iobase+AD_CLEAR_REG ); */
530 /* reset the Analog Input MUX Counter to 0 */
531 /* outw( 0, dev->iobase+MUX_CNTR_REG ); */
533 /* set the Input MUX gain */
534 outw(chan | (gain << 6), dev->iobase + MUX_GAIN_REG);
536 for (i = 0; i < insn->n; i++) {
537 /* start the conversion */
538 outw(0, dev->iobase + START_CONVERT_REG);
539 /* wait for it to finish */
540 for (t = 0; t < ATMIO16D_TIMEOUT; t++) {
541 /* check conversion status */
542 status = inw(dev->iobase + STAT_REG);
544 printk(KERN_DEBUG "status=%x\n", status);
546 if (status & STAT_AD_CONVAVAIL) {
547 /* read the data now */
548 data[i] = inw(dev->iobase + AD_FIFO_REG);
549 /* change to two's complement if need be */
550 if (devpriv->adc_coding == adc_2comp)
554 if (status & STAT_AD_OVERFLOW) {
555 printk(KERN_INFO "atmio16d: a/d FIFO overflow\n");
556 outw(0, dev->iobase + AD_CLEAR_REG);
561 /* end waiting, now check if it timed out */
562 if (t == ATMIO16D_TIMEOUT) {
563 printk(KERN_INFO "atmio16d: timeout\n");
572 static int atmio16d_ao_insn_read(struct comedi_device *dev,
573 struct comedi_subdevice *s,
574 struct comedi_insn *insn, unsigned int *data)
578 printk(KERN_DEBUG "atmio16d_ao_insn_read\n");
581 for (i = 0; i < insn->n; i++)
582 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
586 static int atmio16d_ao_insn_write(struct comedi_device *dev,
587 struct comedi_subdevice *s,
588 struct comedi_insn *insn, unsigned int *data)
594 printk(KERN_DEBUG "atmio16d_ao_insn_write\n");
597 chan = CR_CHAN(insn->chanspec);
599 for (i = 0; i < insn->n; i++) {
603 if (devpriv->dac0_coding == dac_2comp)
605 outw(d, dev->iobase + DAC0_REG);
608 if (devpriv->dac1_coding == dac_2comp)
610 outw(d, dev->iobase + DAC1_REG);
615 devpriv->ao_readback[chan] = data[i];
620 static int atmio16d_dio_insn_bits(struct comedi_device *dev,
621 struct comedi_subdevice *s,
622 struct comedi_insn *insn, unsigned int *data)
628 s->state &= ~data[0];
629 s->state |= (data[0] | data[1]);
630 outw(s->state, dev->iobase + MIO_16_DIG_OUT_REG);
632 data[1] = inw(dev->iobase + MIO_16_DIG_IN_REG);
637 static int atmio16d_dio_insn_config(struct comedi_device *dev,
638 struct comedi_subdevice *s,
639 struct comedi_insn *insn,
645 for (i = 0; i < insn->n; i++) {
646 mask = (CR_CHAN(insn->chanspec) < 4) ? 0x0f : 0xf0;
651 devpriv->com_reg_2_state &= ~(COMREG2_DOUTEN0 | COMREG2_DOUTEN1);
652 if (s->io_bits & 0x0f)
653 devpriv->com_reg_2_state |= COMREG2_DOUTEN0;
654 if (s->io_bits & 0xf0)
655 devpriv->com_reg_2_state |= COMREG2_DOUTEN1;
656 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
662 options[0] - I/O port
665 N == irq N {3,4,5,6,7,9,10,11,12,14,15}
668 N == irq N {3,4,5,6,7,9}
669 options[3] - DMA1 channel
672 options[4] - DMA2 channel
677 0=differential, 1=single
678 options[6] - a/d range
679 0=bipolar10, 1=bipolar5, 2=unipolar10
681 options[7] - dac0 range
682 0=bipolar, 1=unipolar
683 options[8] - dac0 reference
684 0=internal, 1=external
685 options[9] - dac0 coding
686 0=2's comp, 1=straight binary
688 options[10] - dac1 range
689 options[11] - dac1 reference
690 options[12] - dac1 coding
693 static int atmio16d_attach(struct comedi_device *dev,
694 struct comedi_devconfig *it)
697 unsigned long iobase;
700 struct comedi_subdevice *s;
702 /* make sure the address range is free and allocate it */
703 iobase = it->options[0];
704 printk(KERN_INFO "comedi%d: atmio16d: 0x%04lx ", dev->minor, iobase);
705 if (!request_region(iobase, ATMIO16D_SIZE, "ni_atmio16d")) {
706 printk("I/O port conflict\n");
709 dev->iobase = iobase;
712 dev->board_name = boardtype->name;
714 ret = alloc_subdevices(dev, 4);
718 ret = alloc_private(dev, sizeof(struct atmio16d_private));
722 /* reset the atmio16d hardware */
725 /* check if our interrupt is available and get it */
726 irq = it->options[1];
729 ret = request_irq(irq, atmio16d_interrupt, 0, "atmio16d", dev);
731 printk(KERN_INFO "failed to allocate irq %u\n", irq);
735 printk(KERN_INFO "( irq = %u )\n", irq);
737 printk(KERN_INFO "( no irq )");
740 /* set device options */
741 devpriv->adc_mux = it->options[5];
742 devpriv->adc_range = it->options[6];
744 devpriv->dac0_range = it->options[7];
745 devpriv->dac0_reference = it->options[8];
746 devpriv->dac0_coding = it->options[9];
747 devpriv->dac1_range = it->options[10];
748 devpriv->dac1_reference = it->options[11];
749 devpriv->dac1_coding = it->options[12];
751 /* setup sub-devices */
752 s = dev->subdevices + 0;
753 dev->read_subdev = s;
755 s->type = COMEDI_SUBD_AI;
756 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_CMD_READ;
757 s->n_chan = (devpriv->adc_mux ? 16 : 8);
758 s->len_chanlist = 16;
759 s->insn_read = atmio16d_ai_insn_read;
760 s->do_cmdtest = atmio16d_ai_cmdtest;
761 s->do_cmd = atmio16d_ai_cmd;
762 s->cancel = atmio16d_ai_cancel;
763 s->maxdata = 0xfff; /* 4095 decimal */
764 switch (devpriv->adc_range) {
766 s->range_table = &range_atmio16d_ai_10_bipolar;
769 s->range_table = &range_atmio16d_ai_5_bipolar;
772 s->range_table = &range_atmio16d_ai_unipolar;
778 s->type = COMEDI_SUBD_AO;
779 s->subdev_flags = SDF_WRITABLE;
781 s->insn_read = atmio16d_ao_insn_read;
782 s->insn_write = atmio16d_ao_insn_write;
783 s->maxdata = 0xfff; /* 4095 decimal */
784 s->range_table_list = devpriv->ao_range_type_list;
785 switch (devpriv->dac0_range) {
787 devpriv->ao_range_type_list[0] = &range_bipolar10;
790 devpriv->ao_range_type_list[0] = &range_unipolar10;
793 switch (devpriv->dac1_range) {
795 devpriv->ao_range_type_list[1] = &range_bipolar10;
798 devpriv->ao_range_type_list[1] = &range_unipolar10;
804 s->type = COMEDI_SUBD_DIO;
805 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
807 s->insn_bits = atmio16d_dio_insn_bits;
808 s->insn_config = atmio16d_dio_insn_config;
810 s->range_table = &range_digital;
814 if (boardtype->has_8255)
815 subdev_8255_init(dev, s, NULL, dev->iobase);
817 s->type = COMEDI_SUBD_UNUSED;
819 /* don't yet know how to deal with counter/timers */
823 s->type = COMEDI_SUBD_TIMER;
832 static void atmio16d_detach(struct comedi_device *dev)
834 if (dev->subdevices && boardtype->has_8255)
835 subdev_8255_cleanup(dev, dev->subdevices + 3);
837 free_irq(dev->irq, dev);
840 release_region(dev->iobase, ATMIO16D_SIZE);
843 static const struct atmio16_board_t atmio16_boards[] = {
853 static struct comedi_driver atmio16d_driver = {
854 .driver_name = "atmio16",
855 .module = THIS_MODULE,
856 .attach = atmio16d_attach,
857 .detach = atmio16d_detach,
858 .board_name = &atmio16_boards[0].name,
859 .num_names = ARRAY_SIZE(atmio16_boards),
860 .offset = sizeof(struct atmio16_board_t),
862 module_comedi_driver(atmio16d_driver);
864 MODULE_AUTHOR("Comedi http://www.comedi.org");
865 MODULE_DESCRIPTION("Comedi low-level driver");
866 MODULE_LICENSE("GPL");