2 comedi/drivers/ni_atmio16d.c
3 Hardware driver for National Instruments AT-MIO16D board
4 Copyright (C) 2000 Chris R. Baugher <baugher@enteract.com>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
18 Description: National Instruments AT-MIO-16D
19 Author: Chris R. Baugher <baugher@enteract.com>
21 Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d)
24 * I must give credit here to Michal Dobes <dobes@tesnet.cz> who
25 * wrote the driver for Advantec's pcl812 boards. I used the interrupt
26 * handling code from his driver as an example for this one.
33 #include <linux/module.h>
34 #include <linux/interrupt.h>
35 #include "../comedidev.h"
37 #include <linux/ioport.h>
39 #include "comedi_fc.h"
42 /* Configuration and Status Registers */
43 #define COM_REG_1 0x00 /* wo 16 */
44 #define STAT_REG 0x00 /* ro 16 */
45 #define COM_REG_2 0x02 /* wo 16 */
46 /* Event Strobe Registers */
47 #define START_CONVERT_REG 0x08 /* wo 16 */
48 #define START_DAQ_REG 0x0A /* wo 16 */
49 #define AD_CLEAR_REG 0x0C /* wo 16 */
50 #define EXT_STROBE_REG 0x0E /* wo 16 */
51 /* Analog Output Registers */
52 #define DAC0_REG 0x10 /* wo 16 */
53 #define DAC1_REG 0x12 /* wo 16 */
54 #define INT2CLR_REG 0x14 /* wo 16 */
55 /* Analog Input Registers */
56 #define MUX_CNTR_REG 0x04 /* wo 16 */
57 #define MUX_GAIN_REG 0x06 /* wo 16 */
58 #define AD_FIFO_REG 0x16 /* ro 16 */
59 #define DMA_TC_INT_CLR_REG 0x16 /* wo 16 */
60 /* AM9513A Counter/Timer Registers */
61 #define AM9513A_DATA_REG 0x18 /* rw 16 */
62 #define AM9513A_COM_REG 0x1A /* wo 16 */
63 #define AM9513A_STAT_REG 0x1A /* ro 16 */
64 /* MIO-16 Digital I/O Registers */
65 #define MIO_16_DIG_IN_REG 0x1C /* ro 16 */
66 #define MIO_16_DIG_OUT_REG 0x1C /* wo 16 */
67 /* RTSI Switch Registers */
68 #define RTSI_SW_SHIFT_REG 0x1E /* wo 8 */
69 #define RTSI_SW_STROBE_REG 0x1F /* wo 8 */
70 /* DIO-24 Registers */
71 #define DIO_24_PORTA_REG 0x00 /* rw 8 */
72 #define DIO_24_PORTB_REG 0x01 /* rw 8 */
73 #define DIO_24_PORTC_REG 0x02 /* rw 8 */
74 #define DIO_24_CNFG_REG 0x03 /* wo 8 */
76 /* Command Register bits */
77 #define COMREG1_2SCADC 0x0001
78 #define COMREG1_1632CNT 0x0002
79 #define COMREG1_SCANEN 0x0008
80 #define COMREG1_DAQEN 0x0010
81 #define COMREG1_DMAEN 0x0020
82 #define COMREG1_CONVINTEN 0x0080
83 #define COMREG2_SCN2 0x0010
84 #define COMREG2_INTEN 0x0080
85 #define COMREG2_DOUTEN0 0x0100
86 #define COMREG2_DOUTEN1 0x0200
87 /* Status Register bits */
88 #define STAT_AD_OVERRUN 0x0100
89 #define STAT_AD_OVERFLOW 0x0200
90 #define STAT_AD_DAQPROG 0x0800
91 #define STAT_AD_CONVAVAIL 0x2000
92 #define STAT_AD_DAQSTOPINT 0x4000
93 /* AM9513A Counter/Timer defines */
94 #define CLOCK_1_MHZ 0x8B25
95 #define CLOCK_100_KHZ 0x8C25
96 #define CLOCK_10_KHZ 0x8D25
97 #define CLOCK_1_KHZ 0x8E25
98 #define CLOCK_100_HZ 0x8F25
99 /* Other miscellaneous defines */
100 #define ATMIO16D_SIZE 32 /* bus address range */
101 #define ATMIO16D_TIMEOUT 10
103 struct atmio16_board_t {
110 static const struct comedi_lrange range_atmio16d_ai_10_bipolar = { 4, {
122 static const struct comedi_lrange range_atmio16d_ai_5_bipolar = { 4, {
134 static const struct comedi_lrange range_atmio16d_ai_unipolar = { 4, {
146 /* private data struct */
147 struct atmio16d_private {
148 enum { adc_diff, adc_singleended } adc_mux;
149 enum { adc_bipolar10, adc_bipolar5, adc_unipolar10 } adc_range;
150 enum { adc_2comp, adc_straight } adc_coding;
151 enum { dac_bipolar, dac_unipolar } dac0_range, dac1_range;
152 enum { dac_internal, dac_external } dac0_reference, dac1_reference;
153 enum { dac_2comp, dac_straight } dac0_coding, dac1_coding;
154 const struct comedi_lrange *ao_range_type_list[2];
155 unsigned int ao_readback[2];
156 unsigned int com_reg_1_state; /* current state of command register 1 */
157 unsigned int com_reg_2_state; /* current state of command register 2 */
160 static void reset_counters(struct comedi_device *dev)
163 outw(0xFFC2, dev->iobase + AM9513A_COM_REG);
164 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
165 outw(0x4, dev->iobase + AM9513A_DATA_REG);
166 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
167 outw(0x3, dev->iobase + AM9513A_DATA_REG);
168 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
169 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
171 outw(0xFFC4, dev->iobase + AM9513A_COM_REG);
172 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
173 outw(0x4, dev->iobase + AM9513A_DATA_REG);
174 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
175 outw(0x3, dev->iobase + AM9513A_DATA_REG);
176 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
177 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
179 outw(0xFFC8, dev->iobase + AM9513A_COM_REG);
180 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
181 outw(0x4, dev->iobase + AM9513A_DATA_REG);
182 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
183 outw(0x3, dev->iobase + AM9513A_DATA_REG);
184 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
185 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
187 outw(0xFFD0, dev->iobase + AM9513A_COM_REG);
188 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
189 outw(0x4, dev->iobase + AM9513A_DATA_REG);
190 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
191 outw(0x3, dev->iobase + AM9513A_DATA_REG);
192 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
193 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
195 outw(0, dev->iobase + AD_CLEAR_REG);
198 static void reset_atmio16d(struct comedi_device *dev)
200 struct atmio16d_private *devpriv = dev->private;
203 /* now we need to initialize the board */
204 outw(0, dev->iobase + COM_REG_1);
205 outw(0, dev->iobase + COM_REG_2);
206 outw(0, dev->iobase + MUX_GAIN_REG);
207 /* init AM9513A timer */
208 outw(0xFFFF, dev->iobase + AM9513A_COM_REG);
209 outw(0xFFEF, dev->iobase + AM9513A_COM_REG);
210 outw(0xFF17, dev->iobase + AM9513A_COM_REG);
211 outw(0xF000, dev->iobase + AM9513A_DATA_REG);
212 for (i = 1; i <= 5; ++i) {
213 outw(0xFF00 + i, dev->iobase + AM9513A_COM_REG);
214 outw(0x0004, dev->iobase + AM9513A_DATA_REG);
215 outw(0xFF08 + i, dev->iobase + AM9513A_COM_REG);
216 outw(0x3, dev->iobase + AM9513A_DATA_REG);
218 outw(0xFF5F, dev->iobase + AM9513A_COM_REG);
219 /* timer init done */
220 outw(0, dev->iobase + AD_CLEAR_REG);
221 outw(0, dev->iobase + INT2CLR_REG);
222 /* select straight binary mode for Analog Input */
223 devpriv->com_reg_1_state |= 1;
224 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
225 devpriv->adc_coding = adc_straight;
226 /* zero the analog outputs */
227 outw(2048, dev->iobase + DAC0_REG);
228 outw(2048, dev->iobase + DAC1_REG);
231 static irqreturn_t atmio16d_interrupt(int irq, void *d)
233 struct comedi_device *dev = d;
234 struct comedi_subdevice *s = &dev->subdevices[0];
236 comedi_buf_put(s->async, inw(dev->iobase + AD_FIFO_REG));
238 comedi_event(dev, s);
242 static int atmio16d_ai_cmdtest(struct comedi_device *dev,
243 struct comedi_subdevice *s,
244 struct comedi_cmd *cmd)
248 /* Step 1 : check if triggers are trivially valid */
250 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
251 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
252 TRIG_FOLLOW | TRIG_TIMER);
253 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER);
254 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
255 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
260 /* Step 2a : make sure trigger sources are unique */
262 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
263 err |= cfc_check_trigger_is_unique(cmd->stop_src);
265 /* Step 2b : and mutually compatible */
270 /* Step 3: check if arguments are trivially valid */
272 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
274 if (cmd->scan_begin_src == TRIG_FOLLOW) {
275 /* internal trigger */
276 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
279 /* external trigger */
280 /* should be level/edge, hi/lo specification here */
281 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
285 err |= cfc_check_trigger_arg_min(&cmd->convert_arg, 10000);
287 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, SLOWEST_TIMER);
290 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
292 if (cmd->stop_src == TRIG_COUNT) {
293 /* any count is allowed */
294 } else { /* TRIG_NONE */
295 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
304 static int atmio16d_ai_cmd(struct comedi_device *dev,
305 struct comedi_subdevice *s)
307 struct atmio16d_private *devpriv = dev->private;
308 struct comedi_cmd *cmd = &s->async->cmd;
309 unsigned int timer, base_clock;
310 unsigned int sample_count, tmp, chan, gain;
313 /* This is slowly becoming a working command interface. *
314 * It is still uber-experimental */
317 s->async->cur_chan = 0;
319 /* check if scanning multiple channels */
320 if (cmd->chanlist_len < 2) {
321 devpriv->com_reg_1_state &= ~COMREG1_SCANEN;
322 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
324 devpriv->com_reg_1_state |= COMREG1_SCANEN;
325 devpriv->com_reg_2_state |= COMREG2_SCN2;
326 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
327 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
330 /* Setup the Mux-Gain Counter */
331 for (i = 0; i < cmd->chanlist_len; ++i) {
332 chan = CR_CHAN(cmd->chanlist[i]);
333 gain = CR_RANGE(cmd->chanlist[i]);
334 outw(i, dev->iobase + MUX_CNTR_REG);
335 tmp = chan | (gain << 6);
336 if (i == cmd->scan_end_arg - 1)
337 tmp |= 0x0010; /* set LASTONE bit */
338 outw(tmp, dev->iobase + MUX_GAIN_REG);
341 /* Now program the sample interval timer */
342 /* Figure out which clock to use then get an
343 * appropriate timer value */
344 if (cmd->convert_arg < 65536000) {
345 base_clock = CLOCK_1_MHZ;
346 timer = cmd->convert_arg / 1000;
347 } else if (cmd->convert_arg < 655360000) {
348 base_clock = CLOCK_100_KHZ;
349 timer = cmd->convert_arg / 10000;
350 } else if (cmd->convert_arg <= 0xffffffff /* 6553600000 */) {
351 base_clock = CLOCK_10_KHZ;
352 timer = cmd->convert_arg / 100000;
353 } else if (cmd->convert_arg <= 0xffffffff /* 65536000000 */) {
354 base_clock = CLOCK_1_KHZ;
355 timer = cmd->convert_arg / 1000000;
357 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
358 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
359 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
360 outw(0x2, dev->iobase + AM9513A_DATA_REG);
361 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
362 outw(0xFFF3, dev->iobase + AM9513A_COM_REG);
363 outw(timer, dev->iobase + AM9513A_DATA_REG);
364 outw(0xFF24, dev->iobase + AM9513A_COM_REG);
366 /* Now figure out how many samples to get */
367 /* and program the sample counter */
368 sample_count = cmd->stop_arg * cmd->scan_end_arg;
369 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
370 outw(0x1025, dev->iobase + AM9513A_DATA_REG);
371 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
372 if (sample_count < 65536) {
373 /* use only Counter 4 */
374 outw(sample_count, dev->iobase + AM9513A_DATA_REG);
375 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
376 outw(0xFFF4, dev->iobase + AM9513A_COM_REG);
377 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
378 devpriv->com_reg_1_state &= ~COMREG1_1632CNT;
379 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
381 /* Counter 4 and 5 are needed */
383 tmp = sample_count & 0xFFFF;
385 outw(tmp - 1, dev->iobase + AM9513A_DATA_REG);
387 outw(0xFFFF, dev->iobase + AM9513A_DATA_REG);
389 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
390 outw(0, dev->iobase + AM9513A_DATA_REG);
391 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
392 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
393 outw(0x25, dev->iobase + AM9513A_DATA_REG);
394 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
395 tmp = sample_count & 0xFFFF;
396 if ((tmp == 0) || (tmp == 1)) {
397 outw((sample_count >> 16) & 0xFFFF,
398 dev->iobase + AM9513A_DATA_REG);
400 outw(((sample_count >> 16) & 0xFFFF) + 1,
401 dev->iobase + AM9513A_DATA_REG);
403 outw(0xFF70, dev->iobase + AM9513A_COM_REG);
404 devpriv->com_reg_1_state |= COMREG1_1632CNT;
405 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
408 /* Program the scan interval timer ONLY IF SCANNING IS ENABLED */
409 /* Figure out which clock to use then get an
410 * appropriate timer value */
411 if (cmd->chanlist_len > 1) {
412 if (cmd->scan_begin_arg < 65536000) {
413 base_clock = CLOCK_1_MHZ;
414 timer = cmd->scan_begin_arg / 1000;
415 } else if (cmd->scan_begin_arg < 655360000) {
416 base_clock = CLOCK_100_KHZ;
417 timer = cmd->scan_begin_arg / 10000;
418 } else if (cmd->scan_begin_arg < 0xffffffff /* 6553600000 */) {
419 base_clock = CLOCK_10_KHZ;
420 timer = cmd->scan_begin_arg / 100000;
421 } else if (cmd->scan_begin_arg < 0xffffffff /* 65536000000 */) {
422 base_clock = CLOCK_1_KHZ;
423 timer = cmd->scan_begin_arg / 1000000;
425 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
426 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
427 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
428 outw(0x2, dev->iobase + AM9513A_DATA_REG);
429 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
430 outw(0xFFF2, dev->iobase + AM9513A_COM_REG);
431 outw(timer, dev->iobase + AM9513A_DATA_REG);
432 outw(0xFF22, dev->iobase + AM9513A_COM_REG);
435 /* Clear the A/D FIFO and reset the MUX counter */
436 outw(0, dev->iobase + AD_CLEAR_REG);
437 outw(0, dev->iobase + MUX_CNTR_REG);
438 outw(0, dev->iobase + INT2CLR_REG);
439 /* enable this acquisition operation */
440 devpriv->com_reg_1_state |= COMREG1_DAQEN;
441 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
442 /* enable interrupts for conversion completion */
443 devpriv->com_reg_1_state |= COMREG1_CONVINTEN;
444 devpriv->com_reg_2_state |= COMREG2_INTEN;
445 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
446 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
447 /* apply a trigger. this starts the counters! */
448 outw(0, dev->iobase + START_DAQ_REG);
453 /* This will cancel a running acquisition operation */
454 static int atmio16d_ai_cancel(struct comedi_device *dev,
455 struct comedi_subdevice *s)
462 /* Mode 0 is used to get a single conversion on demand */
463 static int atmio16d_ai_insn_read(struct comedi_device *dev,
464 struct comedi_subdevice *s,
465 struct comedi_insn *insn, unsigned int *data)
467 struct atmio16d_private *devpriv = dev->private;
473 chan = CR_CHAN(insn->chanspec);
474 gain = CR_RANGE(insn->chanspec);
476 /* reset the Analog input circuitry */
477 /* outw( 0, dev->iobase+AD_CLEAR_REG ); */
478 /* reset the Analog Input MUX Counter to 0 */
479 /* outw( 0, dev->iobase+MUX_CNTR_REG ); */
481 /* set the Input MUX gain */
482 outw(chan | (gain << 6), dev->iobase + MUX_GAIN_REG);
484 for (i = 0; i < insn->n; i++) {
485 /* start the conversion */
486 outw(0, dev->iobase + START_CONVERT_REG);
487 /* wait for it to finish */
488 for (t = 0; t < ATMIO16D_TIMEOUT; t++) {
489 /* check conversion status */
490 status = inw(dev->iobase + STAT_REG);
491 if (status & STAT_AD_CONVAVAIL) {
492 /* read the data now */
493 data[i] = inw(dev->iobase + AD_FIFO_REG);
494 /* change to two's complement if need be */
495 if (devpriv->adc_coding == adc_2comp)
499 if (status & STAT_AD_OVERFLOW) {
500 printk(KERN_INFO "atmio16d: a/d FIFO overflow\n");
501 outw(0, dev->iobase + AD_CLEAR_REG);
506 /* end waiting, now check if it timed out */
507 if (t == ATMIO16D_TIMEOUT) {
508 printk(KERN_INFO "atmio16d: timeout\n");
517 static int atmio16d_ao_insn_read(struct comedi_device *dev,
518 struct comedi_subdevice *s,
519 struct comedi_insn *insn, unsigned int *data)
521 struct atmio16d_private *devpriv = dev->private;
524 for (i = 0; i < insn->n; i++)
525 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
529 static int atmio16d_ao_insn_write(struct comedi_device *dev,
530 struct comedi_subdevice *s,
531 struct comedi_insn *insn, unsigned int *data)
533 struct atmio16d_private *devpriv = dev->private;
538 chan = CR_CHAN(insn->chanspec);
540 for (i = 0; i < insn->n; i++) {
544 if (devpriv->dac0_coding == dac_2comp)
546 outw(d, dev->iobase + DAC0_REG);
549 if (devpriv->dac1_coding == dac_2comp)
551 outw(d, dev->iobase + DAC1_REG);
556 devpriv->ao_readback[chan] = data[i];
561 static int atmio16d_dio_insn_bits(struct comedi_device *dev,
562 struct comedi_subdevice *s,
563 struct comedi_insn *insn, unsigned int *data)
566 s->state &= ~data[0];
567 s->state |= (data[0] | data[1]);
568 outw(s->state, dev->iobase + MIO_16_DIG_OUT_REG);
570 data[1] = inw(dev->iobase + MIO_16_DIG_IN_REG);
575 static int atmio16d_dio_insn_config(struct comedi_device *dev,
576 struct comedi_subdevice *s,
577 struct comedi_insn *insn,
580 struct atmio16d_private *devpriv = dev->private;
584 for (i = 0; i < insn->n; i++) {
585 mask = (CR_CHAN(insn->chanspec) < 4) ? 0x0f : 0xf0;
590 devpriv->com_reg_2_state &= ~(COMREG2_DOUTEN0 | COMREG2_DOUTEN1);
591 if (s->io_bits & 0x0f)
592 devpriv->com_reg_2_state |= COMREG2_DOUTEN0;
593 if (s->io_bits & 0xf0)
594 devpriv->com_reg_2_state |= COMREG2_DOUTEN1;
595 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
601 options[0] - I/O port
604 N == irq N {3,4,5,6,7,9,10,11,12,14,15}
607 N == irq N {3,4,5,6,7,9}
608 options[3] - DMA1 channel
611 options[4] - DMA2 channel
616 0=differential, 1=single
617 options[6] - a/d range
618 0=bipolar10, 1=bipolar5, 2=unipolar10
620 options[7] - dac0 range
621 0=bipolar, 1=unipolar
622 options[8] - dac0 reference
623 0=internal, 1=external
624 options[9] - dac0 coding
625 0=2's comp, 1=straight binary
627 options[10] - dac1 range
628 options[11] - dac1 reference
629 options[12] - dac1 coding
632 static int atmio16d_attach(struct comedi_device *dev,
633 struct comedi_devconfig *it)
635 const struct atmio16_board_t *board = comedi_board(dev);
636 struct atmio16d_private *devpriv;
637 struct comedi_subdevice *s;
641 ret = comedi_request_region(dev, it->options[0], ATMIO16D_SIZE);
645 ret = comedi_alloc_subdevices(dev, 4);
649 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
653 /* reset the atmio16d hardware */
656 /* check if our interrupt is available and get it */
657 irq = it->options[1];
660 ret = request_irq(irq, atmio16d_interrupt, 0, "atmio16d", dev);
662 printk(KERN_INFO "failed to allocate irq %u\n", irq);
666 printk(KERN_INFO "( irq = %u )\n", irq);
668 printk(KERN_INFO "( no irq )");
671 /* set device options */
672 devpriv->adc_mux = it->options[5];
673 devpriv->adc_range = it->options[6];
675 devpriv->dac0_range = it->options[7];
676 devpriv->dac0_reference = it->options[8];
677 devpriv->dac0_coding = it->options[9];
678 devpriv->dac1_range = it->options[10];
679 devpriv->dac1_reference = it->options[11];
680 devpriv->dac1_coding = it->options[12];
682 /* setup sub-devices */
683 s = &dev->subdevices[0];
684 dev->read_subdev = s;
686 s->type = COMEDI_SUBD_AI;
687 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_CMD_READ;
688 s->n_chan = (devpriv->adc_mux ? 16 : 8);
689 s->len_chanlist = 16;
690 s->insn_read = atmio16d_ai_insn_read;
691 s->do_cmdtest = atmio16d_ai_cmdtest;
692 s->do_cmd = atmio16d_ai_cmd;
693 s->cancel = atmio16d_ai_cancel;
694 s->maxdata = 0xfff; /* 4095 decimal */
695 switch (devpriv->adc_range) {
697 s->range_table = &range_atmio16d_ai_10_bipolar;
700 s->range_table = &range_atmio16d_ai_5_bipolar;
703 s->range_table = &range_atmio16d_ai_unipolar;
708 s = &dev->subdevices[1];
709 s->type = COMEDI_SUBD_AO;
710 s->subdev_flags = SDF_WRITABLE;
712 s->insn_read = atmio16d_ao_insn_read;
713 s->insn_write = atmio16d_ao_insn_write;
714 s->maxdata = 0xfff; /* 4095 decimal */
715 s->range_table_list = devpriv->ao_range_type_list;
716 switch (devpriv->dac0_range) {
718 devpriv->ao_range_type_list[0] = &range_bipolar10;
721 devpriv->ao_range_type_list[0] = &range_unipolar10;
724 switch (devpriv->dac1_range) {
726 devpriv->ao_range_type_list[1] = &range_bipolar10;
729 devpriv->ao_range_type_list[1] = &range_unipolar10;
734 s = &dev->subdevices[2];
735 s->type = COMEDI_SUBD_DIO;
736 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
738 s->insn_bits = atmio16d_dio_insn_bits;
739 s->insn_config = atmio16d_dio_insn_config;
741 s->range_table = &range_digital;
744 s = &dev->subdevices[3];
746 subdev_8255_init(dev, s, NULL, dev->iobase);
748 s->type = COMEDI_SUBD_UNUSED;
750 /* don't yet know how to deal with counter/timers */
752 s = &dev->subdevices[4];
754 s->type = COMEDI_SUBD_TIMER;
763 static void atmio16d_detach(struct comedi_device *dev)
766 comedi_legacy_detach(dev);
769 static const struct atmio16_board_t atmio16_boards[] = {
779 static struct comedi_driver atmio16d_driver = {
780 .driver_name = "atmio16",
781 .module = THIS_MODULE,
782 .attach = atmio16d_attach,
783 .detach = atmio16d_detach,
784 .board_name = &atmio16_boards[0].name,
785 .num_names = ARRAY_SIZE(atmio16_boards),
786 .offset = sizeof(struct atmio16_board_t),
788 module_comedi_driver(atmio16d_driver);
790 MODULE_AUTHOR("Comedi http://www.comedi.org");
791 MODULE_DESCRIPTION("Comedi low-level driver");
792 MODULE_LICENSE("GPL");