drivers/staging/comedi/drivers/ni_labpc.c

   1 /*
   2     comedi/drivers/ni_labpc.c
   3     Driver for National Instruments Lab-PC series boards and compatibles
   4     Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19
  20 ************************************************************************
  21 */
  22 /*
  23 Driver: ni_labpc
  24 Description: National Instruments Lab-PC (& compatibles)
  25 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  26 Devices: [National Instruments] Lab-PC-1200 (labpc-1200),
  27   Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc)
  28 Status: works
  29
  30 Tested with lab-pc-1200.  For the older Lab-PC+, not all input ranges
  31 and analog references will work, the available ranges/arefs will
  32 depend on how you have configured the jumpers on your board
  33 (see your owner's manual).
  34
  35 Kernel-level ISA plug-and-play support for the lab-pc-1200
  36 boards has not
  37 yet been added to the driver, mainly due to the fact that
  38 I don't know the device id numbers.  If you have one
  39 of these boards,
  40 please file a bug report at http://comedi.org/
  41 so I can get the necessary information from you.
  42
  43 The 1200 series boards have onboard calibration dacs for correcting
  44 analog input/output offsets and gains.  The proper settings for these
  45 caldacs are stored on the board's eeprom.  To read the caldac values
  46 from the eeprom and store them into a file that can be then be used by
  47 comedilib, use the comedi_calibrate program.
  48
  49 Configuration options - ISA boards:
  50   [0] - I/O port base address
  51   [1] - IRQ (optional, required for timed or externally triggered conversions)
  52   [2] - DMA channel (optional)
  53
  54 Configuration options - PCI boards:
  55   [0] - bus (optional)
  56   [1] - slot (optional)
  57
  58 The Lab-pc+ has quirky chanlist requirements
  59 when scanning multiple channels.  Multiple channel scan
  60 sequence must start at highest channel, then decrement down to
  61 channel 0.  The rest of the cards can scan down like lab-pc+ or scan
  62 up from channel zero.  Chanlists consisting of all one channel
  63 are also legal, and allow you to pace conversions in bursts.
  64
  65 */
  66
  67 /*
  68
  69 NI manuals:
  70 341309a (labpc-1200 register manual)
  71 340914a (pci-1200)
  72 320502b (lab-pc+)
  73
  74 */
  75
  76 #include <linux/pci.h>
  77 #include <linux/interrupt.h>
  78 #include <linux/slab.h>
  79 #include <linux/io.h>
  80 #include <linux/delay.h>
  81
  82 #include "../comedidev.h"
  83
  84 #include <asm/dma.h>
  85
  86 #include "8253.h"
  87 #include "8255.h"
  88 #include "mite.h"
  89 #include "comedi_fc.h"
  90 #include "ni_labpc.h"
  91
  92 #define DRV_NAME "ni_labpc"
  93
  94 /* size of io region used by board */
  95 #define LABPC_SIZE           32
  96 /* 2 MHz master clock */
  97 #define LABPC_TIMER_BASE            500
  98
  99 /* Registers for the lab-pc+ */
 100
 101 /* write-only registers */
 102 #define COMMAND1_REG    0x0
 103 #define   ADC_GAIN_MASK (0x7 << 4)
 104 #define   ADC_CHAN_BITS(x)      ((x) & 0x7)
 105 /* enables multi channel scans */
 106 #define   ADC_SCAN_EN_BIT       0x80
 107 #define COMMAND2_REG    0x1
 108 /* enable pretriggering (used in conjunction with SWTRIG) */
 109 #define   PRETRIG_BIT   0x1
 110 /* enable paced conversions on external trigger */
 111 #define   HWTRIG_BIT    0x2
 112 /* enable paced conversions */
 113 #define   SWTRIG_BIT    0x4
 114 /* use two cascaded counters for pacing */
 115 #define   CASCADE_BIT   0x8
 116 #define   DAC_PACED_BIT(channel)        (0x40 << ((channel) & 0x1))
 117 #define COMMAND3_REG    0x2
 118 /* enable dma transfers */
 119 #define   DMA_EN_BIT    0x1
 120 /* enable interrupts for 8255 */
 121 #define   DIO_INTR_EN_BIT       0x2
 122 /* enable dma terminal count interrupt */
 123 #define   DMATC_INTR_EN_BIT     0x4
 124 /* enable timer interrupt */
 125 #define   TIMER_INTR_EN_BIT     0x8
 126 /* enable error interrupt */
 127 #define   ERR_INTR_EN_BIT       0x10
 128 /* enable fifo not empty interrupt */
 129 #define   ADC_FNE_INTR_EN_BIT   0x20
 130 #define ADC_CONVERT_REG 0x3
 131 #define DAC_LSB_REG(channel)    (0x4 + 2 * ((channel) & 0x1))
 132 #define DAC_MSB_REG(channel)    (0x5 + 2 * ((channel) & 0x1))
 133 #define ADC_CLEAR_REG   0x8
 134 #define DMATC_CLEAR_REG 0xa
 135 #define TIMER_CLEAR_REG 0xc
 136 /* 1200 boards only */
 137 #define COMMAND6_REG    0xe
 138 /* select ground or common-mode reference */
 139 #define   ADC_COMMON_BIT        0x1
 140 /*  adc unipolar */
 141 #define   ADC_UNIP_BIT  0x2
 142 /*  dac unipolar */
 143 #define   DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1))
 144 /* enable fifo half full interrupt */
 145 #define   ADC_FHF_INTR_EN_BIT   0x20
 146 /* enable interrupt on end of hardware count */
 147 #define   A1_INTR_EN_BIT        0x40
 148 /* scan up from channel zero instead of down to zero */
 149 #define   ADC_SCAN_UP_BIT 0x80
 150 #define COMMAND4_REG    0xf
 151 /* enables 'interval' scanning */
 152 #define   INTERVAL_SCAN_EN_BIT  0x1
 153 /* enables external signal on counter b1 output to trigger scan */
 154 #define   EXT_SCAN_EN_BIT       0x2
 155 /* chooses direction (output or input) for EXTCONV* line */
 156 #define   EXT_CONVERT_OUT_BIT   0x4
 157 /* chooses differential inputs for adc (in conjunction with board jumper) */
 158 #define   ADC_DIFF_BIT  0x8
 159 #define   EXT_CONVERT_DISABLE_BIT       0x10
 160 /* 1200 boards only, calibration stuff */
 161 #define COMMAND5_REG    0x1c
 162 /* enable eeprom for write */
 163 #define   EEPROM_WRITE_UNPROTECT_BIT    0x4
 164 /* enable dithering */
 165 #define   DITHER_EN_BIT 0x8
 166 /* load calibration dac */
 167 #define   CALDAC_LOAD_BIT       0x10
 168 /* serial clock - rising edge writes, falling edge reads */
 169 #define   SCLOCK_BIT    0x20
 170 /* serial data bit for writing to eeprom or calibration dacs */
 171 #define   SDATA_BIT     0x40
 172 /* enable eeprom for read/write */
 173 #define   EEPROM_EN_BIT 0x80
 174 #define INTERVAL_COUNT_REG      0x1e
 175 #define INTERVAL_LOAD_REG       0x1f
 176 #define   INTERVAL_LOAD_BITS    0x1
 177
 178 /* read-only registers */
 179 #define STATUS1_REG     0x0
 180 /* data is available in fifo */
 181 #define   DATA_AVAIL_BIT        0x1
 182 /* overrun has occurred */
 183 #define   OVERRUN_BIT   0x2
 184 /* fifo overflow */
 185 #define   OVERFLOW_BIT  0x4
 186 /* timer interrupt has occurred */
 187 #define   TIMER_BIT     0x8
 188 /* dma terminal count has occurred */
 189 #define   DMATC_BIT     0x10
 190 /* external trigger has occurred */
 191 #define   EXT_TRIG_BIT  0x40
 192 /* 1200 boards only */
 193 #define STATUS2_REG     0x1d
 194 /* programmable eeprom serial output */
 195 #define   EEPROM_OUT_BIT        0x1
 196 /* counter A1 terminal count */
 197 #define   A1_TC_BIT     0x2
 198 /* fifo not half full */
 199 #define   FNHF_BIT      0x4
 200 #define ADC_FIFO_REG    0xa
 201
 202 #define DIO_BASE_REG    0x10
 203 #define COUNTER_A_BASE_REG      0x14
 204 #define COUNTER_A_CONTROL_REG   (COUNTER_A_BASE_REG + 0x3)
 205 /* check modes put conversion pacer output in harmless state (a0 mode 2) */
 206 #define   INIT_A0_BITS  0x14
 207 /* put hardware conversion counter output in harmless state (a1 mode 0) */
 208 #define   INIT_A1_BITS  0x70
 209 #define COUNTER_B_BASE_REG      0x18
 210
 211 enum scan_mode {
 212         MODE_SINGLE_CHAN,
 213         MODE_SINGLE_CHAN_INTERVAL,
 214         MODE_MULT_CHAN_UP,
 215         MODE_MULT_CHAN_DOWN,
 216 };
 217
 218 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
 219 static irqreturn_t labpc_interrupt(int irq, void *d);
 220 static int labpc_drain_fifo(struct comedi_device *dev);
 221 #ifdef CONFIG_ISA_DMA_API
 222 static void labpc_drain_dma(struct comedi_device *dev);
 223 static void handle_isa_dma(struct comedi_device *dev);
 224 #endif
 225 static void labpc_drain_dregs(struct comedi_device *dev);
 226 static int labpc_ai_cmdtest(struct comedi_device *dev,
 227                             struct comedi_subdevice *s, struct comedi_cmd *cmd);
 228 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 229 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
 230                           struct comedi_insn *insn, unsigned int *data);
 231 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
 232                           struct comedi_insn *insn, unsigned int *data);
 233 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
 234                           struct comedi_insn *insn, unsigned int *data);
 235 static int labpc_calib_read_insn(struct comedi_device *dev,
 236                                  struct comedi_subdevice *s,
 237                                  struct comedi_insn *insn, unsigned int *data);
 238 static int labpc_calib_write_insn(struct comedi_device *dev,
 239                                   struct comedi_subdevice *s,
 240                                   struct comedi_insn *insn, unsigned int *data);
 241 static int labpc_eeprom_read_insn(struct comedi_device *dev,
 242                                   struct comedi_subdevice *s,
 243                                   struct comedi_insn *insn, unsigned int *data);
 244 static int labpc_eeprom_write_insn(struct comedi_device *dev,
 245                                    struct comedi_subdevice *s,
 246                                    struct comedi_insn *insn,
 247                                    unsigned int *data);
 248 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd,
 249                              enum scan_mode scan_mode);
 250 #ifdef CONFIG_ISA_DMA_API
 251 static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd);
 252 #endif
 253 static int labpc_dio_mem_callback(int dir, int port, int data,
 254                                   unsigned long arg);
 255 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
 256                              unsigned int num_bits);
 257 static unsigned int labpc_serial_in(struct comedi_device *dev);
 258 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
 259                                       unsigned int address);
 260 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev);
 261 static int labpc_eeprom_write(struct comedi_device *dev,
 262                                        unsigned int address,
 263                                        unsigned int value);
 264 static void write_caldac(struct comedi_device *dev, unsigned int channel,
 265                          unsigned int value);
 266
 267 /* analog input ranges */
 268 #define NUM_LABPC_PLUS_AI_RANGES 16
 269 /* indicates unipolar ranges */
 270 static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = {
 271         0,
 272         0,
 273         0,
 274         0,
 275         0,
 276         0,
 277         0,
 278         0,
 279         1,
 280         1,
 281         1,
 282         1,
 283         1,
 284         1,
 285         1,
 286         1,
 287 };
 288
 289 /* map range index to gain bits */
 290 static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = {
 291         0x00,
 292         0x10,
 293         0x20,
 294         0x30,
 295         0x40,
 296         0x50,
 297         0x60,
 298         0x70,
 299         0x00,
 300         0x10,
 301         0x20,
 302         0x30,
 303         0x40,
 304         0x50,
 305         0x60,
 306         0x70,
 307 };
 308
 309 static const struct comedi_lrange range_labpc_plus_ai = {
 310         NUM_LABPC_PLUS_AI_RANGES,
 311         {
 312          BIP_RANGE(5),
 313          BIP_RANGE(4),
 314          BIP_RANGE(2.5),
 315          BIP_RANGE(1),
 316          BIP_RANGE(0.5),
 317          BIP_RANGE(0.25),
 318          BIP_RANGE(0.1),
 319          BIP_RANGE(0.05),
 320          UNI_RANGE(10),
 321          UNI_RANGE(8),
 322          UNI_RANGE(5),
 323          UNI_RANGE(2),
 324          UNI_RANGE(1),
 325          UNI_RANGE(0.5),
 326          UNI_RANGE(0.2),
 327          UNI_RANGE(0.1),
 328          }
 329 };
 330
 331 #define NUM_LABPC_1200_AI_RANGES 14
 332 /* indicates unipolar ranges */
 333 const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = {
 334         0,
 335         0,
 336         0,
 337         0,
 338         0,
 339         0,
 340         0,
 341         1,
 342         1,
 343         1,
 344         1,
 345         1,
 346         1,
 347         1,
 348 };
 349 EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar);
 350
 351 /* map range index to gain bits */
 352 const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = {
 353         0x00,
 354         0x20,
 355         0x30,
 356         0x40,
 357         0x50,
 358         0x60,
 359         0x70,
 360         0x00,
 361         0x20,
 362         0x30,
 363         0x40,
 364         0x50,
 365         0x60,
 366         0x70,
 367 };
 368 EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits);
 369
 370 const struct comedi_lrange range_labpc_1200_ai = {
 371         NUM_LABPC_1200_AI_RANGES,
 372         {
 373          BIP_RANGE(5),
 374          BIP_RANGE(2.5),
 375          BIP_RANGE(1),
 376          BIP_RANGE(0.5),
 377          BIP_RANGE(0.25),
 378          BIP_RANGE(0.1),
 379          BIP_RANGE(0.05),
 380          UNI_RANGE(10),
 381          UNI_RANGE(5),
 382          UNI_RANGE(2),
 383          UNI_RANGE(1),
 384          UNI_RANGE(0.5),
 385          UNI_RANGE(0.2),
 386          UNI_RANGE(0.1),
 387          }
 388 };
 389 EXPORT_SYMBOL_GPL(range_labpc_1200_ai);
 390
 391 /* analog output ranges */
 392 #define AO_RANGE_IS_UNIPOLAR 0x1
 393 static const struct comedi_lrange range_labpc_ao = {
 394         2,
 395         {
 396          BIP_RANGE(5),
 397          UNI_RANGE(10),
 398          }
 399 };
 400
 401 /* functions that do inb/outb and readb/writeb so we can use
 402  * function pointers to decide which to use */
 403 static inline unsigned int labpc_inb(unsigned long address)
 404 {
 405         return inb(address);
 406 }
 407
 408 static inline void labpc_outb(unsigned int byte, unsigned long address)
 409 {
 410         outb(byte, address);
 411 }
 412
 413 static inline unsigned int labpc_readb(unsigned long address)
 414 {
 415         return readb((void __iomem *)address);
 416 }
 417
 418 static inline void labpc_writeb(unsigned int byte, unsigned long address)
 419 {
 420         writeb(byte, (void __iomem *)address);
 421 }
 422
 423 static const struct labpc_board_struct labpc_boards[] = {
 424         {
 425          .name = "lab-pc-1200",
 426          .ai_speed = 10000,
 427          .bustype = isa_bustype,
 428          .register_layout = labpc_1200_layout,
 429          .has_ao = 1,
 430          .ai_range_table = &range_labpc_1200_ai,
 431          .ai_range_code = labpc_1200_ai_gain_bits,
 432          .ai_range_is_unipolar = labpc_1200_is_unipolar,
 433          .ai_scan_up = 1,
 434          .memory_mapped_io = 0,
 435          },
 436         {
 437          .name = "lab-pc-1200ai",
 438          .ai_speed = 10000,
 439          .bustype = isa_bustype,
 440          .register_layout = labpc_1200_layout,
 441          .has_ao = 0,
 442          .ai_range_table = &range_labpc_1200_ai,
 443          .ai_range_code = labpc_1200_ai_gain_bits,
 444          .ai_range_is_unipolar = labpc_1200_is_unipolar,
 445          .ai_scan_up = 1,
 446          .memory_mapped_io = 0,
 447          },
 448         {
 449          .name = "lab-pc+",
 450          .ai_speed = 12000,
 451          .bustype = isa_bustype,
 452          .register_layout = labpc_plus_layout,
 453          .has_ao = 1,
 454          .ai_range_table = &range_labpc_plus_ai,
 455          .ai_range_code = labpc_plus_ai_gain_bits,
 456          .ai_range_is_unipolar = labpc_plus_is_unipolar,
 457          .ai_scan_up = 0,
 458          .memory_mapped_io = 0,
 459          },
 460 #ifdef CONFIG_COMEDI_PCI_DRIVERS
 461         {
 462          .name = "pci-1200",
 463          .device_id = 0x161,
 464          .ai_speed = 10000,
 465          .bustype = pci_bustype,
 466          .register_layout = labpc_1200_layout,
 467          .has_ao = 1,
 468          .ai_range_table = &range_labpc_1200_ai,
 469          .ai_range_code = labpc_1200_ai_gain_bits,
 470          .ai_range_is_unipolar = labpc_1200_is_unipolar,
 471          .ai_scan_up = 1,
 472          .memory_mapped_io = 1,
 473          },
 474 /* dummy entry so pci board works when comedi_config is passed driver name */
 475         {
 476          .name = DRV_NAME,
 477          .bustype = pci_bustype,
 478          },
 479 #endif
 480 };
 481
 482 /*
 483  * Useful for shorthand access to the particular board structure
 484  */
 485 #define thisboard ((struct labpc_board_struct *)dev->board_ptr)
 486
 487 /* size in bytes of dma buffer */
 488 static const int dma_buffer_size = 0xff00;
 489 /* 2 bytes per sample */
 490 static const int sample_size = 2;
 491
 492 static inline int labpc_counter_load(struct comedi_device *dev,
 493                                      unsigned long base_address,
 494                                      unsigned int counter_number,
 495                                      unsigned int count, unsigned int mode)
 496 {
 497         if (thisboard->memory_mapped_io)
 498                 return i8254_mm_load((void __iomem *)base_address, 0,
 499                                      counter_number, count, mode);
 500         else
 501                 return i8254_load(base_address, 0, counter_number, count, mode);
 502 }
 503
 504 int labpc_common_attach(struct comedi_device *dev, unsigned long iobase,
 505                         unsigned int irq, unsigned int dma_chan)
 506 {
 507         struct labpc_private *devpriv = dev->private;
 508         struct comedi_subdevice *s;
 509         int i;
 510         unsigned long isr_flags;
 511 #ifdef CONFIG_ISA_DMA_API
 512         unsigned long dma_flags;
 513 #endif
 514         short lsb, msb;
 515         int ret;
 516
 517         dev_info(dev->class_dev, "ni_labpc: %s\n", thisboard->name);
 518         if (iobase == 0) {
 519                 dev_err(dev->class_dev, "io base address is zero!\n");
 520                 return -EINVAL;
 521         }
 522         /*  request io regions for isa boards */
 523         if (thisboard->bustype == isa_bustype) {
 524                 /* check if io addresses are available */
 525                 if (!request_region(iobase, LABPC_SIZE, DRV_NAME)) {
 526                         dev_err(dev->class_dev, "I/O port conflict\n");
 527                         return -EIO;
 528                 }
 529         }
 530         dev->iobase = iobase;
 531
 532         if (thisboard->memory_mapped_io) {
 533                 devpriv->read_byte = labpc_readb;
 534                 devpriv->write_byte = labpc_writeb;
 535         } else {
 536                 devpriv->read_byte = labpc_inb;
 537                 devpriv->write_byte = labpc_outb;
 538         }
 539         /* initialize board's command registers */
 540         devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
 541         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
 542         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
 543         devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
 544         if (thisboard->register_layout == labpc_1200_layout) {
 545                 devpriv->write_byte(devpriv->command5_bits,
 546                                     dev->iobase + COMMAND5_REG);
 547                 devpriv->write_byte(devpriv->command6_bits,
 548                                     dev->iobase + COMMAND6_REG);
 549         }
 550
 551         /* grab our IRQ */
 552         if (irq) {
 553                 isr_flags = 0;
 554                 if (thisboard->bustype == pci_bustype
 555                     || thisboard->bustype == pcmcia_bustype)
 556                         isr_flags |= IRQF_SHARED;
 557                 if (request_irq(irq, labpc_interrupt, isr_flags,
 558                                 DRV_NAME, dev)) {
 559                         dev_err(dev->class_dev, "unable to allocate irq %u\n",
 560                                 irq);
 561                         return -EINVAL;
 562                 }
 563         }
 564         dev->irq = irq;
 565
 566 #ifdef CONFIG_ISA_DMA_API
 567         /* grab dma channel */
 568         if (dma_chan > 3) {
 569                 dev_err(dev->class_dev, "invalid dma channel %u\n", dma_chan);
 570                 return -EINVAL;
 571         } else if (dma_chan) {
 572                 /* allocate dma buffer */
 573                 devpriv->dma_buffer =
 574                     kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA);
 575                 if (devpriv->dma_buffer == NULL) {
 576                         dev_err(dev->class_dev,
 577                                 "failed to allocate dma buffer\n");
 578                         return -ENOMEM;
 579                 }
 580                 if (request_dma(dma_chan, DRV_NAME)) {
 581                         dev_err(dev->class_dev,
 582                                 "failed to allocate dma channel %u\n",
 583                                 dma_chan);
 584                         return -EINVAL;
 585                 }
 586                 devpriv->dma_chan = dma_chan;
 587                 dma_flags = claim_dma_lock();
 588                 disable_dma(devpriv->dma_chan);
 589                 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ);
 590                 release_dma_lock(dma_flags);
 591         }
 592 #endif
 593
 594         dev->board_name = thisboard->name;
 595
 596         ret = comedi_alloc_subdevices(dev, 5);
 597         if (ret)
 598                 return ret;
 599
 600         /* analog input subdevice */
 601         s = &dev->subdevices[0];
 602         dev->read_subdev = s;
 603         s->type = COMEDI_SUBD_AI;
 604         s->subdev_flags =
 605             SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
 606         s->n_chan = 8;
 607         s->len_chanlist = 8;
 608         s->maxdata = (1 << 12) - 1;     /* 12 bit resolution */
 609         s->range_table = thisboard->ai_range_table;
 610         s->do_cmd = labpc_ai_cmd;
 611         s->do_cmdtest = labpc_ai_cmdtest;
 612         s->insn_read = labpc_ai_rinsn;
 613         s->cancel = labpc_cancel;
 614
 615         /* analog output */
 616         s = &dev->subdevices[1];
 617         if (thisboard->has_ao) {
 618                 /*
 619                  * Could provide command support, except it only has a
 620                  * one sample hardware buffer for analog output and no
 621                  * underrun flag.
 622                  */
 623                 s->type = COMEDI_SUBD_AO;
 624                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND;
 625                 s->n_chan = NUM_AO_CHAN;
 626                 s->maxdata = (1 << 12) - 1;     /*  12 bit resolution */
 627                 s->range_table = &range_labpc_ao;
 628                 s->insn_read = labpc_ao_rinsn;
 629                 s->insn_write = labpc_ao_winsn;
 630                 /* initialize analog outputs to a known value */
 631                 for (i = 0; i < s->n_chan; i++) {
 632                         devpriv->ao_value[i] = s->maxdata / 2;
 633                         lsb = devpriv->ao_value[i] & 0xff;
 634                         msb = (devpriv->ao_value[i] >> 8) & 0xff;
 635                         devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i));
 636                         devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i));
 637                 }
 638         } else {
 639                 s->type = COMEDI_SUBD_UNUSED;
 640         }
 641
 642         /* 8255 dio */
 643         s = &dev->subdevices[2];
 644         /*  if board uses io memory we have to give a custom callback
 645          * function to the 8255 driver */
 646         if (thisboard->memory_mapped_io)
 647                 subdev_8255_init(dev, s, labpc_dio_mem_callback,
 648                                  (unsigned long)(dev->iobase + DIO_BASE_REG));
 649         else
 650                 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG);
 651
 652         /*  calibration subdevices for boards that have one */
 653         s = &dev->subdevices[3];
 654         if (thisboard->register_layout == labpc_1200_layout) {
 655                 s->type = COMEDI_SUBD_CALIB;
 656                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
 657                 s->n_chan = 16;
 658                 s->maxdata = 0xff;
 659                 s->insn_read = labpc_calib_read_insn;
 660                 s->insn_write = labpc_calib_write_insn;
 661
 662                 for (i = 0; i < s->n_chan; i++)
 663                         write_caldac(dev, i, s->maxdata / 2);
 664         } else
 665                 s->type = COMEDI_SUBD_UNUSED;
 666
 667         /* EEPROM */
 668         s = &dev->subdevices[4];
 669         if (thisboard->register_layout == labpc_1200_layout) {
 670                 s->type = COMEDI_SUBD_MEMORY;
 671                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
 672                 s->n_chan = EEPROM_SIZE;
 673                 s->maxdata = 0xff;
 674                 s->insn_read = labpc_eeprom_read_insn;
 675                 s->insn_write = labpc_eeprom_write_insn;
 676
 677                 for (i = 0; i < EEPROM_SIZE; i++)
 678                         devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i);
 679         } else
 680                 s->type = COMEDI_SUBD_UNUSED;
 681
 682         return 0;
 683 }
 684 EXPORT_SYMBOL_GPL(labpc_common_attach);
 685
 686 static const struct labpc_board_struct *
 687 labpc_pci_find_boardinfo(struct pci_dev *pcidev)
 688 {
 689         unsigned int device_id = pcidev->device;
 690         unsigned int n;
 691
 692         for (n = 0; n < ARRAY_SIZE(labpc_boards); n++) {
 693                 const struct labpc_board_struct *board = &labpc_boards[n];
 694                 if (board->bustype == pci_bustype &&
 695                     board->device_id == device_id)
 696                         return board;
 697         }
 698         return NULL;
 699 }
 700
 701 static int labpc_auto_attach(struct comedi_device *dev,
 702                                        unsigned long context_unused)
 703 {
 704         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 705         struct labpc_private *devpriv;
 706         unsigned long iobase;
 707         unsigned int irq;
 708         int ret;
 709
 710         if (!IS_ENABLED(CONFIG_COMEDI_PCI_DRIVERS))
 711                 return -ENODEV;
 712
 713         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
 714         if (!devpriv)
 715                 return -ENOMEM;
 716         dev->private = devpriv;
 717
 718         dev->board_ptr = labpc_pci_find_boardinfo(pcidev);
 719         if (!dev->board_ptr)
 720                 return -ENODEV;
 721         devpriv->mite = mite_alloc(pcidev);
 722         if (!devpriv->mite)
 723                 return -ENOMEM;
 724         ret = mite_setup(devpriv->mite);
 725         if (ret < 0)
 726                 return ret;
 727         iobase = (unsigned long)devpriv->mite->daq_io_addr;
 728         irq = mite_irq(devpriv->mite);
 729         return labpc_common_attach(dev, iobase, irq, 0);
 730 }
 731
 732 static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it)
 733 {
 734         struct labpc_private *devpriv;
 735         unsigned long iobase = 0;
 736         unsigned int irq = 0;
 737         unsigned int dma_chan = 0;
 738
 739         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
 740         if (!devpriv)
 741                 return -ENOMEM;
 742         dev->private = devpriv;
 743
 744         /* get base address, irq etc. based on bustype */
 745         switch (thisboard->bustype) {
 746         case isa_bustype:
 747 #ifdef CONFIG_ISA_DMA_API
 748                 iobase = it->options[0];
 749                 irq = it->options[1];
 750                 dma_chan = it->options[2];
 751 #else
 752                 dev_err(dev->class_dev,
 753                         "ni_labpc driver has not been built with ISA DMA support.\n");
 754                 return -EINVAL;
 755 #endif
 756                 break;
 757         case pci_bustype:
 758 #ifdef CONFIG_COMEDI_PCI_DRIVERS
 759                 dev_err(dev->class_dev,
 760                         "manual configuration of PCI board '%s' is not supported\n",
 761                         thisboard->name);
 762                 return -EINVAL;
 763 #else
 764                 dev_err(dev->class_dev,
 765                         "ni_labpc driver has not been built with PCI support.\n");
 766                 return -EINVAL;
 767 #endif
 768                 break;
 769         default:
 770                 dev_err(dev->class_dev,
 771                         "ni_labpc: bug! couldn't determine board type\n");
 772                 return -EINVAL;
 773                 break;
 774         }
 775
 776         return labpc_common_attach(dev, iobase, irq, dma_chan);
 777 }
 778
 779 void labpc_common_detach(struct comedi_device *dev)
 780 {
 781         struct labpc_private *devpriv = dev->private;
 782         struct comedi_subdevice *s;
 783
 784         if (!thisboard)
 785                 return;
 786         if (dev->subdevices) {
 787                 s = &dev->subdevices[2];
 788                 subdev_8255_cleanup(dev, s);
 789         }
 790 #ifdef CONFIG_ISA_DMA_API
 791         /* only free stuff if it has been allocated by _attach */
 792         kfree(devpriv->dma_buffer);
 793         if (devpriv->dma_chan)
 794                 free_dma(devpriv->dma_chan);
 795 #endif
 796         if (dev->irq)
 797                 free_irq(dev->irq, dev);
 798         if (thisboard->bustype == isa_bustype && dev->iobase)
 799                 release_region(dev->iobase, LABPC_SIZE);
 800 #ifdef CONFIG_COMEDI_PCI_DRIVERS
 801         if (devpriv->mite) {
 802                 mite_unsetup(devpriv->mite);
 803                 mite_free(devpriv->mite);
 804         }
 805 #endif
 806 };
 807 EXPORT_SYMBOL_GPL(labpc_common_detach);
 808
 809 static void labpc_clear_adc_fifo(const struct comedi_device *dev)
 810 {
 811         struct labpc_private *devpriv = dev->private;
 812
 813         devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
 814         devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
 815         devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
 816 }
 817
 818 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
 819 {
 820         struct labpc_private *devpriv = dev->private;
 821         unsigned long flags;
 822
 823         spin_lock_irqsave(&dev->spinlock, flags);
 824         devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
 825         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
 826         spin_unlock_irqrestore(&dev->spinlock, flags);
 827
 828         devpriv->command3_bits = 0;
 829         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
 830
 831         return 0;
 832 }
 833
 834 static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd)
 835 {
 836         if (cmd->chanlist_len == 1)
 837                 return MODE_SINGLE_CHAN;
 838
 839         /* chanlist may be NULL during cmdtest. */
 840         if (cmd->chanlist == NULL)
 841                 return MODE_MULT_CHAN_UP;
 842
 843         if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1]))
 844                 return MODE_SINGLE_CHAN_INTERVAL;
 845
 846         if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1]))
 847                 return MODE_MULT_CHAN_UP;
 848
 849         if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1]))
 850                 return MODE_MULT_CHAN_DOWN;
 851
 852         pr_err("ni_labpc: bug! cannot determine AI scan mode\n");
 853         return 0;
 854 }
 855
 856 static int labpc_ai_chanlist_invalid(const struct comedi_device *dev,
 857                                      const struct comedi_cmd *cmd,
 858                                      enum scan_mode mode)
 859 {
 860         int channel, range, aref, i;
 861
 862         if (cmd->chanlist == NULL)
 863                 return 0;
 864
 865         if (mode == MODE_SINGLE_CHAN)
 866                 return 0;
 867
 868         if (mode == MODE_SINGLE_CHAN_INTERVAL) {
 869                 if (cmd->chanlist_len > 0xff) {
 870                         comedi_error(dev,
 871                                      "ni_labpc: chanlist too long for single channel interval mode\n");
 872                         return 1;
 873                 }
 874         }
 875
 876         channel = CR_CHAN(cmd->chanlist[0]);
 877         range = CR_RANGE(cmd->chanlist[0]);
 878         aref = CR_AREF(cmd->chanlist[0]);
 879
 880         for (i = 0; i < cmd->chanlist_len; i++) {
 881
 882                 switch (mode) {
 883                 case MODE_SINGLE_CHAN_INTERVAL:
 884                         if (CR_CHAN(cmd->chanlist[i]) != channel) {
 885                                 comedi_error(dev,
 886                                              "channel scanning order specified in chanlist is not supported by hardware.\n");
 887                                 return 1;
 888                         }
 889                         break;
 890                 case MODE_MULT_CHAN_UP:
 891                         if (CR_CHAN(cmd->chanlist[i]) != i) {
 892                                 comedi_error(dev,
 893                                              "channel scanning order specified in chanlist is not supported by hardware.\n");
 894                                 return 1;
 895                         }
 896                         break;
 897                 case MODE_MULT_CHAN_DOWN:
 898                         if (CR_CHAN(cmd->chanlist[i]) !=
 899                             cmd->chanlist_len - i - 1) {
 900                                 comedi_error(dev,
 901                                              "channel scanning order specified in chanlist is not supported by hardware.\n");
 902                                 return 1;
 903                         }
 904                         break;
 905                 default:
 906                         dev_err(dev->class_dev,
 907                                 "ni_labpc: bug! in chanlist check\n");
 908                         return 1;
 909                         break;
 910                 }
 911
 912                 if (CR_RANGE(cmd->chanlist[i]) != range) {
 913                         comedi_error(dev,
 914                                      "entries in chanlist must all have the same range\n");
 915                         return 1;
 916                 }
 917
 918                 if (CR_AREF(cmd->chanlist[i]) != aref) {
 919                         comedi_error(dev,
 920                                      "entries in chanlist must all have the same reference\n");
 921                         return 1;
 922                 }
 923         }
 924
 925         return 0;
 926 }
 927
 928 static int labpc_use_continuous_mode(const struct comedi_cmd *cmd,
 929                                      enum scan_mode mode)
 930 {
 931         if (mode == MODE_SINGLE_CHAN)
 932                 return 1;
 933
 934         if (cmd->scan_begin_src == TRIG_FOLLOW)
 935                 return 1;
 936
 937         return 0;
 938 }
 939
 940 static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd,
 941                                             enum scan_mode mode)
 942 {
 943         if (cmd->convert_src != TRIG_TIMER)
 944                 return 0;
 945
 946         if (mode == MODE_SINGLE_CHAN && cmd->scan_begin_src == TRIG_TIMER)
 947                 return cmd->scan_begin_arg;
 948
 949         return cmd->convert_arg;
 950 }
 951
 952 static void labpc_set_ai_convert_period(struct comedi_cmd *cmd,
 953                                         enum scan_mode mode, unsigned int ns)
 954 {
 955         if (cmd->convert_src != TRIG_TIMER)
 956                 return;
 957
 958         if (mode == MODE_SINGLE_CHAN &&
 959             cmd->scan_begin_src == TRIG_TIMER) {
 960                 cmd->scan_begin_arg = ns;
 961                 if (cmd->convert_arg > cmd->scan_begin_arg)
 962                         cmd->convert_arg = cmd->scan_begin_arg;
 963         } else
 964                 cmd->convert_arg = ns;
 965 }
 966
 967 static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd,
 968                                         enum scan_mode mode)
 969 {
 970         if (cmd->scan_begin_src != TRIG_TIMER)
 971                 return 0;
 972
 973         if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER)
 974                 return 0;
 975
 976         return cmd->scan_begin_arg;
 977 }
 978
 979 static void labpc_set_ai_scan_period(struct comedi_cmd *cmd,
 980                                      enum scan_mode mode, unsigned int ns)
 981 {
 982         if (cmd->scan_begin_src != TRIG_TIMER)
 983                 return;
 984
 985         if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER)
 986                 return;
 987
 988         cmd->scan_begin_arg = ns;
 989 }
 990
 991 static int labpc_ai_cmdtest(struct comedi_device *dev,
 992                             struct comedi_subdevice *s, struct comedi_cmd *cmd)
 993 {
 994         int err = 0;
 995         int tmp, tmp2;
 996         unsigned int stop_mask;
 997         enum scan_mode mode;
 998
 999         /* Step 1 : check if triggers are trivially valid */
1000
1001         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
1002         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
1003                                         TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT);
1004         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
1005         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
1006
1007         stop_mask = TRIG_COUNT | TRIG_NONE;
1008         if (thisboard->register_layout == labpc_1200_layout)
1009                 stop_mask |= TRIG_EXT;
1010         err |= cfc_check_trigger_src(&cmd->stop_src, stop_mask);
1011
1012         if (err)
1013                 return 1;
1014
1015         /* Step 2a : make sure trigger sources are unique */
1016
1017         err |= cfc_check_trigger_is_unique(cmd->start_src);
1018         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
1019         err |= cfc_check_trigger_is_unique(cmd->convert_src);
1020         err |= cfc_check_trigger_is_unique(cmd->stop_src);
1021
1022         /* Step 2b : and mutually compatible */
1023
1024         /* can't have external stop and start triggers at once */
1025         if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT)
1026                 err++;
1027
1028         if (err)
1029                 return 2;
1030
1031         /* Step 3: check if arguments are trivially valid */
1032
1033         if (cmd->start_arg == TRIG_NOW)
1034                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
1035
1036         if (!cmd->chanlist_len)
1037                 err |= -EINVAL;
1038         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
1039
1040         if (cmd->convert_src == TRIG_TIMER)
1041                 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
1042                                                  thisboard->ai_speed);
1043
1044         /* make sure scan timing is not too fast */
1045         if (cmd->scan_begin_src == TRIG_TIMER) {
1046                 if (cmd->convert_src == TRIG_TIMER)
1047                         err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
1048                                         cmd->convert_arg * cmd->chanlist_len);
1049                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
1050                                 thisboard->ai_speed * cmd->chanlist_len);
1051         }
1052
1053         switch (cmd->stop_src) {
1054         case TRIG_COUNT:
1055                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
1056                 break;
1057         case TRIG_NONE:
1058                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
1059                 break;
1060                 /*
1061                  * TRIG_EXT doesn't care since it doesn't
1062                  * trigger off a numbered channel
1063                  */
1064         default:
1065                 break;
1066         }
1067
1068         if (err)
1069                 return 3;
1070
1071         /* step 4: fix up any arguments */
1072
1073         tmp = cmd->convert_arg;
1074         tmp2 = cmd->scan_begin_arg;
1075         mode = labpc_ai_scan_mode(cmd);
1076         labpc_adc_timing(dev, cmd, mode);
1077         if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg)
1078                 err++;
1079
1080         if (err)
1081                 return 4;
1082
1083         if (labpc_ai_chanlist_invalid(dev, cmd, mode))
1084                 return 5;
1085
1086         return 0;
1087 }
1088
1089 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1090 {
1091         struct labpc_private *devpriv = dev->private;
1092         int channel, range, aref;
1093 #ifdef CONFIG_ISA_DMA_API
1094         unsigned long irq_flags;
1095 #endif
1096         int ret;
1097         struct comedi_async *async = s->async;
1098         struct comedi_cmd *cmd = &async->cmd;
1099         enum transfer_type xfer;
1100         enum scan_mode mode;
1101         unsigned long flags;
1102
1103         if (!dev->irq) {
1104                 comedi_error(dev, "no irq assigned, cannot perform command");
1105                 return -1;
1106         }
1107
1108         range = CR_RANGE(cmd->chanlist[0]);
1109         aref = CR_AREF(cmd->chanlist[0]);
1110
1111         /* make sure board is disabled before setting up acquisition */
1112         spin_lock_irqsave(&dev->spinlock, flags);
1113         devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1114         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1115         spin_unlock_irqrestore(&dev->spinlock, flags);
1116
1117         devpriv->command3_bits = 0;
1118         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1119
1120         /*  initialize software conversion count */
1121         if (cmd->stop_src == TRIG_COUNT)
1122                 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
1123
1124         /*  setup hardware conversion counter */
1125         if (cmd->stop_src == TRIG_EXT) {
1126                 /*
1127                  * load counter a1 with count of 3
1128                  * (pc+ manual says this is minimum allowed) using mode 0
1129                  */
1130                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1131                                          1, 3, 0);
1132                 if (ret < 0) {
1133                         comedi_error(dev, "error loading counter a1");
1134                         return -1;
1135                 }
1136         } else                  /*
1137                                  * otherwise, just put a1 in mode 0
1138                                  * with no count to set its output low
1139                                  */
1140                 devpriv->write_byte(INIT_A1_BITS,
1141                                     dev->iobase + COUNTER_A_CONTROL_REG);
1142
1143 #ifdef CONFIG_ISA_DMA_API
1144         /*  figure out what method we will use to transfer data */
1145         if (devpriv->dma_chan &&        /*  need a dma channel allocated */
1146                 /*
1147                  * dma unsafe at RT priority,
1148                  * and too much setup time for TRIG_WAKE_EOS for
1149                  */
1150             (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 &&
1151             /*  only available on the isa boards */
1152             thisboard->bustype == isa_bustype) {
1153                 xfer = isa_dma_transfer;
1154                 /* pc-plus has no fifo-half full interrupt */
1155         } else
1156 #endif
1157         if (thisboard->register_layout == labpc_1200_layout &&
1158                    /*  wake-end-of-scan should interrupt on fifo not empty */
1159                    (cmd->flags & TRIG_WAKE_EOS) == 0 &&
1160                    /*  make sure we are taking more than just a few points */
1161                    (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) {
1162                 xfer = fifo_half_full_transfer;
1163         } else
1164                 xfer = fifo_not_empty_transfer;
1165         devpriv->current_transfer = xfer;
1166         mode = labpc_ai_scan_mode(cmd);
1167
1168         /*  setup command6 register for 1200 boards */
1169         if (thisboard->register_layout == labpc_1200_layout) {
1170                 /*  reference inputs to ground or common? */
1171                 if (aref != AREF_GROUND)
1172                         devpriv->command6_bits |= ADC_COMMON_BIT;
1173                 else
1174                         devpriv->command6_bits &= ~ADC_COMMON_BIT;
1175                 /*  bipolar or unipolar range? */
1176                 if (thisboard->ai_range_is_unipolar[range])
1177                         devpriv->command6_bits |= ADC_UNIP_BIT;
1178                 else
1179                         devpriv->command6_bits &= ~ADC_UNIP_BIT;
1180                 /*  interrupt on fifo half full? */
1181                 if (xfer == fifo_half_full_transfer)
1182                         devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT;
1183                 else
1184                         devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1185                 /*  enable interrupt on counter a1 terminal count? */
1186                 if (cmd->stop_src == TRIG_EXT)
1187                         devpriv->command6_bits |= A1_INTR_EN_BIT;
1188                 else
1189                         devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1190                 /*  are we scanning up or down through channels? */
1191                 if (mode == MODE_MULT_CHAN_UP)
1192                         devpriv->command6_bits |= ADC_SCAN_UP_BIT;
1193                 else
1194                         devpriv->command6_bits &= ~ADC_SCAN_UP_BIT;
1195                 /*  write to register */
1196                 devpriv->write_byte(devpriv->command6_bits,
1197                                     dev->iobase + COMMAND6_REG);
1198         }
1199
1200         /* setup channel list, etc (command1 register) */
1201         devpriv->command1_bits = 0;
1202         if (mode == MODE_MULT_CHAN_UP)
1203                 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
1204         else
1205                 channel = CR_CHAN(cmd->chanlist[0]);
1206         /* munge channel bits for differential / scan disabled mode */
1207         if (mode != MODE_SINGLE_CHAN && aref == AREF_DIFF)
1208                 channel *= 2;
1209         devpriv->command1_bits |= ADC_CHAN_BITS(channel);
1210         devpriv->command1_bits |= thisboard->ai_range_code[range];
1211         devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1212         /* manual says to set scan enable bit on second pass */
1213         if (mode == MODE_MULT_CHAN_UP || mode == MODE_MULT_CHAN_DOWN) {
1214                 devpriv->command1_bits |= ADC_SCAN_EN_BIT;
1215                 /* need a brief delay before enabling scan, or scan
1216                  * list will get screwed when you switch
1217                  * between scan up to scan down mode - dunno why */
1218                 udelay(1);
1219                 devpriv->write_byte(devpriv->command1_bits,
1220                                     dev->iobase + COMMAND1_REG);
1221         }
1222         /*  setup any external triggering/pacing (command4 register) */
1223         devpriv->command4_bits = 0;
1224         if (cmd->convert_src != TRIG_EXT)
1225                 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1226         /* XXX should discard first scan when using interval scanning
1227          * since manual says it is not synced with scan clock */
1228         if (labpc_use_continuous_mode(cmd, mode) == 0) {
1229                 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT;
1230                 if (cmd->scan_begin_src == TRIG_EXT)
1231                         devpriv->command4_bits |= EXT_SCAN_EN_BIT;
1232         }
1233         /*  single-ended/differential */
1234         if (aref == AREF_DIFF)
1235                 devpriv->command4_bits |= ADC_DIFF_BIT;
1236         devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1237
1238         devpriv->write_byte(cmd->chanlist_len,
1239                             dev->iobase + INTERVAL_COUNT_REG);
1240         /*  load count */
1241         devpriv->write_byte(INTERVAL_LOAD_BITS,
1242                             dev->iobase + INTERVAL_LOAD_REG);
1243
1244         if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) {
1245                 /*  set up pacing */
1246                 labpc_adc_timing(dev, cmd, mode);
1247                 /*  load counter b0 in mode 3 */
1248                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1249                                          0, devpriv->divisor_b0, 3);
1250                 if (ret < 0) {
1251                         comedi_error(dev, "error loading counter b0");
1252                         return -1;
1253                 }
1254         }
1255         /*  set up conversion pacing */
1256         if (labpc_ai_convert_period(cmd, mode)) {
1257                 /*  load counter a0 in mode 2 */
1258                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1259                                          0, devpriv->divisor_a0, 2);
1260                 if (ret < 0) {
1261                         comedi_error(dev, "error loading counter a0");
1262                         return -1;
1263                 }
1264         } else
1265                 devpriv->write_byte(INIT_A0_BITS,
1266                                     dev->iobase + COUNTER_A_CONTROL_REG);
1267
1268         /*  set up scan pacing */
1269         if (labpc_ai_scan_period(cmd, mode)) {
1270                 /*  load counter b1 in mode 2 */
1271                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1272                                          1, devpriv->divisor_b1, 2);
1273                 if (ret < 0) {
1274                         comedi_error(dev, "error loading counter b1");
1275                         return -1;
1276                 }
1277         }
1278
1279         labpc_clear_adc_fifo(dev);
1280
1281 #ifdef CONFIG_ISA_DMA_API
1282         /*  set up dma transfer */
1283         if (xfer == isa_dma_transfer) {
1284                 irq_flags = claim_dma_lock();
1285                 disable_dma(devpriv->dma_chan);
1286                 /* clear flip-flop to make sure 2-byte registers for
1287                  * count and address get set correctly */
1288                 clear_dma_ff(devpriv->dma_chan);
1289                 set_dma_addr(devpriv->dma_chan,
1290                              virt_to_bus(devpriv->dma_buffer));
1291                 /*  set appropriate size of transfer */
1292                 devpriv->dma_transfer_size = labpc_suggest_transfer_size(cmd);
1293                 if (cmd->stop_src == TRIG_COUNT &&
1294                     devpriv->count * sample_size < devpriv->dma_transfer_size) {
1295                         devpriv->dma_transfer_size =
1296                             devpriv->count * sample_size;
1297                 }
1298                 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size);
1299                 enable_dma(devpriv->dma_chan);
1300                 release_dma_lock(irq_flags);
1301                 /*  enable board's dma */
1302                 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT;
1303         } else
1304                 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT;
1305 #endif
1306
1307         /*  enable error interrupts */
1308         devpriv->command3_bits |= ERR_INTR_EN_BIT;
1309         /*  enable fifo not empty interrupt? */
1310         if (xfer == fifo_not_empty_transfer)
1311                 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT;
1312         else
1313                 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT;
1314         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1315
1316         /*  startup acquisition */
1317
1318         /*  command2 reg */
1319         /*  use 2 cascaded counters for pacing */
1320         spin_lock_irqsave(&dev->spinlock, flags);
1321         devpriv->command2_bits |= CASCADE_BIT;
1322         switch (cmd->start_src) {
1323         case TRIG_EXT:
1324                 devpriv->command2_bits |= HWTRIG_BIT;
1325                 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT;
1326                 break;
1327         case TRIG_NOW:
1328                 devpriv->command2_bits |= SWTRIG_BIT;
1329                 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT;
1330                 break;
1331         default:
1332                 comedi_error(dev, "bug with start_src");
1333                 spin_unlock_irqrestore(&dev->spinlock, flags);
1334                 return -1;
1335                 break;
1336         }
1337         switch (cmd->stop_src) {
1338         case TRIG_EXT:
1339                 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT;
1340                 break;
1341         case TRIG_COUNT:
1342         case TRIG_NONE:
1343                 break;
1344         default:
1345                 comedi_error(dev, "bug with stop_src");
1346                 spin_unlock_irqrestore(&dev->spinlock, flags);
1347                 return -1;
1348         }
1349         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1350         spin_unlock_irqrestore(&dev->spinlock, flags);
1351
1352         return 0;
1353 }
1354
1355 /* interrupt service routine */
1356 static irqreturn_t labpc_interrupt(int irq, void *d)
1357 {
1358         struct comedi_device *dev = d;
1359         struct labpc_private *devpriv = dev->private;
1360         struct comedi_subdevice *s = dev->read_subdev;
1361         struct comedi_async *async;
1362         struct comedi_cmd *cmd;
1363
1364         if (dev->attached == 0) {
1365                 comedi_error(dev, "premature interrupt");
1366                 return IRQ_HANDLED;
1367         }
1368
1369         async = s->async;
1370         cmd = &async->cmd;
1371         async->events = 0;
1372
1373         /* read board status */
1374         devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1375         if (thisboard->register_layout == labpc_1200_layout)
1376                 devpriv->status2_bits =
1377                     devpriv->read_byte(dev->iobase + STATUS2_REG);
1378
1379         if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT |
1380                                       OVERRUN_BIT | DATA_AVAIL_BIT)) == 0
1381             && (devpriv->status2_bits & A1_TC_BIT) == 0
1382             && (devpriv->status2_bits & FNHF_BIT)) {
1383                 return IRQ_NONE;
1384         }
1385
1386         if (devpriv->status1_bits & OVERRUN_BIT) {
1387                 /* clear error interrupt */
1388                 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1389                 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1390                 comedi_event(dev, s);
1391                 comedi_error(dev, "overrun");
1392                 return IRQ_HANDLED;
1393         }
1394
1395 #ifdef CONFIG_ISA_DMA_API
1396         if (devpriv->current_transfer == isa_dma_transfer) {
1397                 /*
1398                  * if a dma terminal count of external stop trigger
1399                  * has occurred
1400                  */
1401                 if (devpriv->status1_bits & DMATC_BIT ||
1402                     (thisboard->register_layout == labpc_1200_layout
1403                      && devpriv->status2_bits & A1_TC_BIT)) {
1404                         handle_isa_dma(dev);
1405                 }
1406         } else
1407 #endif
1408                 labpc_drain_fifo(dev);
1409
1410         if (devpriv->status1_bits & TIMER_BIT) {
1411                 comedi_error(dev, "handled timer interrupt?");
1412                 /*  clear it */
1413                 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG);
1414         }
1415
1416         if (devpriv->status1_bits & OVERFLOW_BIT) {
1417                 /*  clear error interrupt */
1418                 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1419                 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1420                 comedi_event(dev, s);
1421                 comedi_error(dev, "overflow");
1422                 return IRQ_HANDLED;
1423         }
1424         /*  handle external stop trigger */
1425         if (cmd->stop_src == TRIG_EXT) {
1426                 if (devpriv->status2_bits & A1_TC_BIT) {
1427                         labpc_drain_dregs(dev);
1428                         labpc_cancel(dev, s);
1429                         async->events |= COMEDI_CB_EOA;
1430                 }
1431         }
1432
1433         /* TRIG_COUNT end of acquisition */
1434         if (cmd->stop_src == TRIG_COUNT) {
1435                 if (devpriv->count == 0) {
1436                         labpc_cancel(dev, s);
1437                         async->events |= COMEDI_CB_EOA;
1438                 }
1439         }
1440
1441         comedi_event(dev, s);
1442         return IRQ_HANDLED;
1443 }
1444
1445 /* read all available samples from ai fifo */
1446 static int labpc_drain_fifo(struct comedi_device *dev)
1447 {
1448         struct labpc_private *devpriv = dev->private;
1449         unsigned int lsb, msb;
1450         short data;
1451         struct comedi_async *async = dev->read_subdev->async;
1452         const int timeout = 10000;
1453         unsigned int i;
1454
1455         devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1456
1457         for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout;
1458              i++) {
1459                 /*  quit if we have all the data we want */
1460                 if (async->cmd.stop_src == TRIG_COUNT) {
1461                         if (devpriv->count == 0)
1462                                 break;
1463                         devpriv->count--;
1464                 }
1465                 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1466                 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1467                 data = (msb << 8) | lsb;
1468                 cfc_write_to_buffer(dev->read_subdev, data);
1469                 devpriv->status1_bits =
1470                     devpriv->read_byte(dev->iobase + STATUS1_REG);
1471         }
1472         if (i == timeout) {
1473                 comedi_error(dev, "ai timeout, fifo never empties");
1474                 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1475                 return -1;
1476         }
1477
1478         return 0;
1479 }
1480
1481 #ifdef CONFIG_ISA_DMA_API
1482 static void labpc_drain_dma(struct comedi_device *dev)
1483 {
1484         struct labpc_private *devpriv = dev->private;
1485         struct comedi_subdevice *s = dev->read_subdev;
1486         struct comedi_async *async = s->async;
1487         int status;
1488         unsigned long flags;
1489         unsigned int max_points, num_points, residue, leftover;
1490         int i;
1491
1492         status = devpriv->status1_bits;
1493
1494         flags = claim_dma_lock();
1495         disable_dma(devpriv->dma_chan);
1496         /* clear flip-flop to make sure 2-byte registers for
1497          * count and address get set correctly */
1498         clear_dma_ff(devpriv->dma_chan);
1499
1500         /*  figure out how many points to read */
1501         max_points = devpriv->dma_transfer_size / sample_size;
1502         /* residue is the number of points left to be done on the dma
1503          * transfer.  It should always be zero at this point unless
1504          * the stop_src is set to external triggering.
1505          */
1506         residue = get_dma_residue(devpriv->dma_chan) / sample_size;
1507         num_points = max_points - residue;
1508         if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT)
1509                 num_points = devpriv->count;
1510
1511         /*  figure out how many points will be stored next time */
1512         leftover = 0;
1513         if (async->cmd.stop_src != TRIG_COUNT) {
1514                 leftover = devpriv->dma_transfer_size / sample_size;
1515         } else if (devpriv->count > num_points) {
1516                 leftover = devpriv->count - num_points;
1517                 if (leftover > max_points)
1518                         leftover = max_points;
1519         }
1520
1521         /* write data to comedi buffer */
1522         for (i = 0; i < num_points; i++)
1523                 cfc_write_to_buffer(s, devpriv->dma_buffer[i]);
1524
1525         if (async->cmd.stop_src == TRIG_COUNT)
1526                 devpriv->count -= num_points;
1527
1528         /*  set address and count for next transfer */
1529         set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer));
1530         set_dma_count(devpriv->dma_chan, leftover * sample_size);
1531         release_dma_lock(flags);
1532
1533         async->events |= COMEDI_CB_BLOCK;
1534 }
1535
1536 static void handle_isa_dma(struct comedi_device *dev)
1537 {
1538         struct labpc_private *devpriv = dev->private;
1539
1540         labpc_drain_dma(dev);
1541
1542         enable_dma(devpriv->dma_chan);
1543
1544         /*  clear dma tc interrupt */
1545         devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG);
1546 }
1547 #endif
1548
1549 /* makes sure all data acquired by board is transferred to comedi (used
1550  * when acquisition is terminated by stop_src == TRIG_EXT). */
1551 static void labpc_drain_dregs(struct comedi_device *dev)
1552 {
1553 #ifdef CONFIG_ISA_DMA_API
1554         struct labpc_private *devpriv = dev->private;
1555
1556         if (devpriv->current_transfer == isa_dma_transfer)
1557                 labpc_drain_dma(dev);
1558 #endif
1559
1560         labpc_drain_fifo(dev);
1561 }
1562
1563 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1564                           struct comedi_insn *insn, unsigned int *data)
1565 {
1566         struct labpc_private *devpriv = dev->private;
1567         int i, n;
1568         int chan, range;
1569         int lsb, msb;
1570         int timeout = 1000;
1571         unsigned long flags;
1572
1573         /*  disable timed conversions */
1574         spin_lock_irqsave(&dev->spinlock, flags);
1575         devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1576         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1577         spin_unlock_irqrestore(&dev->spinlock, flags);
1578
1579         /*  disable interrupt generation and dma */
1580         devpriv->command3_bits = 0;
1581         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1582
1583         /* set gain and channel */
1584         devpriv->command1_bits = 0;
1585         chan = CR_CHAN(insn->chanspec);
1586         range = CR_RANGE(insn->chanspec);
1587         devpriv->command1_bits |= thisboard->ai_range_code[range];
1588         /* munge channel bits for differential/scan disabled mode */
1589         if (CR_AREF(insn->chanspec) == AREF_DIFF)
1590                 chan *= 2;
1591         devpriv->command1_bits |= ADC_CHAN_BITS(chan);
1592         devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1593
1594         /* setup command6 register for 1200 boards */
1595         if (thisboard->register_layout == labpc_1200_layout) {
1596                 /*  reference inputs to ground or common? */
1597                 if (CR_AREF(insn->chanspec) != AREF_GROUND)
1598                         devpriv->command6_bits |= ADC_COMMON_BIT;
1599                 else
1600                         devpriv->command6_bits &= ~ADC_COMMON_BIT;
1601                 /* bipolar or unipolar range? */
1602                 if (thisboard->ai_range_is_unipolar[range])
1603                         devpriv->command6_bits |= ADC_UNIP_BIT;
1604                 else
1605                         devpriv->command6_bits &= ~ADC_UNIP_BIT;
1606                 /* don't interrupt on fifo half full */
1607                 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1608                 /* don't enable interrupt on counter a1 terminal count? */
1609                 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1610                 /* write to register */
1611                 devpriv->write_byte(devpriv->command6_bits,
1612                                     dev->iobase + COMMAND6_REG);
1613         }
1614         /* setup command4 register */
1615         devpriv->command4_bits = 0;
1616         devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1617         /* single-ended/differential */
1618         if (CR_AREF(insn->chanspec) == AREF_DIFF)
1619                 devpriv->command4_bits |= ADC_DIFF_BIT;
1620         devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1621
1622         /*
1623          * initialize pacer counter output to make sure it doesn't
1624          * cause any problems
1625          */
1626         devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG);
1627
1628         labpc_clear_adc_fifo(dev);
1629
1630         for (n = 0; n < insn->n; n++) {
1631                 /* trigger conversion */
1632                 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG);
1633
1634                 for (i = 0; i < timeout; i++) {
1635                         if (devpriv->read_byte(dev->iobase +
1636                                                STATUS1_REG) & DATA_AVAIL_BIT)
1637                                 break;
1638                         udelay(1);
1639                 }
1640                 if (i == timeout) {
1641                         comedi_error(dev, "timeout");
1642                         return -ETIME;
1643                 }
1644                 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1645                 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1646                 data[n] = (msb << 8) | lsb;
1647         }
1648
1649         return n;
1650 }
1651
1652 /* analog output insn */
1653 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1654                           struct comedi_insn *insn, unsigned int *data)
1655 {
1656         struct labpc_private *devpriv = dev->private;
1657         int channel, range;
1658         unsigned long flags;
1659         int lsb, msb;
1660
1661         channel = CR_CHAN(insn->chanspec);
1662
1663         /* turn off pacing of analog output channel */
1664         /* note: hardware bug in daqcard-1200 means pacing cannot
1665          * be independently enabled/disabled for its the two channels */
1666         spin_lock_irqsave(&dev->spinlock, flags);
1667         devpriv->command2_bits &= ~DAC_PACED_BIT(channel);
1668         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1669         spin_unlock_irqrestore(&dev->spinlock, flags);
1670
1671         /* set range */
1672         if (thisboard->register_layout == labpc_1200_layout) {
1673                 range = CR_RANGE(insn->chanspec);
1674                 if (range & AO_RANGE_IS_UNIPOLAR)
1675                         devpriv->command6_bits |= DAC_UNIP_BIT(channel);
1676                 else
1677                         devpriv->command6_bits &= ~DAC_UNIP_BIT(channel);
1678                 /*  write to register */
1679                 devpriv->write_byte(devpriv->command6_bits,
1680                                     dev->iobase + COMMAND6_REG);
1681         }
1682         /* send data */
1683         lsb = data[0] & 0xff;
1684         msb = (data[0] >> 8) & 0xff;
1685         devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel));
1686         devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel));
1687
1688         /* remember value for readback */
1689         devpriv->ao_value[channel] = data[0];
1690
1691         return 1;
1692 }
1693
1694 /* analog output readback insn */
1695 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1696                           struct comedi_insn *insn, unsigned int *data)
1697 {
1698         struct labpc_private *devpriv = dev->private;
1699
1700         data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
1701
1702         return 1;
1703 }
1704
1705 static int labpc_calib_read_insn(struct comedi_device *dev,
1706                                  struct comedi_subdevice *s,
1707                                  struct comedi_insn *insn, unsigned int *data)
1708 {
1709         struct labpc_private *devpriv = dev->private;
1710
1711         data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)];
1712
1713         return 1;
1714 }
1715
1716 static int labpc_calib_write_insn(struct comedi_device *dev,
1717                                   struct comedi_subdevice *s,
1718                                   struct comedi_insn *insn, unsigned int *data)
1719 {
1720         int channel = CR_CHAN(insn->chanspec);
1721
1722         write_caldac(dev, channel, data[0]);
1723         return 1;
1724 }
1725
1726 static int labpc_eeprom_read_insn(struct comedi_device *dev,
1727                                   struct comedi_subdevice *s,
1728                                   struct comedi_insn *insn, unsigned int *data)
1729 {
1730         struct labpc_private *devpriv = dev->private;
1731
1732         data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)];
1733
1734         return 1;
1735 }
1736
1737 static int labpc_eeprom_write_insn(struct comedi_device *dev,
1738                                    struct comedi_subdevice *s,
1739                                    struct comedi_insn *insn, unsigned int *data)
1740 {
1741         int channel = CR_CHAN(insn->chanspec);
1742         int ret;
1743
1744         /*  only allow writes to user area of eeprom */
1745         if (channel < 16 || channel > 127) {
1746                 dev_dbg(dev->class_dev,
1747                         "eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)\n");
1748                 return -EINVAL;
1749         }
1750
1751         ret = labpc_eeprom_write(dev, channel, data[0]);
1752         if (ret < 0)
1753                 return ret;
1754
1755         return 1;
1756 }
1757
1758 #ifdef CONFIG_ISA_DMA_API
1759 /* utility function that suggests a dma transfer size in bytes */
1760 static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd)
1761 {
1762         unsigned int size;
1763         unsigned int freq;
1764
1765         if (cmd->convert_src == TRIG_TIMER)
1766                 freq = 1000000000 / cmd->convert_arg;
1767         /* return some default value */
1768         else
1769                 freq = 0xffffffff;
1770
1771         /* make buffer fill in no more than 1/3 second */
1772         size = (freq / 3) * sample_size;
1773
1774         /* set a minimum and maximum size allowed */
1775         if (size > dma_buffer_size)
1776                 size = dma_buffer_size - dma_buffer_size % sample_size;
1777         else if (size < sample_size)
1778                 size = sample_size;
1779
1780         return size;
1781 }
1782 #endif
1783
1784 /* figures out what counter values to use based on command */
1785 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd,
1786                              enum scan_mode mode)
1787 {
1788         struct labpc_private *devpriv = dev->private;
1789         /* max value for 16 bit counter in mode 2 */
1790         const int max_counter_value = 0x10000;
1791         /* min value for 16 bit counter in mode 2 */
1792         const int min_counter_value = 2;
1793         unsigned int base_period;
1794         unsigned int scan_period;
1795         unsigned int convert_period;
1796
1797         /*
1798          * if both convert and scan triggers are TRIG_TIMER, then they
1799          * both rely on counter b0
1800          */
1801         convert_period = labpc_ai_convert_period(cmd, mode);
1802         scan_period = labpc_ai_scan_period(cmd, mode);
1803         if (convert_period && scan_period) {
1804                 /*
1805                  * pick the lowest b0 divisor value we can (for maximum input
1806                  * clock speed on convert and scan counters)
1807                  */
1808                 devpriv->divisor_b0 = (scan_period - 1) /
1809                     (LABPC_TIMER_BASE * max_counter_value) + 1;
1810                 if (devpriv->divisor_b0 < min_counter_value)
1811                         devpriv->divisor_b0 = min_counter_value;
1812                 if (devpriv->divisor_b0 > max_counter_value)
1813                         devpriv->divisor_b0 = max_counter_value;
1814
1815                 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0;
1816
1817                 /*  set a0 for conversion frequency and b1 for scan frequency */
1818                 switch (cmd->flags & TRIG_ROUND_MASK) {
1819                 default:
1820                 case TRIG_ROUND_NEAREST:
1821                         devpriv->divisor_a0 =
1822                             (convert_period + (base_period / 2)) / base_period;
1823                         devpriv->divisor_b1 =
1824                             (scan_period + (base_period / 2)) / base_period;
1825                         break;
1826                 case TRIG_ROUND_UP:
1827                         devpriv->divisor_a0 =
1828                             (convert_period + (base_period - 1)) / base_period;
1829                         devpriv->divisor_b1 =
1830                             (scan_period + (base_period - 1)) / base_period;
1831                         break;
1832                 case TRIG_ROUND_DOWN:
1833                         devpriv->divisor_a0 = convert_period / base_period;
1834                         devpriv->divisor_b1 = scan_period / base_period;
1835                         break;
1836                 }
1837                 /*  make sure a0 and b1 values are acceptable */
1838                 if (devpriv->divisor_a0 < min_counter_value)
1839                         devpriv->divisor_a0 = min_counter_value;
1840                 if (devpriv->divisor_a0 > max_counter_value)
1841                         devpriv->divisor_a0 = max_counter_value;
1842                 if (devpriv->divisor_b1 < min_counter_value)
1843                         devpriv->divisor_b1 = min_counter_value;
1844                 if (devpriv->divisor_b1 > max_counter_value)
1845                         devpriv->divisor_b1 = max_counter_value;
1846                 /*  write corrected timings to command */
1847                 labpc_set_ai_convert_period(cmd, mode,
1848                                             base_period * devpriv->divisor_a0);
1849                 labpc_set_ai_scan_period(cmd, mode,
1850                                          base_period * devpriv->divisor_b1);
1851                 /*
1852                  * if only one TRIG_TIMER is used, we can employ the generic
1853                  * cascaded timing functions
1854                  */
1855         } else if (scan_period) {
1856                 /*
1857                  * calculate cascaded counter values
1858                  * that give desired scan timing
1859                  */
1860                 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1861                                                &(devpriv->divisor_b1),
1862                                                &(devpriv->divisor_b0),
1863                                                &scan_period,
1864                                                cmd->flags & TRIG_ROUND_MASK);
1865                 labpc_set_ai_scan_period(cmd, mode, scan_period);
1866         } else if (convert_period) {
1867                 /*
1868                  * calculate cascaded counter values
1869                  * that give desired conversion timing
1870                  */
1871                 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1872                                                &(devpriv->divisor_a0),
1873                                                &(devpriv->divisor_b0),
1874                                                &convert_period,
1875                                                cmd->flags & TRIG_ROUND_MASK);
1876                 labpc_set_ai_convert_period(cmd, mode, convert_period);
1877         }
1878 }
1879
1880 static int labpc_dio_mem_callback(int dir, int port, int data,
1881                                   unsigned long iobase)
1882 {
1883         if (dir) {
1884                 writeb(data, (void __iomem *)(iobase + port));
1885                 return 0;
1886         } else {
1887                 return readb((void __iomem *)(iobase + port));
1888         }
1889 }
1890
1891 /* lowlevel write to eeprom/dac */
1892 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
1893                              unsigned int value_width)
1894 {
1895         struct labpc_private *devpriv = dev->private;
1896         int i;
1897
1898         for (i = 1; i <= value_width; i++) {
1899                 /*  clear serial clock */
1900                 devpriv->command5_bits &= ~SCLOCK_BIT;
1901                 /*  send bits most significant bit first */
1902                 if (value & (1 << (value_width - i)))
1903                         devpriv->command5_bits |= SDATA_BIT;
1904                 else
1905                         devpriv->command5_bits &= ~SDATA_BIT;
1906                 udelay(1);
1907                 devpriv->write_byte(devpriv->command5_bits,
1908                                     dev->iobase + COMMAND5_REG);
1909                 /*  set clock to load bit */
1910                 devpriv->command5_bits |= SCLOCK_BIT;
1911                 udelay(1);
1912                 devpriv->write_byte(devpriv->command5_bits,
1913                                     dev->iobase + COMMAND5_REG);
1914         }
1915 }
1916
1917 /* lowlevel read from eeprom */
1918 static unsigned int labpc_serial_in(struct comedi_device *dev)
1919 {
1920         struct labpc_private *devpriv = dev->private;
1921         unsigned int value = 0;
1922         int i;
1923         const int value_width = 8;      /*  number of bits wide values are */
1924
1925         for (i = 1; i <= value_width; i++) {
1926                 /*  set serial clock */
1927                 devpriv->command5_bits |= SCLOCK_BIT;
1928                 udelay(1);
1929                 devpriv->write_byte(devpriv->command5_bits,
1930                                     dev->iobase + COMMAND5_REG);
1931                 /*  clear clock bit */
1932                 devpriv->command5_bits &= ~SCLOCK_BIT;
1933                 udelay(1);
1934                 devpriv->write_byte(devpriv->command5_bits,
1935                                     dev->iobase + COMMAND5_REG);
1936                 /*  read bits most significant bit first */
1937                 udelay(1);
1938                 devpriv->status2_bits =
1939                     devpriv->read_byte(dev->iobase + STATUS2_REG);
1940                 if (devpriv->status2_bits & EEPROM_OUT_BIT)
1941                         value |= 1 << (value_width - i);
1942         }
1943
1944         return value;
1945 }
1946
1947 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
1948                                       unsigned int address)
1949 {
1950         struct labpc_private *devpriv = dev->private;
1951         unsigned int value;
1952         /*  bits to tell eeprom to expect a read */
1953         const int read_instruction = 0x3;
1954         /*  8 bit write lengths to eeprom */
1955         const int write_length = 8;
1956
1957         /*  enable read/write to eeprom */
1958         devpriv->command5_bits &= ~EEPROM_EN_BIT;
1959         udelay(1);
1960         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1961         devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1962         udelay(1);
1963         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1964
1965         /*  send read instruction */
1966         labpc_serial_out(dev, read_instruction, write_length);
1967         /*  send 8 bit address to read from */
1968         labpc_serial_out(dev, address, write_length);
1969         /*  read result */
1970         value = labpc_serial_in(dev);
1971
1972         /*  disable read/write to eeprom */
1973         devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1974         udelay(1);
1975         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1976
1977         return value;
1978 }
1979
1980 static int labpc_eeprom_write(struct comedi_device *dev,
1981                                 unsigned int address, unsigned int value)
1982 {
1983         struct labpc_private *devpriv = dev->private;
1984         const int write_enable_instruction = 0x6;
1985         const int write_instruction = 0x2;
1986         const int write_length = 8;     /*  8 bit write lengths to eeprom */
1987         const int write_in_progress_bit = 0x1;
1988         const int timeout = 10000;
1989         int i;
1990
1991         /*  make sure there isn't already a write in progress */
1992         for (i = 0; i < timeout; i++) {
1993                 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) ==
1994                     0)
1995                         break;
1996         }
1997         if (i == timeout) {
1998                 comedi_error(dev, "eeprom write timed out");
1999                 return -ETIME;
2000         }
2001         /*  update software copy of eeprom */
2002         devpriv->eeprom_data[address] = value;
2003
2004         /*  enable read/write to eeprom */
2005         devpriv->command5_bits &= ~EEPROM_EN_BIT;
2006         udelay(1);
2007         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2008         devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
2009         udelay(1);
2010         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2011
2012         /*  send write_enable instruction */
2013         labpc_serial_out(dev, write_enable_instruction, write_length);
2014         devpriv->command5_bits &= ~EEPROM_EN_BIT;
2015         udelay(1);
2016         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2017
2018         /*  send write instruction */
2019         devpriv->command5_bits |= EEPROM_EN_BIT;
2020         udelay(1);
2021         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2022         labpc_serial_out(dev, write_instruction, write_length);
2023         /*  send 8 bit address to write to */
2024         labpc_serial_out(dev, address, write_length);
2025         /*  write value */
2026         labpc_serial_out(dev, value, write_length);
2027         devpriv->command5_bits &= ~EEPROM_EN_BIT;
2028         udelay(1);
2029         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2030
2031         /*  disable read/write to eeprom */
2032         devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2033         udelay(1);
2034         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2035
2036         return 0;
2037 }
2038
2039 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev)
2040 {
2041         struct labpc_private *devpriv = dev->private;
2042         unsigned int value;
2043         const int read_status_instruction = 0x5;
2044         const int write_length = 8;     /*  8 bit write lengths to eeprom */
2045
2046         /*  enable read/write to eeprom */
2047         devpriv->command5_bits &= ~EEPROM_EN_BIT;
2048         udelay(1);
2049         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2050         devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
2051         udelay(1);
2052         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2053
2054         /*  send read status instruction */
2055         labpc_serial_out(dev, read_status_instruction, write_length);
2056         /*  read result */
2057         value = labpc_serial_in(dev);
2058
2059         /*  disable read/write to eeprom */
2060         devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2061         udelay(1);
2062         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2063
2064         return value;
2065 }
2066
2067 /* writes to 8 bit calibration dacs */
2068 static void write_caldac(struct comedi_device *dev, unsigned int channel,
2069                          unsigned int value)
2070 {
2071         struct labpc_private *devpriv = dev->private;
2072
2073         if (value == devpriv->caldac[channel])
2074                 return;
2075         devpriv->caldac[channel] = value;
2076
2077         /*  clear caldac load bit and make sure we don't write to eeprom */
2078         devpriv->command5_bits &=
2079             ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2080         udelay(1);
2081         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2082
2083         /*  write 4 bit channel */
2084         labpc_serial_out(dev, channel, 4);
2085         /*  write 8 bit caldac value */
2086         labpc_serial_out(dev, value, 8);
2087
2088         /*  set and clear caldac bit to load caldac value */
2089         devpriv->command5_bits |= CALDAC_LOAD_BIT;
2090         udelay(1);
2091         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2092         devpriv->command5_bits &= ~CALDAC_LOAD_BIT;
2093         udelay(1);
2094         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2095 }
2096
2097 static struct comedi_driver labpc_driver = {
2098         .driver_name = DRV_NAME,
2099         .module = THIS_MODULE,
2100         .attach = labpc_attach,
2101         .auto_attach = labpc_auto_attach,
2102         .detach = labpc_common_detach,
2103         .num_names = ARRAY_SIZE(labpc_boards),
2104         .board_name = &labpc_boards[0].name,
2105         .offset = sizeof(struct labpc_board_struct),
2106 };
2107
2108 #ifdef CONFIG_COMEDI_PCI_DRIVERS
2109 static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = {
2110         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x161)},
2111         {0}
2112 };
2113 MODULE_DEVICE_TABLE(pci, labpc_pci_table);
2114
2115 static int labpc_pci_probe(struct pci_dev *dev,
2116                                      const struct pci_device_id *ent)
2117 {
2118         return comedi_pci_auto_config(dev, &labpc_driver);
2119 }
2120
2121 static struct pci_driver labpc_pci_driver = {
2122         .name = DRV_NAME,
2123         .id_table = labpc_pci_table,
2124         .probe = labpc_pci_probe,
2125         .remove         = comedi_pci_auto_unconfig,
2126 };
2127 module_comedi_pci_driver(labpc_driver, labpc_pci_driver);
2128 #else
2129 module_comedi_driver(labpc_driver);
2130 #endif
2131
2132
2133 MODULE_AUTHOR("Comedi http://www.comedi.org");
2134 MODULE_DESCRIPTION("Comedi low-level driver");
2135 MODULE_LICENSE("GPL");