drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21         This file is meant to be included by another file, e.g.,
  22         ni_atmio.c or ni_pcimio.c.
  23
  24         Interrupt support originally added by Truxton Fulton
  25         <trux@truxton.com>
  26
  27         References (from ftp://ftp.natinst.com/support/manuals):
  28
  29            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  30            341079b.pdf  PCI E Series RLPM
  31            340934b.pdf  DAQ-STC reference manual
  32         67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  33         release_ni611x.pdf
  34         release_ni67xx.pdf
  35         Other possibly relevant info:
  36
  37            320517c.pdf  User manual (obsolete)
  38            320517f.pdf  User manual (new)
  39            320889a.pdf  delete
  40            320906c.pdf  maximum signal ratings
  41            321066a.pdf  about 16x
  42            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  43            321808a.pdf  about at-mio-16e-10 rev P
  44            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  45            321838a.pdf  about at-mio-16de-10 rev N
  46
  47         ISSUES:
  48
  49          - the interrupt routine needs to be cleaned up
  50
  51         2006-02-07: S-Series PCI-6143: Support has been added but is not
  52                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  53 */
  54
  55 #include <linux/interrupt.h>
  56 #include <linux/sched.h>
  57 #include <linux/delay.h>
  58 #include "8255.h"
  59 #include "mite.h"
  60 #include "comedi_fc.h"
  61
  62 /* A timeout count */
  63 #define NI_TIMEOUT 1000
  64 static const unsigned old_RTSI_clock_channel = 7;
  65
  66 /* Note: this table must match the ai_gain_* definitions */
  67 static const short ni_gainlkup[][16] = {
  68         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  69                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  70         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  71         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  72                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  73         [ai_gain_4] = {0, 1, 4, 7},
  74         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  75                           0x003, 0x004, 0x005, 0x006},
  76         [ai_gain_622x] = {0, 1, 4, 5},
  77         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  78         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  79 };
  80
  81 static const struct comedi_lrange range_ni_E_ai = {
  82         16, {
  83                 BIP_RANGE(10),
  84                 BIP_RANGE(5),
  85                 BIP_RANGE(2.5),
  86                 BIP_RANGE(1),
  87                 BIP_RANGE(0.5),
  88                 BIP_RANGE(0.25),
  89                 BIP_RANGE(0.1),
  90                 BIP_RANGE(0.05),
  91                 UNI_RANGE(20),
  92                 UNI_RANGE(10),
  93                 UNI_RANGE(5),
  94                 UNI_RANGE(2),
  95                 UNI_RANGE(1),
  96                 UNI_RANGE(0.5),
  97                 UNI_RANGE(0.2),
  98                 UNI_RANGE(0.1)
  99         }
 100 };
 101
 102 static const struct comedi_lrange range_ni_E_ai_limited = {
 103         8, {
 104                 BIP_RANGE(10),
 105                 BIP_RANGE(5),
 106                 BIP_RANGE(1),
 107                 BIP_RANGE(0.1),
 108                 UNI_RANGE(10),
 109                 UNI_RANGE(5),
 110                 UNI_RANGE(1),
 111                 UNI_RANGE(0.1)
 112         }
 113 };
 114
 115 static const struct comedi_lrange range_ni_E_ai_limited14 = {
 116         14, {
 117                 BIP_RANGE(10),
 118                 BIP_RANGE(5),
 119                 BIP_RANGE(2),
 120                 BIP_RANGE(1),
 121                 BIP_RANGE(0.5),
 122                 BIP_RANGE(0.2),
 123                 BIP_RANGE(0.1),
 124                 UNI_RANGE(10),
 125                 UNI_RANGE(5),
 126                 UNI_RANGE(2),
 127                 UNI_RANGE(1),
 128                 UNI_RANGE(0.5),
 129                 UNI_RANGE(0.2),
 130                 UNI_RANGE(0.1)
 131         }
 132 };
 133
 134 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
 135         4, {
 136                 BIP_RANGE(10),
 137                 BIP_RANGE(5),
 138                 BIP_RANGE(0.5),
 139                 BIP_RANGE(0.05)
 140         }
 141 };
 142
 143 static const struct comedi_lrange range_ni_E_ai_611x = {
 144         8, {
 145                 BIP_RANGE(50),
 146                 BIP_RANGE(20),
 147                 BIP_RANGE(10),
 148                 BIP_RANGE(5),
 149                 BIP_RANGE(2),
 150                 BIP_RANGE(1),
 151                 BIP_RANGE(0.5),
 152                 BIP_RANGE(0.2)
 153         }
 154 };
 155
 156 static const struct comedi_lrange range_ni_M_ai_622x = {
 157         4, {
 158                 BIP_RANGE(10),
 159                 BIP_RANGE(5),
 160                 BIP_RANGE(1),
 161                 BIP_RANGE(0.2)
 162         }
 163 };
 164
 165 static const struct comedi_lrange range_ni_M_ai_628x = {
 166         7, {
 167                 BIP_RANGE(10),
 168                 BIP_RANGE(5),
 169                 BIP_RANGE(2),
 170                 BIP_RANGE(1),
 171                 BIP_RANGE(0.5),
 172                 BIP_RANGE(0.2),
 173                 BIP_RANGE(0.1)
 174         }
 175 };
 176
 177 static const struct comedi_lrange range_ni_E_ao_ext = {
 178         4, {
 179                 BIP_RANGE(10),
 180                 UNI_RANGE(10),
 181                 RANGE_ext(-1, 1),
 182                 RANGE_ext(0, 1)
 183         }
 184 };
 185
 186 static const struct comedi_lrange *const ni_range_lkup[] = {
 187         [ai_gain_16] = &range_ni_E_ai,
 188         [ai_gain_8] = &range_ni_E_ai_limited,
 189         [ai_gain_14] = &range_ni_E_ai_limited14,
 190         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 191         [ai_gain_611x] = &range_ni_E_ai_611x,
 192         [ai_gain_622x] = &range_ni_M_ai_622x,
 193         [ai_gain_628x] = &range_ni_M_ai_628x,
 194         [ai_gain_6143] = &range_bipolar5
 195 };
 196
 197 static int ni_dio_insn_config(struct comedi_device *dev,
 198                               struct comedi_subdevice *s,
 199                               struct comedi_insn *insn, unsigned int *data);
 200 static int ni_dio_insn_bits(struct comedi_device *dev,
 201                             struct comedi_subdevice *s,
 202                             struct comedi_insn *insn, unsigned int *data);
 203 static int ni_cdio_cmdtest(struct comedi_device *dev,
 204                            struct comedi_subdevice *s, struct comedi_cmd *cmd);
 205 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 206 static int ni_cdio_cancel(struct comedi_device *dev,
 207                           struct comedi_subdevice *s);
 208 static void handle_cdio_interrupt(struct comedi_device *dev);
 209 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 210                           unsigned int trignum);
 211
 212 static int ni_serial_insn_config(struct comedi_device *dev,
 213                                  struct comedi_subdevice *s,
 214                                  struct comedi_insn *insn, unsigned int *data);
 215 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
 216                                    struct comedi_subdevice *s,
 217                                    unsigned char data_out,
 218                                    unsigned char *data_in);
 219 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
 220                                    struct comedi_subdevice *s,
 221                                    unsigned char data_out,
 222                                    unsigned char *data_in);
 223
 224 static int ni_calib_insn_read(struct comedi_device *dev,
 225                               struct comedi_subdevice *s,
 226                               struct comedi_insn *insn, unsigned int *data);
 227 static int ni_calib_insn_write(struct comedi_device *dev,
 228                                struct comedi_subdevice *s,
 229                                struct comedi_insn *insn, unsigned int *data);
 230
 231 static int ni_eeprom_insn_read(struct comedi_device *dev,
 232                                struct comedi_subdevice *s,
 233                                struct comedi_insn *insn, unsigned int *data);
 234 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
 235                                         struct comedi_subdevice *s,
 236                                         struct comedi_insn *insn,
 237                                         unsigned int *data);
 238
 239 static int ni_pfi_insn_bits(struct comedi_device *dev,
 240                             struct comedi_subdevice *s,
 241                             struct comedi_insn *insn, unsigned int *data);
 242 static int ni_pfi_insn_config(struct comedi_device *dev,
 243                               struct comedi_subdevice *s,
 244                               struct comedi_insn *insn, unsigned int *data);
 245 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
 246                                        unsigned chan);
 247
 248 static void ni_rtsi_init(struct comedi_device *dev);
 249 static int ni_rtsi_insn_bits(struct comedi_device *dev,
 250                              struct comedi_subdevice *s,
 251                              struct comedi_insn *insn, unsigned int *data);
 252 static int ni_rtsi_insn_config(struct comedi_device *dev,
 253                                struct comedi_subdevice *s,
 254                                struct comedi_insn *insn, unsigned int *data);
 255
 256 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
 257 static int ni_read_eeprom(struct comedi_device *dev, int addr);
 258
 259 #ifndef PCIDMA
 260 static void ni_handle_fifo_half_full(struct comedi_device *dev);
 261 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
 262                                  struct comedi_subdevice *s);
 263 #endif
 264 static void ni_handle_fifo_dregs(struct comedi_device *dev);
 265 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 266                          unsigned int trignum);
 267 static void ni_load_channelgain_list(struct comedi_device *dev,
 268                                      unsigned int n_chan, unsigned int *list);
 269 static void shutdown_ai_command(struct comedi_device *dev);
 270
 271 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
 272                          unsigned int trignum);
 273
 274 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
 275
 276 #ifdef PCIDMA
 277 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 278 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
 279 #endif
 280 static void handle_gpct_interrupt(struct comedi_device *dev,
 281                                   unsigned short counter_index);
 282
 283 static int init_cs5529(struct comedi_device *dev);
 284 static int cs5529_do_conversion(struct comedi_device *dev,
 285                                 unsigned short *data);
 286 static int cs5529_ai_insn_read(struct comedi_device *dev,
 287                                struct comedi_subdevice *s,
 288                                struct comedi_insn *insn, unsigned int *data);
 289 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
 290                                 unsigned int reg_select_bits);
 291
 292 static int ni_m_series_pwm_config(struct comedi_device *dev,
 293                                   struct comedi_subdevice *s,
 294                                   struct comedi_insn *insn, unsigned int *data);
 295 static int ni_6143_pwm_config(struct comedi_device *dev,
 296                               struct comedi_subdevice *s,
 297                               struct comedi_insn *insn, unsigned int *data);
 298
 299 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
 300                                unsigned period_ns);
 301 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
 302 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
 303
 304 enum aimodes {
 305         AIMODE_NONE = 0,
 306         AIMODE_HALF_FULL = 1,
 307         AIMODE_SCAN = 2,
 308         AIMODE_SAMPLE = 3,
 309 };
 310
 311 enum ni_common_subdevices {
 312         NI_AI_SUBDEV,
 313         NI_AO_SUBDEV,
 314         NI_DIO_SUBDEV,
 315         NI_8255_DIO_SUBDEV,
 316         NI_UNUSED_SUBDEV,
 317         NI_CALIBRATION_SUBDEV,
 318         NI_EEPROM_SUBDEV,
 319         NI_PFI_DIO_SUBDEV,
 320         NI_CS5529_CALIBRATION_SUBDEV,
 321         NI_SERIAL_SUBDEV,
 322         NI_RTSI_SUBDEV,
 323         NI_GPCT0_SUBDEV,
 324         NI_GPCT1_SUBDEV,
 325         NI_FREQ_OUT_SUBDEV,
 326         NI_NUM_SUBDEVICES
 327 };
 328 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 329 {
 330         switch (counter_index) {
 331         case 0:
 332                 return NI_GPCT0_SUBDEV;
 333                 break;
 334         case 1:
 335                 return NI_GPCT1_SUBDEV;
 336                 break;
 337         default:
 338                 break;
 339         }
 340         BUG();
 341         return NI_GPCT0_SUBDEV;
 342 }
 343
 344 enum timebase_nanoseconds {
 345         TIMEBASE_1_NS = 50,
 346         TIMEBASE_2_NS = 10000
 347 };
 348
 349 #define SERIAL_DISABLED         0
 350 #define SERIAL_600NS            600
 351 #define SERIAL_1_2US            1200
 352 #define SERIAL_10US                     10000
 353
 354 static const int num_adc_stages_611x = 3;
 355
 356 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
 357                                unsigned ai_mite_status);
 358 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
 359                                unsigned ao_mite_status);
 360 static void get_last_sample_611x(struct comedi_device *dev);
 361 static void get_last_sample_6143(struct comedi_device *dev);
 362
 363 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 364                                    unsigned bit_mask, unsigned bit_values)
 365 {
 366         struct ni_private *devpriv = dev->private;
 367         unsigned long flags;
 368
 369         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 370         switch (reg) {
 371         case Interrupt_A_Enable_Register:
 372                 devpriv->int_a_enable_reg &= ~bit_mask;
 373                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 374                 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
 375                                     Interrupt_A_Enable_Register);
 376                 break;
 377         case Interrupt_B_Enable_Register:
 378                 devpriv->int_b_enable_reg &= ~bit_mask;
 379                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 380                 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
 381                                     Interrupt_B_Enable_Register);
 382                 break;
 383         case IO_Bidirection_Pin_Register:
 384                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 385                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 386                 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
 387                                     IO_Bidirection_Pin_Register);
 388                 break;
 389         case AI_AO_Select:
 390                 devpriv->ai_ao_select_reg &= ~bit_mask;
 391                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 392                 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
 393                 break;
 394         case G0_G1_Select:
 395                 devpriv->g0_g1_select_reg &= ~bit_mask;
 396                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 397                 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
 398                 break;
 399         default:
 400                 printk("Warning %s() called with invalid register\n", __func__);
 401                 printk("reg is %d\n", reg);
 402                 break;
 403         }
 404         mmiowb();
 405         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 406 }
 407
 408 #ifdef PCIDMA
 409 static int ni_ai_drain_dma(struct comedi_device *dev);
 410
 411 /* DMA channel setup */
 412
 413 /* negative channel means no channel */
 414 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
 415 {
 416         unsigned bitfield;
 417
 418         if (channel >= 0) {
 419                 bitfield =
 420                     (ni_stc_dma_channel_select_bitfield(channel) <<
 421                      AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
 422         } else {
 423                 bitfield = 0;
 424         }
 425         ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
 426 }
 427
 428 /* negative channel means no channel */
 429 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
 430 {
 431         unsigned bitfield;
 432
 433         if (channel >= 0) {
 434                 bitfield =
 435                     (ni_stc_dma_channel_select_bitfield(channel) <<
 436                      AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
 437         } else {
 438                 bitfield = 0;
 439         }
 440         ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
 441 }
 442
 443 /* negative mite_channel means no channel */
 444 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 445                                            unsigned gpct_index,
 446                                            int mite_channel)
 447 {
 448         unsigned bitfield;
 449
 450         if (mite_channel >= 0)
 451                 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
 452         else
 453                 bitfield = 0;
 454         ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
 455                         bitfield);
 456 }
 457
 458 /* negative mite_channel means no channel */
 459 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 460                                           int mite_channel)
 461 {
 462         struct ni_private *devpriv = dev->private;
 463         unsigned long flags;
 464
 465         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 466         devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
 467         if (mite_channel >= 0) {
 468                 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
 469                    under the assumption the cdio dma selection works just like ai/ao/gpct.
 470                    Definitely works for dma channels 0 and 1. */
 471                 devpriv->cdio_dma_select_reg |=
 472                     (ni_stc_dma_channel_select_bitfield(mite_channel) <<
 473                      CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
 474         }
 475         ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
 476         mmiowb();
 477         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 478 }
 479
 480 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 481 {
 482         struct ni_private *devpriv = dev->private;
 483         unsigned long flags;
 484
 485         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 486         BUG_ON(devpriv->ai_mite_chan);
 487         devpriv->ai_mite_chan =
 488             mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 489         if (devpriv->ai_mite_chan == NULL) {
 490                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 491                 comedi_error(dev,
 492                              "failed to reserve mite dma channel for analog input.");
 493                 return -EBUSY;
 494         }
 495         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 496         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 497         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 498         return 0;
 499 }
 500
 501 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 502 {
 503         struct ni_private *devpriv = dev->private;
 504         unsigned long flags;
 505
 506         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 507         BUG_ON(devpriv->ao_mite_chan);
 508         devpriv->ao_mite_chan =
 509             mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 510         if (devpriv->ao_mite_chan == NULL) {
 511                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 512                 comedi_error(dev,
 513                              "failed to reserve mite dma channel for analog outut.");
 514                 return -EBUSY;
 515         }
 516         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 517         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 518         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 519         return 0;
 520 }
 521
 522 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 523                                         unsigned gpct_index,
 524                                         enum comedi_io_direction direction)
 525 {
 526         struct ni_private *devpriv = dev->private;
 527         unsigned long flags;
 528         struct mite_channel *mite_chan;
 529
 530         BUG_ON(gpct_index >= NUM_GPCT);
 531         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 532         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 533         mite_chan =
 534             mite_request_channel(devpriv->mite,
 535                                  devpriv->gpct_mite_ring[gpct_index]);
 536         if (mite_chan == NULL) {
 537                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 538                 comedi_error(dev,
 539                              "failed to reserve mite dma channel for counter.");
 540                 return -EBUSY;
 541         }
 542         mite_chan->dir = direction;
 543         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 544                                 mite_chan);
 545         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 546         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 547         return 0;
 548 }
 549
 550 #endif /*  PCIDMA */
 551
 552 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 553 {
 554 #ifdef PCIDMA
 555         struct ni_private *devpriv = dev->private;
 556         unsigned long flags;
 557
 558         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 559         BUG_ON(devpriv->cdo_mite_chan);
 560         devpriv->cdo_mite_chan =
 561             mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 562         if (devpriv->cdo_mite_chan == NULL) {
 563                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 564                 comedi_error(dev,
 565                              "failed to reserve mite dma channel for correlated digital outut.");
 566                 return -EBUSY;
 567         }
 568         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 569         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 570         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 571 #endif /*  PCIDMA */
 572         return 0;
 573 }
 574
 575 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 576 {
 577 #ifdef PCIDMA
 578         struct ni_private *devpriv = dev->private;
 579         unsigned long flags;
 580
 581         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 582         if (devpriv->ai_mite_chan) {
 583                 ni_set_ai_dma_channel(dev, -1);
 584                 mite_release_channel(devpriv->ai_mite_chan);
 585                 devpriv->ai_mite_chan = NULL;
 586         }
 587         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 588 #endif /*  PCIDMA */
 589 }
 590
 591 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 592 {
 593 #ifdef PCIDMA
 594         struct ni_private *devpriv = dev->private;
 595         unsigned long flags;
 596
 597         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 598         if (devpriv->ao_mite_chan) {
 599                 ni_set_ao_dma_channel(dev, -1);
 600                 mite_release_channel(devpriv->ao_mite_chan);
 601                 devpriv->ao_mite_chan = NULL;
 602         }
 603         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 604 #endif /*  PCIDMA */
 605 }
 606
 607 #ifdef PCIDMA
 608 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 609                                          unsigned gpct_index)
 610 {
 611         struct ni_private *devpriv = dev->private;
 612         unsigned long flags;
 613
 614         BUG_ON(gpct_index >= NUM_GPCT);
 615         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 616         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 617                 struct mite_channel *mite_chan =
 618                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 619
 620                 ni_set_gpct_dma_channel(dev, gpct_index, -1);
 621                 ni_tio_set_mite_channel(&devpriv->
 622                                         counter_dev->counters[gpct_index],
 623                                         NULL);
 624                 mite_release_channel(mite_chan);
 625         }
 626         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 627 }
 628 #endif /*  PCIDMA */
 629
 630 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 631 {
 632 #ifdef PCIDMA
 633         struct ni_private *devpriv = dev->private;
 634         unsigned long flags;
 635
 636         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 637         if (devpriv->cdo_mite_chan) {
 638                 ni_set_cdo_dma_channel(dev, -1);
 639                 mite_release_channel(devpriv->cdo_mite_chan);
 640                 devpriv->cdo_mite_chan = NULL;
 641         }
 642         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 643 #endif /*  PCIDMA */
 644 }
 645
 646 /* e-series boards use the second irq signals to generate dma requests for their counters */
 647 #ifdef PCIDMA
 648 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 649                                           unsigned gpct_index, short enable)
 650 {
 651         const struct ni_board_struct *board = comedi_board(dev);
 652         struct ni_private *devpriv = dev->private;
 653
 654         if (board->reg_type & ni_reg_m_series_mask)
 655                 return;
 656         switch (gpct_index) {
 657         case 0:
 658                 if (enable) {
 659                         devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
 660                                             Second_IRQ_A_Enable_Register);
 661                 } else {
 662                         devpriv->stc_writew(dev, 0,
 663                                             Second_IRQ_A_Enable_Register);
 664                 }
 665                 break;
 666         case 1:
 667                 if (enable) {
 668                         devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
 669                                             Second_IRQ_B_Enable_Register);
 670                 } else {
 671                         devpriv->stc_writew(dev, 0,
 672                                             Second_IRQ_B_Enable_Register);
 673                 }
 674                 break;
 675         default:
 676                 BUG();
 677                 break;
 678         }
 679 }
 680 #endif /*  PCIDMA */
 681
 682 static void ni_clear_ai_fifo(struct comedi_device *dev)
 683 {
 684         const struct ni_board_struct *board = comedi_board(dev);
 685         struct ni_private *devpriv = dev->private;
 686         static const int timeout = 10000;
 687         int i;
 688
 689         if (board->reg_type == ni_reg_6143) {
 690                 /*  Flush the 6143 data FIFO */
 691                 ni_writel(0x10, AIFIFO_Control_6143);   /*  Flush fifo */
 692                 ni_writel(0x00, AIFIFO_Control_6143);   /*  Flush fifo */
 693                 /*  Wait for complete */
 694                 for (i = 0; i < timeout; i++) {
 695                         if (!(ni_readl(AIFIFO_Status_6143) & 0x10))
 696                                 break;
 697                         udelay(1);
 698                 }
 699                 if (i == timeout) {
 700                         comedi_error(dev, "FIFO flush timeout.");
 701                 }
 702         } else {
 703                 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
 704                 if (board->reg_type == ni_reg_625x) {
 705                         ni_writeb(0, M_Offset_Static_AI_Control(0));
 706                         ni_writeb(1, M_Offset_Static_AI_Control(0));
 707 #if 0
 708                         /* the NI example code does 3 convert pulses for 625x boards,
 709                            but that appears to be wrong in practice. */
 710                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 711                                             AI_Command_1_Register);
 712                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 713                                             AI_Command_1_Register);
 714                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
 715                                             AI_Command_1_Register);
 716 #endif
 717                 }
 718         }
 719 }
 720
 721 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
 722 {
 723         struct ni_private *devpriv = dev->private;
 724
 725         devpriv->stc_writew(dev, data >> 16, reg);
 726         devpriv->stc_writew(dev, data & 0xffff, reg + 1);
 727 }
 728
 729 static uint32_t win_in2(struct comedi_device *dev, int reg)
 730 {
 731         struct ni_private *devpriv = dev->private;
 732         uint32_t bits;
 733
 734         bits = devpriv->stc_readw(dev, reg) << 16;
 735         bits |= devpriv->stc_readw(dev, reg + 1);
 736         return bits;
 737 }
 738
 739 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
 740 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 741                                   int addr)
 742 {
 743         struct ni_private *devpriv = dev->private;
 744         unsigned long flags;
 745
 746         spin_lock_irqsave(&devpriv->window_lock, flags);
 747         ni_writew(addr, AO_Window_Address_611x);
 748         ni_writew(data, AO_Window_Data_611x);
 749         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 750 }
 751
 752 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 753                                   int addr)
 754 {
 755         struct ni_private *devpriv = dev->private;
 756         unsigned long flags;
 757
 758         spin_lock_irqsave(&devpriv->window_lock, flags);
 759         ni_writew(addr, AO_Window_Address_611x);
 760         ni_writel(data, AO_Window_Data_611x);
 761         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 762 }
 763
 764 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 765 {
 766         struct ni_private *devpriv = dev->private;
 767         unsigned long flags;
 768         unsigned short data;
 769
 770         spin_lock_irqsave(&devpriv->window_lock, flags);
 771         ni_writew(addr, AO_Window_Address_611x);
 772         data = ni_readw(AO_Window_Data_611x);
 773         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 774         return data;
 775 }
 776
 777 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 778 * share registers (such as Interrupt_A_Register) without interfering with
 779 * each other.
 780 *
 781 * NOTE: the switch/case statements are optimized out for a constant argument
 782 * so this is actually quite fast---  If you must wrap another function around this
 783 * make it inline to avoid a large speed penalty.
 784 *
 785 * value should only be 1 or 0.
 786 */
 787 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 788                                unsigned bits, unsigned value)
 789 {
 790         unsigned bit_values;
 791
 792         if (value)
 793                 bit_values = bits;
 794         else
 795                 bit_values = 0;
 796         ni_set_bitfield(dev, reg, bits, bit_values);
 797 }
 798
 799 static irqreturn_t ni_E_interrupt(int irq, void *d)
 800 {
 801         struct comedi_device *dev = d;
 802         struct ni_private *devpriv = dev->private;
 803         unsigned short a_status;
 804         unsigned short b_status;
 805         unsigned int ai_mite_status = 0;
 806         unsigned int ao_mite_status = 0;
 807         unsigned long flags;
 808 #ifdef PCIDMA
 809         struct mite_struct *mite = devpriv->mite;
 810 #endif
 811
 812         if (!dev->attached)
 813                 return IRQ_NONE;
 814         smp_mb();               /*  make sure dev->attached is checked before handler does anything else. */
 815
 816         /*  lock to avoid race with comedi_poll */
 817         spin_lock_irqsave(&dev->spinlock, flags);
 818         a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
 819         b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 820 #ifdef PCIDMA
 821         if (mite) {
 822                 unsigned long flags_too;
 823
 824                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
 825                 if (devpriv->ai_mite_chan) {
 826                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
 827                         if (ai_mite_status & CHSR_LINKC)
 828                                 writel(CHOR_CLRLC,
 829                                        devpriv->mite->mite_io_addr +
 830                                        MITE_CHOR(devpriv->
 831                                                  ai_mite_chan->channel));
 832                 }
 833                 if (devpriv->ao_mite_chan) {
 834                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
 835                         if (ao_mite_status & CHSR_LINKC)
 836                                 writel(CHOR_CLRLC,
 837                                        mite->mite_io_addr +
 838                                        MITE_CHOR(devpriv->
 839                                                  ao_mite_chan->channel));
 840                 }
 841                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
 842         }
 843 #endif
 844         ack_a_interrupt(dev, a_status);
 845         ack_b_interrupt(dev, b_status);
 846         if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
 847                 handle_a_interrupt(dev, a_status, ai_mite_status);
 848         if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
 849                 handle_b_interrupt(dev, b_status, ao_mite_status);
 850         handle_gpct_interrupt(dev, 0);
 851         handle_gpct_interrupt(dev, 1);
 852         handle_cdio_interrupt(dev);
 853
 854         spin_unlock_irqrestore(&dev->spinlock, flags);
 855         return IRQ_HANDLED;
 856 }
 857
 858 #ifdef PCIDMA
 859 static void ni_sync_ai_dma(struct comedi_device *dev)
 860 {
 861         struct ni_private *devpriv = dev->private;
 862         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 863         unsigned long flags;
 864
 865         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 866         if (devpriv->ai_mite_chan)
 867                 mite_sync_input_dma(devpriv->ai_mite_chan, s);
 868         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 869 }
 870
 871 static void mite_handle_b_linkc(struct mite_struct *mite,
 872                                 struct comedi_device *dev)
 873 {
 874         struct ni_private *devpriv = dev->private;
 875         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
 876         unsigned long flags;
 877
 878         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 879         if (devpriv->ao_mite_chan)
 880                 mite_sync_output_dma(devpriv->ao_mite_chan, s);
 881         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 882 }
 883
 884 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 885 {
 886         struct ni_private *devpriv = dev->private;
 887         static const int timeout = 10000;
 888         int i;
 889         for (i = 0; i < timeout; i++) {
 890                 unsigned short b_status;
 891
 892                 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
 893                 if (b_status & AO_FIFO_Half_Full_St)
 894                         break;
 895                 /* if we poll too often, the pci bus activity seems
 896                    to slow the dma transfer down */
 897                 udelay(10);
 898         }
 899         if (i == timeout) {
 900                 comedi_error(dev, "timed out waiting for dma load");
 901                 return -EPIPE;
 902         }
 903         return 0;
 904 }
 905
 906 #endif /* PCIDMA */
 907 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
 908 {
 909         struct ni_private *devpriv = dev->private;
 910
 911         if (devpriv->aimode == AIMODE_SCAN) {
 912 #ifdef PCIDMA
 913                 static const int timeout = 10;
 914                 int i;
 915
 916                 for (i = 0; i < timeout; i++) {
 917                         ni_sync_ai_dma(dev);
 918                         if ((s->async->events & COMEDI_CB_EOS))
 919                                 break;
 920                         udelay(1);
 921                 }
 922 #else
 923                 ni_handle_fifo_dregs(dev);
 924                 s->async->events |= COMEDI_CB_EOS;
 925 #endif
 926         }
 927         /* handle special case of single scan using AI_End_On_End_Of_Scan */
 928         if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan))
 929                 shutdown_ai_command(dev);
 930 }
 931
 932 static void shutdown_ai_command(struct comedi_device *dev)
 933 {
 934         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 935
 936 #ifdef PCIDMA
 937         ni_ai_drain_dma(dev);
 938 #endif
 939         ni_handle_fifo_dregs(dev);
 940         get_last_sample_611x(dev);
 941         get_last_sample_6143(dev);
 942
 943         s->async->events |= COMEDI_CB_EOA;
 944 }
 945
 946 static void handle_gpct_interrupt(struct comedi_device *dev,
 947                                   unsigned short counter_index)
 948 {
 949 #ifdef PCIDMA
 950         struct ni_private *devpriv = dev->private;
 951         struct comedi_subdevice *s;
 952
 953         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
 954
 955         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
 956                                 s);
 957         cfc_handle_events(dev, s);
 958 #endif
 959 }
 960
 961 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
 962 {
 963         struct ni_private *devpriv = dev->private;
 964         unsigned short ack = 0;
 965
 966         if (a_status & AI_SC_TC_St)
 967                 ack |= AI_SC_TC_Interrupt_Ack;
 968         if (a_status & AI_START1_St)
 969                 ack |= AI_START1_Interrupt_Ack;
 970         if (a_status & AI_START_St)
 971                 ack |= AI_START_Interrupt_Ack;
 972         if (a_status & AI_STOP_St)
 973                 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
 974                 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */;
 975         if (ack)
 976                 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
 977 }
 978
 979 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
 980                                unsigned ai_mite_status)
 981 {
 982         struct ni_private *devpriv = dev->private;
 983         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
 984
 985         /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
 986         if (s->type == COMEDI_SUBD_UNUSED)
 987                 return;
 988
 989 #ifdef PCIDMA
 990         if (ai_mite_status & CHSR_LINKC)
 991                 ni_sync_ai_dma(dev);
 992
 993         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
 994                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
 995                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
 996                 printk
 997                     ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
 998                      ai_mite_status);
 999                 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1000                 /* disable_irq(dev->irq); */
1001         }
1002 #endif
1003
1004         /* test for all uncommon interrupt events at the same time */
1005         if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1006                       AI_SC_TC_St | AI_START1_St)) {
1007                 if (status == 0xffff) {
1008                         printk
1009                             ("ni_mio_common: a_status=0xffff.  Card removed?\n");
1010                         /* we probably aren't even running a command now,
1011                          * so it's a good idea to be careful. */
1012                         if (comedi_is_subdevice_running(s)) {
1013                                 s->async->events |=
1014                                     COMEDI_CB_ERROR | COMEDI_CB_EOA;
1015                                 cfc_handle_events(dev, s);
1016                         }
1017                         return;
1018                 }
1019                 if (status & (AI_Overrun_St | AI_Overflow_St |
1020                               AI_SC_TC_Error_St)) {
1021                         printk("ni_mio_common: ai error a_status=%04x\n",
1022                                status);
1023
1024                         shutdown_ai_command(dev);
1025
1026                         s->async->events |= COMEDI_CB_ERROR;
1027                         if (status & (AI_Overrun_St | AI_Overflow_St))
1028                                 s->async->events |= COMEDI_CB_OVERFLOW;
1029
1030                         cfc_handle_events(dev, s);
1031                         return;
1032                 }
1033                 if (status & AI_SC_TC_St) {
1034                         if (!devpriv->ai_continuous)
1035                                 shutdown_ai_command(dev);
1036                 }
1037         }
1038 #ifndef PCIDMA
1039         if (status & AI_FIFO_Half_Full_St) {
1040                 int i;
1041                 static const int timeout = 10;
1042                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1043                  *fail to get the fifo less than half full, so loop to be sure.*/
1044                 for (i = 0; i < timeout; ++i) {
1045                         ni_handle_fifo_half_full(dev);
1046                         if ((devpriv->stc_readw(dev,
1047                                                 AI_Status_1_Register) &
1048                              AI_FIFO_Half_Full_St) == 0)
1049                                 break;
1050                 }
1051         }
1052 #endif /*  !PCIDMA */
1053
1054         if ((status & AI_STOP_St))
1055                 ni_handle_eos(dev, s);
1056
1057         cfc_handle_events(dev, s);
1058 }
1059
1060 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1061 {
1062         struct ni_private *devpriv = dev->private;
1063         unsigned short ack = 0;
1064
1065         if (b_status & AO_BC_TC_St)
1066                 ack |= AO_BC_TC_Interrupt_Ack;
1067         if (b_status & AO_Overrun_St)
1068                 ack |= AO_Error_Interrupt_Ack;
1069         if (b_status & AO_START_St)
1070                 ack |= AO_START_Interrupt_Ack;
1071         if (b_status & AO_START1_St)
1072                 ack |= AO_START1_Interrupt_Ack;
1073         if (b_status & AO_UC_TC_St)
1074                 ack |= AO_UC_TC_Interrupt_Ack;
1075         if (b_status & AO_UI2_TC_St)
1076                 ack |= AO_UI2_TC_Interrupt_Ack;
1077         if (b_status & AO_UPDATE_St)
1078                 ack |= AO_UPDATE_Interrupt_Ack;
1079         if (ack)
1080                 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1081 }
1082
1083 static void handle_b_interrupt(struct comedi_device *dev,
1084                                unsigned short b_status, unsigned ao_mite_status)
1085 {
1086         struct ni_private *devpriv = dev->private;
1087         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1088         /* unsigned short ack=0; */
1089
1090 #ifdef PCIDMA
1091         /* Currently, mite.c requires us to handle LINKC */
1092         if (ao_mite_status & CHSR_LINKC)
1093                 mite_handle_b_linkc(devpriv->mite, dev);
1094
1095         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1096                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1097                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1098                 printk
1099                     ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1100                      ao_mite_status);
1101                 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1102         }
1103 #endif
1104
1105         if (b_status == 0xffff)
1106                 return;
1107         if (b_status & AO_Overrun_St) {
1108                 printk
1109                     ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1110                      b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1111                 s->async->events |= COMEDI_CB_OVERFLOW;
1112         }
1113
1114         if (b_status & AO_BC_TC_St)
1115                 s->async->events |= COMEDI_CB_EOA;
1116
1117 #ifndef PCIDMA
1118         if (b_status & AO_FIFO_Request_St) {
1119                 int ret;
1120
1121                 ret = ni_ao_fifo_half_empty(dev, s);
1122                 if (!ret) {
1123                         printk("ni_mio_common: AO buffer underrun\n");
1124                         ni_set_bits(dev, Interrupt_B_Enable_Register,
1125                                     AO_FIFO_Interrupt_Enable |
1126                                     AO_Error_Interrupt_Enable, 0);
1127                         s->async->events |= COMEDI_CB_OVERFLOW;
1128                 }
1129         }
1130 #endif
1131
1132         cfc_handle_events(dev, s);
1133 }
1134
1135 #ifndef PCIDMA
1136
1137 static void ni_ao_fifo_load(struct comedi_device *dev,
1138                             struct comedi_subdevice *s, int n)
1139 {
1140         const struct ni_board_struct *board = comedi_board(dev);
1141         struct comedi_async *async = s->async;
1142         struct comedi_cmd *cmd = &async->cmd;
1143         int chan;
1144         int i;
1145         unsigned short d;
1146         u32 packed_data;
1147         int range;
1148         int err = 1;
1149
1150         chan = async->cur_chan;
1151         for (i = 0; i < n; i++) {
1152                 err &= comedi_buf_get(s, &d);
1153                 if (err == 0)
1154                         break;
1155
1156                 range = CR_RANGE(cmd->chanlist[chan]);
1157
1158                 if (board->reg_type & ni_reg_6xxx_mask) {
1159                         packed_data = d & 0xffff;
1160                         /* 6711 only has 16 bit wide ao fifo */
1161                         if (board->reg_type != ni_reg_6711) {
1162                                 err &= comedi_buf_get(s, &d);
1163                                 if (err == 0)
1164                                         break;
1165                                 chan++;
1166                                 i++;
1167                                 packed_data |= (d << 16) & 0xffff0000;
1168                         }
1169                         ni_writel(packed_data, DAC_FIFO_Data_611x);
1170                 } else {
1171                         ni_writew(d, DAC_FIFO_Data);
1172                 }
1173                 chan++;
1174                 chan %= cmd->chanlist_len;
1175         }
1176         async->cur_chan = chan;
1177         if (err == 0)
1178                 async->events |= COMEDI_CB_OVERFLOW;
1179 }
1180
1181 /*
1182  *  There's a small problem if the FIFO gets really low and we
1183  *  don't have the data to fill it.  Basically, if after we fill
1184  *  the FIFO with all the data available, the FIFO is _still_
1185  *  less than half full, we never clear the interrupt.  If the
1186  *  IRQ is in edge mode, we never get another interrupt, because
1187  *  this one wasn't cleared.  If in level mode, we get flooded
1188  *  with interrupts that we can't fulfill, because nothing ever
1189  *  gets put into the buffer.
1190  *
1191  *  This kind of situation is recoverable, but it is easier to
1192  *  just pretend we had a FIFO underrun, since there is a good
1193  *  chance it will happen anyway.  This is _not_ the case for
1194  *  RT code, as RT code might purposely be running close to the
1195  *  metal.  Needs to be fixed eventually.
1196  */
1197 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1198                                  struct comedi_subdevice *s)
1199 {
1200         const struct ni_board_struct *board = comedi_board(dev);
1201         int n;
1202
1203         n = comedi_buf_read_n_available(s);
1204         if (n == 0) {
1205                 s->async->events |= COMEDI_CB_OVERFLOW;
1206                 return 0;
1207         }
1208
1209         n /= sizeof(short);
1210         if (n > board->ao_fifo_depth / 2)
1211                 n = board->ao_fifo_depth / 2;
1212
1213         ni_ao_fifo_load(dev, s, n);
1214
1215         s->async->events |= COMEDI_CB_BLOCK;
1216
1217         return 1;
1218 }
1219
1220 static int ni_ao_prep_fifo(struct comedi_device *dev,
1221                            struct comedi_subdevice *s)
1222 {
1223         const struct ni_board_struct *board = comedi_board(dev);
1224         struct ni_private *devpriv = dev->private;
1225         int n;
1226
1227         /* reset fifo */
1228         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1229         if (board->reg_type & ni_reg_6xxx_mask)
1230                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1231
1232         /* load some data */
1233         n = comedi_buf_read_n_available(s);
1234         if (n == 0)
1235                 return 0;
1236
1237         n /= sizeof(short);
1238         if (n > board->ao_fifo_depth)
1239                 n = board->ao_fifo_depth;
1240
1241         ni_ao_fifo_load(dev, s, n);
1242
1243         return n;
1244 }
1245
1246 static void ni_ai_fifo_read(struct comedi_device *dev,
1247                             struct comedi_subdevice *s, int n)
1248 {
1249         const struct ni_board_struct *board = comedi_board(dev);
1250         struct ni_private *devpriv = dev->private;
1251         struct comedi_async *async = s->async;
1252         int i;
1253
1254         if (board->reg_type == ni_reg_611x) {
1255                 unsigned short data[2];
1256                 u32 dl;
1257
1258                 for (i = 0; i < n / 2; i++) {
1259                         dl = ni_readl(ADC_FIFO_Data_611x);
1260                         /* This may get the hi/lo data in the wrong order */
1261                         data[0] = (dl >> 16) & 0xffff;
1262                         data[1] = dl & 0xffff;
1263                         cfc_write_array_to_buffer(s, data, sizeof(data));
1264                 }
1265                 /* Check if there's a single sample stuck in the FIFO */
1266                 if (n % 2) {
1267                         dl = ni_readl(ADC_FIFO_Data_611x);
1268                         data[0] = dl & 0xffff;
1269                         cfc_write_to_buffer(s, data[0]);
1270                 }
1271         } else if (board->reg_type == ni_reg_6143) {
1272                 unsigned short data[2];
1273                 u32 dl;
1274
1275                 /*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1276                 for (i = 0; i < n / 2; i++) {
1277                         dl = ni_readl(AIFIFO_Data_6143);
1278
1279                         data[0] = (dl >> 16) & 0xffff;
1280                         data[1] = dl & 0xffff;
1281                         cfc_write_array_to_buffer(s, data, sizeof(data));
1282                 }
1283                 if (n % 2) {
1284                         /* Assume there is a single sample stuck in the FIFO */
1285                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1286                         dl = ni_readl(AIFIFO_Data_6143);
1287                         data[0] = (dl >> 16) & 0xffff;
1288                         cfc_write_to_buffer(s, data[0]);
1289                 }
1290         } else {
1291                 if (n > sizeof(devpriv->ai_fifo_buffer) /
1292                     sizeof(devpriv->ai_fifo_buffer[0])) {
1293                         comedi_error(dev, "bug! ai_fifo_buffer too small");
1294                         async->events |= COMEDI_CB_ERROR;
1295                         return;
1296                 }
1297                 for (i = 0; i < n; i++) {
1298                         devpriv->ai_fifo_buffer[i] =
1299                             ni_readw(ADC_FIFO_Data_Register);
1300                 }
1301                 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1302                                           n *
1303                                           sizeof(devpriv->ai_fifo_buffer[0]));
1304         }
1305 }
1306
1307 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1308 {
1309         const struct ni_board_struct *board = comedi_board(dev);
1310         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1311         int n;
1312
1313         n = board->ai_fifo_depth / 2;
1314
1315         ni_ai_fifo_read(dev, s, n);
1316 }
1317 #endif
1318
1319 #ifdef PCIDMA
1320 static int ni_ai_drain_dma(struct comedi_device *dev)
1321 {
1322         struct ni_private *devpriv = dev->private;
1323         int i;
1324         static const int timeout = 10000;
1325         unsigned long flags;
1326         int retval = 0;
1327
1328         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1329         if (devpriv->ai_mite_chan) {
1330                 for (i = 0; i < timeout; i++) {
1331                         if ((devpriv->stc_readw(dev,
1332                                                 AI_Status_1_Register) &
1333                              AI_FIFO_Empty_St)
1334                             && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1335                             0)
1336                                 break;
1337                         udelay(5);
1338                 }
1339                 if (i == timeout) {
1340                         printk("ni_mio_common: wait for dma drain timed out\n");
1341                         printk
1342                             ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1343                              mite_bytes_in_transit(devpriv->ai_mite_chan),
1344                              devpriv->stc_readw(dev, AI_Status_1_Register));
1345                         retval = -1;
1346                 }
1347         }
1348         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1349
1350         ni_sync_ai_dma(dev);
1351
1352         return retval;
1353 }
1354 #endif
1355 /*
1356    Empties the AI fifo
1357 */
1358 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1359 {
1360         const struct ni_board_struct *board = comedi_board(dev);
1361         struct ni_private *devpriv = dev->private;
1362         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1363         unsigned short data[2];
1364         u32 dl;
1365         unsigned short fifo_empty;
1366         int i;
1367
1368         if (board->reg_type == ni_reg_611x) {
1369                 while ((devpriv->stc_readw(dev,
1370                                            AI_Status_1_Register) &
1371                         AI_FIFO_Empty_St) == 0) {
1372                         dl = ni_readl(ADC_FIFO_Data_611x);
1373
1374                         /* This may get the hi/lo data in the wrong order */
1375                         data[0] = (dl >> 16);
1376                         data[1] = (dl & 0xffff);
1377                         cfc_write_array_to_buffer(s, data, sizeof(data));
1378                 }
1379         } else if (board->reg_type == ni_reg_6143) {
1380                 i = 0;
1381                 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1382                         dl = ni_readl(AIFIFO_Data_6143);
1383
1384                         /* This may get the hi/lo data in the wrong order */
1385                         data[0] = (dl >> 16);
1386                         data[1] = (dl & 0xffff);
1387                         cfc_write_array_to_buffer(s, data, sizeof(data));
1388                         i += 2;
1389                 }
1390                 /*  Check if stranded sample is present */
1391                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1392                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1393                         dl = ni_readl(AIFIFO_Data_6143);
1394                         data[0] = (dl >> 16) & 0xffff;
1395                         cfc_write_to_buffer(s, data[0]);
1396                 }
1397
1398         } else {
1399                 fifo_empty =
1400                     devpriv->stc_readw(dev,
1401                                        AI_Status_1_Register) & AI_FIFO_Empty_St;
1402                 while (fifo_empty == 0) {
1403                         for (i = 0;
1404                              i <
1405                              sizeof(devpriv->ai_fifo_buffer) /
1406                              sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1407                                 fifo_empty =
1408                                     devpriv->stc_readw(dev,
1409                                                        AI_Status_1_Register) &
1410                                     AI_FIFO_Empty_St;
1411                                 if (fifo_empty)
1412                                         break;
1413                                 devpriv->ai_fifo_buffer[i] =
1414                                     ni_readw(ADC_FIFO_Data_Register);
1415                         }
1416                         cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1417                                                   i *
1418                                                   sizeof(devpriv->
1419                                                          ai_fifo_buffer[0]));
1420                 }
1421         }
1422 }
1423
1424 static void get_last_sample_611x(struct comedi_device *dev)
1425 {
1426         const struct ni_board_struct *board = comedi_board(dev);
1427         struct ni_private *devpriv __maybe_unused = dev->private;
1428         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1429         unsigned short data;
1430         u32 dl;
1431
1432         if (board->reg_type != ni_reg_611x)
1433                 return;
1434
1435         /* Check if there's a single sample stuck in the FIFO */
1436         if (ni_readb(XXX_Status) & 0x80) {
1437                 dl = ni_readl(ADC_FIFO_Data_611x);
1438                 data = (dl & 0xffff);
1439                 cfc_write_to_buffer(s, data);
1440         }
1441 }
1442
1443 static void get_last_sample_6143(struct comedi_device *dev)
1444 {
1445         const struct ni_board_struct *board = comedi_board(dev);
1446         struct ni_private *devpriv __maybe_unused = dev->private;
1447         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1448         unsigned short data;
1449         u32 dl;
1450
1451         if (board->reg_type != ni_reg_6143)
1452                 return;
1453
1454         /* Check if there's a single sample stuck in the FIFO */
1455         if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1456                 ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1457                 dl = ni_readl(AIFIFO_Data_6143);
1458
1459                 /* This may get the hi/lo data in the wrong order */
1460                 data = (dl >> 16) & 0xffff;
1461                 cfc_write_to_buffer(s, data);
1462         }
1463 }
1464
1465 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1466                         void *data, unsigned int num_bytes,
1467                         unsigned int chan_index)
1468 {
1469         struct ni_private *devpriv = dev->private;
1470         struct comedi_async *async = s->async;
1471         struct comedi_cmd *cmd = &async->cmd;
1472         unsigned int length = num_bytes / bytes_per_sample(s);
1473         unsigned short *array = data;
1474         unsigned int *larray = data;
1475         unsigned int i;
1476
1477         for (i = 0; i < length; i++) {
1478 #ifdef PCIDMA
1479                 if (s->subdev_flags & SDF_LSAMPL)
1480                         larray[i] = le32_to_cpu(larray[i]);
1481                 else
1482                         array[i] = le16_to_cpu(array[i]);
1483 #endif
1484                 if (s->subdev_flags & SDF_LSAMPL)
1485                         larray[i] += devpriv->ai_offset[chan_index];
1486                 else
1487                         array[i] += devpriv->ai_offset[chan_index];
1488                 chan_index++;
1489                 chan_index %= cmd->chanlist_len;
1490         }
1491 }
1492
1493 #ifdef PCIDMA
1494
1495 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1496 {
1497         const struct ni_board_struct *board = comedi_board(dev);
1498         struct ni_private *devpriv = dev->private;
1499         struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1500         int retval;
1501         unsigned long flags;
1502
1503         retval = ni_request_ai_mite_channel(dev);
1504         if (retval)
1505                 return retval;
1506 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1507
1508         /* write alloc the entire buffer */
1509         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1510
1511         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1512         if (devpriv->ai_mite_chan == NULL) {
1513                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1514                 return -EIO;
1515         }
1516
1517         switch (board->reg_type) {
1518         case ni_reg_611x:
1519         case ni_reg_6143:
1520                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1521                 break;
1522         case ni_reg_628x:
1523                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1524                 break;
1525         default:
1526                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1527                 break;
1528         }
1529         /*start the MITE */
1530         mite_dma_arm(devpriv->ai_mite_chan);
1531         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1532
1533         return 0;
1534 }
1535
1536 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1537 {
1538         const struct ni_board_struct *board = comedi_board(dev);
1539         struct ni_private *devpriv = dev->private;
1540         struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1541         int retval;
1542         unsigned long flags;
1543
1544         retval = ni_request_ao_mite_channel(dev);
1545         if (retval)
1546                 return retval;
1547
1548         /* read alloc the entire buffer */
1549         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1550
1551         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1552         if (devpriv->ao_mite_chan) {
1553                 if (board->reg_type & (ni_reg_611x | ni_reg_6713)) {
1554                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1555                 } else {
1556                         /* doing 32 instead of 16 bit wide transfers from memory
1557                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1558                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1559                 }
1560                 mite_dma_arm(devpriv->ao_mite_chan);
1561         } else
1562                 retval = -EIO;
1563         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1564
1565         return retval;
1566 }
1567
1568 #endif /*  PCIDMA */
1569
1570 /*
1571    used for both cancel ioctl and board initialization
1572
1573    this is pretty harsh for a cancel, but it works...
1574  */
1575
1576 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1577 {
1578         const struct ni_board_struct *board = comedi_board(dev);
1579         struct ni_private *devpriv = dev->private;
1580
1581         ni_release_ai_mite_channel(dev);
1582         /* ai configuration */
1583         devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1584                             Joint_Reset_Register);
1585
1586         ni_set_bits(dev, Interrupt_A_Enable_Register,
1587                     AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1588                     AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1589                     AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1590                     AI_FIFO_Interrupt_Enable, 0);
1591
1592         ni_clear_ai_fifo(dev);
1593
1594         if (board->reg_type != ni_reg_6143)
1595                 ni_writeb(0, Misc_Command);
1596
1597         devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register);     /* reset pulses */
1598         devpriv->stc_writew(dev,
1599                             AI_Start_Stop | AI_Mode_1_Reserved
1600                             /*| AI_Trigger_Once */ ,
1601                             AI_Mode_1_Register);
1602         devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1603         /* generate FIFO interrupts on non-empty */
1604         devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1605         if (board->reg_type == ni_reg_611x) {
1606                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1607                                     AI_SOC_Polarity |
1608                                     AI_LOCALMUX_CLK_Pulse_Width,
1609                                     AI_Personal_Register);
1610                 devpriv->stc_writew(dev,
1611                                     AI_SCAN_IN_PROG_Output_Select(3) |
1612                                     AI_EXTMUX_CLK_Output_Select(0) |
1613                                     AI_LOCALMUX_CLK_Output_Select(2) |
1614                                     AI_SC_TC_Output_Select(3) |
1615                                     AI_CONVERT_Output_Select
1616                                     (AI_CONVERT_Output_Enable_High),
1617                                     AI_Output_Control_Register);
1618         } else if (board->reg_type == ni_reg_6143) {
1619                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1620                                     AI_SOC_Polarity |
1621                                     AI_LOCALMUX_CLK_Pulse_Width,
1622                                     AI_Personal_Register);
1623                 devpriv->stc_writew(dev,
1624                                     AI_SCAN_IN_PROG_Output_Select(3) |
1625                                     AI_EXTMUX_CLK_Output_Select(0) |
1626                                     AI_LOCALMUX_CLK_Output_Select(2) |
1627                                     AI_SC_TC_Output_Select(3) |
1628                                     AI_CONVERT_Output_Select
1629                                     (AI_CONVERT_Output_Enable_Low),
1630                                     AI_Output_Control_Register);
1631         } else {
1632                 unsigned ai_output_control_bits;
1633                 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1634                                     AI_SOC_Polarity |
1635                                     AI_CONVERT_Pulse_Width |
1636                                     AI_LOCALMUX_CLK_Pulse_Width,
1637                                     AI_Personal_Register);
1638                 ai_output_control_bits =
1639                     AI_SCAN_IN_PROG_Output_Select(3) |
1640                     AI_EXTMUX_CLK_Output_Select(0) |
1641                     AI_LOCALMUX_CLK_Output_Select(2) |
1642                     AI_SC_TC_Output_Select(3);
1643                 if (board->reg_type == ni_reg_622x)
1644                         ai_output_control_bits |=
1645                             AI_CONVERT_Output_Select
1646                             (AI_CONVERT_Output_Enable_High);
1647                 else
1648                         ai_output_control_bits |=
1649                             AI_CONVERT_Output_Select
1650                             (AI_CONVERT_Output_Enable_Low);
1651                 devpriv->stc_writew(dev, ai_output_control_bits,
1652                                     AI_Output_Control_Register);
1653         }
1654         /* the following registers should not be changed, because there
1655          * are no backup registers in devpriv.  If you want to change
1656          * any of these, add a backup register and other appropriate code:
1657          *      AI_Mode_1_Register
1658          *      AI_Mode_3_Register
1659          *      AI_Personal_Register
1660          *      AI_Output_Control_Register
1661          */
1662         devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register);      /* clear interrupts */
1663
1664         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1665
1666         return 0;
1667 }
1668
1669 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1670 {
1671         unsigned long flags;
1672         int count;
1673
1674         /*  lock to avoid race with interrupt handler */
1675         spin_lock_irqsave(&dev->spinlock, flags);
1676 #ifndef PCIDMA
1677         ni_handle_fifo_dregs(dev);
1678 #else
1679         ni_sync_ai_dma(dev);
1680 #endif
1681         count = s->async->buf_write_count - s->async->buf_read_count;
1682         spin_unlock_irqrestore(&dev->spinlock, flags);
1683
1684         return count;
1685 }
1686
1687 static int ni_ai_insn_read(struct comedi_device *dev,
1688                            struct comedi_subdevice *s, struct comedi_insn *insn,
1689                            unsigned int *data)
1690 {
1691         const struct ni_board_struct *board = comedi_board(dev);
1692         struct ni_private *devpriv = dev->private;
1693         int i, n;
1694         const unsigned int mask = (1 << board->adbits) - 1;
1695         unsigned signbits;
1696         unsigned short d;
1697         unsigned long dl;
1698
1699         ni_load_channelgain_list(dev, 1, &insn->chanspec);
1700
1701         ni_clear_ai_fifo(dev);
1702
1703         signbits = devpriv->ai_offset[0];
1704         if (board->reg_type == ni_reg_611x) {
1705                 for (n = 0; n < num_adc_stages_611x; n++) {
1706                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1707                                             AI_Command_1_Register);
1708                         udelay(1);
1709                 }
1710                 for (n = 0; n < insn->n; n++) {
1711                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1712                                             AI_Command_1_Register);
1713                         /* The 611x has screwy 32-bit FIFOs. */
1714                         d = 0;
1715                         for (i = 0; i < NI_TIMEOUT; i++) {
1716                                 if (ni_readb(XXX_Status) & 0x80) {
1717                                         d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1718                                             & 0xffff;
1719                                         break;
1720                                 }
1721                                 if (!(devpriv->stc_readw(dev,
1722                                                          AI_Status_1_Register) &
1723                                       AI_FIFO_Empty_St)) {
1724                                         d = ni_readl(ADC_FIFO_Data_611x) &
1725                                             0xffff;
1726                                         break;
1727                                 }
1728                         }
1729                         if (i == NI_TIMEOUT) {
1730                                 printk
1731                                     ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1732                                 return -ETIME;
1733                         }
1734                         d += signbits;
1735                         data[n] = d;
1736                 }
1737         } else if (board->reg_type == ni_reg_6143) {
1738                 for (n = 0; n < insn->n; n++) {
1739                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1740                                             AI_Command_1_Register);
1741
1742                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1743                         dl = 0;
1744                         for (i = 0; i < NI_TIMEOUT; i++) {
1745                                 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1746                                         ni_writel(0x01, AIFIFO_Control_6143);   /*  Get stranded sample into FIFO */
1747                                         dl = ni_readl(AIFIFO_Data_6143);
1748                                         break;
1749                                 }
1750                         }
1751                         if (i == NI_TIMEOUT) {
1752                                 printk
1753                                     ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1754                                 return -ETIME;
1755                         }
1756                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1757                 }
1758         } else {
1759                 for (n = 0; n < insn->n; n++) {
1760                         devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1761                                             AI_Command_1_Register);
1762                         for (i = 0; i < NI_TIMEOUT; i++) {
1763                                 if (!(devpriv->stc_readw(dev,
1764                                                          AI_Status_1_Register) &
1765                                       AI_FIFO_Empty_St))
1766                                         break;
1767                         }
1768                         if (i == NI_TIMEOUT) {
1769                                 printk
1770                                     ("ni_mio_common: timeout in ni_ai_insn_read\n");
1771                                 return -ETIME;
1772                         }
1773                         if (board->reg_type & ni_reg_m_series_mask) {
1774                                 data[n] =
1775                                     ni_readl(M_Offset_AI_FIFO_Data) & mask;
1776                         } else {
1777                                 d = ni_readw(ADC_FIFO_Data_Register);
1778                                 d += signbits;  /* subtle: needs to be short addition */
1779                                 data[n] = d;
1780                         }
1781                 }
1782         }
1783         return insn->n;
1784 }
1785
1786 static void ni_prime_channelgain_list(struct comedi_device *dev)
1787 {
1788         struct ni_private *devpriv = dev->private;
1789         int i;
1790
1791         devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1792         for (i = 0; i < NI_TIMEOUT; ++i) {
1793                 if (!(devpriv->stc_readw(dev,
1794                                          AI_Status_1_Register) &
1795                       AI_FIFO_Empty_St)) {
1796                         devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1797                         return;
1798                 }
1799                 udelay(1);
1800         }
1801         printk("ni_mio_common: timeout loading channel/gain list\n");
1802 }
1803
1804 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1805                                               unsigned int n_chan,
1806                                               unsigned int *list)
1807 {
1808         const struct ni_board_struct *board = comedi_board(dev);
1809         struct ni_private *devpriv = dev->private;
1810         unsigned int chan, range, aref;
1811         unsigned int i;
1812         unsigned offset;
1813         unsigned int dither;
1814         unsigned range_code;
1815
1816         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1817
1818 /* offset = 1 << (board->adbits - 1); */
1819         if ((list[0] & CR_ALT_SOURCE)) {
1820                 unsigned bypass_bits;
1821                 chan = CR_CHAN(list[0]);
1822                 range = CR_RANGE(list[0]);
1823                 range_code = ni_gainlkup[board->gainlkup][range];
1824                 dither = ((list[0] & CR_ALT_FILTER) != 0);
1825                 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1826                 bypass_bits |= chan;
1827                 bypass_bits |=
1828                     (devpriv->ai_calib_source) &
1829                     (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1830                      MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1831                      MSeries_AI_Bypass_Mode_Mux_Mask |
1832                      MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1833                 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1834                 if (dither)
1835                         bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1836                 /*  don't use 2's complement encoding */
1837                 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1838                 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1839         } else {
1840                 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1841         }
1842         offset = 0;
1843         for (i = 0; i < n_chan; i++) {
1844                 unsigned config_bits = 0;
1845                 chan = CR_CHAN(list[i]);
1846                 aref = CR_AREF(list[i]);
1847                 range = CR_RANGE(list[i]);
1848                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1849
1850                 range_code = ni_gainlkup[board->gainlkup][range];
1851                 devpriv->ai_offset[i] = offset;
1852                 switch (aref) {
1853                 case AREF_DIFF:
1854                         config_bits |=
1855                             MSeries_AI_Config_Channel_Type_Differential_Bits;
1856                         break;
1857                 case AREF_COMMON:
1858                         config_bits |=
1859                             MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1860                         break;
1861                 case AREF_GROUND:
1862                         config_bits |=
1863                             MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1864                         break;
1865                 case AREF_OTHER:
1866                         break;
1867                 }
1868                 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1869                 config_bits |=
1870                     MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
1871                 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1872                 if (i == n_chan - 1)
1873                         config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1874                 if (dither)
1875                         config_bits |= MSeries_AI_Config_Dither_Bit;
1876                 /*  don't use 2's complement encoding */
1877                 config_bits |= MSeries_AI_Config_Polarity_Bit;
1878                 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1879         }
1880         ni_prime_channelgain_list(dev);
1881 }
1882
1883 /*
1884  * Notes on the 6110 and 6111:
1885  * These boards a slightly different than the rest of the series, since
1886  * they have multiple A/D converters.
1887  * From the driver side, the configuration memory is a
1888  * little different.
1889  * Configuration Memory Low:
1890  *   bits 15-9: same
1891  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1892  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1893  *       1001 gain=0.1 (+/- 50)
1894  *       1010 0.2
1895  *       1011 0.1
1896  *       0001 1
1897  *       0010 2
1898  *       0011 5
1899  *       0100 10
1900  *       0101 20
1901  *       0110 50
1902  * Configuration Memory High:
1903  *   bits 12-14: Channel Type
1904  *       001 for differential
1905  *       000 for calibration
1906  *   bit 11: coupling  (this is not currently handled)
1907  *       1 AC coupling
1908  *       0 DC coupling
1909  *   bits 0-2: channel
1910  *       valid channels are 0-3
1911  */
1912 static void ni_load_channelgain_list(struct comedi_device *dev,
1913                                      unsigned int n_chan, unsigned int *list)
1914 {
1915         const struct ni_board_struct *board = comedi_board(dev);
1916         struct ni_private *devpriv = dev->private;
1917         unsigned int chan, range, aref;
1918         unsigned int i;
1919         unsigned int hi, lo;
1920         unsigned offset;
1921         unsigned int dither;
1922
1923         if (board->reg_type & ni_reg_m_series_mask) {
1924                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1925                 return;
1926         }
1927         if (n_chan == 1 && (board->reg_type != ni_reg_611x)
1928             && (board->reg_type != ni_reg_6143)) {
1929                 if (devpriv->changain_state
1930                     && devpriv->changain_spec == list[0]) {
1931                         /*  ready to go. */
1932                         return;
1933                 }
1934                 devpriv->changain_state = 1;
1935                 devpriv->changain_spec = list[0];
1936         } else {
1937                 devpriv->changain_state = 0;
1938         }
1939
1940         devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1941
1942         /*  Set up Calibration mode if required */
1943         if (board->reg_type == ni_reg_6143) {
1944                 if ((list[0] & CR_ALT_SOURCE)
1945                     && !devpriv->ai_calib_source_enabled) {
1946                         /*  Strobe Relay enable bit */
1947                         ni_writew(devpriv->ai_calib_source |
1948                                   Calibration_Channel_6143_RelayOn,
1949                                   Calibration_Channel_6143);
1950                         ni_writew(devpriv->ai_calib_source,
1951                                   Calibration_Channel_6143);
1952                         devpriv->ai_calib_source_enabled = 1;
1953                         msleep_interruptible(100);      /*  Allow relays to change */
1954                 } else if (!(list[0] & CR_ALT_SOURCE)
1955                            && devpriv->ai_calib_source_enabled) {
1956                         /*  Strobe Relay disable bit */
1957                         ni_writew(devpriv->ai_calib_source |
1958                                   Calibration_Channel_6143_RelayOff,
1959                                   Calibration_Channel_6143);
1960                         ni_writew(devpriv->ai_calib_source,
1961                                   Calibration_Channel_6143);
1962                         devpriv->ai_calib_source_enabled = 0;
1963                         msleep_interruptible(100);      /*  Allow relays to change */
1964                 }
1965         }
1966
1967         offset = 1 << (board->adbits - 1);
1968         for (i = 0; i < n_chan; i++) {
1969                 if ((board->reg_type != ni_reg_6143)
1970                     && (list[i] & CR_ALT_SOURCE)) {
1971                         chan = devpriv->ai_calib_source;
1972                 } else {
1973                         chan = CR_CHAN(list[i]);
1974                 }
1975                 aref = CR_AREF(list[i]);
1976                 range = CR_RANGE(list[i]);
1977                 dither = ((list[i] & CR_ALT_FILTER) != 0);
1978
1979                 /* fix the external/internal range differences */
1980                 range = ni_gainlkup[board->gainlkup][range];
1981                 if (board->reg_type == ni_reg_611x)
1982                         devpriv->ai_offset[i] = offset;
1983                 else
1984                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1985
1986                 hi = 0;
1987                 if ((list[i] & CR_ALT_SOURCE)) {
1988                         if (board->reg_type == ni_reg_611x)
1989                                 ni_writew(CR_CHAN(list[i]) & 0x0003,
1990                                           Calibration_Channel_Select_611x);
1991                 } else {
1992                         if (board->reg_type == ni_reg_611x)
1993                                 aref = AREF_DIFF;
1994                         else if (board->reg_type == ni_reg_6143)
1995                                 aref = AREF_OTHER;
1996                         switch (aref) {
1997                         case AREF_DIFF:
1998                                 hi |= AI_DIFFERENTIAL;
1999                                 break;
2000                         case AREF_COMMON:
2001                                 hi |= AI_COMMON;
2002                                 break;
2003                         case AREF_GROUND:
2004                                 hi |= AI_GROUND;
2005                                 break;
2006                         case AREF_OTHER:
2007                                 break;
2008                         }
2009                 }
2010                 hi |= AI_CONFIG_CHANNEL(chan);
2011
2012                 ni_writew(hi, Configuration_Memory_High);
2013
2014                 if (board->reg_type != ni_reg_6143) {
2015                         lo = range;
2016                         if (i == n_chan - 1)
2017                                 lo |= AI_LAST_CHANNEL;
2018                         if (dither)
2019                                 lo |= AI_DITHER;
2020
2021                         ni_writew(lo, Configuration_Memory_Low);
2022                 }
2023         }
2024
2025         /* prime the channel/gain list */
2026         if ((board->reg_type != ni_reg_611x)
2027             && (board->reg_type != ni_reg_6143)) {
2028                 ni_prime_channelgain_list(dev);
2029         }
2030 }
2031
2032 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2033                           int round_mode)
2034 {
2035         struct ni_private *devpriv = dev->private;
2036         int divider;
2037
2038         switch (round_mode) {
2039         case TRIG_ROUND_NEAREST:
2040         default:
2041                 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2042                 break;
2043         case TRIG_ROUND_DOWN:
2044                 divider = (nanosec) / devpriv->clock_ns;
2045                 break;
2046         case TRIG_ROUND_UP:
2047                 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2048                 break;
2049         }
2050         return divider - 1;
2051 }
2052
2053 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2054 {
2055         struct ni_private *devpriv = dev->private;
2056
2057         return devpriv->clock_ns * (timer + 1);
2058 }
2059
2060 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2061                                          unsigned num_channels)
2062 {
2063         const struct ni_board_struct *board = comedi_board(dev);
2064
2065         switch (board->reg_type) {
2066         case ni_reg_611x:
2067         case ni_reg_6143:
2068                 /*  simultaneously-sampled inputs */
2069                 return board->ai_speed;
2070                 break;
2071         default:
2072                 /*  multiplexed inputs */
2073                 break;
2074         }
2075         return board->ai_speed * num_channels;
2076 }
2077
2078 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2079                          struct comedi_cmd *cmd)
2080 {
2081         const struct ni_board_struct *board = comedi_board(dev);
2082         struct ni_private *devpriv = dev->private;
2083         int err = 0;
2084         unsigned int tmp;
2085         unsigned int sources;
2086
2087         /* Step 1 : check if triggers are trivially valid */
2088
2089         if ((cmd->flags & CMDF_WRITE))
2090                 cmd->flags &= ~CMDF_WRITE;
2091
2092         err |= cfc_check_trigger_src(&cmd->start_src,
2093                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2094         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2095                                         TRIG_TIMER | TRIG_EXT);
2096
2097         sources = TRIG_TIMER | TRIG_EXT;
2098         if (board->reg_type == ni_reg_611x ||
2099             board->reg_type == ni_reg_6143)
2100                 sources |= TRIG_NOW;
2101         err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2102
2103         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2104         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2105
2106         if (err)
2107                 return 1;
2108
2109         /* Step 2a : make sure trigger sources are unique */
2110
2111         err |= cfc_check_trigger_is_unique(cmd->start_src);
2112         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2113         err |= cfc_check_trigger_is_unique(cmd->convert_src);
2114         err |= cfc_check_trigger_is_unique(cmd->stop_src);
2115
2116         /* Step 2b : and mutually compatible */
2117
2118         if (err)
2119                 return 2;
2120
2121         /* Step 3: check if arguments are trivially valid */
2122
2123         switch (cmd->start_src) {
2124         case TRIG_NOW:
2125         case TRIG_INT:
2126                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2127                 break;
2128         case TRIG_EXT:
2129                 tmp = CR_CHAN(cmd->start_arg);
2130
2131                 if (tmp > 16)
2132                         tmp = 16;
2133                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2134                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2135                 break;
2136         }
2137
2138         if (cmd->scan_begin_src == TRIG_TIMER) {
2139                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2140                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2141                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2142                                                  devpriv->clock_ns * 0xffffff);
2143         } else if (cmd->scan_begin_src == TRIG_EXT) {
2144                 /* external trigger */
2145                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2146
2147                 if (tmp > 16)
2148                         tmp = 16;
2149                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2150                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2151         } else {                /* TRIG_OTHER */
2152                 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2153         }
2154
2155         if (cmd->convert_src == TRIG_TIMER) {
2156                 if ((board->reg_type == ni_reg_611x)
2157                     || (board->reg_type == ni_reg_6143)) {
2158                         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2159                 } else {
2160                         err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2161                                                          board->ai_speed);
2162                         err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2163                                                 devpriv->clock_ns * 0xffff);
2164                 }
2165         } else if (cmd->convert_src == TRIG_EXT) {
2166                 /* external trigger */
2167                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2168
2169                 if (tmp > 16)
2170                         tmp = 16;
2171                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2172                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2173         } else if (cmd->convert_src == TRIG_NOW) {
2174                 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2175         }
2176
2177         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2178
2179         if (cmd->stop_src == TRIG_COUNT) {
2180                 unsigned int max_count = 0x01000000;
2181
2182                 if (board->reg_type == ni_reg_611x)
2183                         max_count -= num_adc_stages_611x;
2184                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2185                 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2186         } else {
2187                 /* TRIG_NONE */
2188                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2189         }
2190
2191         if (err)
2192                 return 3;
2193
2194         /* step 4: fix up any arguments */
2195
2196         if (cmd->scan_begin_src == TRIG_TIMER) {
2197                 tmp = cmd->scan_begin_arg;
2198                 cmd->scan_begin_arg =
2199                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2200                                                        cmd->scan_begin_arg,
2201                                                        cmd->
2202                                                        flags &
2203                                                        TRIG_ROUND_MASK));
2204                 if (tmp != cmd->scan_begin_arg)
2205                         err++;
2206         }
2207         if (cmd->convert_src == TRIG_TIMER) {
2208                 if ((board->reg_type != ni_reg_611x)
2209                     && (board->reg_type != ni_reg_6143)) {
2210                         tmp = cmd->convert_arg;
2211                         cmd->convert_arg =
2212                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2213                                                                cmd->convert_arg,
2214                                                                cmd->
2215                                                                flags &
2216                                                                TRIG_ROUND_MASK));
2217                         if (tmp != cmd->convert_arg)
2218                                 err++;
2219                         if (cmd->scan_begin_src == TRIG_TIMER &&
2220                             cmd->scan_begin_arg <
2221                             cmd->convert_arg * cmd->scan_end_arg) {
2222                                 cmd->scan_begin_arg =
2223                                     cmd->convert_arg * cmd->scan_end_arg;
2224                                 err++;
2225                         }
2226                 }
2227         }
2228
2229         if (err)
2230                 return 4;
2231
2232         return 0;
2233 }
2234
2235 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2236 {
2237         const struct ni_board_struct *board = comedi_board(dev);
2238         struct ni_private *devpriv = dev->private;
2239         const struct comedi_cmd *cmd = &s->async->cmd;
2240         int timer;
2241         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2242         int mode2 = 0;
2243         int start_stop_select = 0;
2244         unsigned int stop_count;
2245         int interrupt_a_enable = 0;
2246
2247         if (dev->irq == 0) {
2248                 comedi_error(dev, "cannot run command without an irq");
2249                 return -EIO;
2250         }
2251         ni_clear_ai_fifo(dev);
2252
2253         ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2254
2255         /* start configuration */
2256         devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2257
2258         /* disable analog triggering for now, since it
2259          * interferes with the use of pfi0 */
2260         devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2261         devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2262                             Analog_Trigger_Etc_Register);
2263
2264         switch (cmd->start_src) {
2265         case TRIG_INT:
2266         case TRIG_NOW:
2267                 devpriv->stc_writew(dev, AI_START2_Select(0) |
2268                                     AI_START1_Sync | AI_START1_Edge |
2269                                     AI_START1_Select(0),
2270                                     AI_Trigger_Select_Register);
2271                 break;
2272         case TRIG_EXT:
2273                 {
2274                         int chan = CR_CHAN(cmd->start_arg);
2275                         unsigned int bits = AI_START2_Select(0) |
2276                             AI_START1_Sync | AI_START1_Select(chan + 1);
2277
2278                         if (cmd->start_arg & CR_INVERT)
2279                                 bits |= AI_START1_Polarity;
2280                         if (cmd->start_arg & CR_EDGE)
2281                                 bits |= AI_START1_Edge;
2282                         devpriv->stc_writew(dev, bits,
2283                                             AI_Trigger_Select_Register);
2284                         break;
2285                 }
2286         }
2287
2288         mode2 &= ~AI_Pre_Trigger;
2289         mode2 &= ~AI_SC_Initial_Load_Source;
2290         mode2 &= ~AI_SC_Reload_Mode;
2291         devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2292
2293         if (cmd->chanlist_len == 1 || (board->reg_type == ni_reg_611x)
2294             || (board->reg_type == ni_reg_6143)) {
2295                 start_stop_select |= AI_STOP_Polarity;
2296                 start_stop_select |= AI_STOP_Select(31);        /*  logic low */
2297                 start_stop_select |= AI_STOP_Sync;
2298         } else {
2299                 start_stop_select |= AI_STOP_Select(19);        /*  ai configuration memory */
2300         }
2301         devpriv->stc_writew(dev, start_stop_select,
2302                             AI_START_STOP_Select_Register);
2303
2304         devpriv->ai_cmd2 = 0;
2305         switch (cmd->stop_src) {
2306         case TRIG_COUNT:
2307                 stop_count = cmd->stop_arg - 1;
2308
2309                 if (board->reg_type == ni_reg_611x) {
2310                         /*  have to take 3 stage adc pipeline into account */
2311                         stop_count += num_adc_stages_611x;
2312                 }
2313                 /* stage number of scans */
2314                 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2315
2316                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2317                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2318                 /* load SC (Scan Count) */
2319                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2320
2321                 devpriv->ai_continuous = 0;
2322                 if (stop_count == 0) {
2323                         devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2324                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2325                         /*  this is required to get the last sample for chanlist_len > 1, not sure why */
2326                         if (cmd->chanlist_len > 1)
2327                                 start_stop_select |=
2328                                     AI_STOP_Polarity | AI_STOP_Edge;
2329                 }
2330                 break;
2331         case TRIG_NONE:
2332                 /* stage number of scans */
2333                 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2334
2335                 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2336                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2337
2338                 /* load SC (Scan Count) */
2339                 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2340
2341                 devpriv->ai_continuous = 1;
2342
2343                 break;
2344         }
2345
2346         switch (cmd->scan_begin_src) {
2347         case TRIG_TIMER:
2348                 /*
2349                    stop bits for non 611x boards
2350                    AI_SI_Special_Trigger_Delay=0
2351                    AI_Pre_Trigger=0
2352                    AI_START_STOP_Select_Register:
2353                    AI_START_Polarity=0 (?)      rising edge
2354                    AI_START_Edge=1              edge triggered
2355                    AI_START_Sync=1 (?)
2356                    AI_START_Select=0            SI_TC
2357                    AI_STOP_Polarity=0           rising edge
2358                    AI_STOP_Edge=0               level
2359                    AI_STOP_Sync=1
2360                    AI_STOP_Select=19            external pin (configuration mem)
2361                  */
2362                 start_stop_select |= AI_START_Edge | AI_START_Sync;
2363                 devpriv->stc_writew(dev, start_stop_select,
2364                                     AI_START_STOP_Select_Register);
2365
2366                 mode2 |= AI_SI_Reload_Mode(0);
2367                 /* AI_SI_Initial_Load_Source=A */
2368                 mode2 &= ~AI_SI_Initial_Load_Source;
2369                 /* mode2 |= AI_SC_Reload_Mode; */
2370                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2371
2372                 /* load SI */
2373                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2374                                        TRIG_ROUND_NEAREST);
2375                 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2376                 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2377                 break;
2378         case TRIG_EXT:
2379                 if (cmd->scan_begin_arg & CR_EDGE)
2380                         start_stop_select |= AI_START_Edge;
2381                 /* AI_START_Polarity==1 is falling edge */
2382                 if (cmd->scan_begin_arg & CR_INVERT)
2383                         start_stop_select |= AI_START_Polarity;
2384                 if (cmd->scan_begin_src != cmd->convert_src ||
2385                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2386                     (cmd->convert_arg & ~CR_EDGE))
2387                         start_stop_select |= AI_START_Sync;
2388                 start_stop_select |=
2389                     AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2390                 devpriv->stc_writew(dev, start_stop_select,
2391                                     AI_START_STOP_Select_Register);
2392                 break;
2393         }
2394
2395         switch (cmd->convert_src) {
2396         case TRIG_TIMER:
2397         case TRIG_NOW:
2398                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2399                         timer = 1;
2400                 else
2401                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2402                                                TRIG_ROUND_NEAREST);
2403                 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register);    /* 0,0 does not work. */
2404                 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2405
2406                 /* AI_SI2_Reload_Mode = alternate */
2407                 /* AI_SI2_Initial_Load_Source = A */
2408                 mode2 &= ~AI_SI2_Initial_Load_Source;
2409                 mode2 |= AI_SI2_Reload_Mode;
2410                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2411
2412                 /* AI_SI2_Load */
2413                 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2414
2415                 mode2 |= AI_SI2_Reload_Mode;    /*  alternate */
2416                 mode2 |= AI_SI2_Initial_Load_Source;    /*  B */
2417
2418                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2419                 break;
2420         case TRIG_EXT:
2421                 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2422                 if ((cmd->convert_arg & CR_INVERT) == 0)
2423                         mode1 |= AI_CONVERT_Source_Polarity;
2424                 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2425
2426                 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2427                 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2428
2429                 break;
2430         }
2431
2432         if (dev->irq) {
2433
2434                 /* interrupt on FIFO, errors, SC_TC */
2435                 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2436                     AI_SC_TC_Interrupt_Enable;
2437
2438 #ifndef PCIDMA
2439                 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2440 #endif
2441
2442                 if (cmd->flags & TRIG_WAKE_EOS
2443                     || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2444                         /* wake on end-of-scan */
2445                         devpriv->aimode = AIMODE_SCAN;
2446                 } else {
2447                         devpriv->aimode = AIMODE_HALF_FULL;
2448                 }
2449
2450                 switch (devpriv->aimode) {
2451                 case AIMODE_HALF_FULL:
2452                         /*generate FIFO interrupts and DMA requests on half-full */
2453 #ifdef PCIDMA
2454                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2455                                             AI_Mode_3_Register);
2456 #else
2457                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2458                                             AI_Mode_3_Register);
2459 #endif
2460                         break;
2461                 case AIMODE_SAMPLE:
2462                         /*generate FIFO interrupts on non-empty */
2463                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2464                                             AI_Mode_3_Register);
2465                         break;
2466                 case AIMODE_SCAN:
2467 #ifdef PCIDMA
2468                         devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2469                                             AI_Mode_3_Register);
2470 #else
2471                         devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2472                                             AI_Mode_3_Register);
2473 #endif
2474                         interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2475                         break;
2476                 default:
2477                         break;
2478                 }
2479
2480                 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register);      /* clear interrupts */
2481
2482                 ni_set_bits(dev, Interrupt_A_Enable_Register,
2483                             interrupt_a_enable, 1);
2484         } else {
2485                 /* interrupt on nothing */
2486                 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2487
2488                 /* XXX start polling if necessary */
2489         }
2490
2491         /* end configuration */
2492         devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2493
2494         switch (cmd->scan_begin_src) {
2495         case TRIG_TIMER:
2496                 devpriv->stc_writew(dev,
2497                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2498                                     AI_SC_Arm, AI_Command_1_Register);
2499                 break;
2500         case TRIG_EXT:
2501                 /* XXX AI_SI_Arm? */
2502                 devpriv->stc_writew(dev,
2503                                     AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2504                                     AI_SC_Arm, AI_Command_1_Register);
2505                 break;
2506         }
2507
2508 #ifdef PCIDMA
2509         {
2510                 int retval = ni_ai_setup_MITE_dma(dev);
2511                 if (retval)
2512                         return retval;
2513         }
2514 #endif
2515
2516         if (cmd->start_src == TRIG_NOW) {
2517                 /* AI_START1_Pulse */
2518                 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2519                                     AI_Command_2_Register);
2520                 s->async->inttrig = NULL;
2521         } else if (cmd->start_src == TRIG_EXT) {
2522                 s->async->inttrig = NULL;
2523         } else {        /* TRIG_INT */
2524                 s->async->inttrig = ni_ai_inttrig;
2525         }
2526
2527         return 0;
2528 }
2529
2530 static int ni_ai_inttrig(struct comedi_device *dev,
2531                          struct comedi_subdevice *s,
2532                          unsigned int trig_num)
2533 {
2534         struct ni_private *devpriv = dev->private;
2535         struct comedi_cmd *cmd = &s->async->cmd;
2536
2537         if (trig_num != cmd->start_arg)
2538                 return -EINVAL;
2539
2540         devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2541                             AI_Command_2_Register);
2542         s->async->inttrig = NULL;
2543
2544         return 1;
2545 }
2546
2547 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2548                                     struct comedi_subdevice *s,
2549                                     struct comedi_insn *insn,
2550                                     unsigned int *data);
2551
2552 static int ni_ai_insn_config(struct comedi_device *dev,
2553                              struct comedi_subdevice *s,
2554                              struct comedi_insn *insn, unsigned int *data)
2555 {
2556         const struct ni_board_struct *board = comedi_board(dev);
2557         struct ni_private *devpriv = dev->private;
2558
2559         if (insn->n < 1)
2560                 return -EINVAL;
2561
2562         switch (data[0]) {
2563         case INSN_CONFIG_ANALOG_TRIG:
2564                 return ni_ai_config_analog_trig(dev, s, insn, data);
2565         case INSN_CONFIG_ALT_SOURCE:
2566                 if (board->reg_type & ni_reg_m_series_mask) {
2567                         if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2568                                         MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2569                                         MSeries_AI_Bypass_Mode_Mux_Mask |
2570                                         MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2571                                 return -EINVAL;
2572                         }
2573                         devpriv->ai_calib_source = data[1];
2574                 } else if (board->reg_type == ni_reg_6143) {
2575                         unsigned int calib_source;
2576
2577                         calib_source = data[1] & 0xf;
2578
2579                         if (calib_source > 0xF)
2580                                 return -EINVAL;
2581
2582                         devpriv->ai_calib_source = calib_source;
2583                         ni_writew(calib_source, Calibration_Channel_6143);
2584                 } else {
2585                         unsigned int calib_source;
2586                         unsigned int calib_source_adjust;
2587
2588                         calib_source = data[1] & 0xf;
2589                         calib_source_adjust = (data[1] >> 4) & 0xff;
2590
2591                         if (calib_source >= 8)
2592                                 return -EINVAL;
2593                         devpriv->ai_calib_source = calib_source;
2594                         if (board->reg_type == ni_reg_611x) {
2595                                 ni_writeb(calib_source_adjust,
2596                                           Cal_Gain_Select_611x);
2597                         }
2598                 }
2599                 return 2;
2600         default:
2601                 break;
2602         }
2603
2604         return -EINVAL;
2605 }
2606
2607 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2608                                     struct comedi_subdevice *s,
2609                                     struct comedi_insn *insn,
2610                                     unsigned int *data)
2611 {
2612         const struct ni_board_struct *board = comedi_board(dev);
2613         struct ni_private *devpriv = dev->private;
2614         unsigned int a, b, modebits;
2615         int err = 0;
2616
2617         /* data[1] is flags
2618          * data[2] is analog line
2619          * data[3] is set level
2620          * data[4] is reset level */
2621         if (!board->has_analog_trig)
2622                 return -EINVAL;
2623         if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2624                 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2625                 err++;
2626         }
2627         if (data[2] >= board->n_adchan) {
2628                 data[2] = board->n_adchan - 1;
2629                 err++;
2630         }
2631         if (data[3] > 255) {    /* a */
2632                 data[3] = 255;
2633                 err++;
2634         }
2635         if (data[4] > 255) {    /* b */
2636                 data[4] = 255;
2637                 err++;
2638         }
2639         /*
2640          * 00 ignore
2641          * 01 set
2642          * 10 reset
2643          *
2644          * modes:
2645          *   1 level:                    +b-   +a-
2646          *     high mode                00 00 01 10
2647          *     low mode                 00 00 10 01
2648          *   2 level: (a<b)
2649          *     hysteresis low mode      10 00 00 01
2650          *     hysteresis high mode     01 00 00 10
2651          *     middle mode              10 01 01 10
2652          */
2653
2654         a = data[3];
2655         b = data[4];
2656         modebits = data[1] & 0xff;
2657         if (modebits & 0xf0) {
2658                 /* two level mode */
2659                 if (b < a) {
2660                         /* swap order */
2661                         a = data[4];
2662                         b = data[3];
2663                         modebits =
2664                             ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2665                 }
2666                 devpriv->atrig_low = a;
2667                 devpriv->atrig_high = b;
2668                 switch (modebits) {
2669                 case 0x81:      /* low hysteresis mode */
2670                         devpriv->atrig_mode = 6;
2671                         break;
2672                 case 0x42:      /* high hysteresis mode */
2673                         devpriv->atrig_mode = 3;
2674                         break;
2675                 case 0x96:      /* middle window mode */
2676                         devpriv->atrig_mode = 2;
2677                         break;
2678                 default:
2679                         data[1] &= ~0xff;
2680                         err++;
2681                 }
2682         } else {
2683                 /* one level mode */
2684                 if (b != 0) {
2685                         data[4] = 0;
2686                         err++;
2687                 }
2688                 switch (modebits) {
2689                 case 0x06:      /* high window mode */
2690                         devpriv->atrig_high = a;
2691                         devpriv->atrig_mode = 0;
2692                         break;
2693                 case 0x09:      /* low window mode */
2694                         devpriv->atrig_low = a;
2695                         devpriv->atrig_mode = 1;
2696                         break;
2697                 default:
2698                         data[1] &= ~0xff;
2699                         err++;
2700                 }
2701         }
2702         if (err)
2703                 return -EAGAIN;
2704         return 5;
2705 }
2706
2707 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2708 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2709                         void *data, unsigned int num_bytes,
2710                         unsigned int chan_index)
2711 {
2712         const struct ni_board_struct *board = comedi_board(dev);
2713         struct comedi_async *async = s->async;
2714         struct comedi_cmd *cmd = &async->cmd;
2715         unsigned int length = num_bytes / sizeof(short);
2716         unsigned int offset = 1 << (board->aobits - 1);
2717         unsigned short *array = data;
2718         unsigned int range;
2719         unsigned int i;
2720
2721         for (i = 0; i < length; i++) {
2722                 range = CR_RANGE(cmd->chanlist[chan_index]);
2723                 if (board->ao_unipolar == 0 || (range & 1) == 0)
2724                         array[i] -= offset;
2725 #ifdef PCIDMA
2726                 array[i] = cpu_to_le16(array[i]);
2727 #endif
2728                 chan_index++;
2729                 chan_index %= cmd->chanlist_len;
2730         }
2731 }
2732
2733 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2734                                           struct comedi_subdevice *s,
2735                                           unsigned int chanspec[],
2736                                           unsigned int n_chans, int timed)
2737 {
2738         const struct ni_board_struct *board = comedi_board(dev);
2739         struct ni_private *devpriv = dev->private;
2740         unsigned int range;
2741         unsigned int chan;
2742         unsigned int conf;
2743         int i;
2744         int invert = 0;
2745
2746         if (timed) {
2747                 for (i = 0; i < board->n_aochan; ++i) {
2748                         devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2749                         ni_writeb(devpriv->ao_conf[i],
2750                                   M_Offset_AO_Config_Bank(i));
2751                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2752                 }
2753         }
2754         for (i = 0; i < n_chans; i++) {
2755                 const struct comedi_krange *krange;
2756                 chan = CR_CHAN(chanspec[i]);
2757                 range = CR_RANGE(chanspec[i]);
2758                 krange = s->range_table->range + range;
2759                 invert = 0;
2760                 conf = 0;
2761                 switch (krange->max - krange->min) {
2762                 case 20000000:
2763                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2764                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2765                         break;
2766                 case 10000000:
2767                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2768                         ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2769                         break;
2770                 case 4000000:
2771                         conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2772                         ni_writeb(MSeries_Attenuate_x5_Bit,
2773                                   M_Offset_AO_Reference_Attenuation(chan));
2774                         break;
2775                 case 2000000:
2776                         conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2777                         ni_writeb(MSeries_Attenuate_x5_Bit,
2778                                   M_Offset_AO_Reference_Attenuation(chan));
2779                         break;
2780                 default:
2781                         printk("%s: bug! unhandled ao reference voltage\n",
2782                                __func__);
2783                         break;
2784                 }
2785                 switch (krange->max + krange->min) {
2786                 case 0:
2787                         conf |= MSeries_AO_DAC_Offset_0V_Bits;
2788                         break;
2789                 case 10000000:
2790                         conf |= MSeries_AO_DAC_Offset_5V_Bits;
2791                         break;
2792                 default:
2793                         printk("%s: bug! unhandled ao offset voltage\n",
2794                                __func__);
2795                         break;
2796                 }
2797                 if (timed)
2798                         conf |= MSeries_AO_Update_Timed_Bit;
2799                 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2800                 devpriv->ao_conf[chan] = conf;
2801                 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2802         }
2803         return invert;
2804 }
2805
2806 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2807                                      struct comedi_subdevice *s,
2808                                      unsigned int chanspec[],
2809                                      unsigned int n_chans)
2810 {
2811         const struct ni_board_struct *board = comedi_board(dev);
2812         struct ni_private *devpriv = dev->private;
2813         unsigned int range;
2814         unsigned int chan;
2815         unsigned int conf;
2816         int i;
2817         int invert = 0;
2818
2819         for (i = 0; i < n_chans; i++) {
2820                 chan = CR_CHAN(chanspec[i]);
2821                 range = CR_RANGE(chanspec[i]);
2822                 conf = AO_Channel(chan);
2823
2824                 if (board->ao_unipolar) {
2825                         if ((range & 1) == 0) {
2826                                 conf |= AO_Bipolar;
2827                                 invert = (1 << (board->aobits - 1));
2828                         } else {
2829                                 invert = 0;
2830                         }
2831                         if (range & 2)
2832                                 conf |= AO_Ext_Ref;
2833                 } else {
2834                         conf |= AO_Bipolar;
2835                         invert = (1 << (board->aobits - 1));
2836                 }
2837
2838                 /* not all boards can deglitch, but this shouldn't hurt */
2839                 if (chanspec[i] & CR_DEGLITCH)
2840                         conf |= AO_Deglitch;
2841
2842                 /* analog reference */
2843                 /* AREF_OTHER connects AO ground to AI ground, i think */
2844                 conf |= (CR_AREF(chanspec[i]) ==
2845                          AREF_OTHER) ? AO_Ground_Ref : 0;
2846
2847                 ni_writew(conf, AO_Configuration);
2848                 devpriv->ao_conf[chan] = conf;
2849         }
2850         return invert;
2851 }
2852
2853 static int ni_ao_config_chanlist(struct comedi_device *dev,
2854                                  struct comedi_subdevice *s,
2855                                  unsigned int chanspec[], unsigned int n_chans,
2856                                  int timed)
2857 {
2858         const struct ni_board_struct *board = comedi_board(dev);
2859
2860         if (board->reg_type & ni_reg_m_series_mask)
2861                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2862                                                       timed);
2863         else
2864                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2865 }
2866
2867 static int ni_ao_insn_read(struct comedi_device *dev,
2868                            struct comedi_subdevice *s, struct comedi_insn *insn,
2869                            unsigned int *data)
2870 {
2871         struct ni_private *devpriv = dev->private;
2872
2873         data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2874
2875         return 1;
2876 }
2877
2878 static int ni_ao_insn_write(struct comedi_device *dev,
2879                             struct comedi_subdevice *s,
2880                             struct comedi_insn *insn, unsigned int *data)
2881 {
2882         const struct ni_board_struct *board = comedi_board(dev);
2883         struct ni_private *devpriv = dev->private;
2884         unsigned int chan = CR_CHAN(insn->chanspec);
2885         unsigned int invert;
2886
2887         invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2888
2889         devpriv->ao[chan] = data[0];
2890
2891         if (board->reg_type & ni_reg_m_series_mask) {
2892                 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2893         } else
2894                 ni_writew(data[0] ^ invert,
2895                           (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
2896
2897         return 1;
2898 }
2899
2900 static int ni_ao_insn_write_671x(struct comedi_device *dev,
2901                                  struct comedi_subdevice *s,
2902                                  struct comedi_insn *insn, unsigned int *data)
2903 {
2904         const struct ni_board_struct *board = comedi_board(dev);
2905         struct ni_private *devpriv = dev->private;
2906         unsigned int chan = CR_CHAN(insn->chanspec);
2907         unsigned int invert;
2908
2909         ao_win_out(1 << chan, AO_Immediate_671x);
2910         invert = 1 << (board->aobits - 1);
2911
2912         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2913
2914         devpriv->ao[chan] = data[0];
2915         ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2916
2917         return 1;
2918 }
2919
2920 static int ni_ao_insn_config(struct comedi_device *dev,
2921                              struct comedi_subdevice *s,
2922                              struct comedi_insn *insn, unsigned int *data)
2923 {
2924         const struct ni_board_struct *board = comedi_board(dev);
2925         struct ni_private *devpriv = dev->private;
2926
2927         switch (data[0]) {
2928         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2929                 switch (data[1]) {
2930                 case COMEDI_OUTPUT:
2931                         data[2] = 1 + board->ao_fifo_depth * sizeof(short);
2932                         if (devpriv->mite)
2933                                 data[2] += devpriv->mite->fifo_size;
2934                         break;
2935                 case COMEDI_INPUT:
2936                         data[2] = 0;
2937                         break;
2938                 default:
2939                         return -EINVAL;
2940                         break;
2941                 }
2942                 return 0;
2943         default:
2944                 break;
2945         }
2946
2947         return -EINVAL;
2948 }
2949
2950 static int ni_ao_inttrig(struct comedi_device *dev,
2951                          struct comedi_subdevice *s,
2952                          unsigned int trig_num)
2953 {
2954         const struct ni_board_struct *board __maybe_unused = comedi_board(dev);
2955         struct ni_private *devpriv = dev->private;
2956         struct comedi_cmd *cmd = &s->async->cmd;
2957         int ret;
2958         int interrupt_b_bits;
2959         int i;
2960         static const int timeout = 1000;
2961
2962         if (trig_num != cmd->start_arg)
2963                 return -EINVAL;
2964
2965         /* Null trig at beginning prevent ao start trigger from executing more than
2966            once per command (and doing things like trying to allocate the ao dma channel
2967            multiple times) */
2968         s->async->inttrig = NULL;
2969
2970         ni_set_bits(dev, Interrupt_B_Enable_Register,
2971                     AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
2972         interrupt_b_bits = AO_Error_Interrupt_Enable;
2973 #ifdef PCIDMA
2974         devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
2975         if (board->reg_type & ni_reg_6xxx_mask)
2976                 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
2977         ret = ni_ao_setup_MITE_dma(dev);
2978         if (ret)
2979                 return ret;
2980         ret = ni_ao_wait_for_dma_load(dev);
2981         if (ret < 0)
2982                 return ret;
2983 #else
2984         ret = ni_ao_prep_fifo(dev, s);
2985         if (ret == 0)
2986                 return -EPIPE;
2987
2988         interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
2989 #endif
2990
2991         devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
2992                             AO_Mode_3_Register);
2993         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
2994         /* wait for DACs to be loaded */
2995         for (i = 0; i < timeout; i++) {
2996                 udelay(1);
2997                 if ((devpriv->stc_readw(dev,
2998                                         Joint_Status_2_Register) &
2999                      AO_TMRDACWRs_In_Progress_St) == 0)
3000                         break;
3001         }
3002         if (i == timeout) {
3003                 comedi_error(dev,
3004                              "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3005                 return -EIO;
3006         }
3007         /*  stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3008         devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3009                             Interrupt_B_Ack_Register);
3010
3011         ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3012
3013         devpriv->stc_writew(dev,
3014                             devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3015                             | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3016                             AO_Command_1_Register);
3017
3018         devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3019                             AO_Command_2_Register);
3020
3021         return 0;
3022 }
3023
3024 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3025 {
3026         const struct ni_board_struct *board = comedi_board(dev);
3027         struct ni_private *devpriv = dev->private;
3028         const struct comedi_cmd *cmd = &s->async->cmd;
3029         int bits;
3030         int i;
3031         unsigned trigvar;
3032
3033         if (dev->irq == 0) {
3034                 comedi_error(dev, "cannot run command without an irq");
3035                 return -EIO;
3036         }
3037
3038         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3039
3040         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3041
3042         if (board->reg_type & ni_reg_6xxx_mask) {
3043                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3044
3045                 bits = 0;
3046                 for (i = 0; i < cmd->chanlist_len; i++) {
3047                         int chan;
3048
3049                         chan = CR_CHAN(cmd->chanlist[i]);
3050                         bits |= 1 << chan;
3051                         ao_win_out(chan, AO_Waveform_Generation_611x);
3052                 }
3053                 ao_win_out(bits, AO_Timed_611x);
3054         }
3055
3056         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3057
3058         if (cmd->stop_src == TRIG_NONE) {
3059                 devpriv->ao_mode1 |= AO_Continuous;
3060                 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3061         } else {
3062                 devpriv->ao_mode1 &= ~AO_Continuous;
3063                 devpriv->ao_mode1 |= AO_Trigger_Once;
3064         }
3065         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3066         switch (cmd->start_src) {
3067         case TRIG_INT:
3068         case TRIG_NOW:
3069                 devpriv->ao_trigger_select &=
3070                     ~(AO_START1_Polarity | AO_START1_Select(-1));
3071                 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3072                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3073                                     AO_Trigger_Select_Register);
3074                 break;
3075         case TRIG_EXT:
3076                 devpriv->ao_trigger_select =
3077                     AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3078                 if (cmd->start_arg & CR_INVERT)
3079                         devpriv->ao_trigger_select |= AO_START1_Polarity;       /*  0=active high, 1=active low. see daq-stc 3-24 (p186) */
3080                 if (cmd->start_arg & CR_EDGE)
3081                         devpriv->ao_trigger_select |= AO_START1_Edge;   /*  0=edge detection disabled, 1=enabled */
3082                 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3083                                     AO_Trigger_Select_Register);
3084                 break;
3085         default:
3086                 BUG();
3087                 break;
3088         }
3089         devpriv->ao_mode3 &= ~AO_Trigger_Length;
3090         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3091
3092         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3093         devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3094         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3095         if (cmd->stop_src == TRIG_NONE)
3096                 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3097         else
3098                 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3099         devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3100         devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3101         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3102         switch (cmd->stop_src) {
3103         case TRIG_COUNT:
3104                 if (board->reg_type & ni_reg_m_series_mask) {
3105                         /*  this is how the NI example code does it for m-series boards, verified correct with 6259 */
3106                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3107                                             AO_UC_Load_A_Register);
3108                         devpriv->stc_writew(dev, AO_UC_Load,
3109                                             AO_Command_1_Register);
3110                 } else {
3111                         devpriv->stc_writel(dev, cmd->stop_arg,
3112                                             AO_UC_Load_A_Register);
3113                         devpriv->stc_writew(dev, AO_UC_Load,
3114                                             AO_Command_1_Register);
3115                         devpriv->stc_writel(dev, cmd->stop_arg - 1,
3116                                             AO_UC_Load_A_Register);
3117                 }
3118                 break;
3119         case TRIG_NONE:
3120                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3121                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3122                 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3123                 break;
3124         default:
3125                 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3126                 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3127                 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3128         }
3129
3130         devpriv->ao_mode1 &=
3131             ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3132               AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3133         switch (cmd->scan_begin_src) {
3134         case TRIG_TIMER:
3135                 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3136                 trigvar =
3137                     ni_ns_to_timer(dev, cmd->scan_begin_arg,
3138                                    TRIG_ROUND_NEAREST);
3139                 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3140                 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3141                 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3142                 break;
3143         case TRIG_EXT:
3144                 devpriv->ao_mode1 |=
3145                     AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3146                 if (cmd->scan_begin_arg & CR_INVERT)
3147                         devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3148                 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3149                 break;
3150         default:
3151                 BUG();
3152                 break;
3153         }
3154         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3155         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3156         devpriv->ao_mode2 &=
3157             ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3158         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3159
3160         if (cmd->scan_end_arg > 1) {
3161                 devpriv->ao_mode1 |= AO_Multiple_Channels;
3162                 devpriv->stc_writew(dev,
3163                                     AO_Number_Of_Channels(cmd->scan_end_arg -
3164                                                           1) |
3165                                     AO_UPDATE_Output_Select
3166                                     (AO_Update_Output_High_Z),
3167                                     AO_Output_Control_Register);
3168         } else {
3169                 unsigned bits;
3170                 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3171                 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3172                 if (board->reg_type &
3173                     (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3174                         bits |= AO_Number_Of_Channels(0);
3175                 } else {
3176                         bits |=
3177                             AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3178                 }
3179                 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3180         }
3181         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3182
3183         devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3184                             AO_Command_1_Register);
3185
3186         devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3187         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3188
3189         devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3190 #ifdef PCIDMA
3191         devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3192 #else
3193         devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3194 #endif
3195         devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3196         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3197
3198         bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3199             AO_TMRDACWR_Pulse_Width;
3200         if (board->ao_fifo_depth)
3201                 bits |= AO_FIFO_Enable;
3202         else
3203                 bits |= AO_DMA_PIO_Control;
3204 #if 0
3205         /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3206            verified with bus analyzer. */
3207         if (board->reg_type & ni_reg_m_series_mask)
3208                 bits |= AO_Number_Of_DAC_Packages;
3209 #endif
3210         devpriv->stc_writew(dev, bits, AO_Personal_Register);
3211         /*  enable sending of ao dma requests */
3212         devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3213
3214         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3215
3216         if (cmd->stop_src == TRIG_COUNT) {
3217                 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3218                                     Interrupt_B_Ack_Register);
3219                 ni_set_bits(dev, Interrupt_B_Enable_Register,
3220                             AO_BC_TC_Interrupt_Enable, 1);
3221         }
3222
3223         s->async->inttrig = ni_ao_inttrig;
3224
3225         return 0;
3226 }
3227
3228 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3229                          struct comedi_cmd *cmd)
3230 {
3231         const struct ni_board_struct *board = comedi_board(dev);
3232         struct ni_private *devpriv = dev->private;
3233         int err = 0;
3234         unsigned int tmp;
3235
3236         /* Step 1 : check if triggers are trivially valid */
3237
3238         if ((cmd->flags & CMDF_WRITE) == 0)
3239                 cmd->flags |= CMDF_WRITE;
3240
3241         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3242         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3243                                         TRIG_TIMER | TRIG_EXT);
3244         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3245         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3246         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3247
3248         if (err)
3249                 return 1;
3250
3251         /* Step 2a : make sure trigger sources are unique */
3252
3253         err |= cfc_check_trigger_is_unique(cmd->start_src);
3254         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3255         err |= cfc_check_trigger_is_unique(cmd->stop_src);
3256
3257         /* Step 2b : and mutually compatible */
3258
3259         if (err)
3260                 return 2;
3261
3262         /* Step 3: check if arguments are trivially valid */
3263
3264         switch (cmd->start_src) {
3265         case TRIG_INT:
3266                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3267                 break;
3268         case TRIG_EXT:
3269                 tmp = CR_CHAN(cmd->start_arg);
3270
3271                 if (tmp > 18)
3272                         tmp = 18;
3273                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3274                 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3275                 break;
3276         }
3277
3278         if (cmd->scan_begin_src == TRIG_TIMER) {
3279                 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3280                                                  board->ao_speed);
3281                 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3282                                                  devpriv->clock_ns * 0xffffff);
3283         }
3284
3285         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3286         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3287
3288         if (cmd->stop_src == TRIG_COUNT)
3289                 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3290         else    /* TRIG_NONE */
3291                 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3292
3293         if (err)
3294                 return 3;
3295
3296         /* step 4: fix up any arguments */
3297         if (cmd->scan_begin_src == TRIG_TIMER) {
3298                 tmp = cmd->scan_begin_arg;
3299                 cmd->scan_begin_arg =
3300                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3301                                                        cmd->scan_begin_arg,
3302                                                        cmd->
3303                                                        flags &
3304                                                        TRIG_ROUND_MASK));
3305                 if (tmp != cmd->scan_begin_arg)
3306                         err++;
3307         }
3308         if (err)
3309                 return 4;
3310
3311         return 0;
3312 }
3313
3314 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3315 {
3316         const struct ni_board_struct *board = comedi_board(dev);
3317         struct ni_private *devpriv = dev->private;
3318
3319         /* devpriv->ao0p=0x0000; */
3320         /* ni_writew(devpriv->ao0p,AO_Configuration); */
3321
3322         /* devpriv->ao1p=AO_Channel(1); */
3323         /* ni_writew(devpriv->ao1p,AO_Configuration); */
3324
3325         ni_release_ao_mite_channel(dev);
3326
3327         devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3328         devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3329         ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3330         devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3331         devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3332         devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3333                             AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3334         devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3335         devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3336         devpriv->ao_cmd1 = 0;
3337         devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3338         devpriv->ao_cmd2 = 0;
3339         devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3340         devpriv->ao_mode1 = 0;
3341         devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3342         devpriv->ao_mode2 = 0;
3343         devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3344         if (board->reg_type & ni_reg_m_series_mask)
3345                 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3346         else
3347                 devpriv->ao_mode3 = 0;
3348         devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3349         devpriv->ao_trigger_select = 0;
3350         devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3351                             AO_Trigger_Select_Register);
3352         if (board->reg_type & ni_reg_6xxx_mask) {
3353                 unsigned immediate_bits = 0;
3354                 unsigned i;
3355                 for (i = 0; i < s->n_chan; ++i)
3356                         immediate_bits |= 1 << i;
3357                 ao_win_out(immediate_bits, AO_Immediate_671x);
3358                 ao_win_out(CLEAR_WG, AO_Misc_611x);
3359         }
3360         devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3361
3362         return 0;
3363 }
3364
3365 /* digital io */
3366
3367 static int ni_dio_insn_config(struct comedi_device *dev,
3368                               struct comedi_subdevice *s,
3369                               struct comedi_insn *insn,
3370                               unsigned int *data)
3371 {
3372         struct ni_private *devpriv = dev->private;
3373         int ret;
3374
3375         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3376         if (ret)
3377                 return ret;
3378
3379         devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3380         devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3381         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3382
3383         return insn->n;
3384 }
3385
3386 static int ni_dio_insn_bits(struct comedi_device *dev,
3387                             struct comedi_subdevice *s,
3388                             struct comedi_insn *insn,
3389                             unsigned int *data)
3390 {
3391         struct ni_private *devpriv = dev->private;
3392
3393         /* Make sure we're not using the serial part of the dio */
3394         if ((data[0] & (DIO_SDIN | DIO_SDOUT)) && devpriv->serial_interval_ns)
3395                 return -EBUSY;
3396
3397         if (comedi_dio_update_state(s, data)) {
3398                 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3399                 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3400                 devpriv->stc_writew(dev, devpriv->dio_output,
3401                                     DIO_Output_Register);
3402         }
3403
3404         data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3405
3406         return insn->n;
3407 }
3408
3409 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3410                                        struct comedi_subdevice *s,
3411                                        struct comedi_insn *insn,
3412                                        unsigned int *data)
3413 {
3414         struct ni_private *devpriv __maybe_unused = dev->private;
3415         int ret;
3416
3417         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3418         if (ret)
3419                 return ret;
3420
3421         ni_writel(s->io_bits, M_Offset_DIO_Direction);
3422
3423         return insn->n;
3424 }
3425
3426 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3427                                      struct comedi_subdevice *s,
3428                                      struct comedi_insn *insn,
3429                                      unsigned int *data)
3430 {
3431         struct ni_private *devpriv __maybe_unused = dev->private;
3432
3433         if (comedi_dio_update_state(s, data))
3434                 ni_writel(s->state, M_Offset_Static_Digital_Output);
3435
3436         data[1] = ni_readl(M_Offset_Static_Digital_Input);
3437
3438         return insn->n;
3439 }
3440
3441 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3442                                   struct comedi_subdevice *s,
3443                                   struct comedi_cmd *cmd)
3444 {
3445         int i;
3446
3447         for (i = 0; i < cmd->chanlist_len; ++i) {
3448                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3449
3450                 if (chan != i)
3451                         return -EINVAL;
3452         }
3453
3454         return 0;
3455 }
3456
3457 static int ni_cdio_cmdtest(struct comedi_device *dev,
3458                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3459 {
3460         int err = 0;
3461         int tmp;
3462
3463         /* Step 1 : check if triggers are trivially valid */
3464
3465         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3466         err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3467         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3468         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3469         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3470
3471         if (err)
3472                 return 1;
3473
3474         /* Step 2a : make sure trigger sources are unique */
3475         /* Step 2b : and mutually compatible */
3476
3477         if (err)
3478                 return 2;
3479
3480         /* Step 3: check if arguments are trivially valid */
3481
3482         err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3483
3484         tmp = cmd->scan_begin_arg;
3485         tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3486         if (tmp != cmd->scan_begin_arg)
3487                 err |= -EINVAL;
3488
3489         err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3490         err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3491         err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3492
3493         if (err)
3494                 return 3;
3495
3496         /* step 4: fix up any arguments */
3497
3498         if (err)
3499                 return 4;
3500
3501         /* Step 5: check channel list if it exists */
3502         if (cmd->chanlist && cmd->chanlist_len > 0)
3503                 err |= ni_cdio_check_chanlist(dev, s, cmd);
3504
3505         if (err)
3506                 return 5;
3507
3508         return 0;
3509 }
3510
3511 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3512 {
3513         struct ni_private *devpriv __maybe_unused = dev->private;
3514         const struct comedi_cmd *cmd = &s->async->cmd;
3515         unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3516         int retval;
3517
3518         ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3519         switch (cmd->scan_begin_src) {
3520         case TRIG_EXT:
3521                 cdo_mode_bits |=
3522                     CR_CHAN(cmd->scan_begin_arg) &
3523                     CDO_Sample_Source_Select_Mask;
3524                 break;
3525         default:
3526                 BUG();
3527                 break;
3528         }
3529         if (cmd->scan_begin_arg & CR_INVERT)
3530                 cdo_mode_bits |= CDO_Polarity_Bit;
3531         ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3532         if (s->io_bits) {
3533                 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3534                 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3535                 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3536         } else {
3537                 comedi_error(dev,
3538                              "attempted to run digital output command with no lines configured as outputs");
3539                 return -EIO;
3540         }
3541         retval = ni_request_cdo_mite_channel(dev);
3542         if (retval < 0)
3543                 return retval;
3544
3545         s->async->inttrig = ni_cdo_inttrig;
3546
3547         return 0;
3548 }
3549
3550 static int ni_cdo_inttrig(struct comedi_device *dev,
3551                           struct comedi_subdevice *s,
3552                           unsigned int trig_num)
3553 {
3554 #ifdef PCIDMA
3555         struct ni_private *devpriv = dev->private;
3556         unsigned long flags;
3557 #endif
3558         struct comedi_cmd *cmd = &s->async->cmd;
3559         int retval = 0;
3560         unsigned i;
3561         const unsigned timeout = 1000;
3562
3563         if (trig_num != cmd->start_arg)
3564                 return -EINVAL;
3565
3566         s->async->inttrig = NULL;
3567
3568         /* read alloc the entire buffer */
3569         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3570
3571 #ifdef PCIDMA
3572         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3573         if (devpriv->cdo_mite_chan) {
3574                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3575                 mite_dma_arm(devpriv->cdo_mite_chan);
3576         } else {
3577                 comedi_error(dev, "BUG: no cdo mite channel?");
3578                 retval = -EIO;
3579         }
3580         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3581         if (retval < 0)
3582                 return retval;
3583 #endif
3584 /*
3585 * XXX not sure what interrupt C group does
3586 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3587 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3588 */
3589         for (i = 0; i < timeout; ++i) {
3590                 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3591                         break;
3592                 udelay(10);
3593         }
3594         if (i == timeout) {
3595                 comedi_error(dev, "dma failed to fill cdo fifo!");
3596                 ni_cdio_cancel(dev, s);
3597                 return -EIO;
3598         }
3599         ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3600                   CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3601                   M_Offset_CDIO_Command);
3602         return retval;
3603 }
3604
3605 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3606 {
3607         struct ni_private *devpriv __maybe_unused = dev->private;
3608
3609         ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3610                   CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3611                   CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3612                   M_Offset_CDIO_Command);
3613 /*
3614 * XXX not sure what interrupt C group does ni_writeb(0,
3615 * M_Offset_Interrupt_C_Enable);
3616 */
3617         ni_writel(0, M_Offset_CDO_Mask_Enable);
3618         ni_release_cdo_mite_channel(dev);
3619         return 0;
3620 }
3621
3622 static void handle_cdio_interrupt(struct comedi_device *dev)
3623 {
3624         const struct ni_board_struct *board = comedi_board(dev);
3625         struct ni_private *devpriv __maybe_unused = dev->private;
3626         unsigned cdio_status;
3627         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3628 #ifdef PCIDMA
3629         unsigned long flags;
3630 #endif
3631
3632         if ((board->reg_type & ni_reg_m_series_mask) == 0)
3633                 return;
3634 #ifdef PCIDMA
3635         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3636         if (devpriv->cdo_mite_chan) {
3637                 unsigned cdo_mite_status =
3638                     mite_get_status(devpriv->cdo_mite_chan);
3639                 if (cdo_mite_status & CHSR_LINKC) {
3640                         writel(CHOR_CLRLC,
3641                                devpriv->mite->mite_io_addr +
3642                                MITE_CHOR(devpriv->cdo_mite_chan->channel));
3643                 }
3644                 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
3645         }
3646         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3647 #endif
3648
3649         cdio_status = ni_readl(M_Offset_CDIO_Status);
3650         if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3651                 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3652                 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command);      /*  XXX just guessing this is needed and does something useful */
3653                 s->async->events |= COMEDI_CB_OVERFLOW;
3654         }
3655         if (cdio_status & CDO_FIFO_Empty_Bit) {
3656                 /* printk("cdio fifo empty\n"); */
3657                 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3658                           M_Offset_CDIO_Command);
3659                 /* s->async->events |= COMEDI_CB_EOA; */
3660         }
3661         cfc_handle_events(dev, s);
3662 }
3663
3664 static int ni_serial_insn_config(struct comedi_device *dev,
3665                                  struct comedi_subdevice *s,
3666                                  struct comedi_insn *insn, unsigned int *data)
3667 {
3668         struct ni_private *devpriv = dev->private;
3669         int err = insn->n;
3670         unsigned char byte_out, byte_in = 0;
3671
3672         if (insn->n != 2)
3673                 return -EINVAL;
3674
3675         switch (data[0]) {
3676         case INSN_CONFIG_SERIAL_CLOCK:
3677                 devpriv->serial_hw_mode = 1;
3678                 devpriv->dio_control |= DIO_HW_Serial_Enable;
3679
3680                 if (data[1] == SERIAL_DISABLED) {
3681                         devpriv->serial_hw_mode = 0;
3682                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3683                                                   DIO_Software_Serial_Control);
3684                         data[1] = SERIAL_DISABLED;
3685                         devpriv->serial_interval_ns = data[1];
3686                 } else if (data[1] <= SERIAL_600NS) {
3687                         /* Warning: this clock speed is too fast to reliably
3688                            control SCXI. */
3689                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3690                         devpriv->clock_and_fout |= Slow_Internal_Timebase;
3691                         devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3692                         data[1] = SERIAL_600NS;
3693                         devpriv->serial_interval_ns = data[1];
3694                 } else if (data[1] <= SERIAL_1_2US) {
3695                         devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3696                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3697                             DIO_Serial_Out_Divide_By_2;
3698                         data[1] = SERIAL_1_2US;
3699                         devpriv->serial_interval_ns = data[1];
3700                 } else if (data[1] <= SERIAL_10US) {
3701                         devpriv->dio_control |= DIO_HW_Serial_Timebase;
3702                         devpriv->clock_and_fout |= Slow_Internal_Timebase |
3703                             DIO_Serial_Out_Divide_By_2;
3704                         /* Note: DIO_Serial_Out_Divide_By_2 only affects
3705                            600ns/1.2us. If you turn divide_by_2 off with the
3706                            slow clock, you will still get 10us, except then
3707                            all your delays are wrong. */
3708                         data[1] = SERIAL_10US;
3709                         devpriv->serial_interval_ns = data[1];
3710                 } else {
3711                         devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3712                                                   DIO_Software_Serial_Control);
3713                         devpriv->serial_hw_mode = 0;
3714                         data[1] = (data[1] / 1000) * 1000;
3715                         devpriv->serial_interval_ns = data[1];
3716                 }
3717
3718                 devpriv->stc_writew(dev, devpriv->dio_control,
3719                                     DIO_Control_Register);
3720                 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3721                                     Clock_and_FOUT_Register);
3722                 return 1;
3723
3724                 break;
3725
3726         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3727
3728                 if (devpriv->serial_interval_ns == 0)
3729                         return -EINVAL;
3730
3731                 byte_out = data[1] & 0xFF;
3732
3733                 if (devpriv->serial_hw_mode) {
3734                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3735                                                       &byte_in);
3736                 } else if (devpriv->serial_interval_ns > 0) {
3737                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3738                                                       &byte_in);
3739                 } else {
3740                         printk("ni_serial_insn_config: serial disabled!\n");
3741                         return -EINVAL;
3742                 }
3743                 if (err < 0)
3744                         return err;
3745                 data[1] = byte_in & 0xFF;
3746                 return insn->n;
3747
3748                 break;
3749         default:
3750                 return -EINVAL;
3751         }
3752
3753 }
3754
3755 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3756                                    struct comedi_subdevice *s,
3757                                    unsigned char data_out,
3758                                    unsigned char *data_in)
3759 {
3760         struct ni_private *devpriv = dev->private;
3761         unsigned int status1;
3762         int err = 0, count = 20;
3763
3764         devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3765         devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3766         devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3767
3768         status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3769         if (status1 & DIO_Serial_IO_In_Progress_St) {
3770                 err = -EBUSY;
3771                 goto Error;
3772         }
3773
3774         devpriv->dio_control |= DIO_HW_Serial_Start;
3775         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3776         devpriv->dio_control &= ~DIO_HW_Serial_Start;
3777
3778         /* Wait until STC says we're done, but don't loop infinitely. */
3779         while ((status1 =
3780                 devpriv->stc_readw(dev,
3781                                    Joint_Status_1_Register)) &
3782                DIO_Serial_IO_In_Progress_St) {
3783                 /* Delay one bit per loop */
3784                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3785                 if (--count < 0) {
3786                         printk
3787                             ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3788                         err = -ETIME;
3789                         goto Error;
3790                 }
3791         }
3792
3793         /* Delay for last bit. This delay is absolutely necessary, because
3794            DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3795         udelay((devpriv->serial_interval_ns + 999) / 1000);
3796
3797         if (data_in != NULL)
3798                 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3799
3800 Error:
3801         devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3802
3803         return err;
3804 }
3805
3806 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3807                                    struct comedi_subdevice *s,
3808                                    unsigned char data_out,
3809                                    unsigned char *data_in)
3810 {
3811         struct ni_private *devpriv = dev->private;
3812         unsigned char mask, input = 0;
3813
3814         /* Wait for one bit before transfer */
3815         udelay((devpriv->serial_interval_ns + 999) / 1000);
3816
3817         for (mask = 0x80; mask; mask >>= 1) {
3818                 /* Output current bit; note that we cannot touch s->state
3819                    because it is a per-subdevice field, and serial is
3820                    a separate subdevice from DIO. */
3821                 devpriv->dio_output &= ~DIO_SDOUT;
3822                 if (data_out & mask)
3823                         devpriv->dio_output |= DIO_SDOUT;
3824                 devpriv->stc_writew(dev, devpriv->dio_output,
3825                                     DIO_Output_Register);
3826
3827                 /* Assert SDCLK (active low, inverted), wait for half of
3828                    the delay, deassert SDCLK, and wait for the other half. */
3829                 devpriv->dio_control |= DIO_Software_Serial_Control;
3830                 devpriv->stc_writew(dev, devpriv->dio_control,
3831                                     DIO_Control_Register);
3832
3833                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3834
3835                 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3836                 devpriv->stc_writew(dev, devpriv->dio_control,
3837                                     DIO_Control_Register);
3838
3839                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3840
3841                 /* Input current bit */
3842                 if (devpriv->stc_readw(dev,
3843                                        DIO_Parallel_Input_Register) & DIO_SDIN) {
3844                         /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3845                         input |= mask;
3846                 }
3847         }
3848
3849         if (data_in)
3850                 *data_in = input;
3851
3852         return 0;
3853 }
3854
3855 static void mio_common_detach(struct comedi_device *dev)
3856 {
3857         struct ni_private *devpriv = dev->private;
3858
3859         if (devpriv) {
3860                 if (devpriv->counter_dev)
3861                         ni_gpct_device_destroy(devpriv->counter_dev);
3862         }
3863 }
3864
3865 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3866 {
3867         int i;
3868
3869         for (i = 0; i < s->n_chan; i++) {
3870                 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
3871                                AO_Configuration_2_67xx);
3872         }
3873         ao_win_out(0x0, AO_Later_Single_Point_Updates);
3874 }
3875
3876 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
3877 {
3878         unsigned stc_register;
3879         switch (reg) {
3880         case NITIO_G0_AUTO_INC:
3881                 stc_register = G_Autoincrement_Register(0);
3882                 break;
3883         case NITIO_G1_AUTO_INC:
3884                 stc_register = G_Autoincrement_Register(1);
3885                 break;
3886         case NITIO_G0_CMD:
3887                 stc_register = G_Command_Register(0);
3888                 break;
3889         case NITIO_G1_CMD:
3890                 stc_register = G_Command_Register(1);
3891                 break;
3892         case NITIO_G0_HW_SAVE:
3893                 stc_register = G_HW_Save_Register(0);
3894                 break;
3895         case NITIO_G1_HW_SAVE:
3896                 stc_register = G_HW_Save_Register(1);
3897                 break;
3898         case NITIO_G0_SW_SAVE:
3899                 stc_register = G_Save_Register(0);
3900                 break;
3901         case NITIO_G1_SW_SAVE:
3902                 stc_register = G_Save_Register(1);
3903                 break;
3904         case NITIO_G0_MODE:
3905                 stc_register = G_Mode_Register(0);
3906                 break;
3907         case NITIO_G1_MODE:
3908                 stc_register = G_Mode_Register(1);
3909                 break;
3910         case NITIO_G0_LOADA:
3911                 stc_register = G_Load_A_Register(0);
3912                 break;
3913         case NITIO_G1_LOADA:
3914                 stc_register = G_Load_A_Register(1);
3915                 break;
3916         case NITIO_G0_LOADB:
3917                 stc_register = G_Load_B_Register(0);
3918                 break;
3919         case NITIO_G1_LOADB:
3920                 stc_register = G_Load_B_Register(1);
3921                 break;
3922         case NITIO_G0_INPUT_SEL:
3923                 stc_register = G_Input_Select_Register(0);
3924                 break;
3925         case NITIO_G1_INPUT_SEL:
3926                 stc_register = G_Input_Select_Register(1);
3927                 break;
3928         case NITIO_G01_STATUS:
3929                 stc_register = G_Status_Register;
3930                 break;
3931         case NITIO_G01_RESET:
3932                 stc_register = Joint_Reset_Register;
3933                 break;
3934         case NITIO_G01_STATUS1:
3935                 stc_register = Joint_Status_1_Register;
3936                 break;
3937         case NITIO_G01_STATUS2:
3938                 stc_register = Joint_Status_2_Register;
3939                 break;
3940         case NITIO_G0_INT_ACK:
3941                 stc_register = Interrupt_A_Ack_Register;
3942                 break;
3943         case NITIO_G1_INT_ACK:
3944                 stc_register = Interrupt_B_Ack_Register;
3945                 break;
3946         case NITIO_G0_STATUS:
3947                 stc_register = AI_Status_1_Register;
3948                 break;
3949         case NITIO_G1_STATUS:
3950                 stc_register = AO_Status_1_Register;
3951                 break;
3952         case NITIO_G0_INT_ENA:
3953                 stc_register = Interrupt_A_Enable_Register;
3954                 break;
3955         case NITIO_G1_INT_ENA:
3956                 stc_register = Interrupt_B_Enable_Register;
3957                 break;
3958         default:
3959                 printk("%s: unhandled register 0x%x in switch.\n",
3960                        __func__, reg);
3961                 BUG();
3962                 return 0;
3963                 break;
3964         }
3965         return stc_register;
3966 }
3967
3968 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
3969                                    enum ni_gpct_register reg)
3970 {
3971         struct comedi_device *dev = counter->counter_dev->dev;
3972         struct ni_private *devpriv = dev->private;
3973         unsigned stc_register;
3974         /* bits in the join reset register which are relevant to counters */
3975         static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
3976         static const unsigned gpct_interrupt_a_enable_mask =
3977             G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
3978         static const unsigned gpct_interrupt_b_enable_mask =
3979             G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
3980
3981         switch (reg) {
3982                 /* m-series-only registers */
3983         case NITIO_G0_CNT_MODE:
3984                 ni_writew(bits, M_Offset_G0_Counting_Mode);
3985                 break;
3986         case NITIO_G1_CNT_MODE:
3987                 ni_writew(bits, M_Offset_G1_Counting_Mode);
3988                 break;
3989         case NITIO_G0_GATE2:
3990                 ni_writew(bits, M_Offset_G0_Second_Gate);
3991                 break;
3992         case NITIO_G1_GATE2:
3993                 ni_writew(bits, M_Offset_G1_Second_Gate);
3994                 break;
3995         case NITIO_G0_DMA_CFG:
3996                 ni_writew(bits, M_Offset_G0_DMA_Config);
3997                 break;
3998         case NITIO_G1_DMA_CFG:
3999                 ni_writew(bits, M_Offset_G1_DMA_Config);
4000                 break;
4001         case NITIO_G0_ABZ:
4002                 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4003                 break;
4004         case NITIO_G1_ABZ:
4005                 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4006                 break;
4007
4008                 /* 32 bit registers */
4009         case NITIO_G0_LOADA:
4010         case NITIO_G1_LOADA:
4011         case NITIO_G0_LOADB:
4012         case NITIO_G1_LOADB:
4013                 stc_register = ni_gpct_to_stc_register(reg);
4014                 devpriv->stc_writel(dev, bits, stc_register);
4015                 break;
4016
4017                 /* 16 bit registers */
4018         case NITIO_G0_INT_ENA:
4019                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4020                 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4021                                 gpct_interrupt_a_enable_mask, bits);
4022                 break;
4023         case NITIO_G1_INT_ENA:
4024                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4025                 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4026                                 gpct_interrupt_b_enable_mask, bits);
4027                 break;
4028         case NITIO_G01_RESET:
4029                 BUG_ON(bits & ~gpct_joint_reset_mask);
4030                 /* fall-through */
4031         default:
4032                 stc_register = ni_gpct_to_stc_register(reg);
4033                 devpriv->stc_writew(dev, bits, stc_register);
4034         }
4035 }
4036
4037 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4038                                       enum ni_gpct_register reg)
4039 {
4040         struct comedi_device *dev = counter->counter_dev->dev;
4041         struct ni_private *devpriv = dev->private;
4042         unsigned stc_register;
4043
4044         switch (reg) {
4045                 /* m-series only registers */
4046         case NITIO_G0_DMA_STATUS:
4047                 return ni_readw(M_Offset_G0_DMA_Status);
4048         case NITIO_G1_DMA_STATUS:
4049                 return ni_readw(M_Offset_G1_DMA_Status);
4050
4051                 /* 32 bit registers */
4052         case NITIO_G0_HW_SAVE:
4053         case NITIO_G1_HW_SAVE:
4054         case NITIO_G0_SW_SAVE:
4055         case NITIO_G1_SW_SAVE:
4056                 stc_register = ni_gpct_to_stc_register(reg);
4057                 return devpriv->stc_readl(dev, stc_register);
4058
4059                 /* 16 bit registers */
4060         default:
4061                 stc_register = ni_gpct_to_stc_register(reg);
4062                 return devpriv->stc_readw(dev, stc_register);
4063                 break;
4064         }
4065         return 0;
4066 }
4067
4068 static int ni_freq_out_insn_read(struct comedi_device *dev,
4069                                  struct comedi_subdevice *s,
4070                                  struct comedi_insn *insn, unsigned int *data)
4071 {
4072         struct ni_private *devpriv = dev->private;
4073
4074         data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4075         return 1;
4076 }
4077
4078 static int ni_freq_out_insn_write(struct comedi_device *dev,
4079                                   struct comedi_subdevice *s,
4080                                   struct comedi_insn *insn, unsigned int *data)
4081 {
4082         struct ni_private *devpriv = dev->private;
4083
4084         devpriv->clock_and_fout &= ~FOUT_Enable;
4085         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4086                             Clock_and_FOUT_Register);
4087         devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4088         devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4089         devpriv->clock_and_fout |= FOUT_Enable;
4090         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4091                             Clock_and_FOUT_Register);
4092         return insn->n;
4093 }
4094
4095 static int ni_set_freq_out_clock(struct comedi_device *dev,
4096                                  unsigned int clock_source)
4097 {
4098         struct ni_private *devpriv = dev->private;
4099
4100         switch (clock_source) {
4101         case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4102                 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4103                 break;
4104         case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4105                 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4106                 break;
4107         default:
4108                 return -EINVAL;
4109         }
4110         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4111                             Clock_and_FOUT_Register);
4112         return 3;
4113 }
4114
4115 static void ni_get_freq_out_clock(struct comedi_device *dev,
4116                                   unsigned int *clock_source,
4117                                   unsigned int *clock_period_ns)
4118 {
4119         struct ni_private *devpriv = dev->private;
4120
4121         if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4122                 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4123                 *clock_period_ns = TIMEBASE_2_NS;
4124         } else {
4125                 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4126                 *clock_period_ns = TIMEBASE_1_NS * 2;
4127         }
4128 }
4129
4130 static int ni_freq_out_insn_config(struct comedi_device *dev,
4131                                    struct comedi_subdevice *s,
4132                                    struct comedi_insn *insn, unsigned int *data)
4133 {
4134         switch (data[0]) {
4135         case INSN_CONFIG_SET_CLOCK_SRC:
4136                 return ni_set_freq_out_clock(dev, data[1]);
4137                 break;
4138         case INSN_CONFIG_GET_CLOCK_SRC:
4139                 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4140                 return 3;
4141         default:
4142                 break;
4143         }
4144         return -EINVAL;
4145 }
4146
4147 static int ni_alloc_private(struct comedi_device *dev)
4148 {
4149         struct ni_private *devpriv;
4150
4151         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
4152         if (!devpriv)
4153                 return -ENOMEM;
4154
4155         spin_lock_init(&devpriv->window_lock);
4156         spin_lock_init(&devpriv->soft_reg_copy_lock);
4157         spin_lock_init(&devpriv->mite_channel_lock);
4158
4159         return 0;
4160 };
4161
4162 static int ni_E_init(struct comedi_device *dev)
4163 {
4164         const struct ni_board_struct *board = comedi_board(dev);
4165         struct ni_private *devpriv = dev->private;
4166         struct comedi_subdevice *s;
4167         unsigned j;
4168         enum ni_gpct_variant counter_variant;
4169         int ret;
4170
4171         if (board->n_aochan > MAX_N_AO_CHAN) {
4172                 printk("bug! n_aochan > MAX_N_AO_CHAN\n");
4173                 return -EINVAL;
4174         }
4175
4176         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4177         if (ret)
4178                 return ret;
4179
4180         /* analog input subdevice */
4181
4182         s = &dev->subdevices[NI_AI_SUBDEV];
4183         dev->read_subdev = s;
4184         if (board->n_adchan) {
4185                 s->type = COMEDI_SUBD_AI;
4186                 s->subdev_flags =
4187                     SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4188                 if (board->reg_type != ni_reg_611x)
4189                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4190                 if (board->adbits > 16)
4191                         s->subdev_flags |= SDF_LSAMPL;
4192                 if (board->reg_type & ni_reg_m_series_mask)
4193                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4194                 s->n_chan = board->n_adchan;
4195                 s->len_chanlist = 512;
4196                 s->maxdata = (1 << board->adbits) - 1;
4197                 s->range_table = ni_range_lkup[board->gainlkup];
4198                 s->insn_read = &ni_ai_insn_read;
4199                 s->insn_config = &ni_ai_insn_config;
4200                 s->do_cmdtest = &ni_ai_cmdtest;
4201                 s->do_cmd = &ni_ai_cmd;
4202                 s->cancel = &ni_ai_reset;
4203                 s->poll = &ni_ai_poll;
4204                 s->munge = &ni_ai_munge;
4205 #ifdef PCIDMA
4206                 s->async_dma_dir = DMA_FROM_DEVICE;
4207 #endif
4208         } else {
4209                 s->type = COMEDI_SUBD_UNUSED;
4210         }
4211
4212         /* analog output subdevice */
4213
4214         s = &dev->subdevices[NI_AO_SUBDEV];
4215         if (board->n_aochan) {
4216                 s->type = COMEDI_SUBD_AO;
4217                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4218                 if (board->reg_type & ni_reg_m_series_mask)
4219                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
4220                 s->n_chan = board->n_aochan;
4221                 s->maxdata = (1 << board->aobits) - 1;
4222                 s->range_table = board->ao_range_table;
4223                 s->insn_read = &ni_ao_insn_read;
4224                 if (board->reg_type & ni_reg_6xxx_mask)
4225                         s->insn_write = &ni_ao_insn_write_671x;
4226                 else
4227                         s->insn_write = &ni_ao_insn_write;
4228                 s->insn_config = &ni_ao_insn_config;
4229 #ifdef PCIDMA
4230                 if (board->n_aochan) {
4231                         s->async_dma_dir = DMA_TO_DEVICE;
4232 #else
4233                 if (board->ao_fifo_depth) {
4234 #endif
4235                         dev->write_subdev = s;
4236                         s->subdev_flags |= SDF_CMD_WRITE;
4237                         s->do_cmd = &ni_ao_cmd;
4238                         s->do_cmdtest = &ni_ao_cmdtest;
4239                         s->len_chanlist = board->n_aochan;
4240                         if ((board->reg_type & ni_reg_m_series_mask) == 0)
4241                                 s->munge = ni_ao_munge;
4242                 }
4243                 s->cancel = &ni_ao_reset;
4244         } else {
4245                 s->type = COMEDI_SUBD_UNUSED;
4246         }
4247         if ((board->reg_type & ni_reg_67xx_mask))
4248                 init_ao_67xx(dev, s);
4249
4250         /* digital i/o subdevice */
4251
4252         s = &dev->subdevices[NI_DIO_SUBDEV];
4253         s->type = COMEDI_SUBD_DIO;
4254         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4255         s->maxdata = 1;
4256         s->io_bits = 0;         /* all bits input */
4257         s->range_table = &range_digital;
4258         s->n_chan = board->num_p0_dio_channels;
4259         if (board->reg_type & ni_reg_m_series_mask) {
4260                 s->subdev_flags |=
4261                     SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */;
4262                 s->insn_bits = &ni_m_series_dio_insn_bits;
4263                 s->insn_config = &ni_m_series_dio_insn_config;
4264                 s->do_cmd = &ni_cdio_cmd;
4265                 s->do_cmdtest = &ni_cdio_cmdtest;
4266                 s->cancel = &ni_cdio_cancel;
4267                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4268                 s->len_chanlist = s->n_chan;
4269
4270                 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4271                 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4272         } else {
4273                 s->insn_bits = &ni_dio_insn_bits;
4274                 s->insn_config = &ni_dio_insn_config;
4275                 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4276                 ni_writew(devpriv->dio_control, DIO_Control_Register);
4277         }
4278
4279         /* 8255 device */
4280         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4281         if (board->has_8255) {
4282                 ret = subdev_8255_init(dev, s, ni_8255_callback,
4283                                        (unsigned long)dev);
4284                 if (ret)
4285                         return ret;
4286         } else {
4287                 s->type = COMEDI_SUBD_UNUSED;
4288         }
4289
4290         /* formerly general purpose counter/timer device, but no longer used */
4291         s = &dev->subdevices[NI_UNUSED_SUBDEV];
4292         s->type = COMEDI_SUBD_UNUSED;
4293
4294         /* calibration subdevice -- ai and ao */
4295         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4296         s->type = COMEDI_SUBD_CALIB;
4297         if (board->reg_type & ni_reg_m_series_mask) {
4298                 /*  internal PWM analog output used for AI nonlinearity calibration */
4299                 s->subdev_flags = SDF_INTERNAL;
4300                 s->insn_config = &ni_m_series_pwm_config;
4301                 s->n_chan = 1;
4302                 s->maxdata = 0;
4303                 ni_writel(0x0, M_Offset_Cal_PWM);
4304         } else if (board->reg_type == ni_reg_6143) {
4305                 /*  internal PWM analog output used for AI nonlinearity calibration */
4306                 s->subdev_flags = SDF_INTERNAL;
4307                 s->insn_config = &ni_6143_pwm_config;
4308                 s->n_chan = 1;
4309                 s->maxdata = 0;
4310         } else {
4311                 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4312                 s->insn_read = &ni_calib_insn_read;
4313                 s->insn_write = &ni_calib_insn_write;
4314                 caldac_setup(dev, s);
4315         }
4316
4317         /* EEPROM */
4318         s = &dev->subdevices[NI_EEPROM_SUBDEV];
4319         s->type = COMEDI_SUBD_MEMORY;
4320         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4321         s->maxdata = 0xff;
4322         if (board->reg_type & ni_reg_m_series_mask) {
4323                 s->n_chan = M_SERIES_EEPROM_SIZE;
4324                 s->insn_read = &ni_m_series_eeprom_insn_read;
4325         } else {
4326                 s->n_chan = 512;
4327                 s->insn_read = &ni_eeprom_insn_read;
4328         }
4329
4330         /* PFI */
4331         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4332         s->type = COMEDI_SUBD_DIO;
4333         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4334         if (board->reg_type & ni_reg_m_series_mask) {
4335                 unsigned i;
4336                 s->n_chan = 16;
4337                 ni_writew(s->state, M_Offset_PFI_DO);
4338                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4339                         ni_writew(devpriv->pfi_output_select_reg[i],
4340                                   M_Offset_PFI_Output_Select(i + 1));
4341                 }
4342         } else {
4343                 s->n_chan = 10;
4344         }
4345         s->maxdata = 1;
4346         if (board->reg_type & ni_reg_m_series_mask)
4347                 s->insn_bits = &ni_pfi_insn_bits;
4348         s->insn_config = &ni_pfi_insn_config;
4349         ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4350
4351         /* cs5529 calibration adc */
4352         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4353         if (board->reg_type & ni_reg_67xx_mask) {
4354                 s->type = COMEDI_SUBD_AI;
4355                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4356                 /*  one channel for each analog output channel */
4357                 s->n_chan = board->n_aochan;
4358                 s->maxdata = (1 << 16) - 1;
4359                 s->range_table = &range_unknown;        /* XXX */
4360                 s->insn_read = cs5529_ai_insn_read;
4361                 s->insn_config = NULL;
4362                 init_cs5529(dev);
4363         } else {
4364                 s->type = COMEDI_SUBD_UNUSED;
4365         }
4366
4367         /* Serial */
4368         s = &dev->subdevices[NI_SERIAL_SUBDEV];
4369         s->type = COMEDI_SUBD_SERIAL;
4370         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4371         s->n_chan = 1;
4372         s->maxdata = 0xff;
4373         s->insn_config = ni_serial_insn_config;
4374         devpriv->serial_interval_ns = 0;
4375         devpriv->serial_hw_mode = 0;
4376
4377         /* RTSI */
4378         s = &dev->subdevices[NI_RTSI_SUBDEV];
4379         s->type = COMEDI_SUBD_DIO;
4380         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4381         s->n_chan = 8;
4382         s->maxdata = 1;
4383         s->insn_bits = ni_rtsi_insn_bits;
4384         s->insn_config = ni_rtsi_insn_config;
4385         ni_rtsi_init(dev);
4386
4387         if (board->reg_type & ni_reg_m_series_mask)
4388                 counter_variant = ni_gpct_variant_m_series;
4389         else
4390                 counter_variant = ni_gpct_variant_e_series;
4391         devpriv->counter_dev = ni_gpct_device_construct(dev,
4392                                                         &ni_gpct_write_register,
4393                                                         &ni_gpct_read_register,
4394                                                         counter_variant,
4395                                                         NUM_GPCT);
4396         if (!devpriv->counter_dev)
4397                 return -ENOMEM;
4398
4399         /* General purpose counters */
4400         for (j = 0; j < NUM_GPCT; ++j) {
4401                 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4402                 s->type = COMEDI_SUBD_COUNTER;
4403                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
4404                 s->n_chan = 3;
4405                 if (board->reg_type & ni_reg_m_series_mask)
4406                         s->maxdata = 0xffffffff;
4407                 else
4408                         s->maxdata = 0xffffff;
4409                 s->insn_read = ni_tio_insn_read;
4410                 s->insn_write = ni_tio_insn_read;
4411                 s->insn_config = ni_tio_insn_config;
4412 #ifdef PCIDMA
4413                 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
4414                 s->do_cmd = &ni_gpct_cmd;
4415                 s->len_chanlist = 1;
4416                 s->do_cmdtest = ni_tio_cmdtest;
4417                 s->cancel = &ni_gpct_cancel;
4418                 s->async_dma_dir = DMA_BIDIRECTIONAL;
4419 #endif
4420                 s->private = &devpriv->counter_dev->counters[j];
4421
4422                 devpriv->counter_dev->counters[j].chip_index = 0;
4423                 devpriv->counter_dev->counters[j].counter_index = j;
4424                 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4425         }
4426
4427         /* Frequency output */
4428         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4429         s->type = COMEDI_SUBD_COUNTER;
4430         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4431         s->n_chan = 1;
4432         s->maxdata = 0xf;
4433         s->insn_read = &ni_freq_out_insn_read;
4434         s->insn_write = &ni_freq_out_insn_write;
4435         s->insn_config = &ni_freq_out_insn_config;
4436
4437         /* ai configuration */
4438         s = &dev->subdevices[NI_AI_SUBDEV];
4439         ni_ai_reset(dev, s);
4440         if ((board->reg_type & ni_reg_6xxx_mask) == 0) {
4441                 /*  BEAM is this needed for PCI-6143 ?? */
4442                 devpriv->clock_and_fout =
4443                     Slow_Internal_Time_Divide_By_2 |
4444                     Slow_Internal_Timebase |
4445                     Clock_To_Board_Divide_By_2 |
4446                     Clock_To_Board |
4447                     AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4448         } else {
4449                 devpriv->clock_and_fout =
4450                     Slow_Internal_Time_Divide_By_2 |
4451                     Slow_Internal_Timebase |
4452                     Clock_To_Board_Divide_By_2 | Clock_To_Board;
4453         }
4454         devpriv->stc_writew(dev, devpriv->clock_and_fout,
4455                             Clock_and_FOUT_Register);
4456
4457         /* analog output configuration */
4458         s = &dev->subdevices[NI_AO_SUBDEV];
4459         ni_ao_reset(dev, s);
4460
4461         if (dev->irq) {
4462                 devpriv->stc_writew(dev,
4463                                     (IRQ_POLARITY ? Interrupt_Output_Polarity :
4464                                      0) | (Interrupt_Output_On_3_Pins & 0) |
4465                                     Interrupt_A_Enable | Interrupt_B_Enable |
4466                                     Interrupt_A_Output_Select(interrupt_pin
4467                                                               (dev->irq)) |
4468                                     Interrupt_B_Output_Select(interrupt_pin
4469                                                               (dev->irq)),
4470                                     Interrupt_Control_Register);
4471         }
4472
4473         /* DMA setup */
4474         ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4475         ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4476
4477         if (board->reg_type & ni_reg_6xxx_mask) {
4478                 ni_writeb(0, Magic_611x);
4479         } else if (board->reg_type & ni_reg_m_series_mask) {
4480                 int channel;
4481                 for (channel = 0; channel < board->n_aochan; ++channel) {
4482                         ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4483                         ni_writeb(0x0,
4484                                   M_Offset_AO_Reference_Attenuation(channel));
4485                 }
4486                 ni_writeb(0x0, M_Offset_AO_Calibration);
4487         }
4488
4489         return 0;
4490 }
4491
4492 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4493 {
4494         struct comedi_device *dev = (struct comedi_device *)arg;
4495         struct ni_private *devpriv __maybe_unused = dev->private;
4496
4497         if (dir) {
4498                 ni_writeb(data, Port_A + 2 * port);
4499                 return 0;
4500         } else {
4501                 return ni_readb(Port_A + 2 * port);
4502         }
4503 }
4504
4505 /*
4506         presents the EEPROM as a subdevice
4507 */
4508
4509 static int ni_eeprom_insn_read(struct comedi_device *dev,
4510                                struct comedi_subdevice *s,
4511                                struct comedi_insn *insn, unsigned int *data)
4512 {
4513         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4514
4515         return 1;
4516 }
4517
4518 /*
4519         reads bytes out of eeprom
4520 */
4521
4522 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4523 {
4524         struct ni_private *devpriv __maybe_unused = dev->private;
4525         int bit;
4526         int bitstring;
4527
4528         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4529         ni_writeb(0x04, Serial_Command);
4530         for (bit = 0x8000; bit; bit >>= 1) {
4531                 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4532                           Serial_Command);
4533                 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4534                           Serial_Command);
4535         }
4536         bitstring = 0;
4537         for (bit = 0x80; bit; bit >>= 1) {
4538                 ni_writeb(0x04, Serial_Command);
4539                 ni_writeb(0x05, Serial_Command);
4540                 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4541         }
4542         ni_writeb(0x00, Serial_Command);
4543
4544         return bitstring;
4545 }
4546
4547 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4548                                         struct comedi_subdevice *s,
4549                                         struct comedi_insn *insn,
4550                                         unsigned int *data)
4551 {
4552         struct ni_private *devpriv = dev->private;
4553
4554         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4555
4556         return 1;
4557 }
4558
4559 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4560 {
4561         struct ni_private *devpriv = dev->private;
4562
4563         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4564         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4565         return 3;
4566 }
4567
4568 static int ni_m_series_pwm_config(struct comedi_device *dev,
4569                                   struct comedi_subdevice *s,
4570                                   struct comedi_insn *insn, unsigned int *data)
4571 {
4572         struct ni_private *devpriv = dev->private;
4573         unsigned up_count, down_count;
4574
4575         switch (data[0]) {
4576         case INSN_CONFIG_PWM_OUTPUT:
4577                 switch (data[1]) {
4578                 case TRIG_ROUND_NEAREST:
4579                         up_count =
4580                             (data[2] +
4581                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4582                         break;
4583                 case TRIG_ROUND_DOWN:
4584                         up_count = data[2] / devpriv->clock_ns;
4585                         break;
4586                 case TRIG_ROUND_UP:
4587                         up_count =
4588                             (data[2] + devpriv->clock_ns -
4589                              1) / devpriv->clock_ns;
4590                         break;
4591                 default:
4592                         return -EINVAL;
4593                         break;
4594                 }
4595                 switch (data[3]) {
4596                 case TRIG_ROUND_NEAREST:
4597                         down_count =
4598                             (data[4] +
4599                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4600                         break;
4601                 case TRIG_ROUND_DOWN:
4602                         down_count = data[4] / devpriv->clock_ns;
4603                         break;
4604                 case TRIG_ROUND_UP:
4605                         down_count =
4606                             (data[4] + devpriv->clock_ns -
4607                              1) / devpriv->clock_ns;
4608                         break;
4609                 default:
4610                         return -EINVAL;
4611                         break;
4612                 }
4613                 if (up_count * devpriv->clock_ns != data[2] ||
4614                     down_count * devpriv->clock_ns != data[4]) {
4615                         data[2] = up_count * devpriv->clock_ns;
4616                         data[4] = down_count * devpriv->clock_ns;
4617                         return -EAGAIN;
4618                 }
4619                 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4620                           MSeries_Cal_PWM_Low_Time_Bits(down_count),
4621                           M_Offset_Cal_PWM);
4622                 devpriv->pwm_up_count = up_count;
4623                 devpriv->pwm_down_count = down_count;
4624                 return 5;
4625                 break;
4626         case INSN_CONFIG_GET_PWM_OUTPUT:
4627                 return ni_get_pwm_config(dev, data);
4628                 break;
4629         default:
4630                 return -EINVAL;
4631                 break;
4632         }
4633         return 0;
4634 }
4635
4636 static int ni_6143_pwm_config(struct comedi_device *dev,
4637                               struct comedi_subdevice *s,
4638                               struct comedi_insn *insn, unsigned int *data)
4639 {
4640         struct ni_private *devpriv = dev->private;
4641         unsigned up_count, down_count;
4642
4643         switch (data[0]) {
4644         case INSN_CONFIG_PWM_OUTPUT:
4645                 switch (data[1]) {
4646                 case TRIG_ROUND_NEAREST:
4647                         up_count =
4648                             (data[2] +
4649                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4650                         break;
4651                 case TRIG_ROUND_DOWN:
4652                         up_count = data[2] / devpriv->clock_ns;
4653                         break;
4654                 case TRIG_ROUND_UP:
4655                         up_count =
4656                             (data[2] + devpriv->clock_ns -
4657                              1) / devpriv->clock_ns;
4658                         break;
4659                 default:
4660                         return -EINVAL;
4661                         break;
4662                 }
4663                 switch (data[3]) {
4664                 case TRIG_ROUND_NEAREST:
4665                         down_count =
4666                             (data[4] +
4667                              devpriv->clock_ns / 2) / devpriv->clock_ns;
4668                         break;
4669                 case TRIG_ROUND_DOWN:
4670                         down_count = data[4] / devpriv->clock_ns;
4671                         break;
4672                 case TRIG_ROUND_UP:
4673                         down_count =
4674                             (data[4] + devpriv->clock_ns -
4675                              1) / devpriv->clock_ns;
4676                         break;
4677                 default:
4678                         return -EINVAL;
4679                         break;
4680                 }
4681                 if (up_count * devpriv->clock_ns != data[2] ||
4682                     down_count * devpriv->clock_ns != data[4]) {
4683                         data[2] = up_count * devpriv->clock_ns;
4684                         data[4] = down_count * devpriv->clock_ns;
4685                         return -EAGAIN;
4686                 }
4687                 ni_writel(up_count, Calibration_HighTime_6143);
4688                 devpriv->pwm_up_count = up_count;
4689                 ni_writel(down_count, Calibration_LowTime_6143);
4690                 devpriv->pwm_down_count = down_count;
4691                 return 5;
4692                 break;
4693         case INSN_CONFIG_GET_PWM_OUTPUT:
4694                 return ni_get_pwm_config(dev, data);
4695         default:
4696                 return -EINVAL;
4697                 break;
4698         }
4699         return 0;
4700 }
4701
4702 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4703 /*
4704         calibration subdevice
4705 */
4706 static int ni_calib_insn_write(struct comedi_device *dev,
4707                                struct comedi_subdevice *s,
4708                                struct comedi_insn *insn, unsigned int *data)
4709 {
4710         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4711
4712         return 1;
4713 }
4714
4715 static int ni_calib_insn_read(struct comedi_device *dev,
4716                               struct comedi_subdevice *s,
4717                               struct comedi_insn *insn, unsigned int *data)
4718 {
4719         struct ni_private *devpriv = dev->private;
4720
4721         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4722
4723         return 1;
4724 }
4725
4726 static int pack_mb88341(int addr, int val, int *bitstring);
4727 static int pack_dac8800(int addr, int val, int *bitstring);
4728 static int pack_dac8043(int addr, int val, int *bitstring);
4729 static int pack_ad8522(int addr, int val, int *bitstring);
4730 static int pack_ad8804(int addr, int val, int *bitstring);
4731 static int pack_ad8842(int addr, int val, int *bitstring);
4732
4733 struct caldac_struct {
4734         int n_chans;
4735         int n_bits;
4736         int (*packbits)(int, int, int *);
4737 };
4738
4739 static struct caldac_struct caldacs[] = {
4740         [mb88341] = {12, 8, pack_mb88341},
4741         [dac8800] = {8, 8, pack_dac8800},
4742         [dac8043] = {1, 12, pack_dac8043},
4743         [ad8522] = {2, 12, pack_ad8522},
4744         [ad8804] = {12, 8, pack_ad8804},
4745         [ad8842] = {8, 8, pack_ad8842},
4746         [ad8804_debug] = {16, 8, pack_ad8804},
4747 };
4748
4749 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4750 {
4751         const struct ni_board_struct *board = comedi_board(dev);
4752         struct ni_private *devpriv = dev->private;
4753         int i, j;
4754         int n_dacs;
4755         int n_chans = 0;
4756         int n_bits;
4757         int diffbits = 0;
4758         int type;
4759         int chan;
4760
4761         type = board->caldac[0];
4762         if (type == caldac_none)
4763                 return;
4764         n_bits = caldacs[type].n_bits;
4765         for (i = 0; i < 3; i++) {
4766                 type = board->caldac[i];
4767                 if (type == caldac_none)
4768                         break;
4769                 if (caldacs[type].n_bits != n_bits)
4770                         diffbits = 1;
4771                 n_chans += caldacs[type].n_chans;
4772         }
4773         n_dacs = i;
4774         s->n_chan = n_chans;
4775
4776         if (diffbits) {
4777                 unsigned int *maxdata_list;
4778
4779                 if (n_chans > MAX_N_CALDACS)
4780                         printk("BUG! MAX_N_CALDACS too small\n");
4781                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4782                 chan = 0;
4783                 for (i = 0; i < n_dacs; i++) {
4784                         type = board->caldac[i];
4785                         for (j = 0; j < caldacs[type].n_chans; j++) {
4786                                 maxdata_list[chan] =
4787                                     (1 << caldacs[type].n_bits) - 1;
4788                                 chan++;
4789                         }
4790                 }
4791
4792                 for (chan = 0; chan < s->n_chan; chan++)
4793                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4794         } else {
4795                 type = board->caldac[0];
4796                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4797
4798                 for (chan = 0; chan < s->n_chan; chan++)
4799                         ni_write_caldac(dev, i, s->maxdata / 2);
4800         }
4801 }
4802
4803 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4804 {
4805         const struct ni_board_struct *board = comedi_board(dev);
4806         struct ni_private *devpriv = dev->private;
4807         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4808         int i;
4809         int type;
4810
4811         /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
4812         if (devpriv->caldacs[addr] == val)
4813                 return;
4814         devpriv->caldacs[addr] = val;
4815
4816         for (i = 0; i < 3; i++) {
4817                 type = board->caldac[i];
4818                 if (type == caldac_none)
4819                         break;
4820                 if (addr < caldacs[type].n_chans) {
4821                         bits = caldacs[type].packbits(addr, val, &bitstring);
4822                         loadbit = SerDacLd(i);
4823                         /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
4824                         break;
4825                 }
4826                 addr -= caldacs[type].n_chans;
4827         }
4828
4829         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4830                 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
4831                 udelay(1);
4832                 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
4833                 udelay(1);
4834         }
4835         ni_writeb(loadbit, Serial_Command);
4836         udelay(1);
4837         ni_writeb(0, Serial_Command);
4838 }
4839
4840 static int pack_mb88341(int addr, int val, int *bitstring)
4841 {
4842         /*
4843            Fujitsu MB 88341
4844            Note that address bits are reversed.  Thanks to
4845            Ingo Keen for noticing this.
4846
4847            Note also that the 88341 expects address values from
4848            1-12, whereas we use channel numbers 0-11.  The NI
4849            docs use 1-12, also, so be careful here.
4850          */
4851         addr++;
4852         *bitstring = ((addr & 0x1) << 11) |
4853             ((addr & 0x2) << 9) |
4854             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4855         return 12;
4856 }
4857
4858 static int pack_dac8800(int addr, int val, int *bitstring)
4859 {
4860         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4861         return 11;
4862 }
4863
4864 static int pack_dac8043(int addr, int val, int *bitstring)
4865 {
4866         *bitstring = val & 0xfff;
4867         return 12;
4868 }
4869
4870 static int pack_ad8522(int addr, int val, int *bitstring)
4871 {
4872         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4873         return 16;
4874 }
4875
4876 static int pack_ad8804(int addr, int val, int *bitstring)
4877 {
4878         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4879         return 12;
4880 }
4881
4882 static int pack_ad8842(int addr, int val, int *bitstring)
4883 {
4884         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4885         return 12;
4886 }
4887
4888 #if 0
4889 /*
4890  *      Read the GPCTs current value.
4891  */
4892 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
4893 {
4894         unsigned int hi1, hi2, lo;
4895
4896         devpriv->gpct_command[chan] &= ~G_Save_Trace;
4897         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
4898                             G_Command_Register(chan));
4899
4900         devpriv->gpct_command[chan] |= G_Save_Trace;
4901         devpriv->stc_writew(dev, devpriv->gpct_command[chan],
4902                             G_Command_Register(chan));
4903
4904         /* This procedure is used because the two registers cannot
4905          * be read atomically. */
4906         do {
4907                 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
4908                 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
4909                 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
4910         } while (hi1 != hi2);
4911
4912         return (hi1 << 16) | lo;
4913 }
4914
4915 static void GPCT_Reset(struct comedi_device *dev, int chan)
4916 {
4917         int temp_ack_reg = 0;
4918
4919         /* printk("GPCT_Reset..."); */
4920         devpriv->gpct_cur_operation[chan] = GPCT_RESET;
4921
4922         switch (chan) {
4923         case 0:
4924                 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
4925                 ni_set_bits(dev, Interrupt_A_Enable_Register,
4926                             G0_TC_Interrupt_Enable, 0);
4927                 ni_set_bits(dev, Interrupt_A_Enable_Register,
4928                             G0_Gate_Interrupt_Enable, 0);
4929                 temp_ack_reg |= G0_Gate_Error_Confirm;
4930                 temp_ack_reg |= G0_TC_Error_Confirm;
4931                 temp_ack_reg |= G0_TC_Interrupt_Ack;
4932                 temp_ack_reg |= G0_Gate_Interrupt_Ack;
4933                 devpriv->stc_writew(dev, temp_ack_reg,
4934                                     Interrupt_A_Ack_Register);
4935
4936                 /* problem...this interferes with the other ctr... */
4937                 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
4938                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
4939                                     Analog_Trigger_Etc_Register);
4940                 break;
4941         case 1:
4942                 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
4943                 ni_set_bits(dev, Interrupt_B_Enable_Register,
4944                             G1_TC_Interrupt_Enable, 0);
4945                 ni_set_bits(dev, Interrupt_B_Enable_Register,
4946                             G0_Gate_Interrupt_Enable, 0);
4947                 temp_ack_reg |= G1_Gate_Error_Confirm;
4948                 temp_ack_reg |= G1_TC_Error_Confirm;
4949                 temp_ack_reg |= G1_TC_Interrupt_Ack;
4950                 temp_ack_reg |= G1_Gate_Interrupt_Ack;
4951                 devpriv->stc_writew(dev, temp_ack_reg,
4952                                     Interrupt_B_Ack_Register);
4953
4954                 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
4955                 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
4956                                     Analog_Trigger_Etc_Register);
4957                 break;
4958         }
4959
4960         devpriv->gpct_mode[chan] = 0;
4961         devpriv->gpct_input_select[chan] = 0;
4962         devpriv->gpct_command[chan] = 0;
4963
4964         devpriv->gpct_command[chan] |= G_Synchronized_Gate;
4965
4966         devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
4967                             G_Mode_Register(chan));
4968         devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
4969                             G_Input_Select_Register(chan));
4970         devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
4971
4972         /* printk("exit GPCT_Reset\n"); */
4973 }
4974
4975 #endif
4976
4977 #ifdef PCIDMA
4978 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
4979 {
4980         struct ni_gpct *counter = s->private;
4981         int retval;
4982
4983         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
4984                                               COMEDI_INPUT);
4985         if (retval) {
4986                 comedi_error(dev,
4987                              "no dma channel available for use by counter");
4988                 return retval;
4989         }
4990         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
4991         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
4992
4993         return ni_tio_cmd(dev, s);
4994 }
4995 #endif
4996
4997 #ifdef PCIDMA
4998 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
4999 {
5000         struct ni_gpct *counter = s->private;
5001         int retval;
5002
5003         retval = ni_tio_cancel(counter);
5004         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5005         ni_release_gpct_mite_channel(dev, counter->counter_index);
5006         return retval;
5007 }
5008 #endif
5009
5010 /*
5011  *
5012  *  Programmable Function Inputs
5013  *
5014  */
5015
5016 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5017                                        unsigned source)
5018 {
5019         struct ni_private *devpriv = dev->private;
5020         unsigned pfi_reg_index;
5021         unsigned array_offset;
5022
5023         if ((source & 0x1f) != source)
5024                 return -EINVAL;
5025         pfi_reg_index = 1 + chan / 3;
5026         array_offset = pfi_reg_index - 1;
5027         devpriv->pfi_output_select_reg[array_offset] &=
5028             ~MSeries_PFI_Output_Select_Mask(chan);
5029         devpriv->pfi_output_select_reg[array_offset] |=
5030             MSeries_PFI_Output_Select_Bits(chan, source);
5031         ni_writew(devpriv->pfi_output_select_reg[array_offset],
5032                   M_Offset_PFI_Output_Select(pfi_reg_index));
5033         return 2;
5034 }
5035
5036 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5037                                   unsigned source)
5038 {
5039         /*  pre-m-series boards have fixed signals on pfi pins */
5040         if (source != ni_old_get_pfi_routing(dev, chan))
5041                 return -EINVAL;
5042         return 2;
5043 }
5044
5045 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5046                               unsigned source)
5047 {
5048         const struct ni_board_struct *board = comedi_board(dev);
5049
5050         if (board->reg_type & ni_reg_m_series_mask)
5051                 return ni_m_series_set_pfi_routing(dev, chan, source);
5052         else
5053                 return ni_old_set_pfi_routing(dev, chan, source);
5054 }
5055
5056 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5057                                             unsigned chan)
5058 {
5059         struct ni_private *devpriv = dev->private;
5060         const unsigned array_offset = chan / 3;
5061
5062         return MSeries_PFI_Output_Select_Source(chan,
5063                                                 devpriv->
5064                                                 pfi_output_select_reg
5065                                                 [array_offset]);
5066 }
5067
5068 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5069 {
5070         /*  pre-m-series boards have fixed signals on pfi pins */
5071         switch (chan) {
5072         case 0:
5073                 return NI_PFI_OUTPUT_AI_START1;
5074                 break;
5075         case 1:
5076                 return NI_PFI_OUTPUT_AI_START2;
5077                 break;
5078         case 2:
5079                 return NI_PFI_OUTPUT_AI_CONVERT;
5080                 break;
5081         case 3:
5082                 return NI_PFI_OUTPUT_G_SRC1;
5083                 break;
5084         case 4:
5085                 return NI_PFI_OUTPUT_G_GATE1;
5086                 break;
5087         case 5:
5088                 return NI_PFI_OUTPUT_AO_UPDATE_N;
5089                 break;
5090         case 6:
5091                 return NI_PFI_OUTPUT_AO_START1;
5092                 break;
5093         case 7:
5094                 return NI_PFI_OUTPUT_AI_START_PULSE;
5095                 break;
5096         case 8:
5097                 return NI_PFI_OUTPUT_G_SRC0;
5098                 break;
5099         case 9:
5100                 return NI_PFI_OUTPUT_G_GATE0;
5101                 break;
5102         default:
5103                 printk("%s: bug, unhandled case in switch.\n", __func__);
5104                 break;
5105         }
5106         return 0;
5107 }
5108
5109 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5110 {
5111         const struct ni_board_struct *board = comedi_board(dev);
5112
5113         if (board->reg_type & ni_reg_m_series_mask)
5114                 return ni_m_series_get_pfi_routing(dev, chan);
5115         else
5116                 return ni_old_get_pfi_routing(dev, chan);
5117 }
5118
5119 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5120                             enum ni_pfi_filter_select filter)
5121 {
5122         const struct ni_board_struct *board = comedi_board(dev);
5123         struct ni_private *devpriv __maybe_unused = dev->private;
5124         unsigned bits;
5125
5126         if ((board->reg_type & ni_reg_m_series_mask) == 0)
5127                 return -ENOTSUPP;
5128         bits = ni_readl(M_Offset_PFI_Filter);
5129         bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5130         bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5131         ni_writel(bits, M_Offset_PFI_Filter);
5132         return 0;
5133 }
5134
5135 static int ni_pfi_insn_bits(struct comedi_device *dev,
5136                             struct comedi_subdevice *s,
5137                             struct comedi_insn *insn,
5138                             unsigned int *data)
5139 {
5140         const struct ni_board_struct *board = comedi_board(dev);
5141         struct ni_private *devpriv __maybe_unused = dev->private;
5142
5143         if (!(board->reg_type & ni_reg_m_series_mask))
5144                 return -ENOTSUPP;
5145
5146         if (comedi_dio_update_state(s, data))
5147                 ni_writew(s->state, M_Offset_PFI_DO);
5148
5149         data[1] = ni_readw(M_Offset_PFI_DI);
5150
5151         return insn->n;
5152 }
5153
5154 static int ni_pfi_insn_config(struct comedi_device *dev,
5155                               struct comedi_subdevice *s,
5156                               struct comedi_insn *insn, unsigned int *data)
5157 {
5158         struct ni_private *devpriv = dev->private;
5159         unsigned int chan;
5160
5161         if (insn->n < 1)
5162                 return -EINVAL;
5163
5164         chan = CR_CHAN(insn->chanspec);
5165
5166         switch (data[0]) {
5167         case COMEDI_OUTPUT:
5168                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5169                 break;
5170         case COMEDI_INPUT:
5171                 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5172                 break;
5173         case INSN_CONFIG_DIO_QUERY:
5174                 data[1] =
5175                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5176                     COMEDI_OUTPUT : COMEDI_INPUT;
5177                 return 0;
5178                 break;
5179         case INSN_CONFIG_SET_ROUTING:
5180                 return ni_set_pfi_routing(dev, chan, data[1]);
5181                 break;
5182         case INSN_CONFIG_GET_ROUTING:
5183                 data[1] = ni_get_pfi_routing(dev, chan);
5184                 break;
5185         case INSN_CONFIG_FILTER:
5186                 return ni_config_filter(dev, chan, data[1]);
5187                 break;
5188         default:
5189                 return -EINVAL;
5190         }
5191         return 0;
5192 }
5193
5194 /*
5195  *
5196  *  NI RTSI Bus Functions
5197  *
5198  */
5199 static void ni_rtsi_init(struct comedi_device *dev)
5200 {
5201         const struct ni_board_struct *board = comedi_board(dev);
5202         struct ni_private *devpriv = dev->private;
5203
5204         /*  Initialises the RTSI bus signal switch to a default state */
5205
5206         /*  Set clock mode to internal */
5207         devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5208         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5209                 printk("ni_set_master_clock failed, bug?");
5210         /*  default internal lines routing to RTSI bus lines */
5211         devpriv->rtsi_trig_a_output_reg =
5212             RTSI_Trig_Output_Bits(0,
5213                                   NI_RTSI_OUTPUT_ADR_START1) |
5214             RTSI_Trig_Output_Bits(1,
5215                                   NI_RTSI_OUTPUT_ADR_START2) |
5216             RTSI_Trig_Output_Bits(2,
5217                                   NI_RTSI_OUTPUT_SCLKG) |
5218             RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5219         devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5220                             RTSI_Trig_A_Output_Register);
5221         devpriv->rtsi_trig_b_output_reg =
5222             RTSI_Trig_Output_Bits(4,
5223                                   NI_RTSI_OUTPUT_DA_START1) |
5224             RTSI_Trig_Output_Bits(5,
5225                                   NI_RTSI_OUTPUT_G_SRC0) |
5226             RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5227         if (board->reg_type & ni_reg_m_series_mask)
5228                 devpriv->rtsi_trig_b_output_reg |=
5229                     RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5230         devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5231                             RTSI_Trig_B_Output_Register);
5232
5233 /*
5234 * Sets the source and direction of the 4 on board lines
5235 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5236 */
5237 }
5238
5239 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5240                              struct comedi_subdevice *s,
5241                              struct comedi_insn *insn, unsigned int *data)
5242 {
5243         data[1] = 0;
5244
5245         return insn->n;
5246 }
5247
5248 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5249  * given an arbitrary frequency input clock */
5250 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5251                                          unsigned *freq_divider,
5252                                          unsigned *freq_multiplier,
5253                                          unsigned *actual_period_ns)
5254 {
5255         unsigned div;
5256         unsigned best_div = 1;
5257         static const unsigned max_div = 0x10;
5258         unsigned mult;
5259         unsigned best_mult = 1;
5260         static const unsigned max_mult = 0x100;
5261         static const unsigned pico_per_nano = 1000;
5262
5263         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5264         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5265          * 20 MHz for most timing clocks */
5266         static const unsigned target_picosec = 12500;
5267         static const unsigned fudge_factor_80_to_20Mhz = 4;
5268         int best_period_picosec = 0;
5269         for (div = 1; div <= max_div; ++div) {
5270                 for (mult = 1; mult <= max_mult; ++mult) {
5271                         unsigned new_period_ps =
5272                             (reference_picosec * div) / mult;
5273                         if (abs(new_period_ps - target_picosec) <
5274                             abs(best_period_picosec - target_picosec)) {
5275                                 best_period_picosec = new_period_ps;
5276                                 best_div = div;
5277                                 best_mult = mult;
5278                         }
5279                 }
5280         }
5281         if (best_period_picosec == 0) {
5282                 printk("%s: bug, failed to find pll parameters\n", __func__);
5283                 return -EIO;
5284         }
5285         *freq_divider = best_div;
5286         *freq_multiplier = best_mult;
5287         *actual_period_ns =
5288             (best_period_picosec * fudge_factor_80_to_20Mhz +
5289              (pico_per_nano / 2)) / pico_per_nano;
5290         return 0;
5291 }
5292
5293 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5294 {
5295         const struct ni_board_struct *board = comedi_board(dev);
5296
5297         if (board->reg_type & ni_reg_m_series_mask)
5298                 return 8;
5299         else
5300                 return 7;
5301 }
5302
5303 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5304                                            unsigned source, unsigned period_ns)
5305 {
5306         struct ni_private *devpriv = dev->private;
5307         static const unsigned min_period_ns = 50;
5308         static const unsigned max_period_ns = 1000;
5309         static const unsigned timeout = 1000;
5310         unsigned pll_control_bits;
5311         unsigned freq_divider;
5312         unsigned freq_multiplier;
5313         unsigned i;
5314         int retval;
5315
5316         if (source == NI_MIO_PLL_PXI10_CLOCK)
5317                 period_ns = 100;
5318         /*  these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5319         if (period_ns < min_period_ns || period_ns > max_period_ns) {
5320                 printk
5321                     ("%s: you must specify an input clock frequency between %i and %i nanosec "
5322                      "for the phased-lock loop.\n", __func__,
5323                      min_period_ns, max_period_ns);
5324                 return -EINVAL;
5325         }
5326         devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5327         devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5328                             RTSI_Trig_Direction_Register);
5329         pll_control_bits =
5330             MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5331         devpriv->clock_and_fout2 |=
5332             MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5333         devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5334         switch (source) {
5335         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5336                 devpriv->clock_and_fout2 |=
5337                     MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5338                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5339                                                        &freq_multiplier,
5340                                                        &devpriv->clock_ns);
5341                 if (retval < 0)
5342                         return retval;
5343                 break;
5344         case NI_MIO_PLL_PXI10_CLOCK:
5345                 /* pxi clock is 10MHz */
5346                 devpriv->clock_and_fout2 |=
5347                     MSeries_PLL_In_Source_Select_PXI_Clock10;
5348                 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5349                                                        &freq_multiplier,
5350                                                        &devpriv->clock_ns);
5351                 if (retval < 0)
5352                         return retval;
5353                 break;
5354         default:
5355                 {
5356                         unsigned rtsi_channel;
5357                         static const unsigned max_rtsi_channel = 7;
5358                         for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5359                              ++rtsi_channel) {
5360                                 if (source ==
5361                                     NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5362                                         devpriv->clock_and_fout2 |=
5363                                             MSeries_PLL_In_Source_Select_RTSI_Bits
5364                                             (rtsi_channel);
5365                                         break;
5366                                 }
5367                         }
5368                         if (rtsi_channel > max_rtsi_channel)
5369                                 return -EINVAL;
5370                         retval = ni_mseries_get_pll_parameters(period_ns,
5371                                                                &freq_divider,
5372                                                                &freq_multiplier,
5373                                                                &devpriv->
5374                                                                clock_ns);
5375                         if (retval < 0)
5376                                 return retval;
5377                 }
5378                 break;
5379         }
5380         ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5381         pll_control_bits |=
5382             MSeries_PLL_Divisor_Bits(freq_divider) |
5383             MSeries_PLL_Multiplier_Bits(freq_multiplier);
5384
5385         /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5386          * freq_divider, freq_multiplier, pll_control_bits); */
5387         /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5388         ni_writew(pll_control_bits, M_Offset_PLL_Control);
5389         devpriv->clock_source = source;
5390         /* it seems to typically take a few hundred microseconds for PLL to lock */
5391         for (i = 0; i < timeout; ++i) {
5392                 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit)
5393                         break;
5394                 udelay(1);
5395         }
5396         if (i == timeout) {
5397                 printk
5398                     ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5399                      __func__, source, period_ns);
5400                 return -ETIMEDOUT;
5401         }
5402         return 3;
5403 }
5404
5405 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5406                                unsigned period_ns)
5407 {
5408         const struct ni_board_struct *board = comedi_board(dev);
5409         struct ni_private *devpriv = dev->private;
5410
5411         if (source == NI_MIO_INTERNAL_CLOCK) {
5412                 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5413                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5414                                     RTSI_Trig_Direction_Register);
5415                 devpriv->clock_ns = TIMEBASE_1_NS;
5416                 if (board->reg_type & ni_reg_m_series_mask) {
5417                         devpriv->clock_and_fout2 &=
5418                             ~(MSeries_Timebase1_Select_Bit |
5419                               MSeries_Timebase3_Select_Bit);
5420                         ni_writew(devpriv->clock_and_fout2,
5421                                   M_Offset_Clock_and_Fout2);
5422                         ni_writew(0, M_Offset_PLL_Control);
5423                 }
5424                 devpriv->clock_source = source;
5425         } else {
5426                 if (board->reg_type & ni_reg_m_series_mask) {
5427                         return ni_mseries_set_pll_master_clock(dev, source,
5428                                                                period_ns);
5429                 } else {
5430                         if (source == NI_MIO_RTSI_CLOCK) {
5431                                 devpriv->rtsi_trig_direction_reg |=
5432                                     Use_RTSI_Clock_Bit;
5433                                 devpriv->stc_writew(dev,
5434                                                     devpriv->
5435                                                     rtsi_trig_direction_reg,
5436                                                     RTSI_Trig_Direction_Register);
5437                                 if (period_ns == 0) {
5438                                         printk
5439                                             ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5440                                              __func__);
5441                                         return -EINVAL;
5442                                 } else {
5443                                         devpriv->clock_ns = period_ns;
5444                                 }
5445                                 devpriv->clock_source = source;
5446                         } else
5447                                 return -EINVAL;
5448                 }
5449         }
5450         return 3;
5451 }
5452
5453 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5454                                        unsigned source)
5455 {
5456         const struct ni_board_struct *board = comedi_board(dev);
5457
5458         if (chan >= num_configurable_rtsi_channels(dev)) {
5459                 if (chan == old_RTSI_clock_channel) {
5460                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5461                                 return 1;
5462                         else {
5463                                 printk
5464                                     ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5465                                      __func__, chan, old_RTSI_clock_channel);
5466                                 return 0;
5467                         }
5468                 }
5469                 return 0;
5470         }
5471         switch (source) {
5472         case NI_RTSI_OUTPUT_ADR_START1:
5473         case NI_RTSI_OUTPUT_ADR_START2:
5474         case NI_RTSI_OUTPUT_SCLKG:
5475         case NI_RTSI_OUTPUT_DACUPDN:
5476         case NI_RTSI_OUTPUT_DA_START1:
5477         case NI_RTSI_OUTPUT_G_SRC0:
5478         case NI_RTSI_OUTPUT_G_GATE0:
5479         case NI_RTSI_OUTPUT_RGOUT0:
5480         case NI_RTSI_OUTPUT_RTSI_BRD_0:
5481                 return 1;
5482                 break;
5483         case NI_RTSI_OUTPUT_RTSI_OSC:
5484                 if (board->reg_type & ni_reg_m_series_mask)
5485                         return 1;
5486                 else
5487                         return 0;
5488                 break;
5489         default:
5490                 return 0;
5491                 break;
5492         }
5493 }
5494
5495 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5496                                unsigned source)
5497 {
5498         struct ni_private *devpriv = dev->private;
5499
5500         if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5501                 return -EINVAL;
5502         if (chan < 4) {
5503                 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5504                 devpriv->rtsi_trig_a_output_reg |=
5505                     RTSI_Trig_Output_Bits(chan, source);
5506                 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5507                                     RTSI_Trig_A_Output_Register);
5508         } else if (chan < 8) {
5509                 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5510                 devpriv->rtsi_trig_b_output_reg |=
5511                     RTSI_Trig_Output_Bits(chan, source);
5512                 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5513                                     RTSI_Trig_B_Output_Register);
5514         }
5515         return 2;
5516 }
5517
5518 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5519 {
5520         struct ni_private *devpriv = dev->private;
5521
5522         if (chan < 4) {
5523                 return RTSI_Trig_Output_Source(chan,
5524                                                devpriv->rtsi_trig_a_output_reg);
5525         } else if (chan < num_configurable_rtsi_channels(dev)) {
5526                 return RTSI_Trig_Output_Source(chan,
5527                                                devpriv->rtsi_trig_b_output_reg);
5528         } else {
5529                 if (chan == old_RTSI_clock_channel)
5530                         return NI_RTSI_OUTPUT_RTSI_OSC;
5531                 printk("%s: bug! should never get here?\n", __func__);
5532                 return 0;
5533         }
5534 }
5535
5536 static int ni_rtsi_insn_config(struct comedi_device *dev,
5537                                struct comedi_subdevice *s,
5538                                struct comedi_insn *insn, unsigned int *data)
5539 {
5540         const struct ni_board_struct *board = comedi_board(dev);
5541         struct ni_private *devpriv = dev->private;
5542         unsigned int chan = CR_CHAN(insn->chanspec);
5543
5544         switch (data[0]) {
5545         case INSN_CONFIG_DIO_OUTPUT:
5546                 if (chan < num_configurable_rtsi_channels(dev)) {
5547                         devpriv->rtsi_trig_direction_reg |=
5548                             RTSI_Output_Bit(chan,
5549                                 (board->reg_type & ni_reg_m_series_mask) != 0);
5550                 } else if (chan == old_RTSI_clock_channel) {
5551                         devpriv->rtsi_trig_direction_reg |=
5552                             Drive_RTSI_Clock_Bit;
5553                 }
5554                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5555                                     RTSI_Trig_Direction_Register);
5556                 break;
5557         case INSN_CONFIG_DIO_INPUT:
5558                 if (chan < num_configurable_rtsi_channels(dev)) {
5559                         devpriv->rtsi_trig_direction_reg &=
5560                             ~RTSI_Output_Bit(chan,
5561                                 (board->reg_type & ni_reg_m_series_mask) != 0);
5562                 } else if (chan == old_RTSI_clock_channel) {
5563                         devpriv->rtsi_trig_direction_reg &=
5564                             ~Drive_RTSI_Clock_Bit;
5565                 }
5566                 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5567                                     RTSI_Trig_Direction_Register);
5568                 break;
5569         case INSN_CONFIG_DIO_QUERY:
5570                 if (chan < num_configurable_rtsi_channels(dev)) {
5571                         data[1] =
5572                             (devpriv->rtsi_trig_direction_reg &
5573                              RTSI_Output_Bit(chan,
5574                                 (board->reg_type & ni_reg_m_series_mask) != 0))
5575                                 ? INSN_CONFIG_DIO_OUTPUT
5576                                 : INSN_CONFIG_DIO_INPUT;
5577                 } else if (chan == old_RTSI_clock_channel) {
5578                         data[1] =
5579                             (devpriv->rtsi_trig_direction_reg &
5580                              Drive_RTSI_Clock_Bit)
5581                             ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5582                 }
5583                 return 2;
5584                 break;
5585         case INSN_CONFIG_SET_CLOCK_SRC:
5586                 return ni_set_master_clock(dev, data[1], data[2]);
5587                 break;
5588         case INSN_CONFIG_GET_CLOCK_SRC:
5589                 data[1] = devpriv->clock_source;
5590                 data[2] = devpriv->clock_ns;
5591                 return 3;
5592                 break;
5593         case INSN_CONFIG_SET_ROUTING:
5594                 return ni_set_rtsi_routing(dev, chan, data[1]);
5595                 break;
5596         case INSN_CONFIG_GET_ROUTING:
5597                 data[1] = ni_get_rtsi_routing(dev, chan);
5598                 return 2;
5599                 break;
5600         default:
5601                 return -EINVAL;
5602                 break;
5603         }
5604         return 1;
5605 }
5606
5607 static int cs5529_wait_for_idle(struct comedi_device *dev)
5608 {
5609         unsigned short status;
5610         const int timeout = HZ;
5611         int i;
5612
5613         for (i = 0; i < timeout; i++) {
5614                 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5615                 if ((status & CSS_ADC_BUSY) == 0)
5616                         break;
5617                 set_current_state(TASK_INTERRUPTIBLE);
5618                 if (schedule_timeout(1))
5619                         return -EIO;
5620         }
5621 /* printk("looped %i times waiting for idle\n", i); */
5622         if (i == timeout) {
5623                 printk("%s: %s: timeout\n", __FILE__, __func__);
5624                 return -ETIME;
5625         }
5626         return 0;
5627 }
5628
5629 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5630 {
5631         static const int timeout = 100;
5632         int i;
5633
5634         ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5635         /* give time for command to start being serially clocked into cs5529.
5636          * this insures that the CSS_ADC_BUSY bit will get properly
5637          * set before we exit this function.
5638          */
5639         for (i = 0; i < timeout; i++) {
5640                 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5641                         break;
5642                 udelay(1);
5643         }
5644 /* printk("looped %i times writing command to cs5529\n", i); */
5645         if (i == timeout)
5646                 comedi_error(dev, "possible problem - never saw adc go busy?");
5647 }
5648
5649 /* write to cs5529 register */
5650 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5651                                 unsigned int reg_select_bits)
5652 {
5653         ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5654                        CAL_ADC_Config_Data_High_Word_67xx);
5655         ni_ao_win_outw(dev, (value & 0xffff),
5656                        CAL_ADC_Config_Data_Low_Word_67xx);
5657         reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5658         cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5659         if (cs5529_wait_for_idle(dev))
5660                 comedi_error(dev, "time or signal in cs5529_config_write()");
5661 }
5662
5663 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5664 {
5665         int retval;
5666         unsigned short status;
5667
5668         cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5669         retval = cs5529_wait_for_idle(dev);
5670         if (retval) {
5671                 comedi_error(dev,
5672                              "timeout or signal in cs5529_do_conversion()");
5673                 return -ETIME;
5674         }
5675         status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5676         if (status & CSS_OSC_DETECT) {
5677                 printk
5678                     ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5679                 return -EIO;
5680         }
5681         if (status & CSS_OVERRANGE) {
5682                 printk
5683                     ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5684         }
5685         if (data) {
5686                 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5687                 /* cs5529 returns 16 bit signed data in bipolar mode */
5688                 *data ^= (1 << 15);
5689         }
5690         return 0;
5691 }
5692
5693 static int cs5529_ai_insn_read(struct comedi_device *dev,
5694                                struct comedi_subdevice *s,
5695                                struct comedi_insn *insn, unsigned int *data)
5696 {
5697         int n, retval;
5698         unsigned short sample;
5699         unsigned int channel_select;
5700         const unsigned int INTERNAL_REF = 0x1000;
5701
5702         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
5703          * do nothing. bit 12 seems to chooses internal reference voltage, bit
5704          * 13 causes the adc input to go overrange (maybe reads external reference?) */
5705         if (insn->chanspec & CR_ALT_SOURCE)
5706                 channel_select = INTERNAL_REF;
5707         else
5708                 channel_select = CR_CHAN(insn->chanspec);
5709         ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5710
5711         for (n = 0; n < insn->n; n++) {
5712                 retval = cs5529_do_conversion(dev, &sample);
5713                 if (retval < 0)
5714                         return retval;
5715                 data[n] = sample;
5716         }
5717         return insn->n;
5718 }
5719
5720 static int init_cs5529(struct comedi_device *dev)
5721 {
5722         unsigned int config_bits =
5723             CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
5724
5725 #if 1
5726         /* do self-calibration */
5727         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
5728                             CSCMD_CONFIG_REGISTER);
5729         /* need to force a conversion for calibration to run */
5730         cs5529_do_conversion(dev, NULL);
5731 #else
5732         /* force gain calibration to 1 */
5733         cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5734         cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
5735                             CSCMD_CONFIG_REGISTER);
5736         if (cs5529_wait_for_idle(dev))
5737                 comedi_error(dev, "timeout or signal in init_cs5529()\n");
5738 #endif
5739         return 0;
5740 }