drivers/staging/comedi/drivers/ni_mio_common.c

   1 /*
   2     comedi/drivers/ni_mio_common.c
   3     Hardware driver for DAQ-STC based boards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7     Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21         This file is meant to be included by another file, e.g.,
  22         ni_atmio.c or ni_pcimio.c.
  23
  24         Interrupt support originally added by Truxton Fulton
  25         <trux@truxton.com>
  26
  27         References (from ftp://ftp.natinst.com/support/manuals):
  28
  29            340747b.pdf  AT-MIO E series Register Level Programmer Manual
  30            341079b.pdf  PCI E Series RLPM
  31            340934b.pdf  DAQ-STC reference manual
  32         67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  33         release_ni611x.pdf
  34         release_ni67xx.pdf
  35         Other possibly relevant info:
  36
  37            320517c.pdf  User manual (obsolete)
  38            320517f.pdf  User manual (new)
  39            320889a.pdf  delete
  40            320906c.pdf  maximum signal ratings
  41            321066a.pdf  about 16x
  42            321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  43            321808a.pdf  about at-mio-16e-10 rev P
  44            321837a.pdf  discontinuation of at-mio-16de-10 rev d
  45            321838a.pdf  about at-mio-16de-10 rev N
  46
  47         ISSUES:
  48
  49          - the interrupt routine needs to be cleaned up
  50
  51         2006-02-07: S-Series PCI-6143: Support has been added but is not
  52                 fully tested as yet. Terry Barnaby, BEAM Ltd.
  53 */
  54
  55 #include <linux/interrupt.h>
  56 #include <linux/sched.h>
  57 #include <linux/delay.h>
  58 #include "8255.h"
  59 #include "mite.h"
  60
  61 /* A timeout count */
  62 #define NI_TIMEOUT 1000
  63
  64 /* Note: this table must match the ai_gain_* definitions */
  65 static const short ni_gainlkup[][16] = {
  66         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  67                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  68         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  69         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  70                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  71         [ai_gain_4] = {0, 1, 4, 7},
  72         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  73                           0x003, 0x004, 0x005, 0x006},
  74         [ai_gain_622x] = {0, 1, 4, 5},
  75         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  76         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  77 };
  78
  79 static const struct comedi_lrange range_ni_E_ai = {
  80         16, {
  81                 BIP_RANGE(10),
  82                 BIP_RANGE(5),
  83                 BIP_RANGE(2.5),
  84                 BIP_RANGE(1),
  85                 BIP_RANGE(0.5),
  86                 BIP_RANGE(0.25),
  87                 BIP_RANGE(0.1),
  88                 BIP_RANGE(0.05),
  89                 UNI_RANGE(20),
  90                 UNI_RANGE(10),
  91                 UNI_RANGE(5),
  92                 UNI_RANGE(2),
  93                 UNI_RANGE(1),
  94                 UNI_RANGE(0.5),
  95                 UNI_RANGE(0.2),
  96                 UNI_RANGE(0.1)
  97         }
  98 };
  99
 100 static const struct comedi_lrange range_ni_E_ai_limited = {
 101         8, {
 102                 BIP_RANGE(10),
 103                 BIP_RANGE(5),
 104                 BIP_RANGE(1),
 105                 BIP_RANGE(0.1),
 106                 UNI_RANGE(10),
 107                 UNI_RANGE(5),
 108                 UNI_RANGE(1),
 109                 UNI_RANGE(0.1)
 110         }
 111 };
 112
 113 static const struct comedi_lrange range_ni_E_ai_limited14 = {
 114         14, {
 115                 BIP_RANGE(10),
 116                 BIP_RANGE(5),
 117                 BIP_RANGE(2),
 118                 BIP_RANGE(1),
 119                 BIP_RANGE(0.5),
 120                 BIP_RANGE(0.2),
 121                 BIP_RANGE(0.1),
 122                 UNI_RANGE(10),
 123                 UNI_RANGE(5),
 124                 UNI_RANGE(2),
 125                 UNI_RANGE(1),
 126                 UNI_RANGE(0.5),
 127                 UNI_RANGE(0.2),
 128                 UNI_RANGE(0.1)
 129         }
 130 };
 131
 132 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
 133         4, {
 134                 BIP_RANGE(10),
 135                 BIP_RANGE(5),
 136                 BIP_RANGE(0.5),
 137                 BIP_RANGE(0.05)
 138         }
 139 };
 140
 141 static const struct comedi_lrange range_ni_E_ai_611x = {
 142         8, {
 143                 BIP_RANGE(50),
 144                 BIP_RANGE(20),
 145                 BIP_RANGE(10),
 146                 BIP_RANGE(5),
 147                 BIP_RANGE(2),
 148                 BIP_RANGE(1),
 149                 BIP_RANGE(0.5),
 150                 BIP_RANGE(0.2)
 151         }
 152 };
 153
 154 static const struct comedi_lrange range_ni_M_ai_622x = {
 155         4, {
 156                 BIP_RANGE(10),
 157                 BIP_RANGE(5),
 158                 BIP_RANGE(1),
 159                 BIP_RANGE(0.2)
 160         }
 161 };
 162
 163 static const struct comedi_lrange range_ni_M_ai_628x = {
 164         7, {
 165                 BIP_RANGE(10),
 166                 BIP_RANGE(5),
 167                 BIP_RANGE(2),
 168                 BIP_RANGE(1),
 169                 BIP_RANGE(0.5),
 170                 BIP_RANGE(0.2),
 171                 BIP_RANGE(0.1)
 172         }
 173 };
 174
 175 static const struct comedi_lrange range_ni_E_ao_ext = {
 176         4, {
 177                 BIP_RANGE(10),
 178                 UNI_RANGE(10),
 179                 RANGE_ext(-1, 1),
 180                 RANGE_ext(0, 1)
 181         }
 182 };
 183
 184 static const struct comedi_lrange *const ni_range_lkup[] = {
 185         [ai_gain_16] = &range_ni_E_ai,
 186         [ai_gain_8] = &range_ni_E_ai_limited,
 187         [ai_gain_14] = &range_ni_E_ai_limited14,
 188         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 189         [ai_gain_611x] = &range_ni_E_ai_611x,
 190         [ai_gain_622x] = &range_ni_M_ai_622x,
 191         [ai_gain_628x] = &range_ni_M_ai_628x,
 192         [ai_gain_6143] = &range_bipolar5
 193 };
 194
 195 enum aimodes {
 196         AIMODE_NONE = 0,
 197         AIMODE_HALF_FULL = 1,
 198         AIMODE_SCAN = 2,
 199         AIMODE_SAMPLE = 3,
 200 };
 201
 202 enum ni_common_subdevices {
 203         NI_AI_SUBDEV,
 204         NI_AO_SUBDEV,
 205         NI_DIO_SUBDEV,
 206         NI_8255_DIO_SUBDEV,
 207         NI_UNUSED_SUBDEV,
 208         NI_CALIBRATION_SUBDEV,
 209         NI_EEPROM_SUBDEV,
 210         NI_PFI_DIO_SUBDEV,
 211         NI_CS5529_CALIBRATION_SUBDEV,
 212         NI_SERIAL_SUBDEV,
 213         NI_RTSI_SUBDEV,
 214         NI_GPCT0_SUBDEV,
 215         NI_GPCT1_SUBDEV,
 216         NI_FREQ_OUT_SUBDEV,
 217         NI_NUM_SUBDEVICES
 218 };
 219 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
 220 {
 221         switch (counter_index) {
 222         case 0:
 223                 return NI_GPCT0_SUBDEV;
 224         case 1:
 225                 return NI_GPCT1_SUBDEV;
 226         default:
 227                 break;
 228         }
 229         BUG();
 230         return NI_GPCT0_SUBDEV;
 231 }
 232
 233 enum timebase_nanoseconds {
 234         TIMEBASE_1_NS = 50,
 235         TIMEBASE_2_NS = 10000
 236 };
 237
 238 #define SERIAL_DISABLED         0
 239 #define SERIAL_600NS            600
 240 #define SERIAL_1_2US            1200
 241 #define SERIAL_10US                     10000
 242
 243 static const int num_adc_stages_611x = 3;
 244
 245 static void ni_writel(struct comedi_device *dev, uint32_t data, int reg)
 246 {
 247         if (dev->mmio)
 248                 writel(data, dev->mmio + reg);
 249         else
 250                 outl(data, dev->iobase + reg);
 251 }
 252
 253 static void ni_writew(struct comedi_device *dev, uint16_t data, int reg)
 254 {
 255         if (dev->mmio)
 256                 writew(data, dev->mmio + reg);
 257         else
 258                 outw(data, dev->iobase + reg);
 259 }
 260
 261 static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg)
 262 {
 263         if (dev->mmio)
 264                 writeb(data, dev->mmio + reg);
 265         else
 266                 outb(data, dev->iobase + reg);
 267 }
 268
 269 static uint32_t ni_readl(struct comedi_device *dev, int reg)
 270 {
 271         if (dev->mmio)
 272                 return readl(dev->mmio + reg);
 273
 274         return inl(dev->iobase + reg);
 275 }
 276
 277 static uint16_t ni_readw(struct comedi_device *dev, int reg)
 278 {
 279         if (dev->mmio)
 280                 return readw(dev->mmio + reg);
 281
 282         return inw(dev->iobase + reg);
 283 }
 284
 285 static uint8_t ni_readb(struct comedi_device *dev, int reg)
 286 {
 287         if (dev->mmio)
 288                 return readb(dev->mmio + reg);
 289
 290         return inb(dev->iobase + reg);
 291 }
 292
 293 /*
 294  * We automatically take advantage of STC registers that can be
 295  * read/written directly in the I/O space of the board.
 296  *
 297  * The AT-MIO and DAQCard devices map the low 8 STC registers to
 298  * iobase+reg*2.
 299  *
 300  * Most PCIMIO devices also map the low 8 STC registers but the
 301  * 611x devices map the read registers to iobase+(addr-1)*2.
 302  * For now non-windowed STC access is disabled if a PCIMIO device
 303  * is detected (devpriv->mite has been initialized).
 304  *
 305  * The M series devices do not used windowed registers for the
 306  * STC registers. The functions below handle the mapping of the
 307  * windowed STC registers to the m series register offsets.
 308  */
 309
 310 struct mio_regmap {
 311         unsigned int mio_reg;
 312         int size;
 313 };
 314
 315 static const struct mio_regmap m_series_stc_write_regmap[] = {
 316         [NISTC_INTA_ACK_REG]            = { 0x104, 2 },
 317         [NISTC_INTB_ACK_REG]            = { 0x106, 2 },
 318         [NISTC_AI_CMD2_REG]             = { 0x108, 2 },
 319         [NISTC_AO_CMD2_REG]             = { 0x10a, 2 },
 320         [NISTC_G0_CMD_REG]              = { 0x10c, 2 },
 321         [NISTC_G1_CMD_REG]              = { 0x10e, 2 },
 322         [NISTC_AI_CMD1_REG]             = { 0x110, 2 },
 323         [NISTC_AO_CMD1_REG]             = { 0x112, 2 },
 324         /*
 325          * NISTC_DIO_OUT_REG maps to:
 326          * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
 327          */
 328         [NISTC_DIO_OUT_REG]             = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 329         [NISTC_DIO_CTRL_REG]            = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 330         [NISTC_AI_MODE1_REG]            = { 0x118, 2 },
 331         [NISTC_AI_MODE2_REG]            = { 0x11a, 2 },
 332         [NISTC_AI_SI_LOADA_REG]         = { 0x11c, 4 },
 333         [NISTC_AI_SI_LOADB_REG]         = { 0x120, 4 },
 334         [NISTC_AI_SC_LOADA_REG]         = { 0x124, 4 },
 335         [NISTC_AI_SC_LOADB_REG]         = { 0x128, 4 },
 336         [NISTC_AI_SI2_LOADA_REG]        = { 0x12c, 4 },
 337         [NISTC_AI_SI2_LOADB_REG]        = { 0x130, 4 },
 338         [NISTC_G0_MODE_REG]             = { 0x134, 2 },
 339         [NISTC_G1_MODE_REG]             = { 0x136, 2 },
 340         [NISTC_G0_LOADA_REG]            = { 0x138, 4 },
 341         [NISTC_G0_LOADB_REG]            = { 0x13c, 4 },
 342         [NISTC_G1_LOADA_REG]            = { 0x140, 4 },
 343         [NISTC_G1_LOADB_REG]            = { 0x144, 4 },
 344         [NISTC_G0_INPUT_SEL_REG]        = { 0x148, 2 },
 345         [NISTC_G1_INPUT_SEL_REG]        = { 0x14a, 2 },
 346         [NISTC_AO_MODE1_REG]            = { 0x14c, 2 },
 347         [NISTC_AO_MODE2_REG]            = { 0x14e, 2 },
 348         [NISTC_AO_UI_LOADA_REG]         = { 0x150, 4 },
 349         [NISTC_AO_UI_LOADB_REG]         = { 0x154, 4 },
 350         [NISTC_AO_BC_LOADA_REG]         = { 0x158, 4 },
 351         [NISTC_AO_BC_LOADB_REG]         = { 0x15c, 4 },
 352         [NISTC_AO_UC_LOADA_REG]         = { 0x160, 4 },
 353         [NISTC_AO_UC_LOADB_REG]         = { 0x164, 4 },
 354         [NISTC_CLK_FOUT_REG]            = { 0x170, 2 },
 355         [NISTC_IO_BIDIR_PIN_REG]        = { 0x172, 2 },
 356         [NISTC_RTSI_TRIG_DIR_REG]       = { 0x174, 2 },
 357         [NISTC_INT_CTRL_REG]            = { 0x176, 2 },
 358         [NISTC_AI_OUT_CTRL_REG]         = { 0x178, 2 },
 359         [NISTC_ATRIG_ETC_REG]           = { 0x17a, 2 },
 360         [NISTC_AI_START_STOP_REG]       = { 0x17c, 2 },
 361         [NISTC_AI_TRIG_SEL_REG]         = { 0x17e, 2 },
 362         [NISTC_AI_DIV_LOADA_REG]        = { 0x180, 4 },
 363         [NISTC_AO_START_SEL_REG]        = { 0x184, 2 },
 364         [NISTC_AO_TRIG_SEL_REG]         = { 0x186, 2 },
 365         [NISTC_G0_AUTOINC_REG]          = { 0x188, 2 },
 366         [NISTC_G1_AUTOINC_REG]          = { 0x18a, 2 },
 367         [NISTC_AO_MODE3_REG]            = { 0x18c, 2 },
 368         [NISTC_RESET_REG]               = { 0x190, 2 },
 369         [NISTC_INTA_ENA_REG]            = { 0x192, 2 },
 370         [NISTC_INTA2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 371         [NISTC_INTB_ENA_REG]            = { 0x196, 2 },
 372         [NISTC_INTB2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 373         [NISTC_AI_PERSONAL_REG]         = { 0x19a, 2 },
 374         [NISTC_AO_PERSONAL_REG]         = { 0x19c, 2 },
 375         [NISTC_RTSI_TRIGA_OUT_REG]      = { 0x19e, 2 },
 376         [NISTC_RTSI_TRIGB_OUT_REG]      = { 0x1a0, 2 },
 377         [NISTC_RTSI_BOARD_REG]          = { 0, 0 }, /* Unknown */
 378         [NISTC_CFG_MEM_CLR_REG]         = { 0x1a4, 2 },
 379         [NISTC_ADC_FIFO_CLR_REG]        = { 0x1a6, 2 },
 380         [NISTC_DAC_FIFO_CLR_REG]        = { 0x1a8, 2 },
 381         [NISTC_AO_OUT_CTRL_REG]         = { 0x1ac, 2 },
 382         [NISTC_AI_MODE3_REG]            = { 0x1ae, 2 },
 383 };
 384
 385 static void m_series_stc_write(struct comedi_device *dev,
 386                                unsigned int data, unsigned int reg)
 387 {
 388         const struct mio_regmap *regmap;
 389
 390         if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
 391                 regmap = &m_series_stc_write_regmap[reg];
 392         } else {
 393                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 394                          __func__, reg);
 395                 return;
 396         }
 397
 398         switch (regmap->size) {
 399         case 4:
 400                 ni_writel(dev, data, regmap->mio_reg);
 401                 break;
 402         case 2:
 403                 ni_writew(dev, data, regmap->mio_reg);
 404                 break;
 405         default:
 406                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 407                          __func__, reg);
 408                 break;
 409         }
 410 }
 411
 412 static const struct mio_regmap m_series_stc_read_regmap[] = {
 413         [NISTC_AI_STATUS1_REG]          = { 0x104, 2 },
 414         [NISTC_AO_STATUS1_REG]          = { 0x106, 2 },
 415         [NISTC_G01_STATUS_REG]          = { 0x108, 2 },
 416         [NISTC_AI_STATUS2_REG]          = { 0, 0 }, /* Unknown */
 417         [NISTC_AO_STATUS2_REG]          = { 0x10c, 2 },
 418         [NISTC_DIO_IN_REG]              = { 0, 0 }, /* Unknown */
 419         [NISTC_G0_HW_SAVE_REG]          = { 0x110, 4 },
 420         [NISTC_G1_HW_SAVE_REG]          = { 0x114, 4 },
 421         [NISTC_G0_SAVE_REG]             = { 0x118, 4 },
 422         [NISTC_G1_SAVE_REG]             = { 0x11c, 4 },
 423         [NISTC_AO_UI_SAVE_REG]          = { 0x120, 4 },
 424         [NISTC_AO_BC_SAVE_REG]          = { 0x124, 4 },
 425         [NISTC_AO_UC_SAVE_REG]          = { 0x128, 4 },
 426         [NISTC_STATUS1_REG]             = { 0x136, 2 },
 427         [NISTC_DIO_SERIAL_IN_REG]       = { 0x009, 1 },
 428         [NISTC_STATUS2_REG]             = { 0x13a, 2 },
 429         [NISTC_AI_SI_SAVE_REG]          = { 0x180, 4 },
 430         [NISTC_AI_SC_SAVE_REG]          = { 0x184, 4 },
 431 };
 432
 433 static unsigned int m_series_stc_read(struct comedi_device *dev,
 434                                       unsigned int reg)
 435 {
 436         const struct mio_regmap *regmap;
 437
 438         if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
 439                 regmap = &m_series_stc_read_regmap[reg];
 440         } else {
 441                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 442                          __func__, reg);
 443                 return 0;
 444         }
 445
 446         switch (regmap->size) {
 447         case 4:
 448                 return ni_readl(dev, regmap->mio_reg);
 449         case 2:
 450                 return ni_readw(dev, regmap->mio_reg);
 451         case 1:
 452                 return ni_readb(dev, regmap->mio_reg);
 453         default:
 454                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 455                          __func__, reg);
 456                 return 0;
 457         }
 458 }
 459
 460 static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
 461 {
 462         struct ni_private *devpriv = dev->private;
 463         unsigned long flags;
 464
 465         if (devpriv->is_m_series) {
 466                 m_series_stc_write(dev, data, reg);
 467         } else {
 468                 spin_lock_irqsave(&devpriv->window_lock, flags);
 469                 if (!devpriv->mite && reg < 8) {
 470                         ni_writew(dev, data, reg * 2);
 471                 } else {
 472                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 473                         ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
 474                 }
 475                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 476         }
 477 }
 478
 479 static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
 480 {
 481         struct ni_private *devpriv = dev->private;
 482
 483         if (devpriv->is_m_series) {
 484                 m_series_stc_write(dev, data, reg);
 485         } else {
 486                 ni_stc_writew(dev, data >> 16, reg);
 487                 ni_stc_writew(dev, data & 0xffff, reg + 1);
 488         }
 489 }
 490
 491 static uint16_t ni_stc_readw(struct comedi_device *dev, int reg)
 492 {
 493         struct ni_private *devpriv = dev->private;
 494         unsigned long flags;
 495         uint16_t val;
 496
 497         if (devpriv->is_m_series) {
 498                 val = m_series_stc_read(dev, reg);
 499         } else {
 500                 spin_lock_irqsave(&devpriv->window_lock, flags);
 501                 if (!devpriv->mite && reg < 8) {
 502                         val = ni_readw(dev, reg * 2);
 503                 } else {
 504                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 505                         val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
 506                 }
 507                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 508         }
 509         return val;
 510 }
 511
 512 static uint32_t ni_stc_readl(struct comedi_device *dev, int reg)
 513 {
 514         struct ni_private *devpriv = dev->private;
 515         uint32_t val;
 516
 517         if (devpriv->is_m_series) {
 518                 val = m_series_stc_read(dev, reg);
 519         } else {
 520                 val = ni_stc_readw(dev, reg) << 16;
 521                 val |= ni_stc_readw(dev, reg + 1);
 522         }
 523         return val;
 524 }
 525
 526 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 527                                    unsigned bit_mask, unsigned bit_values)
 528 {
 529         struct ni_private *devpriv = dev->private;
 530         unsigned long flags;
 531
 532         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 533         switch (reg) {
 534         case NISTC_INTA_ENA_REG:
 535                 devpriv->int_a_enable_reg &= ~bit_mask;
 536                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 537                 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
 538                 break;
 539         case NISTC_INTB_ENA_REG:
 540                 devpriv->int_b_enable_reg &= ~bit_mask;
 541                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 542                 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
 543                 break;
 544         case NISTC_IO_BIDIR_PIN_REG:
 545                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 546                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 547                 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
 548                 break;
 549         case NI_E_DMA_AI_AO_SEL_REG:
 550                 devpriv->ai_ao_select_reg &= ~bit_mask;
 551                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 552                 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
 553                 break;
 554         case NI_E_DMA_G0_G1_SEL_REG:
 555                 devpriv->g0_g1_select_reg &= ~bit_mask;
 556                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 557                 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
 558                 break;
 559         default:
 560                 dev_err(dev->class_dev, "called with invalid register %d\n",
 561                         reg);
 562                 break;
 563         }
 564         mmiowb();
 565         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 566 }
 567
 568 #ifdef PCIDMA
 569 /* DMA channel setup */
 570 static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel)
 571 {
 572         if (channel < 4)
 573                 return 1 << channel;
 574         if (channel == 4)
 575                 return 0x3;
 576         if (channel == 5)
 577                 return 0x5;
 578         BUG();
 579         return 0;
 580 }
 581
 582 static inline void ni_set_ai_dma_channel(struct comedi_device *dev,
 583                                          unsigned channel)
 584 {
 585         unsigned bits = ni_stc_dma_channel_select_bitfield(channel);
 586
 587         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 588                         NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
 589 }
 590
 591 static inline void ni_set_ai_dma_no_channel(struct comedi_device *dev)
 592 {
 593         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, NI_E_DMA_AI_SEL_MASK, 0);
 594 }
 595
 596 static inline void ni_set_ao_dma_channel(struct comedi_device *dev,
 597                                          unsigned channel)
 598 {
 599         unsigned bits = ni_stc_dma_channel_select_bitfield(channel);
 600
 601         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 602                         NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
 603 }
 604
 605 static inline void ni_set_ao_dma_no_channel(struct comedi_device *dev)
 606 {
 607         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG, NI_E_DMA_AO_SEL_MASK, 0);
 608 }
 609
 610 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
 611                                            unsigned gpct_index,
 612                                            unsigned channel)
 613 {
 614         unsigned bits = ni_stc_dma_channel_select_bitfield(channel);
 615
 616         ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 617                         NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
 618                         NI_E_DMA_G0_G1_SEL(gpct_index, bits));
 619 }
 620
 621 static inline void ni_set_gpct_dma_no_channel(struct comedi_device *dev,
 622                                               unsigned gpct_index)
 623 {
 624         ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 625                         NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0);
 626 }
 627
 628 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
 629                                           unsigned mite_channel)
 630 {
 631         struct ni_private *devpriv = dev->private;
 632         unsigned long flags;
 633         unsigned bits;
 634
 635         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 636         devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK;
 637         /*
 638          * XXX just guessing ni_stc_dma_channel_select_bitfield()
 639          * returns the right bits, under the assumption the cdio dma
 640          * selection works just like ai/ao/gpct.
 641          * Definitely works for dma channels 0 and 1.
 642          */
 643         bits = ni_stc_dma_channel_select_bitfield(mite_channel);
 644         devpriv->cdio_dma_select_reg |= NI_M_CDIO_DMA_SEL_CDO(bits);
 645         ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
 646         mmiowb();
 647         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 648 }
 649
 650 static inline void ni_set_cdo_dma_no_channel(struct comedi_device *dev)
 651 {
 652         struct ni_private *devpriv = dev->private;
 653         unsigned long flags;
 654
 655         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 656         devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK;
 657         ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
 658         mmiowb();
 659         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 660 }
 661
 662 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 663 {
 664         struct ni_private *devpriv = dev->private;
 665         unsigned long flags;
 666
 667         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 668         BUG_ON(devpriv->ai_mite_chan);
 669         devpriv->ai_mite_chan =
 670             mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 671         if (!devpriv->ai_mite_chan) {
 672                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 673                 dev_err(dev->class_dev,
 674                         "failed to reserve mite dma channel for analog input\n");
 675                 return -EBUSY;
 676         }
 677         devpriv->ai_mite_chan->dir = COMEDI_INPUT;
 678         ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
 679         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 680         return 0;
 681 }
 682
 683 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 684 {
 685         struct ni_private *devpriv = dev->private;
 686         unsigned long flags;
 687
 688         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 689         BUG_ON(devpriv->ao_mite_chan);
 690         devpriv->ao_mite_chan =
 691             mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 692         if (!devpriv->ao_mite_chan) {
 693                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 694                 dev_err(dev->class_dev,
 695                         "failed to reserve mite dma channel for analog outut\n");
 696                 return -EBUSY;
 697         }
 698         devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
 699         ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
 700         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 701         return 0;
 702 }
 703
 704 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 705                                         unsigned gpct_index,
 706                                         enum comedi_io_direction direction)
 707 {
 708         struct ni_private *devpriv = dev->private;
 709         unsigned long flags;
 710         struct mite_channel *mite_chan;
 711
 712         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 713         BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
 714         mite_chan =
 715             mite_request_channel(devpriv->mite,
 716                                  devpriv->gpct_mite_ring[gpct_index]);
 717         if (!mite_chan) {
 718                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 719                 dev_err(dev->class_dev,
 720                         "failed to reserve mite dma channel for counter\n");
 721                 return -EBUSY;
 722         }
 723         mite_chan->dir = direction;
 724         ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 725                                 mite_chan);
 726         ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
 727         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 728         return 0;
 729 }
 730
 731 #endif /*  PCIDMA */
 732
 733 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 734 {
 735 #ifdef PCIDMA
 736         struct ni_private *devpriv = dev->private;
 737         unsigned long flags;
 738
 739         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 740         BUG_ON(devpriv->cdo_mite_chan);
 741         devpriv->cdo_mite_chan =
 742             mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 743         if (!devpriv->cdo_mite_chan) {
 744                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 745                 dev_err(dev->class_dev,
 746                         "failed to reserve mite dma channel for correlated digital output\n");
 747                 return -EBUSY;
 748         }
 749         devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
 750         ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
 751         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 752 #endif /*  PCIDMA */
 753         return 0;
 754 }
 755
 756 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 757 {
 758 #ifdef PCIDMA
 759         struct ni_private *devpriv = dev->private;
 760         unsigned long flags;
 761
 762         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 763         if (devpriv->ai_mite_chan) {
 764                 ni_set_ai_dma_no_channel(dev);
 765                 mite_release_channel(devpriv->ai_mite_chan);
 766                 devpriv->ai_mite_chan = NULL;
 767         }
 768         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 769 #endif /*  PCIDMA */
 770 }
 771
 772 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 773 {
 774 #ifdef PCIDMA
 775         struct ni_private *devpriv = dev->private;
 776         unsigned long flags;
 777
 778         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 779         if (devpriv->ao_mite_chan) {
 780                 ni_set_ao_dma_no_channel(dev);
 781                 mite_release_channel(devpriv->ao_mite_chan);
 782                 devpriv->ao_mite_chan = NULL;
 783         }
 784         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 785 #endif /*  PCIDMA */
 786 }
 787
 788 #ifdef PCIDMA
 789 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 790                                          unsigned gpct_index)
 791 {
 792         struct ni_private *devpriv = dev->private;
 793         unsigned long flags;
 794
 795         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 796         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 797                 struct mite_channel *mite_chan =
 798                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 799
 800                 ni_set_gpct_dma_no_channel(dev, gpct_index);
 801                 ni_tio_set_mite_channel(&devpriv->
 802                                         counter_dev->counters[gpct_index],
 803                                         NULL);
 804                 mite_release_channel(mite_chan);
 805         }
 806         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 807 }
 808 #endif /*  PCIDMA */
 809
 810 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 811 {
 812 #ifdef PCIDMA
 813         struct ni_private *devpriv = dev->private;
 814         unsigned long flags;
 815
 816         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 817         if (devpriv->cdo_mite_chan) {
 818                 ni_set_cdo_dma_no_channel(dev);
 819                 mite_release_channel(devpriv->cdo_mite_chan);
 820                 devpriv->cdo_mite_chan = NULL;
 821         }
 822         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 823 #endif /*  PCIDMA */
 824 }
 825
 826 #ifdef PCIDMA
 827 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 828                                           unsigned gpct_index, short enable)
 829 {
 830         struct ni_private *devpriv = dev->private;
 831         uint16_t val = 0;
 832         int reg;
 833
 834         if (devpriv->is_m_series || gpct_index > 1)
 835                 return;
 836
 837         /*
 838          * e-series boards use the second irq signals to generate
 839          * dma requests for their counters
 840          */
 841         if (gpct_index == 0) {
 842                 reg = NISTC_INTA2_ENA_REG;
 843                 if (enable)
 844                         val = NISTC_INTA_ENA_G0_GATE;
 845         } else {
 846                 reg = NISTC_INTB2_ENA_REG;
 847                 if (enable)
 848                         val = NISTC_INTB_ENA_G1_GATE;
 849         }
 850         ni_stc_writew(dev, val, reg);
 851 }
 852 #endif /*  PCIDMA */
 853
 854 static void ni_clear_ai_fifo(struct comedi_device *dev)
 855 {
 856         struct ni_private *devpriv = dev->private;
 857         static const int timeout = 10000;
 858         int i;
 859
 860         if (devpriv->is_6143) {
 861                 /*  Flush the 6143 data FIFO */
 862                 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
 863                 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
 864                 /*  Wait for complete */
 865                 for (i = 0; i < timeout; i++) {
 866                         if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
 867                                 break;
 868                         udelay(1);
 869                 }
 870                 if (i == timeout)
 871                         dev_err(dev->class_dev, "FIFO flush timeout\n");
 872         } else {
 873                 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
 874                 if (devpriv->is_625x) {
 875                         ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
 876                         ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
 877 #if 0
 878                         /* the NI example code does 3 convert pulses for 625x boards,
 879                            but that appears to be wrong in practice. */
 880                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 881                                       NISTC_AI_CMD1_REG);
 882                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 883                                       NISTC_AI_CMD1_REG);
 884                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 885                                       NISTC_AI_CMD1_REG);
 886 #endif
 887                 }
 888         }
 889 }
 890
 891 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
 892                                   int addr)
 893 {
 894         struct ni_private *devpriv = dev->private;
 895         unsigned long flags;
 896
 897         spin_lock_irqsave(&devpriv->window_lock, flags);
 898         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 899         ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
 900         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 901 }
 902
 903 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
 904                                   int addr)
 905 {
 906         struct ni_private *devpriv = dev->private;
 907         unsigned long flags;
 908
 909         spin_lock_irqsave(&devpriv->window_lock, flags);
 910         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 911         ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
 912         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 913 }
 914
 915 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 916 {
 917         struct ni_private *devpriv = dev->private;
 918         unsigned long flags;
 919         unsigned short data;
 920
 921         spin_lock_irqsave(&devpriv->window_lock, flags);
 922         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 923         data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
 924         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 925         return data;
 926 }
 927
 928 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
 929 * share registers (such as Interrupt_A_Register) without interfering with
 930 * each other.
 931 *
 932 * NOTE: the switch/case statements are optimized out for a constant argument
 933 * so this is actually quite fast---  If you must wrap another function around this
 934 * make it inline to avoid a large speed penalty.
 935 *
 936 * value should only be 1 or 0.
 937 */
 938 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 939                                unsigned bits, unsigned value)
 940 {
 941         unsigned bit_values;
 942
 943         if (value)
 944                 bit_values = bits;
 945         else
 946                 bit_values = 0;
 947         ni_set_bitfield(dev, reg, bits, bit_values);
 948 }
 949
 950 #ifdef PCIDMA
 951 static void ni_sync_ai_dma(struct comedi_device *dev)
 952 {
 953         struct ni_private *devpriv = dev->private;
 954         struct comedi_subdevice *s = dev->read_subdev;
 955         unsigned long flags;
 956
 957         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 958         if (devpriv->ai_mite_chan)
 959                 mite_sync_input_dma(devpriv->ai_mite_chan, s);
 960         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 961 }
 962
 963 static int ni_ai_drain_dma(struct comedi_device *dev)
 964 {
 965         struct ni_private *devpriv = dev->private;
 966         int i;
 967         static const int timeout = 10000;
 968         unsigned long flags;
 969         int retval = 0;
 970
 971         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 972         if (devpriv->ai_mite_chan) {
 973                 for (i = 0; i < timeout; i++) {
 974                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
 975                              NISTC_AI_STATUS1_FIFO_E)
 976                             && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
 977                             0)
 978                                 break;
 979                         udelay(5);
 980                 }
 981                 if (i == timeout) {
 982                         dev_err(dev->class_dev, "timed out\n");
 983                         dev_err(dev->class_dev,
 984                                 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
 985                                 mite_bytes_in_transit(devpriv->ai_mite_chan),
 986                                 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
 987                         retval = -1;
 988                 }
 989         }
 990         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 991
 992         ni_sync_ai_dma(dev);
 993
 994         return retval;
 995 }
 996
 997 static void mite_handle_b_linkc(struct mite_struct *mite,
 998                                 struct comedi_device *dev)
 999 {
1000         struct ni_private *devpriv = dev->private;
1001         struct comedi_subdevice *s = dev->write_subdev;
1002         unsigned long flags;
1003
1004         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1005         if (devpriv->ao_mite_chan)
1006                 mite_sync_output_dma(devpriv->ao_mite_chan, s);
1007         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1008 }
1009
1010 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
1011 {
1012         static const int timeout = 10000;
1013         int i;
1014
1015         for (i = 0; i < timeout; i++) {
1016                 unsigned short b_status;
1017
1018                 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
1019                 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
1020                         break;
1021                 /* if we poll too often, the pci bus activity seems
1022                    to slow the dma transfer down */
1023                 udelay(10);
1024         }
1025         if (i == timeout) {
1026                 dev_err(dev->class_dev, "timed out waiting for dma load\n");
1027                 return -EPIPE;
1028         }
1029         return 0;
1030 }
1031 #endif /* PCIDMA */
1032
1033 #ifndef PCIDMA
1034
1035 static void ni_ao_fifo_load(struct comedi_device *dev,
1036                             struct comedi_subdevice *s, int n)
1037 {
1038         struct ni_private *devpriv = dev->private;
1039         int i;
1040         unsigned short d;
1041         u32 packed_data;
1042
1043         for (i = 0; i < n; i++) {
1044                 comedi_buf_read_samples(s, &d, 1);
1045
1046                 if (devpriv->is_6xxx) {
1047                         packed_data = d & 0xffff;
1048                         /* 6711 only has 16 bit wide ao fifo */
1049                         if (!devpriv->is_6711) {
1050                                 comedi_buf_read_samples(s, &d, 1);
1051                                 i++;
1052                                 packed_data |= (d << 16) & 0xffff0000;
1053                         }
1054                         ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
1055                 } else {
1056                         ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
1057                 }
1058         }
1059 }
1060
1061 /*
1062  *  There's a small problem if the FIFO gets really low and we
1063  *  don't have the data to fill it.  Basically, if after we fill
1064  *  the FIFO with all the data available, the FIFO is _still_
1065  *  less than half full, we never clear the interrupt.  If the
1066  *  IRQ is in edge mode, we never get another interrupt, because
1067  *  this one wasn't cleared.  If in level mode, we get flooded
1068  *  with interrupts that we can't fulfill, because nothing ever
1069  *  gets put into the buffer.
1070  *
1071  *  This kind of situation is recoverable, but it is easier to
1072  *  just pretend we had a FIFO underrun, since there is a good
1073  *  chance it will happen anyway.  This is _not_ the case for
1074  *  RT code, as RT code might purposely be running close to the
1075  *  metal.  Needs to be fixed eventually.
1076  */
1077 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1078                                  struct comedi_subdevice *s)
1079 {
1080         const struct ni_board_struct *board = dev->board_ptr;
1081         unsigned int nbytes;
1082         unsigned int nsamples;
1083
1084         nbytes = comedi_buf_read_n_available(s);
1085         if (nbytes == 0) {
1086                 s->async->events |= COMEDI_CB_OVERFLOW;
1087                 return 0;
1088         }
1089
1090         nsamples = comedi_bytes_to_samples(s, nbytes);
1091         if (nsamples > board->ao_fifo_depth / 2)
1092                 nsamples = board->ao_fifo_depth / 2;
1093
1094         ni_ao_fifo_load(dev, s, nsamples);
1095
1096         return 1;
1097 }
1098
1099 static int ni_ao_prep_fifo(struct comedi_device *dev,
1100                            struct comedi_subdevice *s)
1101 {
1102         const struct ni_board_struct *board = dev->board_ptr;
1103         struct ni_private *devpriv = dev->private;
1104         unsigned int nbytes;
1105         unsigned int nsamples;
1106
1107         /* reset fifo */
1108         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1109         if (devpriv->is_6xxx)
1110                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1111
1112         /* load some data */
1113         nbytes = comedi_buf_read_n_available(s);
1114         if (nbytes == 0)
1115                 return 0;
1116
1117         nsamples = comedi_bytes_to_samples(s, nbytes);
1118         if (nsamples > board->ao_fifo_depth)
1119                 nsamples = board->ao_fifo_depth;
1120
1121         ni_ao_fifo_load(dev, s, nsamples);
1122
1123         return nsamples;
1124 }
1125
1126 static void ni_ai_fifo_read(struct comedi_device *dev,
1127                             struct comedi_subdevice *s, int n)
1128 {
1129         struct ni_private *devpriv = dev->private;
1130         struct comedi_async *async = s->async;
1131         u32 dl;
1132         unsigned short data;
1133         int i;
1134
1135         if (devpriv->is_611x) {
1136                 for (i = 0; i < n / 2; i++) {
1137                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1138                         /* This may get the hi/lo data in the wrong order */
1139                         data = (dl >> 16) & 0xffff;
1140                         comedi_buf_write_samples(s, &data, 1);
1141                         data = dl & 0xffff;
1142                         comedi_buf_write_samples(s, &data, 1);
1143                 }
1144                 /* Check if there's a single sample stuck in the FIFO */
1145                 if (n % 2) {
1146                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1147                         data = dl & 0xffff;
1148                         comedi_buf_write_samples(s, &data, 1);
1149                 }
1150         } else if (devpriv->is_6143) {
1151                 /*  This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1152                 for (i = 0; i < n / 2; i++) {
1153                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1154
1155                         data = (dl >> 16) & 0xffff;
1156                         comedi_buf_write_samples(s, &data, 1);
1157                         data = dl & 0xffff;
1158                         comedi_buf_write_samples(s, &data, 1);
1159                 }
1160                 if (n % 2) {
1161                         /* Assume there is a single sample stuck in the FIFO */
1162                         /* Get stranded sample into FIFO */
1163                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1164                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1165                         data = (dl >> 16) & 0xffff;
1166                         comedi_buf_write_samples(s, &data, 1);
1167                 }
1168         } else {
1169                 if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) {
1170                         dev_err(dev->class_dev,
1171                                 "bug! ai_fifo_buffer too small\n");
1172                         async->events |= COMEDI_CB_ERROR;
1173                         return;
1174                 }
1175                 for (i = 0; i < n; i++) {
1176                         devpriv->ai_fifo_buffer[i] =
1177                             ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1178                 }
1179                 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1180         }
1181 }
1182
1183 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1184 {
1185         const struct ni_board_struct *board = dev->board_ptr;
1186         struct comedi_subdevice *s = dev->read_subdev;
1187         int n;
1188
1189         n = board->ai_fifo_depth / 2;
1190
1191         ni_ai_fifo_read(dev, s, n);
1192 }
1193 #endif
1194
1195 /*
1196    Empties the AI fifo
1197 */
1198 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1199 {
1200         struct ni_private *devpriv = dev->private;
1201         struct comedi_subdevice *s = dev->read_subdev;
1202         u32 dl;
1203         unsigned short data;
1204         unsigned short fifo_empty;
1205         int i;
1206
1207         if (devpriv->is_611x) {
1208                 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1209                         NISTC_AI_STATUS1_FIFO_E) == 0) {
1210                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1211
1212                         /* This may get the hi/lo data in the wrong order */
1213                         data = dl >> 16;
1214                         comedi_buf_write_samples(s, &data, 1);
1215                         data = dl & 0xffff;
1216                         comedi_buf_write_samples(s, &data, 1);
1217                 }
1218         } else if (devpriv->is_6143) {
1219                 i = 0;
1220                 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1221                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1222
1223                         /* This may get the hi/lo data in the wrong order */
1224                         data = dl >> 16;
1225                         comedi_buf_write_samples(s, &data, 1);
1226                         data = dl & 0xffff;
1227                         comedi_buf_write_samples(s, &data, 1);
1228                         i += 2;
1229                 }
1230                 /*  Check if stranded sample is present */
1231                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1232                         /* Get stranded sample into FIFO */
1233                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1234                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1235                         data = (dl >> 16) & 0xffff;
1236                         comedi_buf_write_samples(s, &data, 1);
1237                 }
1238
1239         } else {
1240                 fifo_empty = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1241                              NISTC_AI_STATUS1_FIFO_E;
1242                 while (fifo_empty == 0) {
1243                         for (i = 0;
1244                              i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) {
1245                                 fifo_empty = ni_stc_readw(dev,
1246                                                           NISTC_AI_STATUS1_REG) &
1247                                                 NISTC_AI_STATUS1_FIFO_E;
1248                                 if (fifo_empty)
1249                                         break;
1250                                 devpriv->ai_fifo_buffer[i] =
1251                                     ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1252                         }
1253                         comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1254                 }
1255         }
1256 }
1257
1258 static void get_last_sample_611x(struct comedi_device *dev)
1259 {
1260         struct ni_private *devpriv = dev->private;
1261         struct comedi_subdevice *s = dev->read_subdev;
1262         unsigned short data;
1263         u32 dl;
1264
1265         if (!devpriv->is_611x)
1266                 return;
1267
1268         /* Check if there's a single sample stuck in the FIFO */
1269         if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1270                 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1271                 data = dl & 0xffff;
1272                 comedi_buf_write_samples(s, &data, 1);
1273         }
1274 }
1275
1276 static void get_last_sample_6143(struct comedi_device *dev)
1277 {
1278         struct ni_private *devpriv = dev->private;
1279         struct comedi_subdevice *s = dev->read_subdev;
1280         unsigned short data;
1281         u32 dl;
1282
1283         if (!devpriv->is_6143)
1284                 return;
1285
1286         /* Check if there's a single sample stuck in the FIFO */
1287         if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1288                 /* Get stranded sample into FIFO */
1289                 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1290                 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1291
1292                 /* This may get the hi/lo data in the wrong order */
1293                 data = (dl >> 16) & 0xffff;
1294                 comedi_buf_write_samples(s, &data, 1);
1295         }
1296 }
1297
1298 static void shutdown_ai_command(struct comedi_device *dev)
1299 {
1300         struct comedi_subdevice *s = dev->read_subdev;
1301
1302 #ifdef PCIDMA
1303         ni_ai_drain_dma(dev);
1304 #endif
1305         ni_handle_fifo_dregs(dev);
1306         get_last_sample_611x(dev);
1307         get_last_sample_6143(dev);
1308
1309         s->async->events |= COMEDI_CB_EOA;
1310 }
1311
1312 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1313 {
1314         struct ni_private *devpriv = dev->private;
1315
1316         if (devpriv->aimode == AIMODE_SCAN) {
1317 #ifdef PCIDMA
1318                 static const int timeout = 10;
1319                 int i;
1320
1321                 for (i = 0; i < timeout; i++) {
1322                         ni_sync_ai_dma(dev);
1323                         if ((s->async->events & COMEDI_CB_EOS))
1324                                 break;
1325                         udelay(1);
1326                 }
1327 #else
1328                 ni_handle_fifo_dregs(dev);
1329                 s->async->events |= COMEDI_CB_EOS;
1330 #endif
1331         }
1332         /* handle special case of single scan */
1333         if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1334                 shutdown_ai_command(dev);
1335 }
1336
1337 static void handle_gpct_interrupt(struct comedi_device *dev,
1338                                   unsigned short counter_index)
1339 {
1340 #ifdef PCIDMA
1341         struct ni_private *devpriv = dev->private;
1342         struct comedi_subdevice *s;
1343
1344         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1345
1346         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1347                                 s);
1348         comedi_handle_events(dev, s);
1349 #endif
1350 }
1351
1352 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1353 {
1354         unsigned short ack = 0;
1355
1356         if (a_status & NISTC_AI_STATUS1_SC_TC)
1357                 ack |= NISTC_INTA_ACK_AI_SC_TC;
1358         if (a_status & NISTC_AI_STATUS1_START1)
1359                 ack |= NISTC_INTA_ACK_AI_START1;
1360         if (a_status & NISTC_AI_STATUS1_START)
1361                 ack |= NISTC_INTA_ACK_AI_START;
1362         if (a_status & NISTC_AI_STATUS1_STOP)
1363                 ack |= NISTC_INTA_ACK_AI_STOP;
1364         if (ack)
1365                 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1366 }
1367
1368 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1369                                unsigned ai_mite_status)
1370 {
1371         struct comedi_subdevice *s = dev->read_subdev;
1372         struct comedi_cmd *cmd = &s->async->cmd;
1373
1374         /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1375         if (s->type == COMEDI_SUBD_UNUSED)
1376                 return;
1377
1378 #ifdef PCIDMA
1379         if (ai_mite_status & CHSR_LINKC)
1380                 ni_sync_ai_dma(dev);
1381
1382         if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1383                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1384                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1385                 dev_err(dev->class_dev,
1386                         "unknown mite interrupt (ai_mite_status=%08x)\n",
1387                         ai_mite_status);
1388                 s->async->events |= COMEDI_CB_ERROR;
1389                 /* disable_irq(dev->irq); */
1390         }
1391 #endif
1392
1393         /* test for all uncommon interrupt events at the same time */
1394         if (status & (NISTC_AI_STATUS1_ERR |
1395                       NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1396                 if (status == 0xffff) {
1397                         dev_err(dev->class_dev, "Card removed?\n");
1398                         /* we probably aren't even running a command now,
1399                          * so it's a good idea to be careful. */
1400                         if (comedi_is_subdevice_running(s)) {
1401                                 s->async->events |= COMEDI_CB_ERROR;
1402                                 comedi_handle_events(dev, s);
1403                         }
1404                         return;
1405                 }
1406                 if (status & NISTC_AI_STATUS1_ERR) {
1407                         dev_err(dev->class_dev, "ai error a_status=%04x\n",
1408                                 status);
1409
1410                         shutdown_ai_command(dev);
1411
1412                         s->async->events |= COMEDI_CB_ERROR;
1413                         if (status & NISTC_AI_STATUS1_OVER)
1414                                 s->async->events |= COMEDI_CB_OVERFLOW;
1415
1416                         comedi_handle_events(dev, s);
1417                         return;
1418                 }
1419                 if (status & NISTC_AI_STATUS1_SC_TC) {
1420                         if (cmd->stop_src == TRIG_COUNT)
1421                                 shutdown_ai_command(dev);
1422                 }
1423         }
1424 #ifndef PCIDMA
1425         if (status & NISTC_AI_STATUS1_FIFO_HF) {
1426                 int i;
1427                 static const int timeout = 10;
1428                 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1429                  *fail to get the fifo less than half full, so loop to be sure.*/
1430                 for (i = 0; i < timeout; ++i) {
1431                         ni_handle_fifo_half_full(dev);
1432                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1433                              NISTC_AI_STATUS1_FIFO_HF) == 0)
1434                                 break;
1435                 }
1436         }
1437 #endif /*  !PCIDMA */
1438
1439         if (status & NISTC_AI_STATUS1_STOP)
1440                 ni_handle_eos(dev, s);
1441
1442         comedi_handle_events(dev, s);
1443 }
1444
1445 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1446 {
1447         unsigned short ack = 0;
1448
1449         if (b_status & NISTC_AO_STATUS1_BC_TC)
1450                 ack |= NISTC_INTB_ACK_AO_BC_TC;
1451         if (b_status & NISTC_AO_STATUS1_OVERRUN)
1452                 ack |= NISTC_INTB_ACK_AO_ERR;
1453         if (b_status & NISTC_AO_STATUS1_START)
1454                 ack |= NISTC_INTB_ACK_AO_START;
1455         if (b_status & NISTC_AO_STATUS1_START1)
1456                 ack |= NISTC_INTB_ACK_AO_START1;
1457         if (b_status & NISTC_AO_STATUS1_UC_TC)
1458                 ack |= NISTC_INTB_ACK_AO_UC_TC;
1459         if (b_status & NISTC_AO_STATUS1_UI2_TC)
1460                 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1461         if (b_status & NISTC_AO_STATUS1_UPDATE)
1462                 ack |= NISTC_INTB_ACK_AO_UPDATE;
1463         if (ack)
1464                 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1465 }
1466
1467 static void handle_b_interrupt(struct comedi_device *dev,
1468                                unsigned short b_status, unsigned ao_mite_status)
1469 {
1470         struct comedi_subdevice *s = dev->write_subdev;
1471         /* unsigned short ack=0; */
1472
1473 #ifdef PCIDMA
1474         /* Currently, mite.c requires us to handle LINKC */
1475         if (ao_mite_status & CHSR_LINKC) {
1476                 struct ni_private *devpriv = dev->private;
1477
1478                 mite_handle_b_linkc(devpriv->mite, dev);
1479         }
1480
1481         if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1482                                CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1483                                CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1484                 dev_err(dev->class_dev,
1485                         "unknown mite interrupt (ao_mite_status=%08x)\n",
1486                         ao_mite_status);
1487                 s->async->events |= COMEDI_CB_ERROR;
1488         }
1489 #endif
1490
1491         if (b_status == 0xffff)
1492                 return;
1493         if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1494                 dev_err(dev->class_dev,
1495                         "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1496                         b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1497                 s->async->events |= COMEDI_CB_OVERFLOW;
1498         }
1499
1500         if (s->async->cmd.stop_src != TRIG_NONE &&
1501             b_status & NISTC_AO_STATUS1_BC_TC)
1502                 s->async->events |= COMEDI_CB_EOA;
1503
1504 #ifndef PCIDMA
1505         if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1506                 int ret;
1507
1508                 ret = ni_ao_fifo_half_empty(dev, s);
1509                 if (!ret) {
1510                         dev_err(dev->class_dev, "AO buffer underrun\n");
1511                         ni_set_bits(dev, NISTC_INTB_ENA_REG,
1512                                     NISTC_INTB_ENA_AO_FIFO |
1513                                     NISTC_INTB_ENA_AO_ERR, 0);
1514                         s->async->events |= COMEDI_CB_OVERFLOW;
1515                 }
1516         }
1517 #endif
1518
1519         comedi_handle_events(dev, s);
1520 }
1521
1522 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1523                         void *data, unsigned int num_bytes,
1524                         unsigned int chan_index)
1525 {
1526         struct ni_private *devpriv = dev->private;
1527         struct comedi_async *async = s->async;
1528         struct comedi_cmd *cmd = &async->cmd;
1529         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1530         unsigned short *array = data;
1531         unsigned int *larray = data;
1532         unsigned int i;
1533 #ifdef PCIDMA
1534         __le16 *barray = data;
1535         __le32 *blarray = data;
1536 #endif
1537
1538         for (i = 0; i < nsamples; i++) {
1539 #ifdef PCIDMA
1540                 if (s->subdev_flags & SDF_LSAMPL)
1541                         larray[i] = le32_to_cpu(blarray[i]);
1542                 else
1543                         array[i] = le16_to_cpu(barray[i]);
1544 #endif
1545                 if (s->subdev_flags & SDF_LSAMPL)
1546                         larray[i] += devpriv->ai_offset[chan_index];
1547                 else
1548                         array[i] += devpriv->ai_offset[chan_index];
1549                 chan_index++;
1550                 chan_index %= cmd->chanlist_len;
1551         }
1552 }
1553
1554 #ifdef PCIDMA
1555
1556 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1557 {
1558         struct ni_private *devpriv = dev->private;
1559         struct comedi_subdevice *s = dev->read_subdev;
1560         int retval;
1561         unsigned long flags;
1562
1563         retval = ni_request_ai_mite_channel(dev);
1564         if (retval)
1565                 return retval;
1566
1567         /* write alloc the entire buffer */
1568         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1569
1570         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1571         if (!devpriv->ai_mite_chan) {
1572                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1573                 return -EIO;
1574         }
1575
1576         if (devpriv->is_611x || devpriv->is_6143)
1577                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1578         else if (devpriv->is_628x)
1579                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1580         else
1581                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1582
1583         /*start the MITE */
1584         mite_dma_arm(devpriv->ai_mite_chan);
1585         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1586
1587         return 0;
1588 }
1589
1590 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1591 {
1592         struct ni_private *devpriv = dev->private;
1593         struct comedi_subdevice *s = dev->write_subdev;
1594         int retval;
1595         unsigned long flags;
1596
1597         retval = ni_request_ao_mite_channel(dev);
1598         if (retval)
1599                 return retval;
1600
1601         /* read alloc the entire buffer */
1602         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1603
1604         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1605         if (devpriv->ao_mite_chan) {
1606                 if (devpriv->is_611x || devpriv->is_6713) {
1607                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1608                 } else {
1609                         /* doing 32 instead of 16 bit wide transfers from memory
1610                            makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1611                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1612                 }
1613                 mite_dma_arm(devpriv->ao_mite_chan);
1614         } else {
1615                 retval = -EIO;
1616         }
1617         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1618
1619         return retval;
1620 }
1621
1622 #endif /*  PCIDMA */
1623
1624 /*
1625    used for both cancel ioctl and board initialization
1626
1627    this is pretty harsh for a cancel, but it works...
1628  */
1629
1630 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1631 {
1632         struct ni_private *devpriv = dev->private;
1633         unsigned ai_personal;
1634         unsigned ai_out_ctrl;
1635
1636         ni_release_ai_mite_channel(dev);
1637         /* ai configuration */
1638         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1639                       NISTC_RESET_REG);
1640
1641         ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1642
1643         ni_clear_ai_fifo(dev);
1644
1645         if (!devpriv->is_6143)
1646                 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1647
1648         ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1649         ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1650                            NISTC_AI_MODE1_RSVD
1651                             /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1652                       NISTC_AI_MODE1_REG);
1653         ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1654         /* generate FIFO interrupts on non-empty */
1655         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1656                       NISTC_AI_MODE3_REG);
1657
1658         ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1659                       NISTC_AI_PERSONAL_SOC_POLARITY |
1660                       NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1661         ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1662                       NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1663                       NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1664                       NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1665         if (devpriv->is_611x) {
1666                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1667         } else if (devpriv->is_6143) {
1668                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1669         } else {
1670                 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1671                 if (devpriv->is_622x)
1672                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1673                 else
1674                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1675         }
1676         ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1677         ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1678
1679         /* the following registers should not be changed, because there
1680          * are no backup registers in devpriv.  If you want to change
1681          * any of these, add a backup register and other appropriate code:
1682          *      NISTC_AI_MODE1_REG
1683          *      NISTC_AI_MODE3_REG
1684          *      NISTC_AI_PERSONAL_REG
1685          *      NISTC_AI_OUT_CTRL_REG
1686          */
1687
1688         /* clear interrupts */
1689         ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1690
1691         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1692
1693         return 0;
1694 }
1695
1696 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1697 {
1698         unsigned long flags;
1699         int count;
1700
1701         /*  lock to avoid race with interrupt handler */
1702         spin_lock_irqsave(&dev->spinlock, flags);
1703 #ifndef PCIDMA
1704         ni_handle_fifo_dregs(dev);
1705 #else
1706         ni_sync_ai_dma(dev);
1707 #endif
1708         count = comedi_buf_n_bytes_ready(s);
1709         spin_unlock_irqrestore(&dev->spinlock, flags);
1710
1711         return count;
1712 }
1713
1714 static void ni_prime_channelgain_list(struct comedi_device *dev)
1715 {
1716         int i;
1717
1718         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1719         for (i = 0; i < NI_TIMEOUT; ++i) {
1720                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1721                       NISTC_AI_STATUS1_FIFO_E)) {
1722                         ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1723                         return;
1724                 }
1725                 udelay(1);
1726         }
1727         dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1728 }
1729
1730 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1731                                               unsigned int n_chan,
1732                                               unsigned int *list)
1733 {
1734         const struct ni_board_struct *board = dev->board_ptr;
1735         struct ni_private *devpriv = dev->private;
1736         unsigned int chan, range, aref;
1737         unsigned int i;
1738         unsigned int dither;
1739         unsigned range_code;
1740
1741         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1742
1743         if ((list[0] & CR_ALT_SOURCE)) {
1744                 unsigned bypass_bits;
1745
1746                 chan = CR_CHAN(list[0]);
1747                 range = CR_RANGE(list[0]);
1748                 range_code = ni_gainlkup[board->gainlkup][range];
1749                 dither = (list[0] & CR_ALT_FILTER) != 0;
1750                 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1751                               NI_M_CFG_BYPASS_AI_CHAN(chan) |
1752                               NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1753                               devpriv->ai_calib_source;
1754                 if (dither)
1755                         bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1756                 /*  don't use 2's complement encoding */
1757                 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1758                 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1759         } else {
1760                 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1761         }
1762         for (i = 0; i < n_chan; i++) {
1763                 unsigned config_bits = 0;
1764
1765                 chan = CR_CHAN(list[i]);
1766                 aref = CR_AREF(list[i]);
1767                 range = CR_RANGE(list[i]);
1768                 dither = (list[i] & CR_ALT_FILTER) != 0;
1769
1770                 range_code = ni_gainlkup[board->gainlkup][range];
1771                 devpriv->ai_offset[i] = 0;
1772                 switch (aref) {
1773                 case AREF_DIFF:
1774                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1775                         break;
1776                 case AREF_COMMON:
1777                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1778                         break;
1779                 case AREF_GROUND:
1780                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1781                         break;
1782                 case AREF_OTHER:
1783                         break;
1784                 }
1785                 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1786                 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1787                 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1788                 if (i == n_chan - 1)
1789                         config_bits |= NI_M_AI_CFG_LAST_CHAN;
1790                 if (dither)
1791                         config_bits |= NI_M_AI_CFG_DITHER;
1792                 /*  don't use 2's complement encoding */
1793                 config_bits |= NI_M_AI_CFG_POLARITY;
1794                 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1795         }
1796         ni_prime_channelgain_list(dev);
1797 }
1798
1799 /*
1800  * Notes on the 6110 and 6111:
1801  * These boards a slightly different than the rest of the series, since
1802  * they have multiple A/D converters.
1803  * From the driver side, the configuration memory is a
1804  * little different.
1805  * Configuration Memory Low:
1806  *   bits 15-9: same
1807  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1808  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1809  *       1001 gain=0.1 (+/- 50)
1810  *       1010 0.2
1811  *       1011 0.1
1812  *       0001 1
1813  *       0010 2
1814  *       0011 5
1815  *       0100 10
1816  *       0101 20
1817  *       0110 50
1818  * Configuration Memory High:
1819  *   bits 12-14: Channel Type
1820  *       001 for differential
1821  *       000 for calibration
1822  *   bit 11: coupling  (this is not currently handled)
1823  *       1 AC coupling
1824  *       0 DC coupling
1825  *   bits 0-2: channel
1826  *       valid channels are 0-3
1827  */
1828 static void ni_load_channelgain_list(struct comedi_device *dev,
1829                                      struct comedi_subdevice *s,
1830                                      unsigned int n_chan, unsigned int *list)
1831 {
1832         const struct ni_board_struct *board = dev->board_ptr;
1833         struct ni_private *devpriv = dev->private;
1834         unsigned int offset = (s->maxdata + 1) >> 1;
1835         unsigned int chan, range, aref;
1836         unsigned int i;
1837         unsigned int hi, lo;
1838         unsigned int dither;
1839
1840         if (devpriv->is_m_series) {
1841                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1842                 return;
1843         }
1844         if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1845                 if (devpriv->changain_state
1846                     && devpriv->changain_spec == list[0]) {
1847                         /*  ready to go. */
1848                         return;
1849                 }
1850                 devpriv->changain_state = 1;
1851                 devpriv->changain_spec = list[0];
1852         } else {
1853                 devpriv->changain_state = 0;
1854         }
1855
1856         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1857
1858         /*  Set up Calibration mode if required */
1859         if (devpriv->is_6143) {
1860                 if ((list[0] & CR_ALT_SOURCE)
1861                     && !devpriv->ai_calib_source_enabled) {
1862                         /*  Strobe Relay enable bit */
1863                         ni_writew(dev, devpriv->ai_calib_source |
1864                                        NI6143_CALIB_CHAN_RELAY_ON,
1865                                   NI6143_CALIB_CHAN_REG);
1866                         ni_writew(dev, devpriv->ai_calib_source,
1867                                   NI6143_CALIB_CHAN_REG);
1868                         devpriv->ai_calib_source_enabled = 1;
1869                         msleep_interruptible(100);      /*  Allow relays to change */
1870                 } else if (!(list[0] & CR_ALT_SOURCE)
1871                            && devpriv->ai_calib_source_enabled) {
1872                         /*  Strobe Relay disable bit */
1873                         ni_writew(dev, devpriv->ai_calib_source |
1874                                        NI6143_CALIB_CHAN_RELAY_OFF,
1875                                   NI6143_CALIB_CHAN_REG);
1876                         ni_writew(dev, devpriv->ai_calib_source,
1877                                   NI6143_CALIB_CHAN_REG);
1878                         devpriv->ai_calib_source_enabled = 0;
1879                         msleep_interruptible(100);      /*  Allow relays to change */
1880                 }
1881         }
1882
1883         for (i = 0; i < n_chan; i++) {
1884                 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1885                         chan = devpriv->ai_calib_source;
1886                 else
1887                         chan = CR_CHAN(list[i]);
1888                 aref = CR_AREF(list[i]);
1889                 range = CR_RANGE(list[i]);
1890                 dither = (list[i] & CR_ALT_FILTER) != 0;
1891
1892                 /* fix the external/internal range differences */
1893                 range = ni_gainlkup[board->gainlkup][range];
1894                 if (devpriv->is_611x)
1895                         devpriv->ai_offset[i] = offset;
1896                 else
1897                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1898
1899                 hi = 0;
1900                 if ((list[i] & CR_ALT_SOURCE)) {
1901                         if (devpriv->is_611x)
1902                                 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1903                                           NI611X_CALIB_CHAN_SEL_REG);
1904                 } else {
1905                         if (devpriv->is_611x)
1906                                 aref = AREF_DIFF;
1907                         else if (devpriv->is_6143)
1908                                 aref = AREF_OTHER;
1909                         switch (aref) {
1910                         case AREF_DIFF:
1911                                 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1912                                 break;
1913                         case AREF_COMMON:
1914                                 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1915                                 break;
1916                         case AREF_GROUND:
1917                                 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1918                                 break;
1919                         case AREF_OTHER:
1920                                 break;
1921                         }
1922                 }
1923                 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1924
1925                 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1926
1927                 if (!devpriv->is_6143) {
1928                         lo = NI_E_AI_CFG_LO_GAIN(range);
1929
1930                         if (i == n_chan - 1)
1931                                 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1932                         if (dither)
1933                                 lo |= NI_E_AI_CFG_LO_DITHER;
1934
1935                         ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1936                 }
1937         }
1938
1939         /* prime the channel/gain list */
1940         if (!devpriv->is_611x && !devpriv->is_6143)
1941                 ni_prime_channelgain_list(dev);
1942 }
1943
1944 static int ni_ai_insn_read(struct comedi_device *dev,
1945                            struct comedi_subdevice *s,
1946                            struct comedi_insn *insn,
1947                            unsigned int *data)
1948 {
1949         struct ni_private *devpriv = dev->private;
1950         unsigned int mask = (s->maxdata + 1) >> 1;
1951         int i, n;
1952         unsigned signbits;
1953         unsigned int d;
1954         unsigned long dl;
1955
1956         ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1957
1958         ni_clear_ai_fifo(dev);
1959
1960         signbits = devpriv->ai_offset[0];
1961         if (devpriv->is_611x) {
1962                 for (n = 0; n < num_adc_stages_611x; n++) {
1963                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1964                                       NISTC_AI_CMD1_REG);
1965                         udelay(1);
1966                 }
1967                 for (n = 0; n < insn->n; n++) {
1968                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1969                                       NISTC_AI_CMD1_REG);
1970                         /* The 611x has screwy 32-bit FIFOs. */
1971                         d = 0;
1972                         for (i = 0; i < NI_TIMEOUT; i++) {
1973                                 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1974                                         d = ni_readl(dev,
1975                                                      NI611X_AI_FIFO_DATA_REG);
1976                                         d >>= 16;
1977                                         d &= 0xffff;
1978                                         break;
1979                                 }
1980                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1981                                       NISTC_AI_STATUS1_FIFO_E)) {
1982                                         d = ni_readl(dev,
1983                                                      NI611X_AI_FIFO_DATA_REG);
1984                                         d &= 0xffff;
1985                                         break;
1986                                 }
1987                         }
1988                         if (i == NI_TIMEOUT) {
1989                                 dev_err(dev->class_dev, "timeout\n");
1990                                 return -ETIME;
1991                         }
1992                         d += signbits;
1993                         data[n] = d;
1994                 }
1995         } else if (devpriv->is_6143) {
1996                 for (n = 0; n < insn->n; n++) {
1997                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1998                                       NISTC_AI_CMD1_REG);
1999
2000                         /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
2001                         dl = 0;
2002                         for (i = 0; i < NI_TIMEOUT; i++) {
2003                                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
2004                                     0x01) {
2005                                         /* Get stranded sample into FIFO */
2006                                         ni_writel(dev, 0x01,
2007                                                   NI6143_AI_FIFO_CTRL_REG);
2008                                         dl = ni_readl(dev,
2009                                                       NI6143_AI_FIFO_DATA_REG);
2010                                         break;
2011                                 }
2012                         }
2013                         if (i == NI_TIMEOUT) {
2014                                 dev_err(dev->class_dev, "timeout\n");
2015                                 return -ETIME;
2016                         }
2017                         data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
2018                 }
2019         } else {
2020                 for (n = 0; n < insn->n; n++) {
2021                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
2022                                       NISTC_AI_CMD1_REG);
2023                         for (i = 0; i < NI_TIMEOUT; i++) {
2024                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
2025                                       NISTC_AI_STATUS1_FIFO_E))
2026                                         break;
2027                         }
2028                         if (i == NI_TIMEOUT) {
2029                                 dev_err(dev->class_dev, "timeout\n");
2030                                 return -ETIME;
2031                         }
2032                         if (devpriv->is_m_series) {
2033                                 dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
2034                                 dl &= mask;
2035                                 data[n] = dl;
2036                         } else {
2037                                 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
2038                                 d += signbits;  /* subtle: needs to be short addition */
2039                                 data[n] = d;
2040                         }
2041                 }
2042         }
2043         return insn->n;
2044 }
2045
2046 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2047                           unsigned int flags)
2048 {
2049         struct ni_private *devpriv = dev->private;
2050         int divider;
2051
2052         switch (flags & CMDF_ROUND_MASK) {
2053         case CMDF_ROUND_NEAREST:
2054         default:
2055                 divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns);
2056                 break;
2057         case CMDF_ROUND_DOWN:
2058                 divider = (nanosec) / devpriv->clock_ns;
2059                 break;
2060         case CMDF_ROUND_UP:
2061                 divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns);
2062                 break;
2063         }
2064         return divider - 1;
2065 }
2066
2067 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2068 {
2069         struct ni_private *devpriv = dev->private;
2070
2071         return devpriv->clock_ns * (timer + 1);
2072 }
2073
2074 static void ni_cmd_set_mite_transfer(struct mite_dma_descriptor_ring *ring,
2075                                      struct comedi_subdevice *sdev,
2076                                      const struct comedi_cmd *cmd,
2077                                      unsigned int max_count) {
2078 #ifdef PCIDMA
2079         unsigned int nbytes = max_count;
2080
2081         if (cmd->stop_arg > 0 && cmd->stop_arg < max_count)
2082                 nbytes = cmd->stop_arg;
2083         nbytes *= comedi_bytes_per_scan(sdev);
2084
2085         if (nbytes > sdev->async->prealloc_bufsz) {
2086                 if (cmd->stop_arg > 0)
2087                         dev_err(sdev->device->class_dev,
2088                                 "ni_cmd_set_mite_transfer: tried exact data transfer limits greater than buffer size\n");
2089
2090                 /*
2091                  * we can only transfer up to the size of the buffer.  In this
2092                  * case, the user is expected to continue to write into the
2093                  * comedi buffer (already implemented as a ring buffer).
2094                  */
2095                 nbytes = sdev->async->prealloc_bufsz;
2096         }
2097
2098         mite_init_ring_descriptors(ring, sdev, nbytes);
2099 #else
2100         dev_err(sdev->device->class_dev,
2101                 "ni_cmd_set_mite_transfer: exact data transfer limits not implemented yet without DMA\n");
2102 #endif
2103 }
2104
2105 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2106                                          unsigned num_channels)
2107 {
2108         const struct ni_board_struct *board = dev->board_ptr;
2109         struct ni_private *devpriv = dev->private;
2110
2111         /* simultaneously-sampled inputs */
2112         if (devpriv->is_611x || devpriv->is_6143)
2113                 return board->ai_speed;
2114
2115         /* multiplexed inputs */
2116         return board->ai_speed * num_channels;
2117 }
2118
2119 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2120                          struct comedi_cmd *cmd)
2121 {
2122         const struct ni_board_struct *board = dev->board_ptr;
2123         struct ni_private *devpriv = dev->private;
2124         int err = 0;
2125         unsigned int tmp;
2126         unsigned int sources;
2127
2128         /* Step 1 : check if triggers are trivially valid */
2129
2130         err |= comedi_check_trigger_src(&cmd->start_src,
2131                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2132         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2133                                         TRIG_TIMER | TRIG_EXT);
2134
2135         sources = TRIG_TIMER | TRIG_EXT;
2136         if (devpriv->is_611x || devpriv->is_6143)
2137                 sources |= TRIG_NOW;
2138         err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2139
2140         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2141         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2142
2143         if (err)
2144                 return 1;
2145
2146         /* Step 2a : make sure trigger sources are unique */
2147
2148         err |= comedi_check_trigger_is_unique(cmd->start_src);
2149         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2150         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2151         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2152
2153         /* Step 2b : and mutually compatible */
2154
2155         if (err)
2156                 return 2;
2157
2158         /* Step 3: check if arguments are trivially valid */
2159
2160         switch (cmd->start_src) {
2161         case TRIG_NOW:
2162         case TRIG_INT:
2163                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2164                 break;
2165         case TRIG_EXT:
2166                 tmp = CR_CHAN(cmd->start_arg);
2167
2168                 if (tmp > 16)
2169                         tmp = 16;
2170                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2171                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2172                 break;
2173         }
2174
2175         if (cmd->scan_begin_src == TRIG_TIMER) {
2176                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2177                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2178                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2179                                                     devpriv->clock_ns *
2180                                                     0xffffff);
2181         } else if (cmd->scan_begin_src == TRIG_EXT) {
2182                 /* external trigger */
2183                 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2184
2185                 if (tmp > 16)
2186                         tmp = 16;
2187                 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2188                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2189         } else {                /* TRIG_OTHER */
2190                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2191         }
2192
2193         if (cmd->convert_src == TRIG_TIMER) {
2194                 if (devpriv->is_611x || devpriv->is_6143) {
2195                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2196                                                            0);
2197                 } else {
2198                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2199                                                             board->ai_speed);
2200                         err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2201                                                             devpriv->clock_ns *
2202                                                             0xffff);
2203                 }
2204         } else if (cmd->convert_src == TRIG_EXT) {
2205                 /* external trigger */
2206                 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2207
2208                 if (tmp > 16)
2209                         tmp = 16;
2210                 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2211                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2212         } else if (cmd->convert_src == TRIG_NOW) {
2213                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2214         }
2215
2216         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2217                                            cmd->chanlist_len);
2218
2219         if (cmd->stop_src == TRIG_COUNT) {
2220                 unsigned int max_count = 0x01000000;
2221
2222                 if (devpriv->is_611x)
2223                         max_count -= num_adc_stages_611x;
2224                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2225                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2226         } else {
2227                 /* TRIG_NONE */
2228                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2229         }
2230
2231         if (err)
2232                 return 3;
2233
2234         /* step 4: fix up any arguments */
2235
2236         if (cmd->scan_begin_src == TRIG_TIMER) {
2237                 tmp = cmd->scan_begin_arg;
2238                 cmd->scan_begin_arg =
2239                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2240                                                        cmd->scan_begin_arg,
2241                                                        cmd->flags));
2242                 if (tmp != cmd->scan_begin_arg)
2243                         err++;
2244         }
2245         if (cmd->convert_src == TRIG_TIMER) {
2246                 if (!devpriv->is_611x && !devpriv->is_6143) {
2247                         tmp = cmd->convert_arg;
2248                         cmd->convert_arg =
2249                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2250                                                                cmd->convert_arg,
2251                                                                cmd->flags));
2252                         if (tmp != cmd->convert_arg)
2253                                 err++;
2254                         if (cmd->scan_begin_src == TRIG_TIMER &&
2255                             cmd->scan_begin_arg <
2256                             cmd->convert_arg * cmd->scan_end_arg) {
2257                                 cmd->scan_begin_arg =
2258                                     cmd->convert_arg * cmd->scan_end_arg;
2259                                 err++;
2260                         }
2261                 }
2262         }
2263
2264         if (err)
2265                 return 4;
2266
2267         return 0;
2268 }
2269
2270 static int ni_ai_inttrig(struct comedi_device *dev,
2271                          struct comedi_subdevice *s,
2272                          unsigned int trig_num)
2273 {
2274         struct ni_private *devpriv = dev->private;
2275         struct comedi_cmd *cmd = &s->async->cmd;
2276
2277         if (trig_num != cmd->start_arg)
2278                 return -EINVAL;
2279
2280         ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2281                       NISTC_AI_CMD2_REG);
2282         s->async->inttrig = NULL;
2283
2284         return 1;
2285 }
2286
2287 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2288 {
2289         struct ni_private *devpriv = dev->private;
2290         const struct comedi_cmd *cmd = &s->async->cmd;
2291         int timer;
2292         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2293         int mode2 = 0;
2294         int start_stop_select = 0;
2295         unsigned int stop_count;
2296         int interrupt_a_enable = 0;
2297         unsigned ai_trig;
2298
2299         if (dev->irq == 0) {
2300                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2301                 return -EIO;
2302         }
2303         ni_clear_ai_fifo(dev);
2304
2305         ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2306
2307         /* start configuration */
2308         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2309
2310         /* disable analog triggering for now, since it
2311          * interferes with the use of pfi0 */
2312         devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2313         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2314
2315         ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2316         switch (cmd->start_src) {
2317         case TRIG_INT:
2318         case TRIG_NOW:
2319                 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2320                            NISTC_AI_TRIG_START1_SEL(0);
2321                 break;
2322         case TRIG_EXT:
2323                 ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2324                                                     1);
2325
2326                 if (cmd->start_arg & CR_INVERT)
2327                         ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2328                 if (cmd->start_arg & CR_EDGE)
2329                         ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2330                 break;
2331         }
2332         ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2333
2334         mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2335         mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2336         mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2337         ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2338
2339         if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2340                 /* logic low */
2341                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2342                                      NISTC_AI_STOP_SEL(31) |
2343                                      NISTC_AI_STOP_SYNC;
2344         } else {
2345                 /*  ai configuration memory */
2346                 start_stop_select |= NISTC_AI_STOP_SEL(19);
2347         }
2348         ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2349
2350         devpriv->ai_cmd2 = 0;
2351         switch (cmd->stop_src) {
2352         case TRIG_COUNT:
2353                 stop_count = cmd->stop_arg - 1;
2354
2355                 if (devpriv->is_611x) {
2356                         /*  have to take 3 stage adc pipeline into account */
2357                         stop_count += num_adc_stages_611x;
2358                 }
2359                 /* stage number of scans */
2360                 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2361
2362                 mode1 |= NISTC_AI_MODE1_START_STOP |
2363                          NISTC_AI_MODE1_RSVD |
2364                          NISTC_AI_MODE1_TRIGGER_ONCE;
2365                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2366                 /* load SC (Scan Count) */
2367                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2368
2369                 if (stop_count == 0) {
2370                         devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2371                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2372                         /*  this is required to get the last sample for chanlist_len > 1, not sure why */
2373                         if (cmd->chanlist_len > 1)
2374                                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2375                                                      NISTC_AI_STOP_EDGE;
2376                 }
2377                 break;
2378         case TRIG_NONE:
2379                 /* stage number of scans */
2380                 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2381
2382                 mode1 |= NISTC_AI_MODE1_START_STOP |
2383                          NISTC_AI_MODE1_RSVD |
2384                          NISTC_AI_MODE1_CONTINUOUS;
2385                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2386
2387                 /* load SC (Scan Count) */
2388                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2389                 break;
2390         }
2391
2392         switch (cmd->scan_begin_src) {
2393         case TRIG_TIMER:
2394                 /*
2395                  * stop bits for non 611x boards
2396                  * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2397                  * NISTC_AI_MODE2_PRE_TRIGGER=0
2398                  * NISTC_AI_START_STOP_REG:
2399                  * NISTC_AI_START_POLARITY=0    (?) rising edge
2400                  * NISTC_AI_START_EDGE=1        edge triggered
2401                  * NISTC_AI_START_SYNC=1        (?)
2402                  * NISTC_AI_START_SEL=0         SI_TC
2403                  * NISTC_AI_STOP_POLARITY=0     rising edge
2404                  * NISTC_AI_STOP_EDGE=0         level
2405                  * NISTC_AI_STOP_SYNC=1
2406                  * NISTC_AI_STOP_SEL=19         external pin (configuration mem)
2407                  */
2408                 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2409                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2410
2411                 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC;      /* A */
2412                 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2413                 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2414                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2415
2416                 /* load SI */
2417                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2418                                        CMDF_ROUND_NEAREST);
2419                 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2420                 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2421                 break;
2422         case TRIG_EXT:
2423                 if (cmd->scan_begin_arg & CR_EDGE)
2424                         start_stop_select |= NISTC_AI_START_EDGE;
2425                 if (cmd->scan_begin_arg & CR_INVERT)    /* falling edge */
2426                         start_stop_select |= NISTC_AI_START_POLARITY;
2427                 if (cmd->scan_begin_src != cmd->convert_src ||
2428                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2429                     (cmd->convert_arg & ~CR_EDGE))
2430                         start_stop_select |= NISTC_AI_START_SYNC;
2431                 start_stop_select |=
2432                     NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2433                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2434                 break;
2435         }
2436
2437         switch (cmd->convert_src) {
2438         case TRIG_TIMER:
2439         case TRIG_NOW:
2440                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2441                         timer = 1;
2442                 else
2443                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2444                                                CMDF_ROUND_NEAREST);
2445                 /* 0,0 does not work */
2446                 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2447                 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2448
2449                 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;     /* A */
2450                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2451                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2452
2453                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2454
2455                 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;      /* B */
2456                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2457                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2458                 break;
2459         case TRIG_EXT:
2460                 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 +
2461                                                     CR_CHAN(cmd->convert_arg));
2462                 if ((cmd->convert_arg & CR_INVERT) == 0)
2463                         mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2464                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2465
2466                 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2467                          NISTC_AI_MODE2_START_STOP_GATE_ENA;
2468                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2469
2470                 break;
2471         }
2472
2473         if (dev->irq) {
2474                 /* interrupt on FIFO, errors, SC_TC */
2475                 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2476                                       NISTC_INTA_ENA_AI_SC_TC;
2477
2478 #ifndef PCIDMA
2479                 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2480 #endif
2481
2482                 if ((cmd->flags & CMDF_WAKE_EOS) ||
2483                     (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2484                         /* wake on end-of-scan */
2485                         devpriv->aimode = AIMODE_SCAN;
2486                 } else {
2487                         devpriv->aimode = AIMODE_HALF_FULL;
2488                 }
2489
2490                 switch (devpriv->aimode) {
2491                 case AIMODE_HALF_FULL:
2492                         /*generate FIFO interrupts and DMA requests on half-full */
2493 #ifdef PCIDMA
2494                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2495                                       NISTC_AI_MODE3_REG);
2496 #else
2497                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2498                                       NISTC_AI_MODE3_REG);
2499 #endif
2500                         break;
2501                 case AIMODE_SAMPLE:
2502                         /*generate FIFO interrupts on non-empty */
2503                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2504                                       NISTC_AI_MODE3_REG);
2505                         break;
2506                 case AIMODE_SCAN:
2507 #ifdef PCIDMA
2508                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2509                                       NISTC_AI_MODE3_REG);
2510 #else
2511                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2512                                       NISTC_AI_MODE3_REG);
2513 #endif
2514                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2515                         break;
2516                 default:
2517                         break;
2518                 }
2519
2520                 /* clear interrupts */
2521                 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2522
2523                 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2524         } else {
2525                 /* interrupt on nothing */
2526                 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2527
2528                 /* XXX start polling if necessary */
2529         }
2530
2531         /* end configuration */
2532         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2533
2534         switch (cmd->scan_begin_src) {
2535         case TRIG_TIMER:
2536                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2537                                    NISTC_AI_CMD1_SI_ARM |
2538                                    NISTC_AI_CMD1_DIV_ARM |
2539                                    NISTC_AI_CMD1_SC_ARM,
2540                               NISTC_AI_CMD1_REG);
2541                 break;
2542         case TRIG_EXT:
2543                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2544                                    NISTC_AI_CMD1_SI_ARM |       /* XXX ? */
2545                                    NISTC_AI_CMD1_DIV_ARM |
2546                                    NISTC_AI_CMD1_SC_ARM,
2547                               NISTC_AI_CMD1_REG);
2548                 break;
2549         }
2550
2551 #ifdef PCIDMA
2552         {
2553                 int retval = ni_ai_setup_MITE_dma(dev);
2554
2555                 if (retval)
2556                         return retval;
2557         }
2558 #endif
2559
2560         if (cmd->start_src == TRIG_NOW) {
2561                 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2562                                    devpriv->ai_cmd2,
2563                               NISTC_AI_CMD2_REG);
2564                 s->async->inttrig = NULL;
2565         } else if (cmd->start_src == TRIG_EXT) {
2566                 s->async->inttrig = NULL;
2567         } else {        /* TRIG_INT */
2568                 s->async->inttrig = ni_ai_inttrig;
2569         }
2570
2571         return 0;
2572 }
2573
2574 static int ni_ai_insn_config(struct comedi_device *dev,
2575                              struct comedi_subdevice *s,
2576                              struct comedi_insn *insn, unsigned int *data)
2577 {
2578         struct ni_private *devpriv = dev->private;
2579
2580         if (insn->n < 1)
2581                 return -EINVAL;
2582
2583         switch (data[0]) {
2584         case INSN_CONFIG_ALT_SOURCE:
2585                 if (devpriv->is_m_series) {
2586                         if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2587                                 return -EINVAL;
2588                         devpriv->ai_calib_source = data[1];
2589                 } else if (devpriv->is_6143) {
2590                         unsigned int calib_source;
2591
2592                         calib_source = data[1] & 0xf;
2593
2594                         devpriv->ai_calib_source = calib_source;
2595                         ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2596                 } else {
2597                         unsigned int calib_source;
2598                         unsigned int calib_source_adjust;
2599
2600                         calib_source = data[1] & 0xf;
2601                         calib_source_adjust = (data[1] >> 4) & 0xff;
2602
2603                         if (calib_source >= 8)
2604                                 return -EINVAL;
2605                         devpriv->ai_calib_source = calib_source;
2606                         if (devpriv->is_611x) {
2607                                 ni_writeb(dev, calib_source_adjust,
2608                                           NI611X_CAL_GAIN_SEL_REG);
2609                         }
2610                 }
2611                 return 2;
2612         default:
2613                 break;
2614         }
2615
2616         return -EINVAL;
2617 }
2618
2619 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2620                         void *data, unsigned int num_bytes,
2621                         unsigned int chan_index)
2622 {
2623         struct comedi_cmd *cmd = &s->async->cmd;
2624         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2625         unsigned short *array = data;
2626         unsigned int i;
2627 #ifdef PCIDMA
2628         __le16 buf, *barray = data;
2629 #endif
2630
2631         for (i = 0; i < nsamples; i++) {
2632                 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2633                 unsigned short val = array[i];
2634
2635                 /*
2636                  * Munge data from unsigned to two's complement for
2637                  * bipolar ranges.
2638                  */
2639                 if (comedi_range_is_bipolar(s, range))
2640                         val = comedi_offset_munge(s, val);
2641 #ifdef PCIDMA
2642                 buf = cpu_to_le16(val);
2643                 barray[i] = buf;
2644 #else
2645                 array[i] = val;
2646 #endif
2647                 chan_index++;
2648                 chan_index %= cmd->chanlist_len;
2649         }
2650 }
2651
2652 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2653                                           struct comedi_subdevice *s,
2654                                           unsigned int chanspec[],
2655                                           unsigned int n_chans, int timed)
2656 {
2657         struct ni_private *devpriv = dev->private;
2658         unsigned int range;
2659         unsigned int chan;
2660         unsigned int conf;
2661         int i;
2662         int invert = 0;
2663
2664         if (timed) {
2665                 for (i = 0; i < s->n_chan; ++i) {
2666                         devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2667                         ni_writeb(dev, devpriv->ao_conf[i],
2668                                   NI_M_AO_CFG_BANK_REG(i));
2669                         ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2670                 }
2671         }
2672         for (i = 0; i < n_chans; i++) {
2673                 const struct comedi_krange *krange;
2674
2675                 chan = CR_CHAN(chanspec[i]);
2676                 range = CR_RANGE(chanspec[i]);
2677                 krange = s->range_table->range + range;
2678                 invert = 0;
2679                 conf = 0;
2680                 switch (krange->max - krange->min) {
2681                 case 20000000:
2682                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2683                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2684                         break;
2685                 case 10000000:
2686                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2687                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2688                         break;
2689                 case 4000000:
2690                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2691                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2692                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2693                         break;
2694                 case 2000000:
2695                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2696                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2697                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2698                         break;
2699                 default:
2700                         dev_err(dev->class_dev,
2701                                 "bug! unhandled ao reference voltage\n");
2702                         break;
2703                 }
2704                 switch (krange->max + krange->min) {
2705                 case 0:
2706                         conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2707                         break;
2708                 case 10000000:
2709                         conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2710                         break;
2711                 default:
2712                         dev_err(dev->class_dev,
2713                                 "bug! unhandled ao offset voltage\n");
2714                         break;
2715                 }
2716                 if (timed)
2717                         conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2718                 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2719                 devpriv->ao_conf[chan] = conf;
2720                 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2721         }
2722         return invert;
2723 }
2724
2725 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2726                                      struct comedi_subdevice *s,
2727                                      unsigned int chanspec[],
2728                                      unsigned int n_chans)
2729 {
2730         struct ni_private *devpriv = dev->private;
2731         unsigned int range;
2732         unsigned int chan;
2733         unsigned int conf;
2734         int i;
2735         int invert = 0;
2736
2737         for (i = 0; i < n_chans; i++) {
2738                 chan = CR_CHAN(chanspec[i]);
2739                 range = CR_RANGE(chanspec[i]);
2740                 conf = NI_E_AO_DACSEL(chan);
2741
2742                 if (comedi_range_is_bipolar(s, range)) {
2743                         conf |= NI_E_AO_CFG_BIP;
2744                         invert = (s->maxdata + 1) >> 1;
2745                 } else {
2746                         invert = 0;
2747                 }
2748                 if (comedi_range_is_external(s, range))
2749                         conf |= NI_E_AO_EXT_REF;
2750
2751                 /* not all boards can deglitch, but this shouldn't hurt */
2752                 if (chanspec[i] & CR_DEGLITCH)
2753                         conf |= NI_E_AO_DEGLITCH;
2754
2755                 /* analog reference */
2756                 /* AREF_OTHER connects AO ground to AI ground, i think */
2757                 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2758                         conf |= NI_E_AO_GROUND_REF;
2759
2760                 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2761                 devpriv->ao_conf[chan] = conf;
2762         }
2763         return invert;
2764 }
2765
2766 static int ni_ao_config_chanlist(struct comedi_device *dev,
2767                                  struct comedi_subdevice *s,
2768                                  unsigned int chanspec[], unsigned int n_chans,
2769                                  int timed)
2770 {
2771         struct ni_private *devpriv = dev->private;
2772
2773         if (devpriv->is_m_series)
2774                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2775                                                       timed);
2776         else
2777                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2778 }
2779
2780 static int ni_ao_insn_write(struct comedi_device *dev,
2781                             struct comedi_subdevice *s,
2782                             struct comedi_insn *insn,
2783                             unsigned int *data)
2784 {
2785         struct ni_private *devpriv = dev->private;
2786         unsigned int chan = CR_CHAN(insn->chanspec);
2787         unsigned int range = CR_RANGE(insn->chanspec);
2788         int reg;
2789         int i;
2790
2791         if (devpriv->is_6xxx) {
2792                 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2793
2794                 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2795         } else if (devpriv->is_m_series) {
2796                 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2797         } else {
2798                 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2799         }
2800
2801         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2802
2803         for (i = 0; i < insn->n; i++) {
2804                 unsigned int val = data[i];
2805
2806                 s->readback[chan] = val;
2807
2808                 if (devpriv->is_6xxx) {
2809                         /*
2810                          * 6xxx boards have bipolar outputs, munge the
2811                          * unsigned comedi values to 2's complement
2812                          */
2813                         val = comedi_offset_munge(s, val);
2814
2815                         ni_ao_win_outw(dev, val, reg);
2816                 } else if (devpriv->is_m_series) {
2817                         /*
2818                          * M-series boards use offset binary values for
2819                          * bipolar and uinpolar outputs
2820                          */
2821                         ni_writew(dev, val, reg);
2822                 } else {
2823                         /*
2824                          * Non-M series boards need two's complement values
2825                          * for bipolar ranges.
2826                          */
2827                         if (comedi_range_is_bipolar(s, range))
2828                                 val = comedi_offset_munge(s, val);
2829
2830                         ni_writew(dev, val, reg);
2831                 }
2832         }
2833
2834         return insn->n;
2835 }
2836
2837 static int ni_ao_insn_config(struct comedi_device *dev,
2838                              struct comedi_subdevice *s,
2839                              struct comedi_insn *insn, unsigned int *data)
2840 {
2841         const struct ni_board_struct *board = dev->board_ptr;
2842         struct ni_private *devpriv = dev->private;
2843         unsigned int nbytes;
2844
2845         switch (data[0]) {
2846         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2847                 switch (data[1]) {
2848                 case COMEDI_OUTPUT:
2849                         nbytes = comedi_samples_to_bytes(s,
2850                                                          board->ao_fifo_depth);
2851                         data[2] = 1 + nbytes;
2852                         if (devpriv->mite)
2853                                 data[2] += devpriv->mite->fifo_size;
2854                         break;
2855                 case COMEDI_INPUT:
2856                         data[2] = 0;
2857                         break;
2858                 default:
2859                         return -EINVAL;
2860                 }
2861                 return 0;
2862         default:
2863                 break;
2864         }
2865
2866         return -EINVAL;
2867 }
2868
2869 static int ni_ao_inttrig(struct comedi_device *dev,
2870                          struct comedi_subdevice *s,
2871                          unsigned int trig_num)
2872 {
2873         struct ni_private *devpriv = dev->private;
2874         struct comedi_cmd *cmd = &s->async->cmd;
2875         int ret;
2876         int interrupt_b_bits;
2877         int i;
2878         static const int timeout = 1000;
2879
2880         if (trig_num != cmd->start_arg)
2881                 return -EINVAL;
2882
2883         /* Null trig at beginning prevent ao start trigger from executing more than
2884            once per command (and doing things like trying to allocate the ao dma channel
2885            multiple times) */
2886         s->async->inttrig = NULL;
2887
2888         ni_set_bits(dev, NISTC_INTB_ENA_REG,
2889                     NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2890         interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2891 #ifdef PCIDMA
2892         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2893         if (devpriv->is_6xxx)
2894                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2895         ret = ni_ao_setup_MITE_dma(dev);
2896         if (ret)
2897                 return ret;
2898         ret = ni_ao_wait_for_dma_load(dev);
2899         if (ret < 0)
2900                 return ret;
2901 #else
2902         ret = ni_ao_prep_fifo(dev, s);
2903         if (ret == 0)
2904                 return -EPIPE;
2905
2906         interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2907 #endif
2908
2909         ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2910                       NISTC_AO_MODE3_REG);
2911         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2912         /* wait for DACs to be loaded */
2913         for (i = 0; i < timeout; i++) {
2914                 udelay(1);
2915                 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2916                      NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2917                         break;
2918         }
2919         if (i == timeout) {
2920                 dev_err(dev->class_dev,
2921                         "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2922                 return -EIO;
2923         }
2924         /*
2925          * stc manual says we are need to clear error interrupt after
2926          * AO_TMRDACWRs_In_Progress_St clears
2927          */
2928         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2929
2930         ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2931
2932         ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2933                            NISTC_AO_CMD1_UC_ARM |
2934                            NISTC_AO_CMD1_BC_ARM |
2935                            devpriv->ao_cmd1,
2936                       NISTC_AO_CMD1_REG);
2937
2938         ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2939                       NISTC_AO_CMD2_REG);
2940
2941         return 0;
2942 }
2943
2944 /*
2945  * begin ni_ao_cmd.
2946  * Organized similar to NI-STC and MHDDK examples.
2947  * ni_ao_cmd is broken out into configuration sub-routines for clarity.
2948  */
2949
2950 static void ni_ao_cmd_personalize(struct comedi_device *dev,
2951                                   const struct comedi_cmd *cmd)
2952 {
2953         const struct ni_board_struct *board = dev->board_ptr;
2954         unsigned bits;
2955
2956         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2957
2958         bits =
2959           /* fast CPU interface--only eseries */
2960           /* ((slow CPU interface) ? 0 : AO_Fast_CPU) | */
2961           NISTC_AO_PERSONAL_BC_SRC_SEL  |
2962           0 /* (use_original_pulse ? 0 : NISTC_AO_PERSONAL_UPDATE_TIMEBASE) */ |
2963           /*
2964            * FIXME:  start setting following bit when appropriate.  Need to
2965            * determine whether board is E4 or E1.
2966            * FROM MHHDK:
2967            * if board is E4 or E1
2968            *   Set bit "NISTC_AO_PERSONAL_UPDATE_PW" to 0
2969            * else
2970            *   set it to 1
2971            */
2972           NISTC_AO_PERSONAL_UPDATE_PW   |
2973           /* FIXME:  when should we set following bit to zero? */
2974           NISTC_AO_PERSONAL_TMRDACWR_PW |
2975           (board->ao_fifo_depth ?
2976             NISTC_AO_PERSONAL_FIFO_ENA : NISTC_AO_PERSONAL_DMA_PIO_CTRL)
2977           ;
2978 #if 0
2979         /*
2980          * FIXME:
2981          * add something like ".has_individual_dacs = 0" to ni_board_struct
2982          * since, as F Hess pointed out, not all in m series have singles.  not
2983          * sure if e-series all have duals...
2984          */
2985
2986         /*
2987          * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit for
2988          * 6281, verified with bus analyzer.
2989          */
2990         if (devpriv->is_m_series)
2991                 bits |= NISTC_AO_PERSONAL_NUM_DAC;
2992 #endif
2993         ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
2994
2995         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2996 }
2997
2998 static void ni_ao_cmd_set_trigger(struct comedi_device *dev,
2999                                   const struct comedi_cmd *cmd)
3000 {
3001         struct ni_private *devpriv = dev->private;
3002
3003         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3004
3005         /* sync */
3006         if (cmd->stop_src == TRIG_NONE) {
3007                 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
3008                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
3009         } else {
3010                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
3011                 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
3012         }
3013         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3014
3015         {
3016                 unsigned int trigsel = devpriv->ao_trigger_select;
3017
3018                 switch (cmd->start_src) {
3019                 case TRIG_INT:
3020                 case TRIG_NOW:
3021                         trigsel &= ~(NISTC_AO_TRIG_START1_POLARITY |
3022                                      NISTC_AO_TRIG_START1_SEL_MASK);
3023                         trigsel |= NISTC_AO_TRIG_START1_EDGE |
3024                                    NISTC_AO_TRIG_START1_SYNC;
3025                         break;
3026                 case TRIG_EXT:
3027                         trigsel = NISTC_AO_TRIG_START1_SEL(
3028                                         CR_CHAN(cmd->start_arg) + 1);
3029                         if (cmd->start_arg & CR_INVERT)
3030                                 /*
3031                                  * 0=active high, 1=active low.
3032                                  * see daq-stc 3-24 (p186)
3033                                  */
3034                                 trigsel |= NISTC_AO_TRIG_START1_POLARITY;
3035                         if (cmd->start_arg & CR_EDGE)
3036                                 /* 0=edge detection disabled, 1=enabled */
3037                                 trigsel |= NISTC_AO_TRIG_START1_EDGE;
3038                         break;
3039                 default:
3040                         BUG();
3041                         break;
3042                 }
3043
3044                 devpriv->ao_trigger_select = trigsel;
3045                 ni_stc_writew(dev, devpriv->ao_trigger_select,
3046                               NISTC_AO_TRIG_SEL_REG);
3047         }
3048         /* AO_Delayed_START1 = 0, we do not support delayed start...yet */
3049
3050         /* sync */
3051         /* select DA_START1 as PFI6/AO_START1 when configured as an output */
3052         devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
3053         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3054
3055         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3056 }
3057
3058 static void ni_ao_cmd_set_counters(struct comedi_device *dev,
3059                                    const struct comedi_cmd *cmd)
3060 {
3061         struct ni_private *devpriv = dev->private;
3062         /* Not supporting 'waveform staging' or 'local buffer with pauses' */
3063
3064         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3065         /*
3066          * This relies on ao_mode1/(Trigger_Once | Continuous) being set in
3067          * set_trigger above.  It is unclear whether we really need to re-write
3068          * this register with these values.  The mhddk examples for e-series
3069          * show writing this in both places, but the examples for m-series show
3070          * a single write in the set_counters function (here).
3071          */
3072         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3073
3074         /* sync (upload number of buffer iterations -1) */
3075         /* indicate that we want to use BC_Load_A_Register as the source */
3076         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
3077         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3078
3079         /*
3080          * if the BC_TC interrupt is still issued in spite of UC, BC, UI
3081          * ignoring BC_TC, then we will need to find a way to ignore that
3082          * interrupt in continuous mode.
3083          */
3084         ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); /* iter once */
3085
3086         /* sync (issue command to load number of buffer iterations -1) */
3087         ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
3088
3089         /* sync (upload number of updates in buffer) */
3090         /* indicate that we want to use UC_Load_A_Register as the source */
3091         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
3092         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3093
3094         /*
3095          * if a user specifies '0', this automatically assumes the entire 24bit
3096          * address space is available for the (multiple iterations of single
3097          * buffer) MISB.  Otherwise, stop_arg specifies the MISB length that
3098          * will be used, regardless of whether we are in continuous mode or not.
3099          * In continuous mode, the output will just iterate indefinitely over
3100          * the MISB.
3101          */
3102         {
3103                 unsigned int stop_arg = cmd->stop_arg > 0 ?
3104                         (cmd->stop_arg & 0xffffff) : 0xffffff;
3105
3106                 if (devpriv->is_m_series) {
3107                         /*
3108                          * this is how the NI example code does it for m-series
3109                          * boards, verified correct with 6259
3110                          */
3111                         ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3112
3113                         /* sync (issue cmd to load number of updates in MISB) */
3114                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3115                                       NISTC_AO_CMD1_REG);
3116                 } else {
3117                         ni_stc_writel(dev, stop_arg, NISTC_AO_UC_LOADA_REG);
3118
3119                         /* sync (issue cmd to load number of updates in MISB) */
3120                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3121                                       NISTC_AO_CMD1_REG);
3122
3123                         /*
3124                          * sync (upload number of updates-1 in MISB)
3125                          * --eseries only?
3126                          */
3127                         ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3128                 }
3129         }
3130
3131         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3132 }
3133
3134 static void ni_ao_cmd_set_update(struct comedi_device *dev,
3135                                  const struct comedi_cmd *cmd)
3136 {
3137         struct ni_private *devpriv = dev->private;
3138
3139         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3140
3141         /*
3142          * zero out these bit fields to be set below. Does an ao-reset do this
3143          * automatically?
3144          */
3145         devpriv->ao_mode1 &= ~(
3146           NISTC_AO_MODE1_UI_SRC_MASK         |
3147           NISTC_AO_MODE1_UI_SRC_POLARITY     |
3148           NISTC_AO_MODE1_UPDATE_SRC_MASK     |
3149           NISTC_AO_MODE1_UPDATE_SRC_POLARITY
3150         );
3151
3152         switch (cmd->scan_begin_src) {
3153         case TRIG_TIMER:
3154                 devpriv->ao_cmd2  &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3155
3156                 /*
3157                  * NOTE: there are several other ways of configuring internal
3158                  * updates, but we'll only support one for now:  using
3159                  * AO_IN_TIMEBASE, w/o waveform staging, w/o a delay between
3160                  * START1 and first update, and also w/o local buffer mode w/
3161                  * pauses.
3162                  */
3163
3164                 /*
3165                  * This is already done above:
3166                  * devpriv->ao_mode1 &= ~(
3167                  *   // set UPDATE_Source to UI_TC:
3168                  *   NISTC_AO_MODE1_UPDATE_SRC_MASK |
3169                  *   // set UPDATE_Source_Polarity to rising (required?)
3170                  *   NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3171                  *   // set UI_Source to AO_IN_TIMEBASE1:
3172                  *   NISTC_AO_MODE1_UI_SRC_MASK     |
3173                  *   // set UI_Source_Polarity to rising (required?)
3174                  *   NISTC_AO_MODE1_UI_SRC_POLARITY
3175                  * );
3176                  */
3177
3178                 /*
3179                  * TODO:  use ao_ui_clock_source to allow all possible signals
3180                  * to be routed to UI_Source_Select.  See tSTC.h for
3181                  * eseries/ni67xx and tMSeries.h for mseries.
3182                  */
3183
3184                 {
3185                         unsigned trigvar = ni_ns_to_timer(dev,
3186                                                           cmd->scan_begin_arg,
3187                                                           CMDF_ROUND_NEAREST);
3188
3189                         /*
3190                          * Wait N TB3 ticks after the start trigger before
3191                          * clocking(N must be >=2).
3192                          */
3193                         /* following line: 2-1 per STC */
3194                         ni_stc_writel(dev, 1,           NISTC_AO_UI_LOADA_REG);
3195                         ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD,
3196                                       NISTC_AO_CMD1_REG);
3197                         /* following line: N-1 per STC */
3198                         ni_stc_writel(dev, trigvar - 1, NISTC_AO_UI_LOADA_REG);
3199                 }
3200                 break;
3201         case TRIG_EXT:
3202                 /* FIXME:  assert scan_begin_arg != 0, ret failure otherwise */
3203                 devpriv->ao_cmd2  |= NISTC_AO_CMD2_BC_GATE_ENA;
3204                 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC(
3205                                         CR_CHAN(cmd->scan_begin_arg));
3206                 if (cmd->scan_begin_arg & CR_INVERT)
3207                         devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3208                 break;
3209         default:
3210                 BUG();
3211                 break;
3212         }
3213
3214         ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3215         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3216         devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3217                                NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3218         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3219
3220         /* Configure DAQ-STC for Timed update mode */
3221         devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3222                             NISTC_AO_CMD1_DAC0_UPDATE_MODE;
3223         /* We are not using UPDATE2-->don't have to set DACx_Source_Select */
3224         ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3225
3226         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3227 }
3228
3229 static void ni_ao_cmd_set_channels(struct comedi_device *dev,
3230                                    struct comedi_subdevice *s)
3231 {
3232         struct ni_private *devpriv = dev->private;
3233         const struct comedi_cmd *cmd = &s->async->cmd;
3234         unsigned bits = 0;
3235
3236         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3237
3238         if (devpriv->is_6xxx) {
3239                 unsigned int i;
3240
3241                 bits = 0;
3242                 for (i = 0; i < cmd->chanlist_len; ++i) {
3243                         int chan = CR_CHAN(cmd->chanlist[i]);
3244
3245                         bits |= 1 << chan;
3246                         ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
3247                 }
3248                 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
3249         }
3250
3251         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3252
3253         if (cmd->scan_end_arg > 1) {
3254                 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3255                 bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1)
3256                                  | NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3257
3258         } else {
3259                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3260                 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3261                 if (devpriv->is_m_series | devpriv->is_6xxx)
3262                         bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3263                 else
3264                         bits |= NISTC_AO_OUT_CTRL_CHANS(
3265                                         CR_CHAN(cmd->chanlist[0]));
3266         }
3267
3268         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3269         ni_stc_writew(dev, bits,              NISTC_AO_OUT_CTRL_REG);
3270
3271         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3272 }
3273
3274 static void ni_ao_cmd_set_stop_conditions(struct comedi_device *dev,
3275                                           const struct comedi_cmd *cmd)
3276 {
3277         struct ni_private *devpriv = dev->private;
3278
3279         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3280
3281         devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3282         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3283
3284         /*
3285          * Since we are not supporting waveform staging, we ignore these errors:
3286          * NISTC_AO_MODE3_STOP_ON_BC_TC_ERR,
3287          * NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR
3288          */
3289
3290         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3291 }
3292
3293 static void ni_ao_cmd_set_fifo_mode(struct comedi_device *dev)
3294 {
3295         struct ni_private *devpriv = dev->private;
3296
3297         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3298
3299         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3300 #ifdef PCIDMA
3301         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3302 #else
3303         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3304 #endif
3305         /* NOTE:  this is where use_onboard_memory=True would be implemented */
3306         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3307         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3308
3309         /* enable sending of ao fifo requests (dma request) */
3310         ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3311
3312         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3313
3314         /* we are not supporting boards with virtual fifos */
3315 }
3316
3317 static void ni_ao_cmd_set_interrupts(struct comedi_device *dev,
3318                                      struct comedi_subdevice *s)
3319 {
3320         if (s->async->cmd.stop_src == TRIG_COUNT)
3321                 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3322                             NISTC_INTB_ENA_AO_BC_TC, 1);
3323
3324         s->async->inttrig = ni_ao_inttrig;
3325 }
3326
3327 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3328 {
3329         struct ni_private *devpriv = dev->private;
3330         const struct comedi_cmd *cmd = &s->async->cmd;
3331
3332         if (dev->irq == 0) {
3333                 dev_err(dev->class_dev, "cannot run command without an irq");
3334                 return -EIO;
3335         }
3336
3337         /* ni_ao_reset should have already been done */
3338         ni_ao_cmd_personalize(dev, cmd);
3339         /* clearing fifo and preload happens elsewhere */
3340
3341         ni_ao_cmd_set_trigger(dev, cmd);
3342         ni_ao_cmd_set_counters(dev, cmd);
3343         ni_ao_cmd_set_update(dev, cmd);
3344         ni_ao_cmd_set_channels(dev, s);
3345         ni_ao_cmd_set_stop_conditions(dev, cmd);
3346         ni_ao_cmd_set_fifo_mode(dev);
3347         ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff);
3348         ni_ao_cmd_set_interrupts(dev, s);
3349
3350         /*
3351          * arm(ing) and star(ting) happen in ni_ao_inttrig, which _must_ be
3352          * called for ao commands since 1) TRIG_NOW is not supported and 2) DMA
3353          * must be setup and initially written to before arm/start happen.
3354          */
3355         return 0;
3356 }
3357
3358 /* end ni_ao_cmd */
3359
3360 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3361                          struct comedi_cmd *cmd)
3362 {
3363         const struct ni_board_struct *board = dev->board_ptr;
3364         struct ni_private *devpriv = dev->private;
3365         int err = 0;
3366         unsigned int tmp;
3367
3368         /* Step 1 : check if triggers are trivially valid */
3369
3370         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3371         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3372                                         TRIG_TIMER | TRIG_EXT);
3373         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3374         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3375         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3376
3377         if (err)
3378                 return 1;
3379
3380         /* Step 2a : make sure trigger sources are unique */
3381
3382         err |= comedi_check_trigger_is_unique(cmd->start_src);
3383         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3384         err |= comedi_check_trigger_is_unique(cmd->stop_src);
3385
3386         /* Step 2b : and mutually compatible */
3387
3388         if (err)
3389                 return 2;
3390
3391         /* Step 3: check if arguments are trivially valid */
3392
3393         switch (cmd->start_src) {
3394         case TRIG_INT:
3395                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3396                 break;
3397         case TRIG_EXT:
3398                 tmp = CR_CHAN(cmd->start_arg);
3399
3400                 if (tmp > 18)
3401                         tmp = 18;
3402                 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3403                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3404                 break;
3405         }
3406
3407         if (cmd->scan_begin_src == TRIG_TIMER) {
3408                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3409                                                     board->ao_speed);
3410                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3411                                                     devpriv->clock_ns *
3412                                                     0xffffff);
3413         }
3414
3415         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3416         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3417                                            cmd->chanlist_len);
3418         err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3419
3420         if (err)
3421                 return 3;
3422
3423         /* step 4: fix up any arguments */
3424         if (cmd->scan_begin_src == TRIG_TIMER) {
3425                 tmp = cmd->scan_begin_arg;
3426                 cmd->scan_begin_arg =
3427                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3428                                                        cmd->scan_begin_arg,
3429                                                        cmd->flags));
3430                 if (tmp != cmd->scan_begin_arg)
3431                         err++;
3432         }
3433         if (err)
3434                 return 4;
3435
3436         return 0;
3437 }
3438
3439 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3440 {
3441         /* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */
3442
3443         /*
3444          * In the following, the "--sync" comments are meant to denote
3445          * asynchronous boundaries for setting the registers as described in the
3446          * DAQ-STC mostly in the order also described in the DAQ-STC.
3447          */
3448
3449         struct ni_private *devpriv = dev->private;
3450
3451         ni_release_ao_mite_channel(dev);
3452
3453         /* --sync (reset AO) */
3454         if (devpriv->is_m_series)
3455                 /* following example in mhddk for m-series */
3456                 ni_stc_writew(dev, NISTC_RESET_AO, NISTC_RESET_REG);
3457
3458         /*--sync (start config) */
3459         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3460
3461         /*--sync (Disarm) */
3462         ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3463
3464         /*
3465          * --sync
3466          * (clear bunch of registers--mseries mhddk examples do not include
3467          * this)
3468          */
3469         devpriv->ao_cmd1  = 0;
3470         devpriv->ao_cmd2  = 0;
3471         devpriv->ao_mode1 = 0;
3472         devpriv->ao_mode2 = 0;
3473         if (devpriv->is_m_series)
3474                 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3475         else
3476                 devpriv->ao_mode3 = 0;
3477         devpriv->ao_trigger_select = 0;
3478
3479         ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG);
3480         ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG);
3481         ni_stc_writew(dev, 0, NISTC_AO_CMD2_REG);
3482         ni_stc_writew(dev, 0, NISTC_AO_MODE1_REG);
3483         ni_stc_writew(dev, 0, NISTC_AO_MODE2_REG);
3484         ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3485         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3486         ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3487         ni_stc_writew(dev, 0, NISTC_AO_TRIG_SEL_REG);
3488
3489         /*--sync (disable interrupts) */
3490         ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3491
3492         /*--sync (ack) */
3493         ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3494         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3495
3496         /*--not in DAQ-STC.  which doc? */
3497         if (devpriv->is_6xxx) {
3498                 ni_ao_win_outw(dev, (1u << s->n_chan) - 1u,
3499                                NI671X_AO_IMMEDIATE_REG);
3500                 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3501                                NI611X_AO_MISC_REG);
3502         }
3503         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3504         /*--end */
3505
3506         return 0;
3507 }
3508
3509 /* digital io */
3510
3511 static int ni_dio_insn_config(struct comedi_device *dev,
3512                               struct comedi_subdevice *s,
3513                               struct comedi_insn *insn,
3514                               unsigned int *data)
3515 {
3516         struct ni_private *devpriv = dev->private;
3517         int ret;
3518
3519         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3520         if (ret)
3521                 return ret;
3522
3523         devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3524         devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3525         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3526
3527         return insn->n;
3528 }
3529
3530 static int ni_dio_insn_bits(struct comedi_device *dev,
3531                             struct comedi_subdevice *s,
3532                             struct comedi_insn *insn,
3533                             unsigned int *data)
3534 {
3535         struct ni_private *devpriv = dev->private;
3536
3537         /* Make sure we're not using the serial part of the dio */
3538         if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3539             devpriv->serial_interval_ns)
3540                 return -EBUSY;
3541
3542         if (comedi_dio_update_state(s, data)) {
3543                 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3544                 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3545                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3546         }
3547
3548         data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3549
3550         return insn->n;
3551 }
3552
3553 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3554                                        struct comedi_subdevice *s,
3555                                        struct comedi_insn *insn,
3556                                        unsigned int *data)
3557 {
3558         int ret;
3559
3560         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3561         if (ret)
3562                 return ret;
3563
3564         ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3565
3566         return insn->n;
3567 }
3568
3569 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3570                                      struct comedi_subdevice *s,
3571                                      struct comedi_insn *insn,
3572                                      unsigned int *data)
3573 {
3574         if (comedi_dio_update_state(s, data))
3575                 ni_writel(dev, s->state, NI_M_DIO_REG);
3576
3577         data[1] = ni_readl(dev, NI_M_DIO_REG);
3578
3579         return insn->n;
3580 }
3581
3582 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3583                                   struct comedi_subdevice *s,
3584                                   struct comedi_cmd *cmd)
3585 {
3586         int i;
3587
3588         for (i = 0; i < cmd->chanlist_len; ++i) {
3589                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3590
3591                 if (chan != i)
3592                         return -EINVAL;
3593         }
3594
3595         return 0;
3596 }
3597
3598 static int ni_cdio_cmdtest(struct comedi_device *dev,
3599                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3600 {
3601         int err = 0;
3602         int tmp;
3603
3604         /* Step 1 : check if triggers are trivially valid */
3605
3606         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3607         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3608         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3609         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3610         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3611
3612         if (err)
3613                 return 1;
3614
3615         /* Step 2a : make sure trigger sources are unique */
3616         /* Step 2b : and mutually compatible */
3617
3618         /* Step 3: check if arguments are trivially valid */
3619
3620         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3621
3622         tmp = cmd->scan_begin_arg;
3623         tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3624         if (tmp != cmd->scan_begin_arg)
3625                 err |= -EINVAL;
3626
3627         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3628         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3629                                            cmd->chanlist_len);
3630         err |= comedi_check_trigger_arg_max(&cmd->stop_arg,
3631                                             s->async->prealloc_bufsz /
3632                                             comedi_bytes_per_scan(s));
3633
3634         if (err)
3635                 return 3;
3636
3637         /* Step 4: fix up any arguments */
3638
3639         /* Step 5: check channel list if it exists */
3640
3641         if (cmd->chanlist && cmd->chanlist_len > 0)
3642                 err |= ni_cdio_check_chanlist(dev, s, cmd);
3643
3644         if (err)
3645                 return 5;
3646
3647         return 0;
3648 }
3649
3650 static int ni_cdo_inttrig(struct comedi_device *dev,
3651                           struct comedi_subdevice *s,
3652                           unsigned int trig_num)
3653 {
3654         struct comedi_cmd *cmd = &s->async->cmd;
3655         const unsigned timeout = 1000;
3656         int retval = 0;
3657         unsigned i;
3658 #ifdef PCIDMA
3659         struct ni_private *devpriv = dev->private;
3660         unsigned long flags;
3661 #endif
3662
3663         if (trig_num != cmd->start_arg)
3664                 return -EINVAL;
3665
3666         s->async->inttrig = NULL;
3667
3668         /* read alloc the entire buffer */
3669         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3670
3671 #ifdef PCIDMA
3672         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3673         if (devpriv->cdo_mite_chan) {
3674                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3675                 mite_dma_arm(devpriv->cdo_mite_chan);
3676         } else {
3677                 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3678                 retval = -EIO;
3679         }
3680         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3681         if (retval < 0)
3682                 return retval;
3683 #endif
3684         /*
3685          * XXX not sure what interrupt C group does
3686          * wait for dma to fill output fifo
3687          * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3688          */
3689         for (i = 0; i < timeout; ++i) {
3690                 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3691                     NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3692                         break;
3693                 udelay(10);
3694         }
3695         if (i == timeout) {
3696                 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3697                 s->cancel(dev, s);
3698                 return -EIO;
3699         }
3700         ni_writel(dev, NI_M_CDO_CMD_ARM |
3701                        NI_M_CDO_CMD_ERR_INT_ENA_SET |
3702                        NI_M_CDO_CMD_F_E_INT_ENA_SET,
3703                   NI_M_CDIO_CMD_REG);
3704         return retval;
3705 }
3706
3707 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3708 {
3709         struct ni_private *devpriv = dev->private;
3710         const struct comedi_cmd *cmd = &s->async->cmd;
3711         unsigned cdo_mode_bits;
3712         int retval;
3713
3714         ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3715         cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3716                         NI_M_CDO_MODE_HALT_ON_ERROR |
3717                         NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3718         if (cmd->scan_begin_arg & CR_INVERT)
3719                 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3720         ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3721         if (s->io_bits) {
3722                 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3723                 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3724                 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3725         } else {
3726                 dev_err(dev->class_dev,
3727                         "attempted to run digital output command with no lines configured as outputs\n");
3728                 return -EIO;
3729         }
3730         retval = ni_request_cdo_mite_channel(dev);
3731         if (retval < 0)
3732                 return retval;
3733
3734         ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd,
3735                                  s->async->prealloc_bufsz /
3736                                  comedi_bytes_per_scan(s));
3737
3738         s->async->inttrig = ni_cdo_inttrig;
3739
3740         return 0;
3741 }
3742
3743 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3744 {
3745         ni_writel(dev, NI_M_CDO_CMD_DISARM |
3746                        NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3747                        NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3748                        NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3749                   NI_M_CDIO_CMD_REG);
3750         /*
3751          * XXX not sure what interrupt C group does
3752          * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3753          */
3754         ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3755         ni_release_cdo_mite_channel(dev);
3756         return 0;
3757 }
3758
3759 static void handle_cdio_interrupt(struct comedi_device *dev)
3760 {
3761         struct ni_private *devpriv = dev->private;
3762         unsigned cdio_status;
3763         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3764 #ifdef PCIDMA
3765         unsigned long flags;
3766 #endif
3767
3768         if (!devpriv->is_m_series)
3769                 return;
3770 #ifdef PCIDMA
3771         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3772         if (devpriv->cdo_mite_chan) {
3773                 unsigned cdo_mite_status =
3774                     mite_get_status(devpriv->cdo_mite_chan);
3775                 if (cdo_mite_status & CHSR_LINKC) {
3776                         writel(CHOR_CLRLC,
3777                                devpriv->mite->mite_io_addr +
3778                                MITE_CHOR(devpriv->cdo_mite_chan->channel));
3779                 }
3780                 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
3781         }
3782         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3783 #endif
3784
3785         cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3786         if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3787                 /* XXX just guessing this is needed and does something useful */
3788                 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3789                           NI_M_CDIO_CMD_REG);
3790                 s->async->events |= COMEDI_CB_OVERFLOW;
3791         }
3792         if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3793                 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3794                           NI_M_CDIO_CMD_REG);
3795                 /* s->async->events |= COMEDI_CB_EOA; */
3796         }
3797         comedi_handle_events(dev, s);
3798 }
3799
3800 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3801                                    struct comedi_subdevice *s,
3802                                    unsigned char data_out,
3803                                    unsigned char *data_in)
3804 {
3805         struct ni_private *devpriv = dev->private;
3806         unsigned int status1;
3807         int err = 0, count = 20;
3808
3809         devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3810         devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3811         ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3812
3813         status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3814         if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3815                 err = -EBUSY;
3816                 goto Error;
3817         }
3818
3819         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3820         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3821         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3822
3823         /* Wait until STC says we're done, but don't loop infinitely. */
3824         while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3825                NISTC_STATUS1_SERIO_IN_PROG) {
3826                 /* Delay one bit per loop */
3827                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3828                 if (--count < 0) {
3829                         dev_err(dev->class_dev,
3830                                 "SPI serial I/O didn't finish in time!\n");
3831                         err = -ETIME;
3832                         goto Error;
3833                 }
3834         }
3835
3836         /*
3837          * Delay for last bit. This delay is absolutely necessary, because
3838          * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3839          */
3840         udelay((devpriv->serial_interval_ns + 999) / 1000);
3841
3842         if (data_in)
3843                 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3844
3845 Error:
3846         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3847
3848         return err;
3849 }
3850
3851 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3852                                    struct comedi_subdevice *s,
3853                                    unsigned char data_out,
3854                                    unsigned char *data_in)
3855 {
3856         struct ni_private *devpriv = dev->private;
3857         unsigned char mask, input = 0;
3858
3859         /* Wait for one bit before transfer */
3860         udelay((devpriv->serial_interval_ns + 999) / 1000);
3861
3862         for (mask = 0x80; mask; mask >>= 1) {
3863                 /* Output current bit; note that we cannot touch s->state
3864                    because it is a per-subdevice field, and serial is
3865                    a separate subdevice from DIO. */
3866                 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3867                 if (data_out & mask)
3868                         devpriv->dio_output |= NISTC_DIO_SDOUT;
3869                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3870
3871                 /* Assert SDCLK (active low, inverted), wait for half of
3872                    the delay, deassert SDCLK, and wait for the other half. */
3873                 devpriv->dio_control |= NISTC_DIO_SDCLK;
3874                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3875
3876                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3877
3878                 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3879                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3880
3881                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3882
3883                 /* Input current bit */
3884                 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3885                         input |= mask;
3886         }
3887
3888         if (data_in)
3889                 *data_in = input;
3890
3891         return 0;
3892 }
3893
3894 static int ni_serial_insn_config(struct comedi_device *dev,
3895                                  struct comedi_subdevice *s,
3896                                  struct comedi_insn *insn,
3897                                  unsigned int *data)
3898 {
3899         struct ni_private *devpriv = dev->private;
3900         unsigned clk_fout = devpriv->clock_and_fout;
3901         int err = insn->n;
3902         unsigned char byte_out, byte_in = 0;
3903
3904         if (insn->n != 2)
3905                 return -EINVAL;
3906
3907         switch (data[0]) {
3908         case INSN_CONFIG_SERIAL_CLOCK:
3909                 devpriv->serial_hw_mode = 1;
3910                 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3911
3912                 if (data[1] == SERIAL_DISABLED) {
3913                         devpriv->serial_hw_mode = 0;
3914                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3915                                                   NISTC_DIO_SDCLK);
3916                         data[1] = SERIAL_DISABLED;
3917                         devpriv->serial_interval_ns = data[1];
3918                 } else if (data[1] <= SERIAL_600NS) {
3919                         /* Warning: this clock speed is too fast to reliably
3920                            control SCXI. */
3921                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3922                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3923                         clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3924                         data[1] = SERIAL_600NS;
3925                         devpriv->serial_interval_ns = data[1];
3926                 } else if (data[1] <= SERIAL_1_2US) {
3927                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3928                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3929                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3930                         data[1] = SERIAL_1_2US;
3931                         devpriv->serial_interval_ns = data[1];
3932                 } else if (data[1] <= SERIAL_10US) {
3933                         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3934                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3935                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3936                         /* Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3937                            600ns/1.2us. If you turn divide_by_2 off with the
3938                            slow clock, you will still get 10us, except then
3939                            all your delays are wrong. */
3940                         data[1] = SERIAL_10US;
3941                         devpriv->serial_interval_ns = data[1];
3942                 } else {
3943                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3944                                                   NISTC_DIO_SDCLK);
3945                         devpriv->serial_hw_mode = 0;
3946                         data[1] = (data[1] / 1000) * 1000;
3947                         devpriv->serial_interval_ns = data[1];
3948                 }
3949                 devpriv->clock_and_fout = clk_fout;
3950
3951                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3952                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3953                 return 1;
3954
3955         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3956
3957                 if (devpriv->serial_interval_ns == 0)
3958                         return -EINVAL;
3959
3960                 byte_out = data[1] & 0xFF;
3961
3962                 if (devpriv->serial_hw_mode) {
3963                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3964                                                       &byte_in);
3965                 } else if (devpriv->serial_interval_ns > 0) {
3966                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3967                                                       &byte_in);
3968                 } else {
3969                         dev_err(dev->class_dev, "serial disabled!\n");
3970                         return -EINVAL;
3971                 }
3972                 if (err < 0)
3973                         return err;
3974                 data[1] = byte_in & 0xFF;
3975                 return insn->n;
3976
3977                 break;
3978         default:
3979                 return -EINVAL;
3980         }
3981 }
3982
3983 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3984 {
3985         int i;
3986
3987         for (i = 0; i < s->n_chan; i++) {
3988                 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3989                                NI67XX_AO_CFG2_REG);
3990         }
3991         ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3992 }
3993
3994 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3995         [NITIO_G0_AUTO_INC]     = { NISTC_G0_AUTOINC_REG, 2 },
3996         [NITIO_G1_AUTO_INC]     = { NISTC_G1_AUTOINC_REG, 2 },
3997         [NITIO_G0_CMD]          = { NISTC_G0_CMD_REG, 2 },
3998         [NITIO_G1_CMD]          = { NISTC_G1_CMD_REG, 2 },
3999         [NITIO_G0_HW_SAVE]      = { NISTC_G0_HW_SAVE_REG, 4 },
4000         [NITIO_G1_HW_SAVE]      = { NISTC_G1_HW_SAVE_REG, 4 },
4001         [NITIO_G0_SW_SAVE]      = { NISTC_G0_SAVE_REG, 4 },
4002         [NITIO_G1_SW_SAVE]      = { NISTC_G1_SAVE_REG, 4 },
4003         [NITIO_G0_MODE]         = { NISTC_G0_MODE_REG, 2 },
4004         [NITIO_G1_MODE]         = { NISTC_G1_MODE_REG, 2 },
4005         [NITIO_G0_LOADA]        = { NISTC_G0_LOADA_REG, 4 },
4006         [NITIO_G1_LOADA]        = { NISTC_G1_LOADA_REG, 4 },
4007         [NITIO_G0_LOADB]        = { NISTC_G0_LOADB_REG, 4 },
4008         [NITIO_G1_LOADB]        = { NISTC_G1_LOADB_REG, 4 },
4009         [NITIO_G0_INPUT_SEL]    = { NISTC_G0_INPUT_SEL_REG, 2 },
4010         [NITIO_G1_INPUT_SEL]    = { NISTC_G1_INPUT_SEL_REG, 2 },
4011         [NITIO_G0_CNT_MODE]     = { 0x1b0, 2 }, /* M-Series only */
4012         [NITIO_G1_CNT_MODE]     = { 0x1b2, 2 }, /* M-Series only */
4013         [NITIO_G0_GATE2]        = { 0x1b4, 2 }, /* M-Series only */
4014         [NITIO_G1_GATE2]        = { 0x1b6, 2 }, /* M-Series only */
4015         [NITIO_G01_STATUS]      = { NISTC_G01_STATUS_REG, 2 },
4016         [NITIO_G01_RESET]       = { NISTC_RESET_REG, 2 },
4017         [NITIO_G01_STATUS1]     = { NISTC_STATUS1_REG, 2 },
4018         [NITIO_G01_STATUS2]     = { NISTC_STATUS2_REG, 2 },
4019         [NITIO_G0_DMA_CFG]      = { 0x1b8, 2 }, /* M-Series only */
4020         [NITIO_G1_DMA_CFG]      = { 0x1ba, 2 }, /* M-Series only */
4021         [NITIO_G0_DMA_STATUS]   = { 0x1b8, 2 }, /* M-Series only */
4022         [NITIO_G1_DMA_STATUS]   = { 0x1ba, 2 }, /* M-Series only */
4023         [NITIO_G0_ABZ]          = { 0x1c0, 2 }, /* M-Series only */
4024         [NITIO_G1_ABZ]          = { 0x1c2, 2 }, /* M-Series only */
4025         [NITIO_G0_INT_ACK]      = { NISTC_INTA_ACK_REG, 2 },
4026         [NITIO_G1_INT_ACK]      = { NISTC_INTB_ACK_REG, 2 },
4027         [NITIO_G0_STATUS]       = { NISTC_AI_STATUS1_REG, 2 },
4028         [NITIO_G1_STATUS]       = { NISTC_AO_STATUS1_REG, 2 },
4029         [NITIO_G0_INT_ENA]      = { NISTC_INTA_ENA_REG, 2 },
4030         [NITIO_G1_INT_ENA]      = { NISTC_INTB_ENA_REG, 2 },
4031 };
4032
4033 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
4034                                             enum ni_gpct_register reg)
4035 {
4036         const struct mio_regmap *regmap;
4037
4038         if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
4039                 regmap = &ni_gpct_to_stc_regmap[reg];
4040         } else {
4041                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
4042                          __func__, reg);
4043                 return 0;
4044         }
4045
4046         return regmap->mio_reg;
4047 }
4048
4049 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4050                                    enum ni_gpct_register reg)
4051 {
4052         struct comedi_device *dev = counter->counter_dev->dev;
4053         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4054         static const unsigned gpct_interrupt_a_enable_mask =
4055             NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC;
4056         static const unsigned gpct_interrupt_b_enable_mask =
4057             NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC;
4058
4059         if (stc_register == 0)
4060                 return;
4061
4062         switch (reg) {
4063                 /* m-series only registers */
4064         case NITIO_G0_CNT_MODE:
4065         case NITIO_G1_CNT_MODE:
4066         case NITIO_G0_GATE2:
4067         case NITIO_G1_GATE2:
4068         case NITIO_G0_DMA_CFG:
4069         case NITIO_G1_DMA_CFG:
4070         case NITIO_G0_ABZ:
4071         case NITIO_G1_ABZ:
4072                 ni_writew(dev, bits, stc_register);
4073                 break;
4074
4075                 /* 32 bit registers */
4076         case NITIO_G0_LOADA:
4077         case NITIO_G1_LOADA:
4078         case NITIO_G0_LOADB:
4079         case NITIO_G1_LOADB:
4080                 ni_stc_writel(dev, bits, stc_register);
4081                 break;
4082
4083                 /* 16 bit registers */
4084         case NITIO_G0_INT_ENA:
4085                 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4086                 ni_set_bitfield(dev, stc_register,
4087                                 gpct_interrupt_a_enable_mask, bits);
4088                 break;
4089         case NITIO_G1_INT_ENA:
4090                 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4091                 ni_set_bitfield(dev, stc_register,
4092                                 gpct_interrupt_b_enable_mask, bits);
4093                 break;
4094         case NITIO_G01_RESET:
4095                 BUG_ON(bits & ~(NISTC_RESET_G0 | NISTC_RESET_G1));
4096                 /* fall-through */
4097         default:
4098                 ni_stc_writew(dev, bits, stc_register);
4099         }
4100 }
4101
4102 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4103                                       enum ni_gpct_register reg)
4104 {
4105         struct comedi_device *dev = counter->counter_dev->dev;
4106         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4107
4108         if (stc_register == 0)
4109                 return 0;
4110
4111         switch (reg) {
4112                 /* m-series only registers */
4113         case NITIO_G0_DMA_STATUS:
4114         case NITIO_G1_DMA_STATUS:
4115                 return ni_readw(dev, stc_register);
4116
4117                 /* 32 bit registers */
4118         case NITIO_G0_HW_SAVE:
4119         case NITIO_G1_HW_SAVE:
4120         case NITIO_G0_SW_SAVE:
4121         case NITIO_G1_SW_SAVE:
4122                 return ni_stc_readl(dev, stc_register);
4123
4124                 /* 16 bit registers */
4125         default:
4126                 return ni_stc_readw(dev, stc_register);
4127         }
4128 }
4129
4130 static int ni_freq_out_insn_read(struct comedi_device *dev,
4131                                  struct comedi_subdevice *s,
4132                                  struct comedi_insn *insn,
4133                                  unsigned int *data)
4134 {
4135         struct ni_private *devpriv = dev->private;
4136         unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
4137         int i;
4138
4139         for (i = 0; i < insn->n; i++)
4140                 data[i] = val;
4141
4142         return insn->n;
4143 }
4144
4145 static int ni_freq_out_insn_write(struct comedi_device *dev,
4146                                   struct comedi_subdevice *s,
4147                                   struct comedi_insn *insn,
4148                                   unsigned int *data)
4149 {
4150         struct ni_private *devpriv = dev->private;
4151
4152         if (insn->n) {
4153                 unsigned int val = data[insn->n - 1];
4154
4155                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
4156                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4157                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
4158
4159                 /* use the last data value to set the fout divider */
4160                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
4161
4162                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
4163                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4164         }
4165         return insn->n;
4166 }
4167
4168 static int ni_freq_out_insn_config(struct comedi_device *dev,
4169                                    struct comedi_subdevice *s,
4170                                    struct comedi_insn *insn,
4171                                    unsigned int *data)
4172 {
4173         struct ni_private *devpriv = dev->private;
4174
4175         switch (data[0]) {
4176         case INSN_CONFIG_SET_CLOCK_SRC:
4177                 switch (data[1]) {
4178                 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4179                         devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
4180                         break;
4181                 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4182                         devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
4183                         break;
4184                 default:
4185                         return -EINVAL;
4186                 }
4187                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4188                 break;
4189         case INSN_CONFIG_GET_CLOCK_SRC:
4190                 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
4191                         data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4192                         data[2] = TIMEBASE_2_NS;
4193                 } else {
4194                         data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4195                         data[2] = TIMEBASE_1_NS * 2;
4196                 }
4197                 break;
4198         default:
4199                 return -EINVAL;
4200         }
4201         return insn->n;
4202 }
4203
4204 static int ni_8255_callback(struct comedi_device *dev,
4205                             int dir, int port, int data, unsigned long iobase)
4206 {
4207         if (dir) {
4208                 ni_writeb(dev, data, iobase + 2 * port);
4209                 return 0;
4210         }
4211
4212         return ni_readb(dev, iobase + 2 * port);
4213 }
4214
4215 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4216 {
4217         struct ni_private *devpriv = dev->private;
4218
4219         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4220         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4221         return 3;
4222 }
4223
4224 static int ni_m_series_pwm_config(struct comedi_device *dev,
4225                                   struct comedi_subdevice *s,
4226                                   struct comedi_insn *insn,
4227                                   unsigned int *data)
4228 {
4229         struct ni_private *devpriv = dev->private;
4230         unsigned up_count, down_count;
4231
4232         switch (data[0]) {
4233         case INSN_CONFIG_PWM_OUTPUT:
4234                 switch (data[1]) {
4235                 case CMDF_ROUND_NEAREST:
4236                         up_count = DIV_ROUND_CLOSEST(data[2],
4237                                                      devpriv->clock_ns);
4238                         break;
4239                 case CMDF_ROUND_DOWN:
4240                         up_count = data[2] / devpriv->clock_ns;
4241                         break;
4242                 case CMDF_ROUND_UP:
4243                         up_count =
4244                             DIV_ROUND_UP(data[2], devpriv->clock_ns);
4245                         break;
4246                 default:
4247                         return -EINVAL;
4248                 }
4249                 switch (data[3]) {
4250                 case CMDF_ROUND_NEAREST:
4251                         down_count = DIV_ROUND_CLOSEST(data[4],
4252                                                        devpriv->clock_ns);
4253                         break;
4254                 case CMDF_ROUND_DOWN:
4255                         down_count = data[4] / devpriv->clock_ns;
4256                         break;
4257                 case CMDF_ROUND_UP:
4258                         down_count =
4259                             DIV_ROUND_UP(data[4], devpriv->clock_ns);
4260                         break;
4261                 default:
4262                         return -EINVAL;
4263                 }
4264                 if (up_count * devpriv->clock_ns != data[2] ||
4265                     down_count * devpriv->clock_ns != data[4]) {
4266                         data[2] = up_count * devpriv->clock_ns;
4267                         data[4] = down_count * devpriv->clock_ns;
4268                         return -EAGAIN;
4269                 }
4270                 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4271                                NI_M_CAL_PWM_LOW_TIME(down_count),
4272                           NI_M_CAL_PWM_REG);
4273                 devpriv->pwm_up_count = up_count;
4274                 devpriv->pwm_down_count = down_count;
4275                 return 5;
4276         case INSN_CONFIG_GET_PWM_OUTPUT:
4277                 return ni_get_pwm_config(dev, data);
4278         default:
4279                 return -EINVAL;
4280         }
4281         return 0;
4282 }
4283
4284 static int ni_6143_pwm_config(struct comedi_device *dev,
4285                               struct comedi_subdevice *s,
4286                               struct comedi_insn *insn,
4287                               unsigned int *data)
4288 {
4289         struct ni_private *devpriv = dev->private;
4290         unsigned up_count, down_count;
4291
4292         switch (data[0]) {
4293         case INSN_CONFIG_PWM_OUTPUT:
4294                 switch (data[1]) {
4295                 case CMDF_ROUND_NEAREST:
4296                         up_count = DIV_ROUND_CLOSEST(data[2],
4297                                                      devpriv->clock_ns);
4298                         break;
4299                 case CMDF_ROUND_DOWN:
4300                         up_count = data[2] / devpriv->clock_ns;
4301                         break;
4302                 case CMDF_ROUND_UP:
4303                         up_count =
4304                             DIV_ROUND_UP(data[2], devpriv->clock_ns);
4305                         break;
4306                 default:
4307                         return -EINVAL;
4308                 }
4309                 switch (data[3]) {
4310                 case CMDF_ROUND_NEAREST:
4311                         down_count = DIV_ROUND_CLOSEST(data[4],
4312                                                        devpriv->clock_ns);
4313                         break;
4314                 case CMDF_ROUND_DOWN:
4315                         down_count = data[4] / devpriv->clock_ns;
4316                         break;
4317                 case CMDF_ROUND_UP:
4318                         down_count =
4319                             DIV_ROUND_UP(data[4], devpriv->clock_ns);
4320                         break;
4321                 default:
4322                         return -EINVAL;
4323                 }
4324                 if (up_count * devpriv->clock_ns != data[2] ||
4325                     down_count * devpriv->clock_ns != data[4]) {
4326                         data[2] = up_count * devpriv->clock_ns;
4327                         data[4] = down_count * devpriv->clock_ns;
4328                         return -EAGAIN;
4329                 }
4330                 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4331                 devpriv->pwm_up_count = up_count;
4332                 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4333                 devpriv->pwm_down_count = down_count;
4334                 return 5;
4335         case INSN_CONFIG_GET_PWM_OUTPUT:
4336                 return ni_get_pwm_config(dev, data);
4337         default:
4338                 return -EINVAL;
4339         }
4340         return 0;
4341 }
4342
4343 static int pack_mb88341(int addr, int val, int *bitstring)
4344 {
4345         /*
4346            Fujitsu MB 88341
4347            Note that address bits are reversed.  Thanks to
4348            Ingo Keen for noticing this.
4349
4350            Note also that the 88341 expects address values from
4351            1-12, whereas we use channel numbers 0-11.  The NI
4352            docs use 1-12, also, so be careful here.
4353          */
4354         addr++;
4355         *bitstring = ((addr & 0x1) << 11) |
4356             ((addr & 0x2) << 9) |
4357             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4358         return 12;
4359 }
4360
4361 static int pack_dac8800(int addr, int val, int *bitstring)
4362 {
4363         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4364         return 11;
4365 }
4366
4367 static int pack_dac8043(int addr, int val, int *bitstring)
4368 {
4369         *bitstring = val & 0xfff;
4370         return 12;
4371 }
4372
4373 static int pack_ad8522(int addr, int val, int *bitstring)
4374 {
4375         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4376         return 16;
4377 }
4378
4379 static int pack_ad8804(int addr, int val, int *bitstring)
4380 {
4381         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4382         return 12;
4383 }
4384
4385 static int pack_ad8842(int addr, int val, int *bitstring)
4386 {
4387         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4388         return 12;
4389 }
4390
4391 struct caldac_struct {
4392         int n_chans;
4393         int n_bits;
4394         int (*packbits)(int, int, int *);
4395 };
4396
4397 static struct caldac_struct caldacs[] = {
4398         [mb88341] = {12, 8, pack_mb88341},
4399         [dac8800] = {8, 8, pack_dac8800},
4400         [dac8043] = {1, 12, pack_dac8043},
4401         [ad8522] = {2, 12, pack_ad8522},
4402         [ad8804] = {12, 8, pack_ad8804},
4403         [ad8842] = {8, 8, pack_ad8842},
4404         [ad8804_debug] = {16, 8, pack_ad8804},
4405 };
4406
4407 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4408 {
4409         const struct ni_board_struct *board = dev->board_ptr;
4410         struct ni_private *devpriv = dev->private;
4411         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4412         unsigned int cmd;
4413         int i;
4414         int type;
4415
4416         if (devpriv->caldacs[addr] == val)
4417                 return;
4418         devpriv->caldacs[addr] = val;
4419
4420         for (i = 0; i < 3; i++) {
4421                 type = board->caldac[i];
4422                 if (type == caldac_none)
4423                         break;
4424                 if (addr < caldacs[type].n_chans) {
4425                         bits = caldacs[type].packbits(addr, val, &bitstring);
4426                         loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4427                         break;
4428                 }
4429                 addr -= caldacs[type].n_chans;
4430         }
4431
4432         /* bits will be 0 if there is no caldac for the given addr */
4433         if (bits == 0)
4434                 return;
4435
4436         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4437                 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4438                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4439                 udelay(1);
4440                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4441                 udelay(1);
4442         }
4443         ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4444         udelay(1);
4445         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4446 }
4447
4448 static int ni_calib_insn_write(struct comedi_device *dev,
4449                                struct comedi_subdevice *s,
4450                                struct comedi_insn *insn,
4451                                unsigned int *data)
4452 {
4453         ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4454
4455         return 1;
4456 }
4457
4458 static int ni_calib_insn_read(struct comedi_device *dev,
4459                               struct comedi_subdevice *s,
4460                               struct comedi_insn *insn,
4461                               unsigned int *data)
4462 {
4463         struct ni_private *devpriv = dev->private;
4464
4465         data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4466
4467         return 1;
4468 }
4469
4470 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4471 {
4472         const struct ni_board_struct *board = dev->board_ptr;
4473         struct ni_private *devpriv = dev->private;
4474         int i, j;
4475         int n_dacs;
4476         int n_chans = 0;
4477         int n_bits;
4478         int diffbits = 0;
4479         int type;
4480         int chan;
4481
4482         type = board->caldac[0];
4483         if (type == caldac_none)
4484                 return;
4485         n_bits = caldacs[type].n_bits;
4486         for (i = 0; i < 3; i++) {
4487                 type = board->caldac[i];
4488                 if (type == caldac_none)
4489                         break;
4490                 if (caldacs[type].n_bits != n_bits)
4491                         diffbits = 1;
4492                 n_chans += caldacs[type].n_chans;
4493         }
4494         n_dacs = i;
4495         s->n_chan = n_chans;
4496
4497         if (diffbits) {
4498                 unsigned int *maxdata_list;
4499
4500                 if (n_chans > MAX_N_CALDACS)
4501                         dev_err(dev->class_dev,
4502                                 "BUG! MAX_N_CALDACS too small\n");
4503                 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4504                 chan = 0;
4505                 for (i = 0; i < n_dacs; i++) {
4506                         type = board->caldac[i];
4507                         for (j = 0; j < caldacs[type].n_chans; j++) {
4508                                 maxdata_list[chan] =
4509                                     (1 << caldacs[type].n_bits) - 1;
4510                                 chan++;
4511                         }
4512                 }
4513
4514                 for (chan = 0; chan < s->n_chan; chan++)
4515                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4516         } else {
4517                 type = board->caldac[0];
4518                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4519
4520                 for (chan = 0; chan < s->n_chan; chan++)
4521                         ni_write_caldac(dev, i, s->maxdata / 2);
4522         }
4523 }
4524
4525 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4526 {
4527         unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4528         int bit;
4529         int bitstring;
4530
4531         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4532         ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4533         for (bit = 0x8000; bit; bit >>= 1) {
4534                 if (bit & bitstring)
4535                         cmd |= NI_E_SERIAL_CMD_SDATA;
4536                 else
4537                         cmd &= ~NI_E_SERIAL_CMD_SDATA;
4538
4539                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4540                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4541         }
4542         cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4543         bitstring = 0;
4544         for (bit = 0x80; bit; bit >>= 1) {
4545                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4546                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4547                 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4548                         bitstring |= bit;
4549         }
4550         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4551
4552         return bitstring;
4553 }
4554
4555 static int ni_eeprom_insn_read(struct comedi_device *dev,
4556                                struct comedi_subdevice *s,
4557                                struct comedi_insn *insn,
4558                                unsigned int *data)
4559 {
4560         data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4561
4562         return 1;
4563 }
4564
4565 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4566                                         struct comedi_subdevice *s,
4567                                         struct comedi_insn *insn,
4568                                         unsigned int *data)
4569 {
4570         struct ni_private *devpriv = dev->private;
4571
4572         data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4573
4574         return 1;
4575 }
4576
4577 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
4578                                        unsigned chan)
4579 {
4580         /*  pre-m-series boards have fixed signals on pfi pins */
4581         switch (chan) {
4582         case 0:
4583                 return NI_PFI_OUTPUT_AI_START1;
4584         case 1:
4585                 return NI_PFI_OUTPUT_AI_START2;
4586         case 2:
4587                 return NI_PFI_OUTPUT_AI_CONVERT;
4588         case 3:
4589                 return NI_PFI_OUTPUT_G_SRC1;
4590         case 4:
4591                 return NI_PFI_OUTPUT_G_GATE1;
4592         case 5:
4593                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4594         case 6:
4595                 return NI_PFI_OUTPUT_AO_START1;
4596         case 7:
4597                 return NI_PFI_OUTPUT_AI_START_PULSE;
4598         case 8:
4599                 return NI_PFI_OUTPUT_G_SRC0;
4600         case 9:
4601                 return NI_PFI_OUTPUT_G_GATE0;
4602         default:
4603                 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4604                 break;
4605         }
4606         return 0;
4607 }
4608
4609 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4610                                   unsigned chan, unsigned source)
4611 {
4612         /*  pre-m-series boards have fixed signals on pfi pins */
4613         if (source != ni_old_get_pfi_routing(dev, chan))
4614                 return -EINVAL;
4615         return 2;
4616 }
4617
4618 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
4619                                             unsigned chan)
4620 {
4621         struct ni_private *devpriv = dev->private;
4622         const unsigned array_offset = chan / 3;
4623
4624         return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4625                                 devpriv->pfi_output_select_reg[array_offset]);
4626 }
4627
4628 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4629                                        unsigned chan, unsigned source)
4630 {
4631         struct ni_private *devpriv = dev->private;
4632         unsigned index = chan / 3;
4633         unsigned short val = devpriv->pfi_output_select_reg[index];
4634
4635         if ((source & 0x1f) != source)
4636                 return -EINVAL;
4637
4638         val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4639         val |= NI_M_PFI_OUT_SEL(chan, source);
4640         ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4641         devpriv->pfi_output_select_reg[index] = val;
4642
4643         return 2;
4644 }
4645
4646 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
4647 {
4648         struct ni_private *devpriv = dev->private;
4649
4650         return (devpriv->is_m_series)
4651                         ? ni_m_series_get_pfi_routing(dev, chan)
4652                         : ni_old_get_pfi_routing(dev, chan);
4653 }
4654
4655 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
4656                               unsigned source)
4657 {
4658         struct ni_private *devpriv = dev->private;
4659
4660         return (devpriv->is_m_series)
4661                         ? ni_m_series_set_pfi_routing(dev, chan, source)
4662                         : ni_old_set_pfi_routing(dev, chan, source);
4663 }
4664
4665 static int ni_config_filter(struct comedi_device *dev,
4666                             unsigned pfi_channel,
4667                             enum ni_pfi_filter_select filter)
4668 {
4669         struct ni_private *devpriv = dev->private;
4670         unsigned bits;
4671
4672         if (!devpriv->is_m_series)
4673                 return -ENOTSUPP;
4674
4675         bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4676         bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4677         bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4678         ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4679         return 0;
4680 }
4681
4682 static int ni_pfi_insn_config(struct comedi_device *dev,
4683                               struct comedi_subdevice *s,
4684                               struct comedi_insn *insn,
4685                               unsigned int *data)
4686 {
4687         struct ni_private *devpriv = dev->private;
4688         unsigned int chan;
4689
4690         if (insn->n < 1)
4691                 return -EINVAL;
4692
4693         chan = CR_CHAN(insn->chanspec);
4694
4695         switch (data[0]) {
4696         case COMEDI_OUTPUT:
4697                 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4698                 break;
4699         case COMEDI_INPUT:
4700                 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4701                 break;
4702         case INSN_CONFIG_DIO_QUERY:
4703                 data[1] =
4704                     (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4705                     COMEDI_OUTPUT : COMEDI_INPUT;
4706                 return 0;
4707         case INSN_CONFIG_SET_ROUTING:
4708                 return ni_set_pfi_routing(dev, chan, data[1]);
4709         case INSN_CONFIG_GET_ROUTING:
4710                 data[1] = ni_get_pfi_routing(dev, chan);
4711                 break;
4712         case INSN_CONFIG_FILTER:
4713                 return ni_config_filter(dev, chan, data[1]);
4714         default:
4715                 return -EINVAL;
4716         }
4717         return 0;
4718 }
4719
4720 static int ni_pfi_insn_bits(struct comedi_device *dev,
4721                             struct comedi_subdevice *s,
4722                             struct comedi_insn *insn,
4723                             unsigned int *data)
4724 {
4725         struct ni_private *devpriv = dev->private;
4726
4727         if (!devpriv->is_m_series)
4728                 return -ENOTSUPP;
4729
4730         if (comedi_dio_update_state(s, data))
4731                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4732
4733         data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4734
4735         return insn->n;
4736 }
4737
4738 static int cs5529_wait_for_idle(struct comedi_device *dev)
4739 {
4740         unsigned short status;
4741         const int timeout = HZ;
4742         int i;
4743
4744         for (i = 0; i < timeout; i++) {
4745                 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4746                 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4747                         break;
4748                 set_current_state(TASK_INTERRUPTIBLE);
4749                 if (schedule_timeout(1))
4750                         return -EIO;
4751         }
4752         if (i == timeout) {
4753                 dev_err(dev->class_dev, "timeout\n");
4754                 return -ETIME;
4755         }
4756         return 0;
4757 }
4758
4759 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4760 {
4761         static const int timeout = 100;
4762         int i;
4763
4764         ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4765         /* give time for command to start being serially clocked into cs5529.
4766          * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4767          * set before we exit this function.
4768          */
4769         for (i = 0; i < timeout; i++) {
4770                 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4771                     NI67XX_CAL_STATUS_BUSY)
4772                         break;
4773                 udelay(1);
4774         }
4775         if (i == timeout)
4776                 dev_err(dev->class_dev,
4777                         "possible problem - never saw adc go busy?\n");
4778 }
4779
4780 static int cs5529_do_conversion(struct comedi_device *dev,
4781                                 unsigned short *data)
4782 {
4783         int retval;
4784         unsigned short status;
4785
4786         cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4787         retval = cs5529_wait_for_idle(dev);
4788         if (retval) {
4789                 dev_err(dev->class_dev,
4790                         "timeout or signal in cs5529_do_conversion()\n");
4791                 return -ETIME;
4792         }
4793         status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4794         if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4795                 dev_err(dev->class_dev,
4796                         "cs5529 conversion error, status CSS_OSC_DETECT\n");
4797                 return -EIO;
4798         }
4799         if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4800                 dev_err(dev->class_dev,
4801                         "cs5529 conversion error, overrange (ignoring)\n");
4802         }
4803         if (data) {
4804                 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4805                 /* cs5529 returns 16 bit signed data in bipolar mode */
4806                 *data ^= (1 << 15);
4807         }
4808         return 0;
4809 }
4810
4811 static int cs5529_ai_insn_read(struct comedi_device *dev,
4812                                struct comedi_subdevice *s,
4813                                struct comedi_insn *insn,
4814                                unsigned int *data)
4815 {
4816         int n, retval;
4817         unsigned short sample;
4818         unsigned int channel_select;
4819         const unsigned int INTERNAL_REF = 0x1000;
4820
4821         /* Set calibration adc source.  Docs lie, reference select bits 8 to 11
4822          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4823          * 13 causes the adc input to go overrange (maybe reads external reference?) */
4824         if (insn->chanspec & CR_ALT_SOURCE)
4825                 channel_select = INTERNAL_REF;
4826         else
4827                 channel_select = CR_CHAN(insn->chanspec);
4828         ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4829
4830         for (n = 0; n < insn->n; n++) {
4831                 retval = cs5529_do_conversion(dev, &sample);
4832                 if (retval < 0)
4833                         return retval;
4834                 data[n] = sample;
4835         }
4836         return insn->n;
4837 }
4838
4839 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4840                                 unsigned int reg_select_bits)
4841 {
4842         ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4843         ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4844         reg_select_bits &= CS5529_CMD_REG_MASK;
4845         cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4846         if (cs5529_wait_for_idle(dev))
4847                 dev_err(dev->class_dev,
4848                         "timeout or signal in %s\n", __func__);
4849 }
4850
4851 static int init_cs5529(struct comedi_device *dev)
4852 {
4853         unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4854                                    CS5529_CFG_WORD_RATE_2180;
4855
4856 #if 1
4857         /* do self-calibration */
4858         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4859                             CS5529_CFG_REG);
4860         /* need to force a conversion for calibration to run */
4861         cs5529_do_conversion(dev, NULL);
4862 #else
4863         /* force gain calibration to 1 */
4864         cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4865         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4866                             CS5529_CFG_REG);
4867         if (cs5529_wait_for_idle(dev))
4868                 dev_err(dev->class_dev,
4869                         "timeout or signal in %s\n", __func__);
4870 #endif
4871         return 0;
4872 }
4873
4874 /*
4875  * Find best multiplier/divider to try and get the PLL running at 80 MHz
4876  * given an arbitrary frequency input clock.
4877  */
4878 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4879                                          unsigned *freq_divider,
4880                                          unsigned *freq_multiplier,
4881                                          unsigned *actual_period_ns)
4882 {
4883         unsigned div;
4884         unsigned best_div = 1;
4885         unsigned mult;
4886         unsigned best_mult = 1;
4887         static const unsigned pico_per_nano = 1000;
4888
4889         const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4890         /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4891          * 20 MHz for most timing clocks */
4892         static const unsigned target_picosec = 12500;
4893         static const unsigned fudge_factor_80_to_20Mhz = 4;
4894         int best_period_picosec = 0;
4895
4896         for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4897                 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4898                         unsigned new_period_ps =
4899                             (reference_picosec * div) / mult;
4900                         if (abs(new_period_ps - target_picosec) <
4901                             abs(best_period_picosec - target_picosec)) {
4902                                 best_period_picosec = new_period_ps;
4903                                 best_div = div;
4904                                 best_mult = mult;
4905                         }
4906                 }
4907         }
4908         if (best_period_picosec == 0)
4909                 return -EIO;
4910
4911         *freq_divider = best_div;
4912         *freq_multiplier = best_mult;
4913         *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec *
4914                                               fudge_factor_80_to_20Mhz,
4915                                               pico_per_nano);
4916         return 0;
4917 }
4918
4919 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4920                                            unsigned source, unsigned period_ns)
4921 {
4922         struct ni_private *devpriv = dev->private;
4923         static const unsigned min_period_ns = 50;
4924         static const unsigned max_period_ns = 1000;
4925         static const unsigned timeout = 1000;
4926         unsigned pll_control_bits;
4927         unsigned freq_divider;
4928         unsigned freq_multiplier;
4929         unsigned rtsi;
4930         unsigned i;
4931         int retval;
4932
4933         if (source == NI_MIO_PLL_PXI10_CLOCK)
4934                 period_ns = 100;
4935         /*  these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
4936         if (period_ns < min_period_ns || period_ns > max_period_ns) {
4937                 dev_err(dev->class_dev,
4938                         "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4939                         __func__, min_period_ns, max_period_ns);
4940                 return -EINVAL;
4941         }
4942         devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4943         ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4944                       NISTC_RTSI_TRIG_DIR_REG);
4945         pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4946         devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4947                                     NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4948         devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4949         switch (source) {
4950         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4951                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4952                 break;
4953         case NI_MIO_PLL_PXI10_CLOCK:
4954                 /* pxi clock is 10MHz */
4955                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4956                 break;
4957         default:
4958                 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4959                         if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4960                                 devpriv->clock_and_fout2 |=
4961                                         NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4962                                 break;
4963                         }
4964                 }
4965                 if (rtsi > NI_M_MAX_RTSI_CHAN)
4966                         return -EINVAL;
4967                 break;
4968         }
4969         retval = ni_mseries_get_pll_parameters(period_ns,
4970                                                &freq_divider,
4971                                                &freq_multiplier,
4972                                                &devpriv->clock_ns);
4973         if (retval < 0) {
4974                 dev_err(dev->class_dev,
4975                         "bug, failed to find pll parameters\n");
4976                 return retval;
4977         }
4978
4979         ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4980         pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4981                             NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4982
4983         ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4984         devpriv->clock_source = source;
4985         /* it seems to typically take a few hundred microseconds for PLL to lock */
4986         for (i = 0; i < timeout; ++i) {
4987                 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4988                         break;
4989                 udelay(1);
4990         }
4991         if (i == timeout) {
4992                 dev_err(dev->class_dev,
4993                         "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4994                         __func__, source, period_ns);
4995                 return -ETIMEDOUT;
4996         }
4997         return 3;
4998 }
4999
5000 static int ni_set_master_clock(struct comedi_device *dev,
5001                                unsigned source, unsigned period_ns)
5002 {
5003         struct ni_private *devpriv = dev->private;
5004
5005         if (source == NI_MIO_INTERNAL_CLOCK) {
5006                 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
5007                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5008                               NISTC_RTSI_TRIG_DIR_REG);
5009                 devpriv->clock_ns = TIMEBASE_1_NS;
5010                 if (devpriv->is_m_series) {
5011                         devpriv->clock_and_fout2 &=
5012                             ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
5013                               NI_M_CLK_FOUT2_TIMEBASE3_PLL);
5014                         ni_writew(dev, devpriv->clock_and_fout2,
5015                                   NI_M_CLK_FOUT2_REG);
5016                         ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
5017                 }
5018                 devpriv->clock_source = source;
5019         } else {
5020                 if (devpriv->is_m_series) {
5021                         return ni_mseries_set_pll_master_clock(dev, source,
5022                                                                period_ns);
5023                 } else {
5024                         if (source == NI_MIO_RTSI_CLOCK) {
5025                                 devpriv->rtsi_trig_direction_reg |=
5026                                     NISTC_RTSI_TRIG_USE_CLK;
5027                                 ni_stc_writew(dev,
5028                                               devpriv->rtsi_trig_direction_reg,
5029                                               NISTC_RTSI_TRIG_DIR_REG);
5030                                 if (period_ns == 0) {
5031                                         dev_err(dev->class_dev,
5032                                                 "we don't handle an unspecified clock period correctly yet, returning error\n");
5033                                         return -EINVAL;
5034                                 }
5035                                 devpriv->clock_ns = period_ns;
5036                                 devpriv->clock_source = source;
5037                         } else {
5038                                 return -EINVAL;
5039                         }
5040                 }
5041         }
5042         return 3;
5043 }
5044
5045 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
5046                                        unsigned chan, unsigned source)
5047 {
5048         struct ni_private *devpriv = dev->private;
5049
5050         if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5051                 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5052                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5053                                 return 1;
5054
5055                         dev_err(dev->class_dev,
5056                                 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
5057                                 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
5058                         return 0;
5059                 }
5060                 return 0;
5061         }
5062         switch (source) {
5063         case NI_RTSI_OUTPUT_ADR_START1:
5064         case NI_RTSI_OUTPUT_ADR_START2:
5065         case NI_RTSI_OUTPUT_SCLKG:
5066         case NI_RTSI_OUTPUT_DACUPDN:
5067         case NI_RTSI_OUTPUT_DA_START1:
5068         case NI_RTSI_OUTPUT_G_SRC0:
5069         case NI_RTSI_OUTPUT_G_GATE0:
5070         case NI_RTSI_OUTPUT_RGOUT0:
5071         case NI_RTSI_OUTPUT_RTSI_BRD_0:
5072                 return 1;
5073         case NI_RTSI_OUTPUT_RTSI_OSC:
5074                 return (devpriv->is_m_series) ? 1 : 0;
5075         default:
5076                 return 0;
5077         }
5078 }
5079
5080 static int ni_set_rtsi_routing(struct comedi_device *dev,
5081                                unsigned chan, unsigned src)
5082 {
5083         struct ni_private *devpriv = dev->private;
5084
5085         if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
5086                 return -EINVAL;
5087         if (chan < 4) {
5088                 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5089                 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
5090                 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5091                               NISTC_RTSI_TRIGA_OUT_REG);
5092         } else if (chan < 8) {
5093                 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5094                 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
5095                 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5096                               NISTC_RTSI_TRIGB_OUT_REG);
5097         }
5098         return 2;
5099 }
5100
5101 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5102 {
5103         struct ni_private *devpriv = dev->private;
5104
5105         if (chan < 4) {
5106                 return NISTC_RTSI_TRIG_TO_SRC(chan,
5107                                               devpriv->rtsi_trig_a_output_reg);
5108         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5109                 return NISTC_RTSI_TRIG_TO_SRC(chan,
5110                                               devpriv->rtsi_trig_b_output_reg);
5111         } else {
5112                 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN)
5113                         return NI_RTSI_OUTPUT_RTSI_OSC;
5114                 dev_err(dev->class_dev, "bug! should never get here?\n");
5115                 return 0;
5116         }
5117 }
5118
5119 static int ni_rtsi_insn_config(struct comedi_device *dev,
5120                                struct comedi_subdevice *s,
5121                                struct comedi_insn *insn,
5122                                unsigned int *data)
5123 {
5124         struct ni_private *devpriv = dev->private;
5125         unsigned int chan = CR_CHAN(insn->chanspec);
5126         unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5127
5128         switch (data[0]) {
5129         case INSN_CONFIG_DIO_OUTPUT:
5130                 if (chan < max_chan) {
5131                         devpriv->rtsi_trig_direction_reg |=
5132                             NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5133                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5134                         devpriv->rtsi_trig_direction_reg |=
5135                             NISTC_RTSI_TRIG_DRV_CLK;
5136                 }
5137                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5138                               NISTC_RTSI_TRIG_DIR_REG);
5139                 break;
5140         case INSN_CONFIG_DIO_INPUT:
5141                 if (chan < max_chan) {
5142                         devpriv->rtsi_trig_direction_reg &=
5143                             ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5144                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5145                         devpriv->rtsi_trig_direction_reg &=
5146                             ~NISTC_RTSI_TRIG_DRV_CLK;
5147                 }
5148                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5149                               NISTC_RTSI_TRIG_DIR_REG);
5150                 break;
5151         case INSN_CONFIG_DIO_QUERY:
5152                 if (chan < max_chan) {
5153                         data[1] =
5154                             (devpriv->rtsi_trig_direction_reg &
5155                              NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
5156                                 ? INSN_CONFIG_DIO_OUTPUT
5157                                 : INSN_CONFIG_DIO_INPUT;
5158                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5159                         data[1] = (devpriv->rtsi_trig_direction_reg &
5160                                    NISTC_RTSI_TRIG_DRV_CLK)
5161                                   ? INSN_CONFIG_DIO_OUTPUT
5162                                   : INSN_CONFIG_DIO_INPUT;
5163                 }
5164                 return 2;
5165         case INSN_CONFIG_SET_CLOCK_SRC:
5166                 return ni_set_master_clock(dev, data[1], data[2]);
5167         case INSN_CONFIG_GET_CLOCK_SRC:
5168                 data[1] = devpriv->clock_source;
5169                 data[2] = devpriv->clock_ns;
5170                 return 3;
5171         case INSN_CONFIG_SET_ROUTING:
5172                 return ni_set_rtsi_routing(dev, chan, data[1]);
5173         case INSN_CONFIG_GET_ROUTING:
5174                 data[1] = ni_get_rtsi_routing(dev, chan);
5175                 return 2;
5176         default:
5177                 return -EINVAL;
5178         }
5179         return 1;
5180 }
5181
5182 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5183                              struct comedi_subdevice *s,
5184                              struct comedi_insn *insn,
5185                              unsigned int *data)
5186 {
5187         data[1] = 0;
5188
5189         return insn->n;
5190 }
5191
5192 static void ni_rtsi_init(struct comedi_device *dev)
5193 {
5194         struct ni_private *devpriv = dev->private;
5195
5196         /*  Initialises the RTSI bus signal switch to a default state */
5197
5198         /*
5199          * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
5200          * to have no effect, at least on pxi-6281, which always uses
5201          * 20MHz rtsi clock frequency
5202          */
5203         devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
5204         /*  Set clock mode to internal */
5205         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5206                 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
5207         /*  default internal lines routing to RTSI bus lines */
5208         devpriv->rtsi_trig_a_output_reg =
5209             NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) |
5210             NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) |
5211             NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) |
5212             NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN);
5213         ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5214                       NISTC_RTSI_TRIGA_OUT_REG);
5215         devpriv->rtsi_trig_b_output_reg =
5216             NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) |
5217             NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) |
5218             NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0);
5219         if (devpriv->is_m_series)
5220                 devpriv->rtsi_trig_b_output_reg |=
5221                     NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC);
5222         ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5223                       NISTC_RTSI_TRIGB_OUT_REG);
5224
5225         /*
5226          * Sets the source and direction of the 4 on board lines
5227          * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG);
5228          */
5229 }
5230
5231 #ifdef PCIDMA
5232 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5233 {
5234         struct ni_gpct *counter = s->private;
5235         int retval;
5236
5237         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5238                                               COMEDI_INPUT);
5239         if (retval) {
5240                 dev_err(dev->class_dev,
5241                         "no dma channel available for use by counter\n");
5242                 return retval;
5243         }
5244         ni_tio_acknowledge(counter);
5245         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5246
5247         return ni_tio_cmd(dev, s);
5248 }
5249
5250 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5251 {
5252         struct ni_gpct *counter = s->private;
5253         int retval;
5254
5255         retval = ni_tio_cancel(counter);
5256         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5257         ni_release_gpct_mite_channel(dev, counter->counter_index);
5258         return retval;
5259 }
5260 #endif
5261
5262 static irqreturn_t ni_E_interrupt(int irq, void *d)
5263 {
5264         struct comedi_device *dev = d;
5265         unsigned short a_status;
5266         unsigned short b_status;
5267         unsigned int ai_mite_status = 0;
5268         unsigned int ao_mite_status = 0;
5269         unsigned long flags;
5270 #ifdef PCIDMA
5271         struct ni_private *devpriv = dev->private;
5272 #endif
5273
5274         if (!dev->attached)
5275                 return IRQ_NONE;
5276         smp_mb();               /*  make sure dev->attached is checked before handler does anything else. */
5277
5278         /*  lock to avoid race with comedi_poll */
5279         spin_lock_irqsave(&dev->spinlock, flags);
5280         a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5281         b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5282 #ifdef PCIDMA
5283         if (devpriv->mite) {
5284                 unsigned long flags_too;
5285
5286                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5287                 if (devpriv->ai_mite_chan) {
5288                         ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
5289                         if (ai_mite_status & CHSR_LINKC)
5290                                 writel(CHOR_CLRLC,
5291                                        devpriv->mite->mite_io_addr +
5292                                        MITE_CHOR(devpriv->
5293                                                  ai_mite_chan->channel));
5294                 }
5295                 if (devpriv->ao_mite_chan) {
5296                         ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
5297                         if (ao_mite_status & CHSR_LINKC)
5298                                 writel(CHOR_CLRLC,
5299                                        devpriv->mite->mite_io_addr +
5300                                        MITE_CHOR(devpriv->
5301                                                  ao_mite_chan->channel));
5302                 }
5303                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5304         }
5305 #endif
5306         ack_a_interrupt(dev, a_status);
5307         ack_b_interrupt(dev, b_status);
5308         if ((a_status & NISTC_AI_STATUS1_INTA) || (ai_mite_status & CHSR_INT))
5309                 handle_a_interrupt(dev, a_status, ai_mite_status);
5310         if ((b_status & NISTC_AO_STATUS1_INTB) || (ao_mite_status & CHSR_INT))
5311                 handle_b_interrupt(dev, b_status, ao_mite_status);
5312         handle_gpct_interrupt(dev, 0);
5313         handle_gpct_interrupt(dev, 1);
5314         handle_cdio_interrupt(dev);
5315
5316         spin_unlock_irqrestore(&dev->spinlock, flags);
5317         return IRQ_HANDLED;
5318 }
5319
5320 static int ni_alloc_private(struct comedi_device *dev)
5321 {
5322         struct ni_private *devpriv;
5323
5324         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5325         if (!devpriv)
5326                 return -ENOMEM;
5327
5328         spin_lock_init(&devpriv->window_lock);
5329         spin_lock_init(&devpriv->soft_reg_copy_lock);
5330         spin_lock_init(&devpriv->mite_channel_lock);
5331
5332         return 0;
5333 }
5334
5335 static int ni_E_init(struct comedi_device *dev,
5336                      unsigned interrupt_pin, unsigned irq_polarity)
5337 {
5338         const struct ni_board_struct *board = dev->board_ptr;
5339         struct ni_private *devpriv = dev->private;
5340         struct comedi_subdevice *s;
5341         int ret;
5342         int i;
5343
5344         if (board->n_aochan > MAX_N_AO_CHAN) {
5345                 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5346                 return -EINVAL;
5347         }
5348
5349         /* initialize clock dividers */
5350         devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5351                                   NISTC_CLK_FOUT_SLOW_TIMEBASE |
5352                                   NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5353                                   NISTC_CLK_FOUT_TO_BOARD;
5354         if (!devpriv->is_6xxx) {
5355                 /* BEAM is this needed for PCI-6143 ?? */
5356                 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5357                                             NISTC_CLK_FOUT_AO_OUT_DIV2);
5358         }
5359         ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5360
5361         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5362         if (ret)
5363                 return ret;
5364
5365         /* Analog Input subdevice */
5366         s = &dev->subdevices[NI_AI_SUBDEV];
5367         if (board->n_adchan) {
5368                 s->type         = COMEDI_SUBD_AI;
5369                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5370                 if (!devpriv->is_611x)
5371                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5372                 if (board->ai_maxdata > 0xffff)
5373                         s->subdev_flags |= SDF_LSAMPL;
5374                 if (devpriv->is_m_series)
5375                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5376                 s->n_chan       = board->n_adchan;
5377                 s->maxdata      = board->ai_maxdata;
5378                 s->range_table  = ni_range_lkup[board->gainlkup];
5379                 s->insn_read    = ni_ai_insn_read;
5380                 s->insn_config  = ni_ai_insn_config;
5381                 if (dev->irq) {
5382                         dev->read_subdev = s;
5383                         s->subdev_flags |= SDF_CMD_READ;
5384                         s->len_chanlist = 512;
5385                         s->do_cmdtest   = ni_ai_cmdtest;
5386                         s->do_cmd       = ni_ai_cmd;
5387                         s->cancel       = ni_ai_reset;
5388                         s->poll         = ni_ai_poll;
5389                         s->munge        = ni_ai_munge;
5390
5391                         if (devpriv->mite)
5392                                 s->async_dma_dir = DMA_FROM_DEVICE;
5393                 }
5394
5395                 /* reset the analog input configuration */
5396                 ni_ai_reset(dev, s);
5397         } else {
5398                 s->type         = COMEDI_SUBD_UNUSED;
5399         }
5400
5401         /* Analog Output subdevice */
5402         s = &dev->subdevices[NI_AO_SUBDEV];
5403         if (board->n_aochan) {
5404                 s->type         = COMEDI_SUBD_AO;
5405                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5406                 if (devpriv->is_m_series)
5407                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
5408                 s->n_chan       = board->n_aochan;
5409                 s->maxdata      = board->ao_maxdata;
5410                 s->range_table  = board->ao_range_table;
5411                 s->insn_config  = ni_ao_insn_config;
5412                 s->insn_write   = ni_ao_insn_write;
5413
5414                 ret = comedi_alloc_subdev_readback(s);
5415                 if (ret)
5416                         return ret;
5417
5418                 /*
5419                  * Along with the IRQ we need either a FIFO or DMA for
5420                  * async command support.
5421                  */
5422                 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5423                         dev->write_subdev = s;
5424                         s->subdev_flags |= SDF_CMD_WRITE;
5425                         s->len_chanlist = s->n_chan;
5426                         s->do_cmdtest   = ni_ao_cmdtest;
5427                         s->do_cmd       = ni_ao_cmd;
5428                         s->cancel       = ni_ao_reset;
5429                         if (!devpriv->is_m_series)
5430                                 s->munge        = ni_ao_munge;
5431
5432                         if (devpriv->mite)
5433                                 s->async_dma_dir = DMA_TO_DEVICE;
5434                 }
5435
5436                 if (devpriv->is_67xx)
5437                         init_ao_67xx(dev, s);
5438
5439                 /* reset the analog output configuration */
5440                 ni_ao_reset(dev, s);
5441         } else {
5442                 s->type         = COMEDI_SUBD_UNUSED;
5443         }
5444
5445         /* Digital I/O subdevice */
5446         s = &dev->subdevices[NI_DIO_SUBDEV];
5447         s->type         = COMEDI_SUBD_DIO;
5448         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5449         s->n_chan       = board->has_32dio_chan ? 32 : 8;
5450         s->maxdata      = 1;
5451         s->range_table  = &range_digital;
5452         if (devpriv->is_m_series) {
5453                 s->subdev_flags |= SDF_LSAMPL;
5454                 s->insn_bits    = ni_m_series_dio_insn_bits;
5455                 s->insn_config  = ni_m_series_dio_insn_config;
5456                 if (dev->irq) {
5457                         s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5458                         s->len_chanlist = s->n_chan;
5459                         s->do_cmdtest   = ni_cdio_cmdtest;
5460                         s->do_cmd       = ni_cdio_cmd;
5461                         s->cancel       = ni_cdio_cancel;
5462
5463                         /* M-series boards use DMA */
5464                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5465                 }
5466
5467                 /* reset DIO and set all channels to inputs */
5468                 ni_writel(dev, NI_M_CDO_CMD_RESET |
5469                                NI_M_CDI_CMD_RESET,
5470                           NI_M_CDIO_CMD_REG);
5471                 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5472         } else {
5473                 s->insn_bits    = ni_dio_insn_bits;
5474                 s->insn_config  = ni_dio_insn_config;
5475
5476                 /* set all channels to inputs */
5477                 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5478                 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5479         }
5480
5481         /* 8255 device */
5482         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5483         if (board->has_8255) {
5484                 ret = subdev_8255_init(dev, s, ni_8255_callback,
5485                                        NI_E_8255_BASE);
5486                 if (ret)
5487                         return ret;
5488         } else {
5489                 s->type = COMEDI_SUBD_UNUSED;
5490         }
5491
5492         /* formerly general purpose counter/timer device, but no longer used */
5493         s = &dev->subdevices[NI_UNUSED_SUBDEV];
5494         s->type = COMEDI_SUBD_UNUSED;
5495
5496         /* Calibration subdevice */
5497         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5498         s->type         = COMEDI_SUBD_CALIB;
5499         s->subdev_flags = SDF_INTERNAL;
5500         s->n_chan       = 1;
5501         s->maxdata      = 0;
5502         if (devpriv->is_m_series) {
5503                 /* internal PWM output used for AI nonlinearity calibration */
5504                 s->insn_config  = ni_m_series_pwm_config;
5505
5506                 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5507         } else if (devpriv->is_6143) {
5508                 /* internal PWM output used for AI nonlinearity calibration */
5509                 s->insn_config  = ni_6143_pwm_config;
5510         } else {
5511                 s->subdev_flags |= SDF_WRITABLE;
5512                 s->insn_read    = ni_calib_insn_read;
5513                 s->insn_write   = ni_calib_insn_write;
5514
5515                 /* setup the caldacs and find the real n_chan and maxdata */
5516                 caldac_setup(dev, s);
5517         }
5518
5519         /* EEPROM subdevice */
5520         s = &dev->subdevices[NI_EEPROM_SUBDEV];
5521         s->type         = COMEDI_SUBD_MEMORY;
5522         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5523         s->maxdata      = 0xff;
5524         if (devpriv->is_m_series) {
5525                 s->n_chan       = M_SERIES_EEPROM_SIZE;
5526                 s->insn_read    = ni_m_series_eeprom_insn_read;
5527         } else {
5528                 s->n_chan       = 512;
5529                 s->insn_read    = ni_eeprom_insn_read;
5530         }
5531
5532         /* Digital I/O (PFI) subdevice */
5533         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5534         s->type         = COMEDI_SUBD_DIO;
5535         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5536         s->maxdata      = 1;
5537         if (devpriv->is_m_series) {
5538                 s->n_chan       = 16;
5539                 s->insn_bits    = ni_pfi_insn_bits;
5540
5541                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5542                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5543                         ni_writew(dev, devpriv->pfi_output_select_reg[i],
5544                                   NI_M_PFI_OUT_SEL_REG(i));
5545                 }
5546         } else {
5547                 s->n_chan       = 10;
5548         }
5549         s->insn_config  = ni_pfi_insn_config;
5550
5551         ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
5552
5553         /* cs5529 calibration adc */
5554         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5555         if (devpriv->is_67xx) {
5556                 s->type = COMEDI_SUBD_AI;
5557                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5558                 /*  one channel for each analog output channel */
5559                 s->n_chan = board->n_aochan;
5560                 s->maxdata = (1 << 16) - 1;
5561                 s->range_table = &range_unknown;        /* XXX */
5562                 s->insn_read = cs5529_ai_insn_read;
5563                 s->insn_config = NULL;
5564                 init_cs5529(dev);
5565         } else {
5566                 s->type = COMEDI_SUBD_UNUSED;
5567         }
5568
5569         /* Serial */
5570         s = &dev->subdevices[NI_SERIAL_SUBDEV];
5571         s->type = COMEDI_SUBD_SERIAL;
5572         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5573         s->n_chan = 1;
5574         s->maxdata = 0xff;
5575         s->insn_config = ni_serial_insn_config;
5576         devpriv->serial_interval_ns = 0;
5577         devpriv->serial_hw_mode = 0;
5578
5579         /* RTSI */
5580         s = &dev->subdevices[NI_RTSI_SUBDEV];
5581         s->type = COMEDI_SUBD_DIO;
5582         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5583         s->n_chan = 8;
5584         s->maxdata = 1;
5585         s->insn_bits = ni_rtsi_insn_bits;
5586         s->insn_config = ni_rtsi_insn_config;
5587         ni_rtsi_init(dev);
5588
5589         /* allocate and initialize the gpct counter device */
5590         devpriv->counter_dev = ni_gpct_device_construct(dev,
5591                                         ni_gpct_write_register,
5592                                         ni_gpct_read_register,
5593                                         (devpriv->is_m_series)
5594                                                 ? ni_gpct_variant_m_series
5595                                                 : ni_gpct_variant_e_series,
5596                                         NUM_GPCT);
5597         if (!devpriv->counter_dev)
5598                 return -ENOMEM;
5599
5600         /* Counter (gpct) subdevices */
5601         for (i = 0; i < NUM_GPCT; ++i) {
5602                 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5603
5604                 /* setup and initialize the counter */
5605                 gpct->chip_index = 0;
5606                 gpct->counter_index = i;
5607                 ni_tio_init_counter(gpct);
5608
5609                 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5610                 s->type         = COMEDI_SUBD_COUNTER;
5611                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5612                 s->n_chan       = 3;
5613                 s->maxdata      = (devpriv->is_m_series) ? 0xffffffff
5614                                                          : 0x00ffffff;
5615                 s->insn_read    = ni_tio_insn_read;
5616                 s->insn_write   = ni_tio_insn_read;
5617                 s->insn_config  = ni_tio_insn_config;
5618 #ifdef PCIDMA
5619                 if (dev->irq && devpriv->mite) {
5620                         s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5621                         s->len_chanlist = 1;
5622                         s->do_cmdtest   = ni_tio_cmdtest;
5623                         s->do_cmd       = ni_gpct_cmd;
5624                         s->cancel       = ni_gpct_cancel;
5625
5626                         s->async_dma_dir = DMA_BIDIRECTIONAL;
5627                 }
5628 #endif
5629                 s->private      = gpct;
5630         }
5631
5632         /* Frequency output subdevice */
5633         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5634         s->type         = COMEDI_SUBD_COUNTER;
5635         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5636         s->n_chan       = 1;
5637         s->maxdata      = 0xf;
5638         s->insn_read    = ni_freq_out_insn_read;
5639         s->insn_write   = ni_freq_out_insn_write;
5640         s->insn_config  = ni_freq_out_insn_config;
5641
5642         if (dev->irq) {
5643                 ni_stc_writew(dev,
5644                               (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5645                               (NISTC_INT_CTRL_3PIN_INT & 0) |
5646                               NISTC_INT_CTRL_INTA_ENA |
5647                               NISTC_INT_CTRL_INTB_ENA |
5648                               NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5649                               NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5650                               NISTC_INT_CTRL_REG);
5651         }
5652
5653         /* DMA setup */
5654         ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
5655         ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
5656
5657         if (devpriv->is_6xxx) {
5658                 ni_writeb(dev, 0, NI611X_MAGIC_REG);
5659         } else if (devpriv->is_m_series) {
5660                 int channel;
5661
5662                 for (channel = 0; channel < board->n_aochan; ++channel) {
5663                         ni_writeb(dev, 0xf,
5664                                   NI_M_AO_WAVEFORM_ORDER_REG(channel));
5665                         ni_writeb(dev, 0x0,
5666                                   NI_M_AO_REF_ATTENUATION_REG(channel));
5667                 }
5668                 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5669         }
5670
5671         return 0;
5672 }
5673
5674 static void mio_common_detach(struct comedi_device *dev)
5675 {
5676         struct ni_private *devpriv = dev->private;
5677
5678         if (devpriv) {
5679                 if (devpriv->counter_dev)
5680                         ni_gpct_device_destroy(devpriv->counter_dev);
5681         }
5682 }