2 comedi/drivers/ni_pcidio.c
3 driver for National Instruments PCI-DIO-32HS
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
20 Description: National Instruments PCI-DIO32HS, PCI-6533
23 Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
24 [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
25 [National Instruments] PCI-6534 (pci-6534)
26 Updated: Mon, 09 Jan 2012 14:27:23 +0000
28 The DIO32HS board appears as one subdevice, with 32 channels.
29 Each channel is individually I/O configurable. The channel order
30 is 0=A0, 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only
31 supports simple digital I/O; no handshaking is supported.
33 DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
35 The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
36 scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
37 scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
40 This driver could be easily modified to support AT-MIO32HS and
43 The PCI-6534 requires a firmware upload after power-up to work, the
44 firmware data and instructions for loading it with comedi_config
45 it are contained in the
46 comedi_nonfree_firmware tarball available from http://www.comedi.org
51 #include <linux/module.h>
52 #include <linux/delay.h>
53 #include <linux/interrupt.h>
54 #include <linux/sched.h>
56 #include "../comedidev.h"
58 #include "comedi_fc.h"
61 /* defines for the PCI-DIO-32HS */
63 #define Window_Address 4 /* W */
64 #define Interrupt_And_Window_Status 4 /* R */
65 #define IntStatus1 (1<<0)
66 #define IntStatus2 (1<<1)
67 #define WindowAddressStatus_mask 0x7c
69 #define Master_DMA_And_Interrupt_Control 5 /* W */
70 #define InterruptLine(x) ((x)&3)
71 #define OpenInt (1<<2)
72 #define Group_Status 5 /* R */
73 #define DataLeft (1<<0)
75 #define StopTrig (1<<3)
77 #define Group_1_Flags 6 /* R */
78 #define Group_2_Flags 7 /* R */
79 #define TransferReady (1<<0)
80 #define CountExpired (1<<1)
82 #define PrimaryTC (1<<6)
83 #define SecondaryTC (1<<7)
84 /* #define SerialRose */
88 #define Group_1_First_Clear 6 /* W */
89 #define Group_2_First_Clear 7 /* W */
90 #define ClearWaited (1<<3)
91 #define ClearPrimaryTC (1<<4)
92 #define ClearSecondaryTC (1<<5)
93 #define DMAReset (1<<6)
94 #define FIFOReset (1<<7)
97 #define Group_1_FIFO 8 /* W */
98 #define Group_2_FIFO 12 /* W */
100 #define Transfer_Count 20
104 #define Chip_Version 27
105 #define Port_IO(x) (28+(x))
106 #define Port_Pin_Directions(x) (32+(x))
107 #define Port_Pin_Mask(x) (36+(x))
108 #define Port_Pin_Polarities(x) (40+(x))
110 #define Master_Clock_Routing 45
111 #define RTSIClocking(x) (((x)&3)<<4)
113 #define Group_1_Second_Clear 46 /* W */
114 #define Group_2_Second_Clear 47 /* W */
115 #define ClearExpired (1<<0)
117 #define Port_Pattern(x) (48+(x))
120 #define FIFOEnableA (1<<0)
121 #define FIFOEnableB (1<<1)
122 #define FIFOEnableC (1<<2)
123 #define FIFOEnableD (1<<3)
124 #define Funneling(x) (((x)&3)<<4)
125 #define GroupDirection (1<<7)
127 #define Protocol_Register_1 65
128 #define OpMode Protocol_Register_1
129 #define RunMode(x) ((x)&7)
130 #define Numbered (1<<3)
132 #define Protocol_Register_2 66
133 #define ClockReg Protocol_Register_2
134 #define ClockLine(x) (((x)&3)<<5)
135 #define InvertStopTrig (1<<7)
136 #define DataLatching(x) (((x)&3)<<5)
138 #define Protocol_Register_3 67
139 #define Sequence Protocol_Register_3
141 #define Protocol_Register_14 68 /* 16 bit */
142 #define ClockSpeed Protocol_Register_14
144 #define Protocol_Register_4 70
145 #define ReqReg Protocol_Register_4
146 #define ReqConditioning(x) (((x)&7)<<3)
148 #define Protocol_Register_5 71
149 #define BlockMode Protocol_Register_5
151 #define FIFO_Control 72
152 #define ReadyLevel(x) ((x)&7)
154 #define Protocol_Register_6 73
155 #define LinePolarities Protocol_Register_6
156 #define InvertAck (1<<0)
157 #define InvertReq (1<<1)
158 #define InvertClock (1<<2)
159 #define InvertSerial (1<<3)
160 #define OpenAck (1<<4)
161 #define OpenClock (1<<5)
163 #define Protocol_Register_7 74
164 #define AckSer Protocol_Register_7
165 #define AckLine(x) (((x)&3)<<2)
166 #define ExchangePins (1<<7)
168 #define Interrupt_Control 75
169 /* bits same as flags */
171 #define DMA_Line_Control_Group1 76
172 #define DMA_Line_Control_Group2 108
173 /* channel zero is none */
174 static inline unsigned primary_DMAChannel_bits(unsigned channel)
176 return channel & 0x3;
179 static inline unsigned secondary_DMAChannel_bits(unsigned channel)
181 return (channel << 2) & 0xc;
184 #define Transfer_Size_Control 77
185 #define TransferWidth(x) ((x)&3)
186 #define TransferLength(x) (((x)&3)<<3)
187 #define RequireRLevel (1<<5)
189 #define Protocol_Register_15 79
190 #define DAQOptions Protocol_Register_15
191 #define StartSource(x) ((x)&0x3)
192 #define InvertStart (1<<2)
193 #define StopSource(x) (((x)&0x3)<<3)
194 #define ReqStart (1<<6)
195 #define PreStart (1<<7)
197 #define Pattern_Detection 81
198 #define DetectionMethod (1<<0)
199 #define InvertMatch (1<<1)
200 #define IE_Pattern_Detection (1<<2)
202 #define Protocol_Register_9 82
203 #define ReqDelay Protocol_Register_9
205 #define Protocol_Register_10 83
206 #define ReqNotDelay Protocol_Register_10
208 #define Protocol_Register_11 84
209 #define AckDelay Protocol_Register_11
211 #define Protocol_Register_12 85
212 #define AckNotDelay Protocol_Register_12
214 #define Protocol_Register_13 86
215 #define Data1Delay Protocol_Register_13
217 #define Protocol_Register_8 88 /* 32 bit */
218 #define StartDelay Protocol_Register_8
220 /* Firmware files for PCI-6524 */
221 #define FW_PCI_6534_MAIN "ni6534a.bin"
222 #define FW_PCI_6534_SCARAB_DI "niscrb01.bin"
223 #define FW_PCI_6534_SCARAB_DO "niscrb02.bin"
224 MODULE_FIRMWARE(FW_PCI_6534_MAIN);
225 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DI);
226 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DO);
228 enum pci_6534_firmware_registers { /* 16 bit */
229 Firmware_Control_Register = 0x100,
230 Firmware_Status_Register = 0x104,
231 Firmware_Data_Register = 0x108,
232 Firmware_Mask_Register = 0x10c,
233 Firmware_Debug_Register = 0x110,
235 /* main fpga registers (32 bit)*/
236 enum pci_6534_fpga_registers {
237 FPGA_Control1_Register = 0x200,
238 FPGA_Control2_Register = 0x204,
239 FPGA_Irq_Mask_Register = 0x208,
240 FPGA_Status_Register = 0x20c,
241 FPGA_Signature_Register = 0x210,
242 FPGA_SCALS_Counter_Register = 0x280, /*write-clear */
243 FPGA_SCAMS_Counter_Register = 0x284, /*write-clear */
244 FPGA_SCBLS_Counter_Register = 0x288, /*write-clear */
245 FPGA_SCBMS_Counter_Register = 0x28c, /*write-clear */
246 FPGA_Temp_Control_Register = 0x2a0,
247 FPGA_DAR_Register = 0x2a8,
248 FPGA_ELC_Read_Register = 0x2b8,
249 FPGA_ELC_Write_Register = 0x2bc,
251 enum FPGA_Control_Bits {
252 FPGA_Enable_Bit = 0x8000,
255 #define TIMER_BASE 50 /* nanoseconds */
258 #define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC)
260 #define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC)
271 unsigned int uses_firmware:1;
274 static const struct nidio_board nidio_boards[] = {
275 [BOARD_PCIDIO_32HS] = {
276 .name = "pci-dio-32hs",
287 struct nidio96_private {
288 struct mite_struct *mite;
291 unsigned short OpModeBits;
292 struct mite_channel *di_mite_chan;
293 struct mite_dma_descriptor_ring *di_mite_ring;
294 spinlock_t mite_channel_lock;
297 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
299 struct nidio96_private *devpriv = dev->private;
302 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
303 BUG_ON(devpriv->di_mite_chan);
304 devpriv->di_mite_chan =
305 mite_request_channel_in_range(devpriv->mite,
306 devpriv->di_mite_ring, 1, 2);
307 if (devpriv->di_mite_chan == NULL) {
308 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
309 dev_err(dev->class_dev, "failed to reserve mite dma channel\n");
312 devpriv->di_mite_chan->dir = COMEDI_INPUT;
313 writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
314 secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
315 dev->mmio + DMA_Line_Control_Group1);
317 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
321 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
323 struct nidio96_private *devpriv = dev->private;
326 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
327 if (devpriv->di_mite_chan) {
328 mite_dma_disarm(devpriv->di_mite_chan);
329 mite_dma_reset(devpriv->di_mite_chan);
330 mite_release_channel(devpriv->di_mite_chan);
331 devpriv->di_mite_chan = NULL;
332 writeb(primary_DMAChannel_bits(0) |
333 secondary_DMAChannel_bits(0),
334 dev->mmio + DMA_Line_Control_Group1);
337 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
340 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
342 struct nidio96_private *devpriv = dev->private;
346 retval = ni_pcidio_request_di_mite_channel(dev);
350 /* write alloc the entire buffer */
351 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
353 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
354 if (devpriv->di_mite_chan) {
355 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
356 mite_dma_arm(devpriv->di_mite_chan);
359 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
364 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
366 struct nidio96_private *devpriv = dev->private;
367 unsigned long irq_flags;
370 spin_lock_irqsave(&dev->spinlock, irq_flags);
371 spin_lock(&devpriv->mite_channel_lock);
372 if (devpriv->di_mite_chan)
373 mite_sync_input_dma(devpriv->di_mite_chan, s);
374 spin_unlock(&devpriv->mite_channel_lock);
375 count = comedi_buf_n_bytes_ready(s);
376 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
380 static irqreturn_t nidio_interrupt(int irq, void *d)
382 struct comedi_device *dev = d;
383 struct nidio96_private *devpriv = dev->private;
384 struct comedi_subdevice *s = dev->read_subdev;
385 struct comedi_async *async = s->async;
386 struct mite_struct *mite = devpriv->mite;
389 unsigned int auxdata = 0;
390 unsigned short data1 = 0;
391 unsigned short data2 = 0;
395 unsigned int m_status = 0;
397 /* interrupcions parasites */
398 if (!dev->attached) {
399 /* assume it's from another card */
403 /* Lock to avoid race with comedi_poll */
404 spin_lock(&dev->spinlock);
406 status = readb(dev->mmio + Interrupt_And_Window_Status);
407 flags = readb(dev->mmio + Group_1_Flags);
409 spin_lock(&devpriv->mite_channel_lock);
410 if (devpriv->di_mite_chan)
411 m_status = mite_get_status(devpriv->di_mite_chan);
413 if (m_status & CHSR_INT) {
414 if (m_status & CHSR_LINKC) {
417 MITE_CHOR(devpriv->di_mite_chan->channel));
418 mite_sync_input_dma(devpriv->di_mite_chan, s);
419 /* XXX need to byteswap */
421 if (m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_DRDY |
422 CHSR_DRQ1 | CHSR_MRDY)) {
423 dev_dbg(dev->class_dev,
424 "unknown mite interrupt, disabling IRQ\n");
425 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
426 disable_irq(dev->irq);
429 spin_unlock(&devpriv->mite_channel_lock);
431 while (status & DataLeft) {
434 dev_dbg(dev->class_dev, "too much work in interrupt\n");
436 dev->mmio + Master_DMA_And_Interrupt_Control);
442 if (flags & TransferReady) {
443 while (flags & TransferReady) {
446 dev_dbg(dev->class_dev,
447 "too much work in interrupt\n");
448 writeb(0x00, dev->mmio +
449 Master_DMA_And_Interrupt_Control
453 auxdata = readl(dev->mmio + Group_1_FIFO);
454 data1 = auxdata & 0xffff;
455 data2 = (auxdata & 0xffff0000) >> 16;
456 comedi_buf_put(s, data1);
457 comedi_buf_put(s, data2);
458 flags = readb(dev->mmio + Group_1_Flags);
460 async->events |= COMEDI_CB_BLOCK;
463 if (flags & CountExpired) {
464 writeb(ClearExpired, dev->mmio + Group_1_Second_Clear);
465 async->events |= COMEDI_CB_EOA;
467 writeb(0x00, dev->mmio + OpMode);
469 } else if (flags & Waited) {
470 writeb(ClearWaited, dev->mmio + Group_1_First_Clear);
471 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
473 } else if (flags & PrimaryTC) {
474 writeb(ClearPrimaryTC,
475 dev->mmio + Group_1_First_Clear);
476 async->events |= COMEDI_CB_EOA;
477 } else if (flags & SecondaryTC) {
478 writeb(ClearSecondaryTC,
479 dev->mmio + Group_1_First_Clear);
480 async->events |= COMEDI_CB_EOA;
483 flags = readb(dev->mmio + Group_1_Flags);
484 status = readb(dev->mmio + Interrupt_And_Window_Status);
488 cfc_handle_events(dev, s);
491 writeb(0x03, dev->mmio + Master_DMA_And_Interrupt_Control);
494 spin_unlock(&dev->spinlock);
498 static int ni_pcidio_insn_config(struct comedi_device *dev,
499 struct comedi_subdevice *s,
500 struct comedi_insn *insn,
505 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
509 writel(s->io_bits, dev->mmio + Port_Pin_Directions(0));
514 static int ni_pcidio_insn_bits(struct comedi_device *dev,
515 struct comedi_subdevice *s,
516 struct comedi_insn *insn,
519 if (comedi_dio_update_state(s, data))
520 writel(s->state, dev->mmio + Port_IO(0));
522 data[1] = readl(dev->mmio + Port_IO(0));
527 static int ni_pcidio_ns_to_timer(int *nanosec, unsigned int flags)
533 switch (flags & TRIG_ROUND_MASK) {
534 case TRIG_ROUND_NEAREST:
536 divider = (*nanosec + base / 2) / base;
538 case TRIG_ROUND_DOWN:
539 divider = (*nanosec) / base;
542 divider = (*nanosec + base - 1) / base;
546 *nanosec = base * divider;
550 static int ni_pcidio_cmdtest(struct comedi_device *dev,
551 struct comedi_subdevice *s, struct comedi_cmd *cmd)
556 /* Step 1 : check if triggers are trivially valid */
558 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
559 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
560 TRIG_TIMER | TRIG_EXT);
561 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
562 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
563 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
568 /* Step 2a : make sure trigger sources are unique */
570 err |= cfc_check_trigger_is_unique(cmd->start_src);
571 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
572 err |= cfc_check_trigger_is_unique(cmd->stop_src);
574 /* Step 2b : and mutually compatible */
579 /* Step 3: check if arguments are trivially valid */
581 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
583 #define MAX_SPEED (TIMER_BASE) /* in nanoseconds */
585 if (cmd->scan_begin_src == TRIG_TIMER) {
586 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
588 /* no minimum speed */
591 /* should be level/edge, hi/lo specification here */
592 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
593 cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
598 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
599 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
601 if (cmd->stop_src == TRIG_COUNT) {
603 } else { /* TRIG_NONE */
604 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
610 /* step 4: fix up any arguments */
612 if (cmd->scan_begin_src == TRIG_TIMER) {
613 arg = cmd->scan_begin_arg;
614 ni_pcidio_ns_to_timer(&arg, cmd->flags);
615 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
624 static int ni_pcidio_inttrig(struct comedi_device *dev,
625 struct comedi_subdevice *s,
626 unsigned int trig_num)
628 struct nidio96_private *devpriv = dev->private;
629 struct comedi_cmd *cmd = &s->async->cmd;
631 if (trig_num != cmd->start_arg)
634 writeb(devpriv->OpModeBits, dev->mmio + OpMode);
635 s->async->inttrig = NULL;
640 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
642 struct nidio96_private *devpriv = dev->private;
643 struct comedi_cmd *cmd = &s->async->cmd;
645 /* XXX configure ports for input */
646 writel(0x0000, dev->mmio + Port_Pin_Directions(0));
649 /* enable fifos A B C D */
650 writeb(0x0f, dev->mmio + Data_Path);
652 /* set transfer width a 32 bits */
653 writeb(TransferWidth(0) | TransferLength(0),
654 dev->mmio + Transfer_Size_Control);
656 writeb(0x03, dev->mmio + Data_Path);
657 writeb(TransferWidth(3) | TransferLength(0),
658 dev->mmio + Transfer_Size_Control);
661 /* protocol configuration */
662 if (cmd->scan_begin_src == TRIG_TIMER) {
663 /* page 4-5, "input with internal REQs" */
664 writeb(0, dev->mmio + OpMode);
665 writeb(0x00, dev->mmio + ClockReg);
666 writeb(1, dev->mmio + Sequence);
667 writeb(0x04, dev->mmio + ReqReg);
668 writeb(4, dev->mmio + BlockMode);
669 writeb(3, dev->mmio + LinePolarities);
670 writeb(0xc0, dev->mmio + AckSer);
671 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
673 dev->mmio + StartDelay);
674 writeb(1, dev->mmio + ReqDelay);
675 writeb(1, dev->mmio + ReqNotDelay);
676 writeb(1, dev->mmio + AckDelay);
677 writeb(0x0b, dev->mmio + AckNotDelay);
678 writeb(0x01, dev->mmio + Data1Delay);
679 /* manual, page 4-5: ClockSpeed comment is incorrectly listed
681 writew(0, dev->mmio + ClockSpeed);
682 writeb(0, dev->mmio + DAQOptions);
685 /* page 4-5, "input with external REQs" */
686 writeb(0, dev->mmio + OpMode);
687 writeb(0x00, dev->mmio + ClockReg);
688 writeb(0, dev->mmio + Sequence);
689 writeb(0x00, dev->mmio + ReqReg);
690 writeb(4, dev->mmio + BlockMode);
691 if (!(cmd->scan_begin_arg & CR_INVERT)) /* Leading Edge */
692 writeb(0, dev->mmio + LinePolarities);
693 else /* Trailing Edge */
694 writeb(2, dev->mmio + LinePolarities);
695 writeb(0x00, dev->mmio + AckSer);
696 writel(1, dev->mmio + StartDelay);
697 writeb(1, dev->mmio + ReqDelay);
698 writeb(1, dev->mmio + ReqNotDelay);
699 writeb(1, dev->mmio + AckDelay);
700 writeb(0x0C, dev->mmio + AckNotDelay);
701 writeb(0x10, dev->mmio + Data1Delay);
702 writew(0, dev->mmio + ClockSpeed);
703 writeb(0x60, dev->mmio + DAQOptions);
706 if (cmd->stop_src == TRIG_COUNT) {
707 writel(cmd->stop_arg,
708 dev->mmio + Transfer_Count);
714 writeb(ClearPrimaryTC | ClearSecondaryTC,
715 dev->mmio + Group_1_First_Clear);
718 int retval = setup_mite_dma(dev, s);
724 writeb(0x00, dev->mmio + DMA_Line_Control_Group1);
726 writeb(0x00, dev->mmio + DMA_Line_Control_Group2);
728 /* clear and enable interrupts */
729 writeb(0xff, dev->mmio + Group_1_First_Clear);
730 /* writeb(ClearExpired, dev->mmio+Group_1_Second_Clear); */
732 writeb(IntEn, dev->mmio + Interrupt_Control);
733 writeb(0x03, dev->mmio + Master_DMA_And_Interrupt_Control);
735 if (cmd->stop_src == TRIG_NONE) {
736 devpriv->OpModeBits = DataLatching(0) | RunMode(7);
737 } else { /* TRIG_TIMER */
738 devpriv->OpModeBits = Numbered | RunMode(7);
740 if (cmd->start_src == TRIG_NOW) {
742 writeb(devpriv->OpModeBits, dev->mmio + OpMode);
743 s->async->inttrig = NULL;
746 s->async->inttrig = ni_pcidio_inttrig;
752 static int ni_pcidio_cancel(struct comedi_device *dev,
753 struct comedi_subdevice *s)
755 writeb(0x00, dev->mmio + Master_DMA_And_Interrupt_Control);
756 ni_pcidio_release_di_mite_channel(dev);
761 static int ni_pcidio_change(struct comedi_device *dev,
762 struct comedi_subdevice *s)
764 struct nidio96_private *devpriv = dev->private;
767 ret = mite_buf_change(devpriv->di_mite_ring, s);
771 memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
776 static int pci_6534_load_fpga(struct comedi_device *dev,
777 const u8 *data, size_t data_len,
778 unsigned long context)
780 static const int timeout = 1000;
781 int fpga_index = context;
785 writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
786 writew(0xc0 | fpga_index, dev->mmio + Firmware_Control_Register);
788 (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0 &&
793 dev_warn(dev->class_dev,
794 "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
798 writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
800 readw(dev->mmio + Firmware_Status_Register) != 0x3 &&
805 dev_warn(dev->class_dev,
806 "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
810 for (j = 0; j + 1 < data_len;) {
811 unsigned int value = data[j++];
813 value |= data[j++] << 8;
814 writew(value, dev->mmio + Firmware_Data_Register);
816 (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0
817 && i < timeout; ++i) {
821 dev_warn(dev->class_dev,
822 "ni_pcidio: failed to load word into fpga %i\n",
829 writew(0x0, dev->mmio + Firmware_Control_Register);
833 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
835 return pci_6534_load_fpga(dev, NULL, 0, fpga_index);
838 static int pci_6534_reset_fpgas(struct comedi_device *dev)
843 writew(0x0, dev->mmio + Firmware_Control_Register);
844 for (i = 0; i < 3; ++i) {
845 ret = pci_6534_reset_fpga(dev, i);
849 writew(0x0, dev->mmio + Firmware_Mask_Register);
853 static void pci_6534_init_main_fpga(struct comedi_device *dev)
855 writel(0, dev->mmio + FPGA_Control1_Register);
856 writel(0, dev->mmio + FPGA_Control2_Register);
857 writel(0, dev->mmio + FPGA_SCALS_Counter_Register);
858 writel(0, dev->mmio + FPGA_SCAMS_Counter_Register);
859 writel(0, dev->mmio + FPGA_SCBLS_Counter_Register);
860 writel(0, dev->mmio + FPGA_SCBMS_Counter_Register);
863 static int pci_6534_upload_firmware(struct comedi_device *dev)
865 struct nidio96_private *devpriv = dev->private;
866 static const char *const fw_file[3] = {
867 FW_PCI_6534_SCARAB_DI, /* loaded into scarab A for DI */
868 FW_PCI_6534_SCARAB_DO, /* loaded into scarab B for DO */
869 FW_PCI_6534_MAIN, /* loaded into main FPGA */
874 ret = pci_6534_reset_fpgas(dev);
877 /* load main FPGA first, then the two scarabs */
878 for (n = 2; n >= 0; n--) {
879 ret = comedi_load_firmware(dev, &devpriv->mite->pcidev->dev,
881 pci_6534_load_fpga, n);
882 if (ret == 0 && n == 2)
883 pci_6534_init_main_fpga(dev);
890 static void nidio_reset_board(struct comedi_device *dev)
892 writel(0, dev->mmio + Port_IO(0));
893 writel(0, dev->mmio + Port_Pin_Directions(0));
894 writel(0, dev->mmio + Port_Pin_Mask(0));
896 /* disable interrupts on board */
897 writeb(0, dev->mmio + Master_DMA_And_Interrupt_Control);
900 static int nidio_auto_attach(struct comedi_device *dev,
901 unsigned long context)
903 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
904 const struct nidio_board *board = NULL;
905 struct nidio96_private *devpriv;
906 struct comedi_subdevice *s;
910 if (context < ARRAY_SIZE(nidio_boards))
911 board = &nidio_boards[context];
914 dev->board_ptr = board;
915 dev->board_name = board->name;
917 ret = comedi_pci_enable(dev);
921 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
925 spin_lock_init(&devpriv->mite_channel_lock);
927 devpriv->mite = mite_alloc(pcidev);
931 ret = mite_setup(dev, devpriv->mite);
935 devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
936 if (devpriv->di_mite_ring == NULL)
939 if (board->uses_firmware) {
940 ret = pci_6534_upload_firmware(dev);
945 nidio_reset_board(dev);
947 ret = comedi_alloc_subdevices(dev, 1);
951 dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
952 readb(dev->mmio + Chip_Version));
954 s = &dev->subdevices[0];
956 dev->read_subdev = s;
957 s->type = COMEDI_SUBD_DIO;
959 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
962 s->range_table = &range_digital;
964 s->insn_config = &ni_pcidio_insn_config;
965 s->insn_bits = &ni_pcidio_insn_bits;
966 s->do_cmd = &ni_pcidio_cmd;
967 s->do_cmdtest = &ni_pcidio_cmdtest;
968 s->cancel = &ni_pcidio_cancel;
969 s->len_chanlist = 32; /* XXX */
970 s->buf_change = &ni_pcidio_change;
971 s->async_dma_dir = DMA_BIDIRECTIONAL;
972 s->poll = &ni_pcidio_poll;
976 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
977 dev->board_name, dev);
985 static void nidio_detach(struct comedi_device *dev)
987 struct nidio96_private *devpriv = dev->private;
990 free_irq(dev->irq, dev);
992 if (devpriv->di_mite_ring) {
993 mite_free_ring(devpriv->di_mite_ring);
994 devpriv->di_mite_ring = NULL;
996 mite_detach(devpriv->mite);
1000 comedi_pci_disable(dev);
1003 static struct comedi_driver ni_pcidio_driver = {
1004 .driver_name = "ni_pcidio",
1005 .module = THIS_MODULE,
1006 .auto_attach = nidio_auto_attach,
1007 .detach = nidio_detach,
1010 static int ni_pcidio_pci_probe(struct pci_dev *dev,
1011 const struct pci_device_id *id)
1013 return comedi_pci_auto_config(dev, &ni_pcidio_driver, id->driver_data);
1016 static const struct pci_device_id ni_pcidio_pci_table[] = {
1017 { PCI_VDEVICE(NI, 0x1150), BOARD_PCIDIO_32HS },
1018 { PCI_VDEVICE(NI, 0x12b0), BOARD_PCI6534 },
1019 { PCI_VDEVICE(NI, 0x1320), BOARD_PXI6533 },
1022 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
1024 static struct pci_driver ni_pcidio_pci_driver = {
1025 .name = "ni_pcidio",
1026 .id_table = ni_pcidio_pci_table,
1027 .probe = ni_pcidio_pci_probe,
1028 .remove = comedi_pci_auto_unconfig,
1030 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1032 MODULE_AUTHOR("Comedi http://www.comedi.org");
1033 MODULE_DESCRIPTION("Comedi low-level driver");
1034 MODULE_LICENSE("GPL");