drivers/staging/comedi/drivers/ni_tio.c

   1 /*
   2   comedi/drivers/ni_tio.c
   3   Support for NI general purpose counters
   4
   5   Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   6
   7   This program is free software; you can redistribute it and/or modify
   8   it under the terms of the GNU General Public License as published by
   9   the Free Software Foundation; either version 2 of the License, or
  10   (at your option) any later version.
  11
  12   This program is distributed in the hope that it will be useful,
  13   but WITHOUT ANY WARRANTY; without even the implied warranty of
  14   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15   GNU General Public License for more details.
  16 */
  17
  18 /*
  19 Driver: ni_tio
  20 Description: National Instruments general purpose counters
  21 Devices:
  22 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  23         Herman.Bruyninckx@mech.kuleuven.ac.be,
  24         Wim.Meeussen@mech.kuleuven.ac.be,
  25         Klaas.Gadeyne@mech.kuleuven.ac.be,
  26         Frank Mori Hess <fmhess@users.sourceforge.net>
  27 Updated: Thu Nov 16 09:50:32 EST 2006
  28 Status: works
  29
  30 This module is not used directly by end-users.  Rather, it
  31 is used by other drivers (for example ni_660x and ni_pcimio)
  32 to provide support for NI's general purpose counters.  It was
  33 originally based on the counter code from ni_660x.c and
  34 ni_mio_common.c.
  35
  36 References:
  37 DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  38 DAQ 6601/6602 User Manual (NI 322137B-01)
  39 340934b.pdf  DAQ-STC reference manual
  40
  41 */
  42 /*
  43 TODO:
  44         Support use of both banks X and Y
  45 */
  46
  47 #include <linux/module.h>
  48 #include <linux/slab.h>
  49
  50 #include "ni_tio_internal.h"
  51
  52 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
  53                                        unsigned generic_clock_source);
  54 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter);
  55
  56 static inline enum Gi_Counting_Mode_Reg_Bits
  57 Gi_Alternate_Sync_Bit(enum ni_gpct_variant variant)
  58 {
  59         switch (variant) {
  60         case ni_gpct_variant_e_series:
  61         default:
  62                 return 0;
  63         case ni_gpct_variant_m_series:
  64                 return Gi_M_Series_Alternate_Sync_Bit;
  65         case ni_gpct_variant_660x:
  66                 return Gi_660x_Alternate_Sync_Bit;
  67         }
  68 }
  69
  70 static inline enum Gi_Counting_Mode_Reg_Bits
  71 Gi_Prescale_X2_Bit(enum ni_gpct_variant variant)
  72 {
  73         switch (variant) {
  74         case ni_gpct_variant_e_series:
  75         default:
  76                 return 0;
  77         case ni_gpct_variant_m_series:
  78                 return Gi_M_Series_Prescale_X2_Bit;
  79         case ni_gpct_variant_660x:
  80                 return Gi_660x_Prescale_X2_Bit;
  81         }
  82 }
  83
  84 static inline enum Gi_Counting_Mode_Reg_Bits
  85 Gi_Prescale_X8_Bit(enum ni_gpct_variant variant)
  86 {
  87         switch (variant) {
  88         case ni_gpct_variant_e_series:
  89         default:
  90                 return 0;
  91         case ni_gpct_variant_m_series:
  92                 return Gi_M_Series_Prescale_X8_Bit;
  93         case ni_gpct_variant_660x:
  94                 return Gi_660x_Prescale_X8_Bit;
  95         }
  96 }
  97
  98 static inline enum Gi_Counting_Mode_Reg_Bits
  99 Gi_HW_Arm_Select_Mask(enum ni_gpct_variant variant)
 100 {
 101         switch (variant) {
 102         case ni_gpct_variant_e_series:
 103         default:
 104                 return 0;
 105         case ni_gpct_variant_m_series:
 106                 return Gi_M_Series_HW_Arm_Select_Mask;
 107         case ni_gpct_variant_660x:
 108                 return Gi_660x_HW_Arm_Select_Mask;
 109         }
 110 }
 111
 112 /* clock sources for ni_660x boards, get bits with Gi_Source_Select_Bits() */
 113 enum ni_660x_clock_source {
 114         NI_660x_Timebase_1_Clock = 0x0, /* 20MHz */
 115         NI_660x_Source_Pin_i_Clock = 0x1,
 116         NI_660x_Next_Gate_Clock = 0xa,
 117         NI_660x_Timebase_2_Clock = 0x12,        /* 100KHz */
 118         NI_660x_Next_TC_Clock = 0x13,
 119         NI_660x_Timebase_3_Clock = 0x1e,        /* 80MHz */
 120         NI_660x_Logic_Low_Clock = 0x1f,
 121 };
 122 static const unsigned ni_660x_max_rtsi_channel = 6;
 123 static inline unsigned NI_660x_RTSI_Clock(unsigned n)
 124 {
 125         BUG_ON(n > ni_660x_max_rtsi_channel);
 126         return 0xb + n;
 127 }
 128
 129 static const unsigned ni_660x_max_source_pin = 7;
 130 static inline unsigned NI_660x_Source_Pin_Clock(unsigned n)
 131 {
 132         BUG_ON(n > ni_660x_max_source_pin);
 133         return 0x2 + n;
 134 }
 135
 136 /* clock sources for ni e and m series boards, get bits with Gi_Source_Select_Bits() */
 137 enum ni_m_series_clock_source {
 138         NI_M_Series_Timebase_1_Clock = 0x0,     /* 20MHz */
 139         NI_M_Series_Timebase_2_Clock = 0x12,    /* 100KHz */
 140         NI_M_Series_Next_TC_Clock = 0x13,
 141         NI_M_Series_Next_Gate_Clock = 0x14,     /* when Gi_Src_SubSelect = 0 */
 142         NI_M_Series_PXI_Star_Trigger_Clock = 0x14,      /* when Gi_Src_SubSelect = 1 */
 143         NI_M_Series_PXI10_Clock = 0x1d,
 144         NI_M_Series_Timebase_3_Clock = 0x1e,    /* 80MHz, when Gi_Src_SubSelect = 0 */
 145         NI_M_Series_Analog_Trigger_Out_Clock = 0x1e,    /* when Gi_Src_SubSelect = 1 */
 146         NI_M_Series_Logic_Low_Clock = 0x1f,
 147 };
 148 static const unsigned ni_m_series_max_pfi_channel = 15;
 149 #define NI_M_PFI_CLK(x)                 (((x) < 10) ? (1 + (x)) : (0xb + (x)))
 150
 151 static const unsigned ni_m_series_max_rtsi_channel = 7;
 152 #define NI_M_RTSI_CLK(x)                (((x) == 7) ? 0x1b : (0xb + (x)))
 153
 154 enum ni_660x_gate_select {
 155         NI_660x_Source_Pin_i_Gate_Select = 0x0,
 156         NI_660x_Gate_Pin_i_Gate_Select = 0x1,
 157         NI_660x_Next_SRC_Gate_Select = 0xa,
 158         NI_660x_Next_Out_Gate_Select = 0x14,
 159         NI_660x_Logic_Low_Gate_Select = 0x1f,
 160 };
 161 static const unsigned ni_660x_max_gate_pin = 7;
 162 static inline unsigned NI_660x_Gate_Pin_Gate_Select(unsigned n)
 163 {
 164         BUG_ON(n > ni_660x_max_gate_pin);
 165         return 0x2 + n;
 166 }
 167
 168 static inline unsigned NI_660x_RTSI_Gate_Select(unsigned n)
 169 {
 170         BUG_ON(n > ni_660x_max_rtsi_channel);
 171         return 0xb + n;
 172 }
 173
 174 enum ni_m_series_gate_select {
 175         NI_M_Series_Timestamp_Mux_Gate_Select = 0x0,
 176         NI_M_Series_AI_START2_Gate_Select = 0x12,
 177         NI_M_Series_PXI_Star_Trigger_Gate_Select = 0x13,
 178         NI_M_Series_Next_Out_Gate_Select = 0x14,
 179         NI_M_Series_AI_START1_Gate_Select = 0x1c,
 180         NI_M_Series_Next_SRC_Gate_Select = 0x1d,
 181         NI_M_Series_Analog_Trigger_Out_Gate_Select = 0x1e,
 182         NI_M_Series_Logic_Low_Gate_Select = 0x1f,
 183 };
 184 static inline unsigned NI_M_Series_RTSI_Gate_Select(unsigned n)
 185 {
 186         BUG_ON(n > ni_m_series_max_rtsi_channel);
 187         if (n == 7)
 188                 return 0x1b;
 189         return 0xb + n;
 190 }
 191
 192 static inline unsigned NI_M_Series_PFI_Gate_Select(unsigned n)
 193 {
 194         BUG_ON(n > ni_m_series_max_pfi_channel);
 195         if (n < 10)
 196                 return 1 + n;
 197         return 0xb + n;
 198 }
 199
 200 static inline unsigned Gi_Source_Select_Bits(unsigned source)
 201 {
 202         return (source << Gi_Source_Select_Shift) & Gi_Source_Select_Mask;
 203 }
 204
 205 static inline unsigned Gi_Gate_Select_Bits(unsigned gate_select)
 206 {
 207         return (gate_select << Gi_Gate_Select_Shift) & Gi_Gate_Select_Mask;
 208 }
 209
 210 enum ni_660x_second_gate_select {
 211         NI_660x_Source_Pin_i_Second_Gate_Select = 0x0,
 212         NI_660x_Up_Down_Pin_i_Second_Gate_Select = 0x1,
 213         NI_660x_Next_SRC_Second_Gate_Select = 0xa,
 214         NI_660x_Next_Out_Second_Gate_Select = 0x14,
 215         NI_660x_Selected_Gate_Second_Gate_Select = 0x1e,
 216         NI_660x_Logic_Low_Second_Gate_Select = 0x1f,
 217 };
 218 static const unsigned ni_660x_max_up_down_pin = 7;
 219 static inline unsigned NI_660x_Up_Down_Pin_Second_Gate_Select(unsigned n)
 220 {
 221         BUG_ON(n > ni_660x_max_up_down_pin);
 222         return 0x2 + n;
 223 }
 224
 225 static inline unsigned NI_660x_RTSI_Second_Gate_Select(unsigned n)
 226 {
 227         BUG_ON(n > ni_660x_max_rtsi_channel);
 228         return 0xb + n;
 229 }
 230
 231 static const unsigned int counter_status_mask =
 232         COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
 233
 234 struct ni_gpct_device *
 235 ni_gpct_device_construct(struct comedi_device *dev,
 236                          void (*write_register)(struct ni_gpct *counter,
 237                                                 unsigned bits,
 238                                                 enum ni_gpct_register reg),
 239                          unsigned (*read_register)(struct ni_gpct *counter,
 240                                                    enum ni_gpct_register reg),
 241                          enum ni_gpct_variant variant,
 242                          unsigned num_counters)
 243 {
 244         unsigned i;
 245
 246         struct ni_gpct_device *counter_dev =
 247             kzalloc(sizeof(struct ni_gpct_device), GFP_KERNEL);
 248         if (counter_dev == NULL)
 249                 return NULL;
 250         counter_dev->dev = dev;
 251         counter_dev->write_register = write_register;
 252         counter_dev->read_register = read_register;
 253         counter_dev->variant = variant;
 254         spin_lock_init(&counter_dev->regs_lock);
 255         BUG_ON(num_counters == 0);
 256         counter_dev->counters =
 257             kzalloc(sizeof(struct ni_gpct) * num_counters, GFP_KERNEL);
 258         if (counter_dev->counters == NULL) {
 259                 kfree(counter_dev);
 260                 return NULL;
 261         }
 262         for (i = 0; i < num_counters; ++i) {
 263                 counter_dev->counters[i].counter_dev = counter_dev;
 264                 spin_lock_init(&counter_dev->counters[i].lock);
 265         }
 266         counter_dev->num_counters = num_counters;
 267         return counter_dev;
 268 }
 269 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
 270
 271 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
 272 {
 273         if (counter_dev->counters == NULL)
 274                 return;
 275         kfree(counter_dev->counters);
 276         kfree(counter_dev);
 277 }
 278 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
 279
 280 static int
 281 ni_tio_second_gate_registers_present(const struct ni_gpct_device *counter_dev)
 282 {
 283         switch (counter_dev->variant) {
 284         case ni_gpct_variant_e_series:
 285         default:
 286                 return 0;
 287         case ni_gpct_variant_m_series:
 288         case ni_gpct_variant_660x:
 289                 return 1;
 290         }
 291 }
 292
 293 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
 294 {
 295         unsigned cidx = counter->counter_index;
 296
 297         write_register(counter, Gi_Reset_Bit(cidx), NITIO_RESET_REG(cidx));
 298 }
 299
 300 void ni_tio_init_counter(struct ni_gpct *counter)
 301 {
 302         struct ni_gpct_device *counter_dev = counter->counter_dev;
 303         unsigned cidx = counter->counter_index;
 304
 305         ni_tio_reset_count_and_disarm(counter);
 306
 307         /* initialize counter registers */
 308         counter_dev->regs[NITIO_AUTO_INC_REG(cidx)] = 0x0;
 309         write_register(counter, counter_dev->regs[NITIO_AUTO_INC_REG(cidx)],
 310                        NITIO_AUTO_INC_REG(cidx));
 311
 312         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
 313                         ~0, Gi_Synchronize_Gate_Bit);
 314
 315         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ~0, 0);
 316
 317         counter_dev->regs[NITIO_LOADA_REG(cidx)] = 0x0;
 318         write_register(counter, counter_dev->regs[NITIO_LOADA_REG(cidx)],
 319                        NITIO_LOADA_REG(cidx));
 320
 321         counter_dev->regs[NITIO_LOADB_REG(cidx)] = 0x0;
 322         write_register(counter, counter_dev->regs[NITIO_LOADB_REG(cidx)],
 323                        NITIO_LOADB_REG(cidx));
 324
 325         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ~0, 0);
 326
 327         if (ni_tio_counting_mode_registers_present(counter_dev))
 328                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ~0, 0);
 329
 330         if (ni_tio_second_gate_registers_present(counter_dev)) {
 331                 counter_dev->regs[NITIO_GATE2_REG(cidx)] = 0x0;
 332                 write_register(counter,
 333                                counter_dev->regs[NITIO_GATE2_REG(cidx)],
 334                                NITIO_GATE2_REG(cidx));
 335         }
 336
 337         ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), ~0, 0x0);
 338
 339         ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ~0, 0x0);
 340 }
 341 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
 342
 343 static unsigned int ni_tio_counter_status(struct ni_gpct *counter)
 344 {
 345         unsigned cidx = counter->counter_index;
 346         const unsigned bits = read_register(counter,
 347                                             NITIO_SHARED_STATUS_REG(cidx));
 348         unsigned int status = 0;
 349
 350         if (bits & Gi_Armed_Bit(cidx)) {
 351                 status |= COMEDI_COUNTER_ARMED;
 352                 if (bits & Gi_Counting_Bit(cidx))
 353                         status |= COMEDI_COUNTER_COUNTING;
 354         }
 355         return status;
 356 }
 357
 358 static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync)
 359 {
 360         struct ni_gpct_device *counter_dev = counter->counter_dev;
 361         unsigned cidx = counter->counter_index;
 362         const unsigned counting_mode_reg = NITIO_CNT_MODE_REG(cidx);
 363         static const uint64_t min_normal_sync_period_ps = 25000;
 364         const uint64_t clock_period_ps = ni_tio_clock_period_ps(counter,
 365                                                                 ni_tio_generic_clock_src_select
 366                                                                 (counter));
 367
 368         if (ni_tio_counting_mode_registers_present(counter_dev) == 0)
 369                 return;
 370
 371         switch (ni_tio_get_soft_copy(counter, counting_mode_reg) & Gi_Counting_Mode_Mask) {
 372         case Gi_Counting_Mode_QuadratureX1_Bits:
 373         case Gi_Counting_Mode_QuadratureX2_Bits:
 374         case Gi_Counting_Mode_QuadratureX4_Bits:
 375         case Gi_Counting_Mode_Sync_Source_Bits:
 376                 force_alt_sync = 1;
 377                 break;
 378         default:
 379                 break;
 380         }
 381         /*
 382          * It's not clear what we should do if clock_period is unknown, so we
 383          * are not using the alt sync bit in that case, but allow the caller
 384          * to decide by using the force_alt_sync parameter.
 385          */
 386         if (force_alt_sync ||
 387             (clock_period_ps && clock_period_ps < min_normal_sync_period_ps)) {
 388                 ni_tio_set_bits(counter, counting_mode_reg,
 389                                 Gi_Alternate_Sync_Bit(counter_dev->variant),
 390                                 Gi_Alternate_Sync_Bit(counter_dev->variant));
 391         } else {
 392                 ni_tio_set_bits(counter, counting_mode_reg,
 393                                 Gi_Alternate_Sync_Bit(counter_dev->variant),
 394                                 0x0);
 395         }
 396 }
 397
 398 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode)
 399 {
 400         struct ni_gpct_device *counter_dev = counter->counter_dev;
 401         unsigned cidx = counter->counter_index;
 402         unsigned mode_reg_mask;
 403         unsigned mode_reg_values;
 404         unsigned input_select_bits = 0;
 405         /* these bits map directly on to the mode register */
 406         static const unsigned mode_reg_direct_mask =
 407             NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
 408             NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
 409             NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
 410             NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
 411
 412         mode_reg_mask = mode_reg_direct_mask | Gi_Reload_Source_Switching_Bit;
 413         mode_reg_values = mode & mode_reg_direct_mask;
 414         switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
 415         case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
 416                 break;
 417         case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
 418                 mode_reg_values |= Gi_Reload_Source_Switching_Bit;
 419                 break;
 420         case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
 421                 input_select_bits |= Gi_Gate_Select_Load_Source_Bit;
 422                 mode_reg_mask |= Gi_Gating_Mode_Mask;
 423                 mode_reg_values |= Gi_Level_Gating_Bits;
 424                 break;
 425         default:
 426                 break;
 427         }
 428         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 429                         mode_reg_mask, mode_reg_values);
 430
 431         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 432                 unsigned counting_mode_bits = 0;
 433
 434                 counting_mode_bits |=
 435                     (mode >> NI_GPCT_COUNTING_MODE_SHIFT) &
 436                     Gi_Counting_Mode_Mask;
 437                 counting_mode_bits |=
 438                     ((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT) <<
 439                      Gi_Index_Phase_Bitshift) & Gi_Index_Phase_Mask;
 440                 if (mode & NI_GPCT_INDEX_ENABLE_BIT)
 441                         counting_mode_bits |= Gi_Index_Mode_Bit;
 442                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 443                                 Gi_Counting_Mode_Mask | Gi_Index_Phase_Mask |
 444                                 Gi_Index_Mode_Bit, counting_mode_bits);
 445                 ni_tio_set_sync_mode(counter, 0);
 446         }
 447
 448         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
 449                         Gi_Up_Down_Mask,
 450                         (mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT) <<
 451                         Gi_Up_Down_Shift);
 452
 453         if (mode & NI_GPCT_OR_GATE_BIT)
 454                 input_select_bits |= Gi_Or_Gate_Bit;
 455         if (mode & NI_GPCT_INVERT_OUTPUT_BIT)
 456                 input_select_bits |= Gi_Output_Polarity_Bit;
 457         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 458                         Gi_Gate_Select_Load_Source_Bit | Gi_Or_Gate_Bit |
 459                         Gi_Output_Polarity_Bit, input_select_bits);
 460
 461         return 0;
 462 }
 463
 464 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger)
 465 {
 466         struct ni_gpct_device *counter_dev = counter->counter_dev;
 467         unsigned cidx = counter->counter_index;
 468         unsigned command_transient_bits = 0;
 469
 470         if (arm) {
 471                 switch (start_trigger) {
 472                 case NI_GPCT_ARM_IMMEDIATE:
 473                         command_transient_bits |= Gi_Arm_Bit;
 474                         break;
 475                 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
 476                         command_transient_bits |= Gi_Arm_Bit | Gi_Arm_Copy_Bit;
 477                         break;
 478                 default:
 479                         break;
 480                 }
 481                 if (ni_tio_counting_mode_registers_present(counter_dev)) {
 482                         unsigned counting_mode_bits = 0;
 483
 484                         switch (start_trigger) {
 485                         case NI_GPCT_ARM_IMMEDIATE:
 486                         case NI_GPCT_ARM_PAIRED_IMMEDIATE:
 487                                 break;
 488                         default:
 489                                 if (start_trigger & NI_GPCT_ARM_UNKNOWN) {
 490                                         /*
 491                                          * pass-through the least significant
 492                                          * bits so we can figure out what
 493                                          * select later
 494                                          */
 495                                         unsigned hw_arm_select_bits =
 496                                             (start_trigger <<
 497                                              Gi_HW_Arm_Select_Shift) &
 498                                             Gi_HW_Arm_Select_Mask
 499                                             (counter_dev->variant);
 500
 501                                         counting_mode_bits |=
 502                                             Gi_HW_Arm_Enable_Bit |
 503                                             hw_arm_select_bits;
 504                                 } else {
 505                                         return -EINVAL;
 506                                 }
 507                                 break;
 508                         }
 509                         ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 510                                         Gi_HW_Arm_Select_Mask
 511                                         (counter_dev->variant) |
 512                                         Gi_HW_Arm_Enable_Bit,
 513                                         counting_mode_bits);
 514                 }
 515         } else {
 516                 command_transient_bits |= Gi_Disarm_Bit;
 517         }
 518         ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
 519                                   0, 0, command_transient_bits);
 520         return 0;
 521 }
 522 EXPORT_SYMBOL_GPL(ni_tio_arm);
 523
 524 static unsigned ni_660x_source_select_bits(unsigned int clock_source)
 525 {
 526         unsigned ni_660x_clock;
 527         unsigned i;
 528         const unsigned clock_select_bits =
 529             clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 530
 531         switch (clock_select_bits) {
 532         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 533                 ni_660x_clock = NI_660x_Timebase_1_Clock;
 534                 break;
 535         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 536                 ni_660x_clock = NI_660x_Timebase_2_Clock;
 537                 break;
 538         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 539                 ni_660x_clock = NI_660x_Timebase_3_Clock;
 540                 break;
 541         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 542                 ni_660x_clock = NI_660x_Logic_Low_Clock;
 543                 break;
 544         case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
 545                 ni_660x_clock = NI_660x_Source_Pin_i_Clock;
 546                 break;
 547         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 548                 ni_660x_clock = NI_660x_Next_Gate_Clock;
 549                 break;
 550         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 551                 ni_660x_clock = NI_660x_Next_TC_Clock;
 552                 break;
 553         default:
 554                 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
 555                         if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 556                                 ni_660x_clock = NI_660x_RTSI_Clock(i);
 557                                 break;
 558                         }
 559                 }
 560                 if (i <= ni_660x_max_rtsi_channel)
 561                         break;
 562                 for (i = 0; i <= ni_660x_max_source_pin; ++i) {
 563                         if (clock_select_bits ==
 564                             NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
 565                                 ni_660x_clock = NI_660x_Source_Pin_Clock(i);
 566                                 break;
 567                         }
 568                 }
 569                 if (i <= ni_660x_max_source_pin)
 570                         break;
 571                 ni_660x_clock = 0;
 572                 BUG();
 573                 break;
 574         }
 575         return Gi_Source_Select_Bits(ni_660x_clock);
 576 }
 577
 578 static unsigned ni_m_series_source_select_bits(unsigned int clock_source)
 579 {
 580         unsigned ni_m_series_clock;
 581         unsigned i;
 582         const unsigned clock_select_bits =
 583             clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 584         switch (clock_select_bits) {
 585         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 586                 ni_m_series_clock = NI_M_Series_Timebase_1_Clock;
 587                 break;
 588         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 589                 ni_m_series_clock = NI_M_Series_Timebase_2_Clock;
 590                 break;
 591         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 592                 ni_m_series_clock = NI_M_Series_Timebase_3_Clock;
 593                 break;
 594         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 595                 ni_m_series_clock = NI_M_Series_Logic_Low_Clock;
 596                 break;
 597         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 598                 ni_m_series_clock = NI_M_Series_Next_Gate_Clock;
 599                 break;
 600         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 601                 ni_m_series_clock = NI_M_Series_Next_TC_Clock;
 602                 break;
 603         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 604                 ni_m_series_clock = NI_M_Series_PXI10_Clock;
 605                 break;
 606         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 607                 ni_m_series_clock = NI_M_Series_PXI_Star_Trigger_Clock;
 608                 break;
 609         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 610                 ni_m_series_clock = NI_M_Series_Analog_Trigger_Out_Clock;
 611                 break;
 612         default:
 613                 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
 614                         if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 615                                 ni_m_series_clock = NI_M_RTSI_CLK(i);
 616                                 break;
 617                         }
 618                 }
 619                 if (i <= ni_m_series_max_rtsi_channel)
 620                         break;
 621                 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
 622                         if (clock_select_bits == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
 623                                 ni_m_series_clock = NI_M_PFI_CLK(i);
 624                                 break;
 625                         }
 626                 }
 627                 if (i <= ni_m_series_max_pfi_channel)
 628                         break;
 629                 printk(KERN_ERR "invalid clock source 0x%lx\n",
 630                        (unsigned long)clock_source);
 631                 BUG();
 632                 ni_m_series_clock = 0;
 633                 break;
 634         }
 635         return Gi_Source_Select_Bits(ni_m_series_clock);
 636 };
 637
 638 static void ni_tio_set_source_subselect(struct ni_gpct *counter,
 639                                         unsigned int clock_source)
 640 {
 641         struct ni_gpct_device *counter_dev = counter->counter_dev;
 642         unsigned cidx = counter->counter_index;
 643         const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
 644
 645         if (counter_dev->variant != ni_gpct_variant_m_series)
 646                 return;
 647         switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 648                 /* Gi_Source_Subselect is zero */
 649         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 650         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 651                 counter_dev->regs[second_gate_reg] &= ~Gi_Source_Subselect_Bit;
 652                 break;
 653                 /* Gi_Source_Subselect is one */
 654         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 655         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 656                 counter_dev->regs[second_gate_reg] |= Gi_Source_Subselect_Bit;
 657                 break;
 658                 /* Gi_Source_Subselect doesn't matter */
 659         default:
 660                 return;
 661         }
 662         write_register(counter, counter_dev->regs[second_gate_reg],
 663                        second_gate_reg);
 664 }
 665
 666 static int ni_tio_set_clock_src(struct ni_gpct *counter,
 667                                 unsigned int clock_source,
 668                                 unsigned int period_ns)
 669 {
 670         struct ni_gpct_device *counter_dev = counter->counter_dev;
 671         unsigned cidx = counter->counter_index;
 672         unsigned input_select_bits = 0;
 673         static const uint64_t pico_per_nano = 1000;
 674
 675 /*FIXME: validate clock source */
 676         switch (counter_dev->variant) {
 677         case ni_gpct_variant_660x:
 678                 input_select_bits |= ni_660x_source_select_bits(clock_source);
 679                 break;
 680         case ni_gpct_variant_e_series:
 681         case ni_gpct_variant_m_series:
 682         default:
 683                 input_select_bits |=
 684                     ni_m_series_source_select_bits(clock_source);
 685                 break;
 686         }
 687         if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
 688                 input_select_bits |= Gi_Source_Polarity_Bit;
 689         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 690                         Gi_Source_Select_Mask | Gi_Source_Polarity_Bit,
 691                         input_select_bits);
 692         ni_tio_set_source_subselect(counter, clock_source);
 693         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 694                 const unsigned prescaling_mode =
 695                     clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK;
 696                 unsigned counting_mode_bits = 0;
 697
 698                 switch (prescaling_mode) {
 699                 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 700                         break;
 701                 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 702                         counting_mode_bits |=
 703                             Gi_Prescale_X2_Bit(counter_dev->variant);
 704                         break;
 705                 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 706                         counting_mode_bits |=
 707                             Gi_Prescale_X8_Bit(counter_dev->variant);
 708                         break;
 709                 default:
 710                         return -EINVAL;
 711                 }
 712                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 713                                 Gi_Prescale_X2_Bit(counter_dev->variant) |
 714                                 Gi_Prescale_X8_Bit(counter_dev->variant),
 715                                 counting_mode_bits);
 716         }
 717         counter->clock_period_ps = pico_per_nano * period_ns;
 718         ni_tio_set_sync_mode(counter, 0);
 719         return 0;
 720 }
 721
 722 static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
 723 {
 724         struct ni_gpct_device *counter_dev = counter->counter_dev;
 725         unsigned cidx = counter->counter_index;
 726         const unsigned counting_mode_bits =
 727                 ni_tio_get_soft_copy(counter, NITIO_CNT_MODE_REG(cidx));
 728         unsigned bits = 0;
 729
 730         if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
 731             Gi_Source_Polarity_Bit)
 732                 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
 733         if (counting_mode_bits & Gi_Prescale_X2_Bit(counter_dev->variant))
 734                 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
 735         if (counting_mode_bits & Gi_Prescale_X8_Bit(counter_dev->variant))
 736                 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
 737         return bits;
 738 }
 739
 740 static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter)
 741 {
 742         struct ni_gpct_device *counter_dev = counter->counter_dev;
 743         unsigned cidx = counter->counter_index;
 744         const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
 745         unsigned clock_source = 0;
 746         unsigned i;
 747         const unsigned input_select =
 748                 (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
 749                         Gi_Source_Select_Mask) >> Gi_Source_Select_Shift;
 750
 751         switch (input_select) {
 752         case NI_M_Series_Timebase_1_Clock:
 753                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 754                 break;
 755         case NI_M_Series_Timebase_2_Clock:
 756                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 757                 break;
 758         case NI_M_Series_Timebase_3_Clock:
 759                 if (counter_dev->regs[second_gate_reg] &
 760                     Gi_Source_Subselect_Bit)
 761                         clock_source =
 762                             NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
 763                 else
 764                         clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 765                 break;
 766         case NI_M_Series_Logic_Low_Clock:
 767                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 768                 break;
 769         case NI_M_Series_Next_Gate_Clock:
 770                 if (counter_dev->regs[second_gate_reg] &
 771                     Gi_Source_Subselect_Bit)
 772                         clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
 773                 else
 774                         clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 775                 break;
 776         case NI_M_Series_PXI10_Clock:
 777                 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
 778                 break;
 779         case NI_M_Series_Next_TC_Clock:
 780                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 781                 break;
 782         default:
 783                 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
 784                         if (input_select == NI_M_RTSI_CLK(i)) {
 785                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 786                                 break;
 787                         }
 788                 }
 789                 if (i <= ni_m_series_max_rtsi_channel)
 790                         break;
 791                 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
 792                         if (input_select == NI_M_PFI_CLK(i)) {
 793                                 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
 794                                 break;
 795                         }
 796                 }
 797                 if (i <= ni_m_series_max_pfi_channel)
 798                         break;
 799                 BUG();
 800                 break;
 801         }
 802         clock_source |= ni_tio_clock_src_modifiers(counter);
 803         return clock_source;
 804 }
 805
 806 static unsigned ni_660x_clock_src_select(const struct ni_gpct *counter)
 807 {
 808         unsigned clock_source = 0;
 809         unsigned cidx = counter->counter_index;
 810         const unsigned input_select =
 811                 (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
 812                         Gi_Source_Select_Mask) >> Gi_Source_Select_Shift;
 813         unsigned i;
 814
 815         switch (input_select) {
 816         case NI_660x_Timebase_1_Clock:
 817                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 818                 break;
 819         case NI_660x_Timebase_2_Clock:
 820                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 821                 break;
 822         case NI_660x_Timebase_3_Clock:
 823                 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 824                 break;
 825         case NI_660x_Logic_Low_Clock:
 826                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 827                 break;
 828         case NI_660x_Source_Pin_i_Clock:
 829                 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
 830                 break;
 831         case NI_660x_Next_Gate_Clock:
 832                 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 833                 break;
 834         case NI_660x_Next_TC_Clock:
 835                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 836                 break;
 837         default:
 838                 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
 839                         if (input_select == NI_660x_RTSI_Clock(i)) {
 840                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 841                                 break;
 842                         }
 843                 }
 844                 if (i <= ni_660x_max_rtsi_channel)
 845                         break;
 846                 for (i = 0; i <= ni_660x_max_source_pin; ++i) {
 847                         if (input_select == NI_660x_Source_Pin_Clock(i)) {
 848                                 clock_source =
 849                                     NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
 850                                 break;
 851                         }
 852                 }
 853                 if (i <= ni_660x_max_source_pin)
 854                         break;
 855                 BUG();
 856                 break;
 857         }
 858         clock_source |= ni_tio_clock_src_modifiers(counter);
 859         return clock_source;
 860 }
 861
 862 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter)
 863 {
 864         switch (counter->counter_dev->variant) {
 865         case ni_gpct_variant_e_series:
 866         case ni_gpct_variant_m_series:
 867         default:
 868                 return ni_m_series_clock_src_select(counter);
 869         case ni_gpct_variant_660x:
 870                 return ni_660x_clock_src_select(counter);
 871         }
 872 }
 873
 874 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
 875                                        unsigned generic_clock_source)
 876 {
 877         uint64_t clock_period_ps;
 878
 879         switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 880         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 881                 clock_period_ps = 50000;
 882                 break;
 883         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 884                 clock_period_ps = 10000000;
 885                 break;
 886         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 887                 clock_period_ps = 12500;
 888                 break;
 889         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 890                 clock_period_ps = 100000;
 891                 break;
 892         default:
 893                 /*
 894                  * clock period is specified by user with prescaling
 895                  * already taken into account.
 896                  */
 897                 return counter->clock_period_ps;
 898         }
 899
 900         switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
 901         case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 902                 break;
 903         case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 904                 clock_period_ps *= 2;
 905                 break;
 906         case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 907                 clock_period_ps *= 8;
 908                 break;
 909         default:
 910                 BUG();
 911                 break;
 912         }
 913         return clock_period_ps;
 914 }
 915
 916 static void ni_tio_get_clock_src(struct ni_gpct *counter,
 917                                  unsigned int *clock_source,
 918                                  unsigned int *period_ns)
 919 {
 920         static const unsigned pico_per_nano = 1000;
 921         uint64_t temp64;
 922         *clock_source = ni_tio_generic_clock_src_select(counter);
 923         temp64 = ni_tio_clock_period_ps(counter, *clock_source);
 924         do_div(temp64, pico_per_nano);
 925         *period_ns = temp64;
 926 }
 927
 928 static void ni_tio_set_first_gate_modifiers(struct ni_gpct *counter,
 929                                             unsigned int gate_source)
 930 {
 931         const unsigned mode_mask = Gi_Gate_Polarity_Bit | Gi_Gating_Mode_Mask;
 932         unsigned cidx = counter->counter_index;
 933         unsigned mode_values = 0;
 934
 935         if (gate_source & CR_INVERT)
 936                 mode_values |= Gi_Gate_Polarity_Bit;
 937         if (gate_source & CR_EDGE)
 938                 mode_values |= Gi_Rising_Edge_Gating_Bits;
 939         else
 940                 mode_values |= Gi_Level_Gating_Bits;
 941         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 942                         mode_mask, mode_values);
 943 }
 944
 945 static int ni_660x_set_first_gate(struct ni_gpct *counter,
 946                                   unsigned int gate_source)
 947 {
 948         unsigned int chan = CR_CHAN(gate_source);
 949         unsigned cidx = counter->counter_index;
 950         unsigned gate_sel;
 951         unsigned i;
 952
 953         switch (chan) {
 954         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 955                 gate_sel = NI_660x_Next_SRC_Gate_Select;
 956                 break;
 957         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 958         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 959         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
 960         case NI_GPCT_GATE_PIN_i_GATE_SELECT:
 961                 gate_sel = chan & 0x1f;
 962                 break;
 963         default:
 964                 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
 965                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 966                                 gate_sel = chan & 0x1f;
 967                                 break;
 968                         }
 969                 }
 970                 if (i <= ni_660x_max_rtsi_channel)
 971                         break;
 972                 for (i = 0; i <= ni_660x_max_gate_pin; ++i) {
 973                         if (chan == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
 974                                 gate_sel = chan & 0x1f;
 975                                 break;
 976                         }
 977                 }
 978                 if (i <= ni_660x_max_gate_pin)
 979                         break;
 980                 return -EINVAL;
 981         }
 982         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 983                         Gi_Gate_Select_Mask, Gi_Gate_Select_Bits(gate_sel));
 984         return 0;
 985 }
 986
 987 static int ni_m_series_set_first_gate(struct ni_gpct *counter,
 988                                       unsigned int gate_source)
 989 {
 990         unsigned int chan = CR_CHAN(gate_source);
 991         unsigned cidx = counter->counter_index;
 992         unsigned gate_sel;
 993         unsigned i;
 994
 995         switch (chan) {
 996         case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
 997         case NI_GPCT_AI_START2_GATE_SELECT:
 998         case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
 999         case NI_GPCT_NEXT_OUT_GATE_SELECT:
1000         case NI_GPCT_AI_START1_GATE_SELECT:
1001         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1002         case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
1003         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1004                 gate_sel = chan & 0x1f;
1005                 break;
1006         default:
1007                 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
1008                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
1009                                 gate_sel = chan & 0x1f;
1010                                 break;
1011                         }
1012                 }
1013                 if (i <= ni_m_series_max_rtsi_channel)
1014                         break;
1015                 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
1016                         if (chan == NI_GPCT_PFI_GATE_SELECT(i)) {
1017                                 gate_sel = chan & 0x1f;
1018                                 break;
1019                         }
1020                 }
1021                 if (i <= ni_m_series_max_pfi_channel)
1022                         break;
1023                 return -EINVAL;
1024         }
1025         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
1026                         Gi_Gate_Select_Mask, Gi_Gate_Select_Bits(gate_sel));
1027         return 0;
1028 }
1029
1030 static int ni_660x_set_second_gate(struct ni_gpct *counter,
1031                                    unsigned int gate_source)
1032 {
1033         struct ni_gpct_device *counter_dev = counter->counter_dev;
1034         unsigned cidx = counter->counter_index;
1035         unsigned int chan = CR_CHAN(gate_source);
1036         unsigned gate2_reg = NITIO_GATE2_REG(cidx);
1037         unsigned gate2_sel;
1038         unsigned i;
1039
1040         switch (chan) {
1041         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
1042         case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
1043         case NI_GPCT_SELECTED_GATE_GATE_SELECT:
1044         case NI_GPCT_NEXT_OUT_GATE_SELECT:
1045         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1046                 gate2_sel = chan & 0x1f;
1047                 break;
1048         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1049                 gate2_sel = NI_660x_Next_SRC_Second_Gate_Select;
1050                 break;
1051         default:
1052                 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1053                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
1054                                 gate2_sel = chan & 0x1f;
1055                                 break;
1056                         }
1057                 }
1058                 if (i <= ni_660x_max_rtsi_channel)
1059                         break;
1060                 for (i = 0; i <= ni_660x_max_up_down_pin; ++i) {
1061                         if (chan == NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
1062                                 gate2_sel = chan & 0x1f;
1063                                 break;
1064                         }
1065                 }
1066                 if (i <= ni_660x_max_up_down_pin)
1067                         break;
1068                 return -EINVAL;
1069         }
1070         counter_dev->regs[gate2_reg] |= Gi_Second_Gate_Mode_Bit;
1071         counter_dev->regs[gate2_reg] &= ~Gi_Second_Gate_Select_Mask;
1072         counter_dev->regs[gate2_reg] |= Gi_Second_Gate_Select_Bits(gate2_sel);
1073         write_register(counter, counter_dev->regs[gate2_reg], gate2_reg);
1074         return 0;
1075 }
1076
1077 static int ni_m_series_set_second_gate(struct ni_gpct *counter,
1078                                        unsigned int gate_source)
1079 {
1080         struct ni_gpct_device *counter_dev = counter->counter_dev;
1081         unsigned cidx = counter->counter_index;
1082         const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
1083         const unsigned selected_second_gate = CR_CHAN(gate_source);
1084         /* bits of second_gate that may be meaningful to second gate register */
1085         static const unsigned selected_second_gate_mask = 0x1f;
1086         unsigned ni_m_series_second_gate_select;
1087
1088         /*
1089          * FIXME: We don't know what the m-series second gate codes are,
1090          * so we'll just pass the bits through for now.
1091          */
1092         switch (selected_second_gate) {
1093         default:
1094                 ni_m_series_second_gate_select =
1095                     selected_second_gate & selected_second_gate_mask;
1096                 break;
1097         }
1098         counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
1099         counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
1100         counter_dev->regs[second_gate_reg] |=
1101             Gi_Second_Gate_Select_Bits(ni_m_series_second_gate_select);
1102         write_register(counter, counter_dev->regs[second_gate_reg],
1103                        second_gate_reg);
1104         return 0;
1105 }
1106
1107 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
1108                         unsigned int gate_source)
1109 {
1110         struct ni_gpct_device *counter_dev = counter->counter_dev;
1111         unsigned cidx = counter->counter_index;
1112         const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
1113
1114         switch (gate_index) {
1115         case 0:
1116                 if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
1117                         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
1118                                         Gi_Gating_Mode_Mask,
1119                                         Gi_Gating_Disabled_Bits);
1120                         return 0;
1121                 }
1122                 ni_tio_set_first_gate_modifiers(counter, gate_source);
1123                 switch (counter_dev->variant) {
1124                 case ni_gpct_variant_e_series:
1125                 case ni_gpct_variant_m_series:
1126                 default:
1127                         return ni_m_series_set_first_gate(counter, gate_source);
1128                 case ni_gpct_variant_660x:
1129                         return ni_660x_set_first_gate(counter, gate_source);
1130                 }
1131                 break;
1132         case 1:
1133                 if (ni_tio_second_gate_registers_present(counter_dev) == 0)
1134                         return -EINVAL;
1135                 if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
1136                         counter_dev->regs[second_gate_reg] &=
1137                             ~Gi_Second_Gate_Mode_Bit;
1138                         write_register(counter,
1139                                        counter_dev->regs[second_gate_reg],
1140                                        second_gate_reg);
1141                         return 0;
1142                 }
1143                 if (gate_source & CR_INVERT) {
1144                         counter_dev->regs[second_gate_reg] |=
1145                             Gi_Second_Gate_Polarity_Bit;
1146                 } else {
1147                         counter_dev->regs[second_gate_reg] &=
1148                             ~Gi_Second_Gate_Polarity_Bit;
1149                 }
1150                 switch (counter_dev->variant) {
1151                 case ni_gpct_variant_m_series:
1152                         return ni_m_series_set_second_gate(counter,
1153                                                            gate_source);
1154                 case ni_gpct_variant_660x:
1155                         return ni_660x_set_second_gate(counter, gate_source);
1156                 default:
1157                         BUG();
1158                         break;
1159                 }
1160                 break;
1161         default:
1162                 return -EINVAL;
1163         }
1164         return 0;
1165 }
1166 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
1167
1168 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned index,
1169                                 unsigned int source)
1170 {
1171         struct ni_gpct_device *counter_dev = counter->counter_dev;
1172         unsigned cidx = counter->counter_index;
1173
1174         if (counter_dev->variant == ni_gpct_variant_m_series) {
1175                 unsigned int abz_reg, shift, mask;
1176
1177                 abz_reg = NITIO_ABZ_REG(cidx);
1178                 switch (index) {
1179                 case NI_GPCT_SOURCE_ENCODER_A:
1180                         shift = 10;
1181                         break;
1182                 case NI_GPCT_SOURCE_ENCODER_B:
1183                         shift = 5;
1184                         break;
1185                 case NI_GPCT_SOURCE_ENCODER_Z:
1186                         shift = 0;
1187                         break;
1188                 default:
1189                         return -EINVAL;
1190                 }
1191                 mask = 0x1f << shift;
1192                 if (source > 0x1f) {
1193                         /* Disable gate */
1194                         source = 0x1f;
1195                 }
1196                 counter_dev->regs[abz_reg] &= ~mask;
1197                 counter_dev->regs[abz_reg] |= (source << shift) & mask;
1198                 write_register(counter, counter_dev->regs[abz_reg], abz_reg);
1199                 return 0;
1200         }
1201         return -EINVAL;
1202 }
1203
1204 static unsigned
1205 ni_660x_first_gate_to_generic_gate_source(unsigned ni_660x_gate_select)
1206 {
1207         unsigned i;
1208
1209         switch (ni_660x_gate_select) {
1210         case NI_660x_Source_Pin_i_Gate_Select:
1211                 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1212         case NI_660x_Gate_Pin_i_Gate_Select:
1213                 return NI_GPCT_GATE_PIN_i_GATE_SELECT;
1214         case NI_660x_Next_SRC_Gate_Select:
1215                 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1216         case NI_660x_Next_Out_Gate_Select:
1217                 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1218         case NI_660x_Logic_Low_Gate_Select:
1219                 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1220         default:
1221                 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1222                         if (ni_660x_gate_select == NI_660x_RTSI_Gate_Select(i))
1223                                 return NI_GPCT_RTSI_GATE_SELECT(i);
1224                 }
1225                 if (i <= ni_660x_max_rtsi_channel)
1226                         break;
1227                 for (i = 0; i <= ni_660x_max_gate_pin; ++i) {
1228                         if (ni_660x_gate_select ==
1229                             NI_660x_Gate_Pin_Gate_Select(i))
1230                                 return NI_GPCT_GATE_PIN_GATE_SELECT(i);
1231                 }
1232                 if (i <= ni_660x_max_gate_pin)
1233                         break;
1234                 BUG();
1235                 break;
1236         }
1237         return 0;
1238 };
1239
1240 static unsigned
1241 ni_m_series_first_gate_to_generic_gate_source(unsigned ni_m_series_gate_select)
1242 {
1243         unsigned i;
1244
1245         switch (ni_m_series_gate_select) {
1246         case NI_M_Series_Timestamp_Mux_Gate_Select:
1247                 return NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1248         case NI_M_Series_AI_START2_Gate_Select:
1249                 return NI_GPCT_AI_START2_GATE_SELECT;
1250         case NI_M_Series_PXI_Star_Trigger_Gate_Select:
1251                 return NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1252         case NI_M_Series_Next_Out_Gate_Select:
1253                 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1254         case NI_M_Series_AI_START1_Gate_Select:
1255                 return NI_GPCT_AI_START1_GATE_SELECT;
1256         case NI_M_Series_Next_SRC_Gate_Select:
1257                 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1258         case NI_M_Series_Analog_Trigger_Out_Gate_Select:
1259                 return NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1260         case NI_M_Series_Logic_Low_Gate_Select:
1261                 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1262         default:
1263                 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
1264                         if (ni_m_series_gate_select ==
1265                             NI_M_Series_RTSI_Gate_Select(i)) {
1266                                 return NI_GPCT_RTSI_GATE_SELECT(i);
1267                         }
1268                 }
1269                 if (i <= ni_m_series_max_rtsi_channel)
1270                         break;
1271                 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
1272                         if (ni_m_series_gate_select ==
1273                             NI_M_Series_PFI_Gate_Select(i)) {
1274                                 return NI_GPCT_PFI_GATE_SELECT(i);
1275                         }
1276                 }
1277                 if (i <= ni_m_series_max_pfi_channel)
1278                         break;
1279                 BUG();
1280                 break;
1281         }
1282         return 0;
1283 };
1284
1285 static unsigned
1286 ni_660x_second_gate_to_generic_gate_source(unsigned ni_660x_gate_select)
1287 {
1288         unsigned i;
1289
1290         switch (ni_660x_gate_select) {
1291         case NI_660x_Source_Pin_i_Second_Gate_Select:
1292                 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1293         case NI_660x_Up_Down_Pin_i_Second_Gate_Select:
1294                 return NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1295         case NI_660x_Next_SRC_Second_Gate_Select:
1296                 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1297         case NI_660x_Next_Out_Second_Gate_Select:
1298                 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1299         case NI_660x_Selected_Gate_Second_Gate_Select:
1300                 return NI_GPCT_SELECTED_GATE_GATE_SELECT;
1301         case NI_660x_Logic_Low_Second_Gate_Select:
1302                 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1303         default:
1304                 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1305                         if (ni_660x_gate_select ==
1306                             NI_660x_RTSI_Second_Gate_Select(i)) {
1307                                 return NI_GPCT_RTSI_GATE_SELECT(i);
1308                         }
1309                 }
1310                 if (i <= ni_660x_max_rtsi_channel)
1311                         break;
1312                 for (i = 0; i <= ni_660x_max_up_down_pin; ++i) {
1313                         if (ni_660x_gate_select ==
1314                             NI_660x_Up_Down_Pin_Second_Gate_Select(i)) {
1315                                 return NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1316                         }
1317                 }
1318                 if (i <= ni_660x_max_up_down_pin)
1319                         break;
1320                 BUG();
1321                 break;
1322         }
1323         return 0;
1324 };
1325
1326 static unsigned
1327 ni_m_series_second_gate_to_generic_gate_source(unsigned ni_m_series_gate_select)
1328 {
1329         /*
1330          * FIXME: the second gate sources for the m series are undocumented,
1331          * so we just return the raw bits for now.
1332          */
1333         switch (ni_m_series_gate_select) {
1334         default:
1335                 return ni_m_series_gate_select;
1336         }
1337         return 0;
1338 };
1339
1340 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
1341                                unsigned int *gate_source)
1342 {
1343         struct ni_gpct_device *counter_dev = counter->counter_dev;
1344         unsigned cidx = counter->counter_index;
1345         const unsigned mode_bits =
1346                 ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx));
1347         const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
1348         unsigned gate_select_bits;
1349
1350         switch (gate_index) {
1351         case 0:
1352                 if ((mode_bits & Gi_Gating_Mode_Mask) ==
1353                     Gi_Gating_Disabled_Bits) {
1354                         *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1355                         return 0;
1356                 }
1357
1358                 gate_select_bits =
1359                     (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
1360                         Gi_Gate_Select_Mask) >> Gi_Gate_Select_Shift;
1361
1362                 switch (counter_dev->variant) {
1363                 case ni_gpct_variant_e_series:
1364                 case ni_gpct_variant_m_series:
1365                 default:
1366                         *gate_source =
1367                             ni_m_series_first_gate_to_generic_gate_source
1368                             (gate_select_bits);
1369                         break;
1370                 case ni_gpct_variant_660x:
1371                         *gate_source =
1372                             ni_660x_first_gate_to_generic_gate_source
1373                             (gate_select_bits);
1374                         break;
1375                 }
1376                 if (mode_bits & Gi_Gate_Polarity_Bit)
1377                         *gate_source |= CR_INVERT;
1378                 if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
1379                         *gate_source |= CR_EDGE;
1380                 break;
1381         case 1:
1382                 if ((mode_bits & Gi_Gating_Mode_Mask) == Gi_Gating_Disabled_Bits
1383                     || (counter_dev->regs[second_gate_reg] &
1384                         Gi_Second_Gate_Mode_Bit)
1385                     == 0) {
1386                         *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1387                         return 0;
1388                 }
1389
1390                 gate_select_bits = (counter_dev->regs[second_gate_reg] &
1391                                 Gi_Second_Gate_Select_Mask) >>
1392                                 Gi_Second_Gate_Select_Shift;
1393                 switch (counter_dev->variant) {
1394                 case ni_gpct_variant_e_series:
1395                 case ni_gpct_variant_m_series:
1396                 default:
1397                         *gate_source =
1398                             ni_m_series_second_gate_to_generic_gate_source
1399                             (gate_select_bits);
1400                         break;
1401                 case ni_gpct_variant_660x:
1402                         *gate_source =
1403                             ni_660x_second_gate_to_generic_gate_source
1404                             (gate_select_bits);
1405                         break;
1406                 }
1407                 if (counter_dev->regs[second_gate_reg] &
1408                     Gi_Second_Gate_Polarity_Bit) {
1409                         *gate_source |= CR_INVERT;
1410                 }
1411                 /* second gate can't have edge/level mode set independently */
1412                 if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
1413                         *gate_source |= CR_EDGE;
1414                 break;
1415         default:
1416                 return -EINVAL;
1417         }
1418         return 0;
1419 }
1420
1421 int ni_tio_insn_config(struct comedi_device *dev,
1422                        struct comedi_subdevice *s,
1423                        struct comedi_insn *insn,
1424                        unsigned int *data)
1425 {
1426         struct ni_gpct *counter = s->private;
1427
1428         switch (data[0]) {
1429         case INSN_CONFIG_SET_COUNTER_MODE:
1430                 return ni_tio_set_counter_mode(counter, data[1]);
1431         case INSN_CONFIG_ARM:
1432                 return ni_tio_arm(counter, 1, data[1]);
1433         case INSN_CONFIG_DISARM:
1434                 ni_tio_arm(counter, 0, 0);
1435                 return 0;
1436         case INSN_CONFIG_GET_COUNTER_STATUS:
1437                 data[1] = ni_tio_counter_status(counter);
1438                 data[2] = counter_status_mask;
1439                 return 0;
1440         case INSN_CONFIG_SET_CLOCK_SRC:
1441                 return ni_tio_set_clock_src(counter, data[1], data[2]);
1442         case INSN_CONFIG_GET_CLOCK_SRC:
1443                 ni_tio_get_clock_src(counter, &data[1], &data[2]);
1444                 return 0;
1445         case INSN_CONFIG_SET_GATE_SRC:
1446                 return ni_tio_set_gate_src(counter, data[1], data[2]);
1447         case INSN_CONFIG_GET_GATE_SRC:
1448                 return ni_tio_get_gate_src(counter, data[1], &data[2]);
1449         case INSN_CONFIG_SET_OTHER_SRC:
1450                 return ni_tio_set_other_src(counter, data[1], data[2]);
1451         case INSN_CONFIG_RESET:
1452                 ni_tio_reset_count_and_disarm(counter);
1453                 return 0;
1454         default:
1455                 break;
1456         }
1457         return -EINVAL;
1458 }
1459 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1460
1461 static unsigned int ni_tio_read_sw_save_reg(struct comedi_device *dev,
1462                                             struct comedi_subdevice *s)
1463 {
1464         struct ni_gpct *counter = s->private;
1465         unsigned cidx = counter->counter_index;
1466         unsigned int first_read;
1467         unsigned int second_read;
1468         unsigned int correct_read;
1469
1470         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), Gi_Save_Trace_Bit, 0);
1471         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1472                         Gi_Save_Trace_Bit, Gi_Save_Trace_Bit);
1473
1474         /*
1475          * The count doesn't get latched until the next clock edge, so it is
1476          * possible the count may change (once) while we are reading. Since
1477          * the read of the SW_Save_Reg isn't atomic (apparently even when it's
1478          * a 32 bit register according to 660x docs), we need to read twice
1479          * and make sure the reading hasn't changed. If it has, a third read
1480          * will be correct since the count value will definitely have latched
1481          * by then.
1482          */
1483         first_read = read_register(counter, NITIO_SW_SAVE_REG(cidx));
1484         second_read = read_register(counter, NITIO_SW_SAVE_REG(cidx));
1485         if (first_read != second_read)
1486                 correct_read = read_register(counter, NITIO_SW_SAVE_REG(cidx));
1487         else
1488                 correct_read = first_read;
1489
1490         return correct_read;
1491 }
1492
1493 int ni_tio_insn_read(struct comedi_device *dev,
1494                      struct comedi_subdevice *s,
1495                      struct comedi_insn *insn,
1496                      unsigned int *data)
1497 {
1498         struct ni_gpct *counter = s->private;
1499         struct ni_gpct_device *counter_dev = counter->counter_dev;
1500         unsigned int channel = CR_CHAN(insn->chanspec);
1501         unsigned cidx = counter->counter_index;
1502         int i;
1503
1504         for (i = 0; i < insn->n; i++) {
1505                 switch (channel) {
1506                 case 0:
1507                         data[i] = ni_tio_read_sw_save_reg(dev, s);
1508                         break;
1509                 case 1:
1510                         data[i] = counter_dev->regs[NITIO_LOADA_REG(cidx)];
1511                         break;
1512                 case 2:
1513                         data[i] = counter_dev->regs[NITIO_LOADB_REG(cidx)];
1514                         break;
1515                 }
1516         }
1517         return insn->n;
1518 }
1519 EXPORT_SYMBOL_GPL(ni_tio_insn_read);
1520
1521 static unsigned ni_tio_next_load_register(struct ni_gpct *counter)
1522 {
1523         unsigned cidx = counter->counter_index;
1524         const unsigned bits =
1525                 read_register(counter, NITIO_SHARED_STATUS_REG(cidx));
1526
1527         return (bits & Gi_Next_Load_Source_Bit(cidx))
1528                         ? NITIO_LOADB_REG(cidx)
1529                         : NITIO_LOADA_REG(cidx);
1530 }
1531
1532 int ni_tio_insn_write(struct comedi_device *dev,
1533                       struct comedi_subdevice *s,
1534                       struct comedi_insn *insn,
1535                       unsigned int *data)
1536 {
1537         struct ni_gpct *counter = s->private;
1538         struct ni_gpct_device *counter_dev = counter->counter_dev;
1539         const unsigned channel = CR_CHAN(insn->chanspec);
1540         unsigned cidx = counter->counter_index;
1541         unsigned load_reg;
1542
1543         if (insn->n < 1)
1544                 return 0;
1545         switch (channel) {
1546         case 0:
1547                 /*
1548                  * Unsafe if counter is armed.
1549                  * Should probably check status and return -EBUSY if armed.
1550                  */
1551
1552                 /*
1553                  * Don't disturb load source select, just use whichever
1554                  * load register is already selected.
1555                  */
1556                 load_reg = ni_tio_next_load_register(counter);
1557                 write_register(counter, data[0], load_reg);
1558                 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
1559                                           0, 0, Gi_Load_Bit);
1560                 /* restore load reg */
1561                 write_register(counter, counter_dev->regs[load_reg], load_reg);
1562                 break;
1563         case 1:
1564                 counter_dev->regs[NITIO_LOADA_REG(cidx)] = data[0];
1565                 write_register(counter, data[0], NITIO_LOADA_REG(cidx));
1566                 break;
1567         case 2:
1568                 counter_dev->regs[NITIO_LOADB_REG(cidx)] = data[0];
1569                 write_register(counter, data[0], NITIO_LOADB_REG(cidx));
1570                 break;
1571         default:
1572                 return -EINVAL;
1573         }
1574         return 0;
1575 }
1576 EXPORT_SYMBOL_GPL(ni_tio_insn_write);
1577
1578 static int __init ni_tio_init_module(void)
1579 {
1580         return 0;
1581 }
1582 module_init(ni_tio_init_module);
1583
1584 static void __exit ni_tio_cleanup_module(void)
1585 {
1586 }
1587 module_exit(ni_tio_cleanup_module);
1588
1589 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
1590 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
1591 MODULE_LICENSE("GPL");