drivers/staging/comedi/drivers/ni_tio.c

   1 /*
   2   comedi/drivers/ni_tio.c
   3   Support for NI general purpose counters
   4
   5   Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   6
   7   This program is free software; you can redistribute it and/or modify
   8   it under the terms of the GNU General Public License as published by
   9   the Free Software Foundation; either version 2 of the License, or
  10   (at your option) any later version.
  11
  12   This program is distributed in the hope that it will be useful,
  13   but WITHOUT ANY WARRANTY; without even the implied warranty of
  14   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15   GNU General Public License for more details.
  16 */
  17
  18 /*
  19 Driver: ni_tio
  20 Description: National Instruments general purpose counters
  21 Devices:
  22 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  23         Herman.Bruyninckx@mech.kuleuven.ac.be,
  24         Wim.Meeussen@mech.kuleuven.ac.be,
  25         Klaas.Gadeyne@mech.kuleuven.ac.be,
  26         Frank Mori Hess <fmhess@users.sourceforge.net>
  27 Updated: Thu Nov 16 09:50:32 EST 2006
  28 Status: works
  29
  30 This module is not used directly by end-users.  Rather, it
  31 is used by other drivers (for example ni_660x and ni_pcimio)
  32 to provide support for NI's general purpose counters.  It was
  33 originally based on the counter code from ni_660x.c and
  34 ni_mio_common.c.
  35
  36 References:
  37 DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  38 DAQ 6601/6602 User Manual (NI 322137B-01)
  39 340934b.pdf  DAQ-STC reference manual
  40
  41 */
  42 /*
  43 TODO:
  44         Support use of both banks X and Y
  45 */
  46
  47 #include <linux/module.h>
  48 #include <linux/slab.h>
  49
  50 #include "ni_tio_internal.h"
  51
  52 /*
  53  * clock sources for ni e and m series boards,
  54  * get bits with Gi_Source_Select_Bits()
  55  */
  56 #define NI_M_TIMEBASE_1_CLK             0x0     /* 20MHz */
  57 #define NI_M_PFI_CLK(x)                 (((x) < 10) ? (1 + (x)) : (0xb + (x)))
  58 #define NI_M_RTSI_CLK(x)                (((x) == 7) ? 0x1b : (0xb + (x)))
  59 #define NI_M_TIMEBASE_2_CLK             0x12    /* 100KHz */
  60 #define NI_M_NEXT_TC_CLK                0x13
  61 #define NI_M_NEXT_GATE_CLK              0x14    /* Gi_Src_SubSelect=0 */
  62 #define NI_M_PXI_STAR_TRIGGER_CLK       0x14    /* Gi_Src_SubSelect=1 */
  63 #define NI_M_PXI10_CLK                  0x1d
  64 #define NI_M_TIMEBASE_3_CLK             0x1e    /* 80MHz, Gi_Src_SubSelect=0 */
  65 #define NI_M_ANALOG_TRIGGER_OUT_CLK     0x1e    /* Gi_Src_SubSelect=1 */
  66 #define NI_M_LOGIC_LOW_CLK              0x1f
  67 #define NI_M_MAX_PFI_CHAN               15
  68 #define NI_M_MAX_RTSI_CHAN              7
  69
  70 /*
  71  * clock sources for ni_660x boards,
  72  * get bits with Gi_Source_Select_Bits()
  73  */
  74 #define NI_660X_TIMEBASE_1_CLK          0x0     /* 20MHz */
  75 #define NI_660X_SRC_PIN_I_CLK           0x1
  76 #define NI_660X_SRC_PIN_CLK(x)          (0x2 + (x))
  77 #define NI_660X_NEXT_GATE_CLK           0xa
  78 #define NI_660X_RTSI_CLK(x)             (0xb + (x))
  79 #define NI_660X_TIMEBASE_2_CLK          0x12    /* 100KHz */
  80 #define NI_660X_NEXT_TC_CLK             0x13
  81 #define NI_660X_TIMEBASE_3_CLK          0x1e    /* 80MHz */
  82 #define NI_660X_LOGIC_LOW_CLK           0x1f
  83 #define NI_660X_MAX_SRC_PIN             7
  84 #define NI_660X_MAX_RTSI_CHAN           6
  85
  86 /* ni m series gate_select */
  87 #define NI_M_TIMESTAMP_MUX_GATE_SEL     0x0
  88 #define NI_M_PFI_GATE_SEL(x)            (((x) < 10) ? (1 + (x)) : (0xb + (x)))
  89 #define NI_M_RTSI_GATE_SEL(x)           (((x) == 7) ? 0x1b : (0xb + (x)))
  90 #define NI_M_AI_START2_GATE_SEL         0x12
  91 #define NI_M_PXI_STAR_TRIGGER_GATE_SEL  0x13
  92 #define NI_M_NEXT_OUT_GATE_SEL          0x14
  93 #define NI_M_AI_START1_GATE_SEL         0x1c
  94 #define NI_M_NEXT_SRC_GATE_SEL          0x1d
  95 #define NI_M_ANALOG_TRIG_OUT_GATE_SEL   0x1e
  96 #define NI_M_LOGIC_LOW_GATE_SEL         0x1f
  97
  98 /* ni_660x gate select */
  99 #define NI_660X_SRC_PIN_I_GATE_SEL      0x0
 100 #define NI_660X_GATE_PIN_I_GATE_SEL     0x1
 101 #define NI_660X_PIN_GATE_SEL(x)         (0x2 + (x))
 102 #define NI_660X_NEXT_SRC_GATE_SEL       0xa
 103 #define NI_660X_RTSI_GATE_SEL(x)        (0xb + (x))
 104 #define NI_660X_NEXT_OUT_GATE_SEL       0x14
 105 #define NI_660X_LOGIC_LOW_GATE_SEL      0x1f
 106 #define NI_660X_MAX_GATE_PIN            7
 107
 108 /* ni_660x second gate select */
 109 #define NI_660X_SRC_PIN_I_GATE2_SEL     0x0
 110 #define NI_660X_UD_PIN_I_GATE2_SEL      0x1
 111 #define NI_660X_UD_PIN_GATE2_SEL(x)     (0x2 + (x))
 112 #define NI_660X_NEXT_SRC_GATE2_SEL      0xa
 113 #define NI_660X_RTSI_GATE2_SEL(x)       (0xb + (x))
 114 #define NI_660X_NEXT_OUT_GATE2_SEL      0x14
 115 #define NI_660X_SELECTED_GATE2_SEL      0x1e
 116 #define NI_660X_LOGIC_LOW_GATE2_SEL     0x1f
 117 #define NI_660X_MAX_UP_DOWN_PIN         7
 118
 119 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
 120                                        unsigned generic_clock_source);
 121 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter);
 122
 123 static inline enum Gi_Counting_Mode_Reg_Bits
 124 Gi_Alternate_Sync_Bit(enum ni_gpct_variant variant)
 125 {
 126         switch (variant) {
 127         case ni_gpct_variant_e_series:
 128         default:
 129                 return 0;
 130         case ni_gpct_variant_m_series:
 131                 return Gi_M_Series_Alternate_Sync_Bit;
 132         case ni_gpct_variant_660x:
 133                 return Gi_660x_Alternate_Sync_Bit;
 134         }
 135 }
 136
 137 static inline enum Gi_Counting_Mode_Reg_Bits
 138 Gi_Prescale_X2_Bit(enum ni_gpct_variant variant)
 139 {
 140         switch (variant) {
 141         case ni_gpct_variant_e_series:
 142         default:
 143                 return 0;
 144         case ni_gpct_variant_m_series:
 145                 return Gi_M_Series_Prescale_X2_Bit;
 146         case ni_gpct_variant_660x:
 147                 return Gi_660x_Prescale_X2_Bit;
 148         }
 149 }
 150
 151 static inline enum Gi_Counting_Mode_Reg_Bits
 152 Gi_Prescale_X8_Bit(enum ni_gpct_variant variant)
 153 {
 154         switch (variant) {
 155         case ni_gpct_variant_e_series:
 156         default:
 157                 return 0;
 158         case ni_gpct_variant_m_series:
 159                 return Gi_M_Series_Prescale_X8_Bit;
 160         case ni_gpct_variant_660x:
 161                 return Gi_660x_Prescale_X8_Bit;
 162         }
 163 }
 164
 165 static inline enum Gi_Counting_Mode_Reg_Bits
 166 Gi_HW_Arm_Select_Mask(enum ni_gpct_variant variant)
 167 {
 168         switch (variant) {
 169         case ni_gpct_variant_e_series:
 170         default:
 171                 return 0;
 172         case ni_gpct_variant_m_series:
 173                 return Gi_M_Series_HW_Arm_Select_Mask;
 174         case ni_gpct_variant_660x:
 175                 return Gi_660x_HW_Arm_Select_Mask;
 176         }
 177 }
 178
 179 static inline unsigned Gi_Source_Select_Bits(unsigned source)
 180 {
 181         return (source << Gi_Source_Select_Shift) & Gi_Source_Select_Mask;
 182 }
 183
 184 static inline unsigned Gi_Gate_Select_Bits(unsigned gate_select)
 185 {
 186         return (gate_select << Gi_Gate_Select_Shift) & Gi_Gate_Select_Mask;
 187 }
 188
 189 static int
 190 ni_tio_second_gate_registers_present(const struct ni_gpct_device *counter_dev)
 191 {
 192         switch (counter_dev->variant) {
 193         case ni_gpct_variant_e_series:
 194         default:
 195                 return 0;
 196         case ni_gpct_variant_m_series:
 197         case ni_gpct_variant_660x:
 198                 return 1;
 199         }
 200 }
 201
 202 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
 203 {
 204         unsigned cidx = counter->counter_index;
 205
 206         write_register(counter, Gi_Reset_Bit(cidx), NITIO_RESET_REG(cidx));
 207 }
 208
 209 static unsigned int ni_tio_counter_status(struct ni_gpct *counter)
 210 {
 211         unsigned cidx = counter->counter_index;
 212         const unsigned bits = read_register(counter,
 213                                             NITIO_SHARED_STATUS_REG(cidx));
 214         unsigned int status = 0;
 215
 216         if (bits & Gi_Armed_Bit(cidx)) {
 217                 status |= COMEDI_COUNTER_ARMED;
 218                 if (bits & Gi_Counting_Bit(cidx))
 219                         status |= COMEDI_COUNTER_COUNTING;
 220         }
 221         return status;
 222 }
 223
 224 static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync)
 225 {
 226         struct ni_gpct_device *counter_dev = counter->counter_dev;
 227         unsigned cidx = counter->counter_index;
 228         const unsigned counting_mode_reg = NITIO_CNT_MODE_REG(cidx);
 229         static const uint64_t min_normal_sync_period_ps = 25000;
 230         const uint64_t clock_period_ps = ni_tio_clock_period_ps(counter,
 231                                                                 ni_tio_generic_clock_src_select
 232                                                                 (counter));
 233
 234         if (ni_tio_counting_mode_registers_present(counter_dev) == 0)
 235                 return;
 236
 237         switch (ni_tio_get_soft_copy(counter, counting_mode_reg) & Gi_Counting_Mode_Mask) {
 238         case Gi_Counting_Mode_QuadratureX1_Bits:
 239         case Gi_Counting_Mode_QuadratureX2_Bits:
 240         case Gi_Counting_Mode_QuadratureX4_Bits:
 241         case Gi_Counting_Mode_Sync_Source_Bits:
 242                 force_alt_sync = 1;
 243                 break;
 244         default:
 245                 break;
 246         }
 247         /*
 248          * It's not clear what we should do if clock_period is unknown, so we
 249          * are not using the alt sync bit in that case, but allow the caller
 250          * to decide by using the force_alt_sync parameter.
 251          */
 252         if (force_alt_sync ||
 253             (clock_period_ps && clock_period_ps < min_normal_sync_period_ps)) {
 254                 ni_tio_set_bits(counter, counting_mode_reg,
 255                                 Gi_Alternate_Sync_Bit(counter_dev->variant),
 256                                 Gi_Alternate_Sync_Bit(counter_dev->variant));
 257         } else {
 258                 ni_tio_set_bits(counter, counting_mode_reg,
 259                                 Gi_Alternate_Sync_Bit(counter_dev->variant),
 260                                 0x0);
 261         }
 262 }
 263
 264 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode)
 265 {
 266         struct ni_gpct_device *counter_dev = counter->counter_dev;
 267         unsigned cidx = counter->counter_index;
 268         unsigned mode_reg_mask;
 269         unsigned mode_reg_values;
 270         unsigned input_select_bits = 0;
 271         /* these bits map directly on to the mode register */
 272         static const unsigned mode_reg_direct_mask =
 273             NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
 274             NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
 275             NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
 276             NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
 277
 278         mode_reg_mask = mode_reg_direct_mask | Gi_Reload_Source_Switching_Bit;
 279         mode_reg_values = mode & mode_reg_direct_mask;
 280         switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
 281         case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
 282                 break;
 283         case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
 284                 mode_reg_values |= Gi_Reload_Source_Switching_Bit;
 285                 break;
 286         case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
 287                 input_select_bits |= Gi_Gate_Select_Load_Source_Bit;
 288                 mode_reg_mask |= Gi_Gating_Mode_Mask;
 289                 mode_reg_values |= Gi_Level_Gating_Bits;
 290                 break;
 291         default:
 292                 break;
 293         }
 294         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 295                         mode_reg_mask, mode_reg_values);
 296
 297         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 298                 unsigned counting_mode_bits = 0;
 299
 300                 counting_mode_bits |=
 301                     (mode >> NI_GPCT_COUNTING_MODE_SHIFT) &
 302                     Gi_Counting_Mode_Mask;
 303                 counting_mode_bits |=
 304                     ((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT) <<
 305                      Gi_Index_Phase_Bitshift) & Gi_Index_Phase_Mask;
 306                 if (mode & NI_GPCT_INDEX_ENABLE_BIT)
 307                         counting_mode_bits |= Gi_Index_Mode_Bit;
 308                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 309                                 Gi_Counting_Mode_Mask | Gi_Index_Phase_Mask |
 310                                 Gi_Index_Mode_Bit, counting_mode_bits);
 311                 ni_tio_set_sync_mode(counter, 0);
 312         }
 313
 314         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
 315                         Gi_Up_Down_Mask,
 316                         (mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT) <<
 317                         Gi_Up_Down_Shift);
 318
 319         if (mode & NI_GPCT_OR_GATE_BIT)
 320                 input_select_bits |= Gi_Or_Gate_Bit;
 321         if (mode & NI_GPCT_INVERT_OUTPUT_BIT)
 322                 input_select_bits |= Gi_Output_Polarity_Bit;
 323         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 324                         Gi_Gate_Select_Load_Source_Bit | Gi_Or_Gate_Bit |
 325                         Gi_Output_Polarity_Bit, input_select_bits);
 326
 327         return 0;
 328 }
 329
 330 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger)
 331 {
 332         struct ni_gpct_device *counter_dev = counter->counter_dev;
 333         unsigned cidx = counter->counter_index;
 334         unsigned command_transient_bits = 0;
 335
 336         if (arm) {
 337                 switch (start_trigger) {
 338                 case NI_GPCT_ARM_IMMEDIATE:
 339                         command_transient_bits |= Gi_Arm_Bit;
 340                         break;
 341                 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
 342                         command_transient_bits |= Gi_Arm_Bit | Gi_Arm_Copy_Bit;
 343                         break;
 344                 default:
 345                         break;
 346                 }
 347                 if (ni_tio_counting_mode_registers_present(counter_dev)) {
 348                         unsigned counting_mode_bits = 0;
 349
 350                         switch (start_trigger) {
 351                         case NI_GPCT_ARM_IMMEDIATE:
 352                         case NI_GPCT_ARM_PAIRED_IMMEDIATE:
 353                                 break;
 354                         default:
 355                                 if (start_trigger & NI_GPCT_ARM_UNKNOWN) {
 356                                         /*
 357                                          * pass-through the least significant
 358                                          * bits so we can figure out what
 359                                          * select later
 360                                          */
 361                                         unsigned hw_arm_select_bits =
 362                                             (start_trigger <<
 363                                              Gi_HW_Arm_Select_Shift) &
 364                                             Gi_HW_Arm_Select_Mask
 365                                             (counter_dev->variant);
 366
 367                                         counting_mode_bits |=
 368                                             Gi_HW_Arm_Enable_Bit |
 369                                             hw_arm_select_bits;
 370                                 } else {
 371                                         return -EINVAL;
 372                                 }
 373                                 break;
 374                         }
 375                         ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 376                                         Gi_HW_Arm_Select_Mask
 377                                         (counter_dev->variant) |
 378                                         Gi_HW_Arm_Enable_Bit,
 379                                         counting_mode_bits);
 380                 }
 381         } else {
 382                 command_transient_bits |= Gi_Disarm_Bit;
 383         }
 384         ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
 385                                   0, 0, command_transient_bits);
 386         return 0;
 387 }
 388 EXPORT_SYMBOL_GPL(ni_tio_arm);
 389
 390 static unsigned ni_660x_source_select_bits(unsigned int clock_source)
 391 {
 392         unsigned ni_660x_clock;
 393         unsigned i;
 394         const unsigned clock_select_bits =
 395             clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 396
 397         switch (clock_select_bits) {
 398         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 399                 ni_660x_clock = NI_660X_TIMEBASE_1_CLK;
 400                 break;
 401         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 402                 ni_660x_clock = NI_660X_TIMEBASE_2_CLK;
 403                 break;
 404         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 405                 ni_660x_clock = NI_660X_TIMEBASE_3_CLK;
 406                 break;
 407         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 408                 ni_660x_clock = NI_660X_LOGIC_LOW_CLK;
 409                 break;
 410         case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
 411                 ni_660x_clock = NI_660X_SRC_PIN_I_CLK;
 412                 break;
 413         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 414                 ni_660x_clock = NI_660X_NEXT_GATE_CLK;
 415                 break;
 416         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 417                 ni_660x_clock = NI_660X_NEXT_TC_CLK;
 418                 break;
 419         default:
 420                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 421                         if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 422                                 ni_660x_clock = NI_660X_RTSI_CLK(i);
 423                                 break;
 424                         }
 425                 }
 426                 if (i <= NI_660X_MAX_RTSI_CHAN)
 427                         break;
 428                 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
 429                         if (clock_select_bits ==
 430                             NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
 431                                 ni_660x_clock = NI_660X_SRC_PIN_CLK(i);
 432                                 break;
 433                         }
 434                 }
 435                 if (i <= NI_660X_MAX_SRC_PIN)
 436                         break;
 437                 ni_660x_clock = 0;
 438                 BUG();
 439                 break;
 440         }
 441         return Gi_Source_Select_Bits(ni_660x_clock);
 442 }
 443
 444 static unsigned ni_m_series_source_select_bits(unsigned int clock_source)
 445 {
 446         unsigned ni_m_series_clock;
 447         unsigned i;
 448         const unsigned clock_select_bits =
 449             clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 450         switch (clock_select_bits) {
 451         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 452                 ni_m_series_clock = NI_M_TIMEBASE_1_CLK;
 453                 break;
 454         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 455                 ni_m_series_clock = NI_M_TIMEBASE_2_CLK;
 456                 break;
 457         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 458                 ni_m_series_clock = NI_M_TIMEBASE_3_CLK;
 459                 break;
 460         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 461                 ni_m_series_clock = NI_M_LOGIC_LOW_CLK;
 462                 break;
 463         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 464                 ni_m_series_clock = NI_M_NEXT_GATE_CLK;
 465                 break;
 466         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 467                 ni_m_series_clock = NI_M_NEXT_TC_CLK;
 468                 break;
 469         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 470                 ni_m_series_clock = NI_M_PXI10_CLK;
 471                 break;
 472         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 473                 ni_m_series_clock = NI_M_PXI_STAR_TRIGGER_CLK;
 474                 break;
 475         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 476                 ni_m_series_clock = NI_M_ANALOG_TRIGGER_OUT_CLK;
 477                 break;
 478         default:
 479                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 480                         if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 481                                 ni_m_series_clock = NI_M_RTSI_CLK(i);
 482                                 break;
 483                         }
 484                 }
 485                 if (i <= NI_M_MAX_RTSI_CHAN)
 486                         break;
 487                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 488                         if (clock_select_bits == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
 489                                 ni_m_series_clock = NI_M_PFI_CLK(i);
 490                                 break;
 491                         }
 492                 }
 493                 if (i <= NI_M_MAX_PFI_CHAN)
 494                         break;
 495                 printk(KERN_ERR "invalid clock source 0x%lx\n",
 496                        (unsigned long)clock_source);
 497                 BUG();
 498                 ni_m_series_clock = 0;
 499                 break;
 500         }
 501         return Gi_Source_Select_Bits(ni_m_series_clock);
 502 };
 503
 504 static void ni_tio_set_source_subselect(struct ni_gpct *counter,
 505                                         unsigned int clock_source)
 506 {
 507         struct ni_gpct_device *counter_dev = counter->counter_dev;
 508         unsigned cidx = counter->counter_index;
 509         const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
 510
 511         if (counter_dev->variant != ni_gpct_variant_m_series)
 512                 return;
 513         switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 514                 /* Gi_Source_Subselect is zero */
 515         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 516         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 517                 counter_dev->regs[second_gate_reg] &= ~Gi_Source_Subselect_Bit;
 518                 break;
 519                 /* Gi_Source_Subselect is one */
 520         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 521         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 522                 counter_dev->regs[second_gate_reg] |= Gi_Source_Subselect_Bit;
 523                 break;
 524                 /* Gi_Source_Subselect doesn't matter */
 525         default:
 526                 return;
 527         }
 528         write_register(counter, counter_dev->regs[second_gate_reg],
 529                        second_gate_reg);
 530 }
 531
 532 static int ni_tio_set_clock_src(struct ni_gpct *counter,
 533                                 unsigned int clock_source,
 534                                 unsigned int period_ns)
 535 {
 536         struct ni_gpct_device *counter_dev = counter->counter_dev;
 537         unsigned cidx = counter->counter_index;
 538         unsigned input_select_bits = 0;
 539         static const uint64_t pico_per_nano = 1000;
 540
 541 /*FIXME: validate clock source */
 542         switch (counter_dev->variant) {
 543         case ni_gpct_variant_660x:
 544                 input_select_bits |= ni_660x_source_select_bits(clock_source);
 545                 break;
 546         case ni_gpct_variant_e_series:
 547         case ni_gpct_variant_m_series:
 548         default:
 549                 input_select_bits |=
 550                     ni_m_series_source_select_bits(clock_source);
 551                 break;
 552         }
 553         if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
 554                 input_select_bits |= Gi_Source_Polarity_Bit;
 555         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 556                         Gi_Source_Select_Mask | Gi_Source_Polarity_Bit,
 557                         input_select_bits);
 558         ni_tio_set_source_subselect(counter, clock_source);
 559         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 560                 const unsigned prescaling_mode =
 561                     clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK;
 562                 unsigned counting_mode_bits = 0;
 563
 564                 switch (prescaling_mode) {
 565                 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 566                         break;
 567                 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 568                         counting_mode_bits |=
 569                             Gi_Prescale_X2_Bit(counter_dev->variant);
 570                         break;
 571                 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 572                         counting_mode_bits |=
 573                             Gi_Prescale_X8_Bit(counter_dev->variant);
 574                         break;
 575                 default:
 576                         return -EINVAL;
 577                 }
 578                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 579                                 Gi_Prescale_X2_Bit(counter_dev->variant) |
 580                                 Gi_Prescale_X8_Bit(counter_dev->variant),
 581                                 counting_mode_bits);
 582         }
 583         counter->clock_period_ps = pico_per_nano * period_ns;
 584         ni_tio_set_sync_mode(counter, 0);
 585         return 0;
 586 }
 587
 588 static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
 589 {
 590         struct ni_gpct_device *counter_dev = counter->counter_dev;
 591         unsigned cidx = counter->counter_index;
 592         const unsigned counting_mode_bits =
 593                 ni_tio_get_soft_copy(counter, NITIO_CNT_MODE_REG(cidx));
 594         unsigned bits = 0;
 595
 596         if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
 597             Gi_Source_Polarity_Bit)
 598                 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
 599         if (counting_mode_bits & Gi_Prescale_X2_Bit(counter_dev->variant))
 600                 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
 601         if (counting_mode_bits & Gi_Prescale_X8_Bit(counter_dev->variant))
 602                 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
 603         return bits;
 604 }
 605
 606 static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter)
 607 {
 608         struct ni_gpct_device *counter_dev = counter->counter_dev;
 609         unsigned cidx = counter->counter_index;
 610         const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
 611         unsigned clock_source = 0;
 612         unsigned i;
 613         const unsigned input_select =
 614                 (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
 615                         Gi_Source_Select_Mask) >> Gi_Source_Select_Shift;
 616
 617         switch (input_select) {
 618         case NI_M_TIMEBASE_1_CLK:
 619                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 620                 break;
 621         case NI_M_TIMEBASE_2_CLK:
 622                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 623                 break;
 624         case NI_M_TIMEBASE_3_CLK:
 625                 if (counter_dev->regs[second_gate_reg] &
 626                     Gi_Source_Subselect_Bit)
 627                         clock_source =
 628                             NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
 629                 else
 630                         clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 631                 break;
 632         case NI_M_LOGIC_LOW_CLK:
 633                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 634                 break;
 635         case NI_M_NEXT_GATE_CLK:
 636                 if (counter_dev->regs[second_gate_reg] &
 637                     Gi_Source_Subselect_Bit)
 638                         clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
 639                 else
 640                         clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 641                 break;
 642         case NI_M_PXI10_CLK:
 643                 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
 644                 break;
 645         case NI_M_NEXT_TC_CLK:
 646                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 647                 break;
 648         default:
 649                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 650                         if (input_select == NI_M_RTSI_CLK(i)) {
 651                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 652                                 break;
 653                         }
 654                 }
 655                 if (i <= NI_M_MAX_RTSI_CHAN)
 656                         break;
 657                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 658                         if (input_select == NI_M_PFI_CLK(i)) {
 659                                 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
 660                                 break;
 661                         }
 662                 }
 663                 if (i <= NI_M_MAX_PFI_CHAN)
 664                         break;
 665                 BUG();
 666                 break;
 667         }
 668         clock_source |= ni_tio_clock_src_modifiers(counter);
 669         return clock_source;
 670 }
 671
 672 static unsigned ni_660x_clock_src_select(const struct ni_gpct *counter)
 673 {
 674         unsigned clock_source = 0;
 675         unsigned cidx = counter->counter_index;
 676         const unsigned input_select =
 677                 (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
 678                         Gi_Source_Select_Mask) >> Gi_Source_Select_Shift;
 679         unsigned i;
 680
 681         switch (input_select) {
 682         case NI_660X_TIMEBASE_1_CLK:
 683                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 684                 break;
 685         case NI_660X_TIMEBASE_2_CLK:
 686                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 687                 break;
 688         case NI_660X_TIMEBASE_3_CLK:
 689                 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 690                 break;
 691         case NI_660X_LOGIC_LOW_CLK:
 692                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 693                 break;
 694         case NI_660X_SRC_PIN_I_CLK:
 695                 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
 696                 break;
 697         case NI_660X_NEXT_GATE_CLK:
 698                 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 699                 break;
 700         case NI_660X_NEXT_TC_CLK:
 701                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 702                 break;
 703         default:
 704                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 705                         if (input_select == NI_660X_RTSI_CLK(i)) {
 706                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 707                                 break;
 708                         }
 709                 }
 710                 if (i <= NI_660X_MAX_RTSI_CHAN)
 711                         break;
 712                 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
 713                         if (input_select == NI_660X_SRC_PIN_CLK(i)) {
 714                                 clock_source =
 715                                     NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
 716                                 break;
 717                         }
 718                 }
 719                 if (i <= NI_660X_MAX_SRC_PIN)
 720                         break;
 721                 BUG();
 722                 break;
 723         }
 724         clock_source |= ni_tio_clock_src_modifiers(counter);
 725         return clock_source;
 726 }
 727
 728 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter)
 729 {
 730         switch (counter->counter_dev->variant) {
 731         case ni_gpct_variant_e_series:
 732         case ni_gpct_variant_m_series:
 733         default:
 734                 return ni_m_series_clock_src_select(counter);
 735         case ni_gpct_variant_660x:
 736                 return ni_660x_clock_src_select(counter);
 737         }
 738 }
 739
 740 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
 741                                        unsigned generic_clock_source)
 742 {
 743         uint64_t clock_period_ps;
 744
 745         switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 746         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 747                 clock_period_ps = 50000;
 748                 break;
 749         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 750                 clock_period_ps = 10000000;
 751                 break;
 752         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 753                 clock_period_ps = 12500;
 754                 break;
 755         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 756                 clock_period_ps = 100000;
 757                 break;
 758         default:
 759                 /*
 760                  * clock period is specified by user with prescaling
 761                  * already taken into account.
 762                  */
 763                 return counter->clock_period_ps;
 764         }
 765
 766         switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
 767         case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 768                 break;
 769         case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 770                 clock_period_ps *= 2;
 771                 break;
 772         case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 773                 clock_period_ps *= 8;
 774                 break;
 775         default:
 776                 BUG();
 777                 break;
 778         }
 779         return clock_period_ps;
 780 }
 781
 782 static void ni_tio_get_clock_src(struct ni_gpct *counter,
 783                                  unsigned int *clock_source,
 784                                  unsigned int *period_ns)
 785 {
 786         static const unsigned pico_per_nano = 1000;
 787         uint64_t temp64;
 788         *clock_source = ni_tio_generic_clock_src_select(counter);
 789         temp64 = ni_tio_clock_period_ps(counter, *clock_source);
 790         do_div(temp64, pico_per_nano);
 791         *period_ns = temp64;
 792 }
 793
 794 static void ni_tio_set_first_gate_modifiers(struct ni_gpct *counter,
 795                                             unsigned int gate_source)
 796 {
 797         const unsigned mode_mask = Gi_Gate_Polarity_Bit | Gi_Gating_Mode_Mask;
 798         unsigned cidx = counter->counter_index;
 799         unsigned mode_values = 0;
 800
 801         if (gate_source & CR_INVERT)
 802                 mode_values |= Gi_Gate_Polarity_Bit;
 803         if (gate_source & CR_EDGE)
 804                 mode_values |= Gi_Rising_Edge_Gating_Bits;
 805         else
 806                 mode_values |= Gi_Level_Gating_Bits;
 807         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 808                         mode_mask, mode_values);
 809 }
 810
 811 static int ni_660x_set_first_gate(struct ni_gpct *counter,
 812                                   unsigned int gate_source)
 813 {
 814         unsigned int chan = CR_CHAN(gate_source);
 815         unsigned cidx = counter->counter_index;
 816         unsigned gate_sel;
 817         unsigned i;
 818
 819         switch (chan) {
 820         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 821                 gate_sel = NI_660X_NEXT_SRC_GATE_SEL;
 822                 break;
 823         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 824         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 825         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
 826         case NI_GPCT_GATE_PIN_i_GATE_SELECT:
 827                 gate_sel = chan & 0x1f;
 828                 break;
 829         default:
 830                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 831                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 832                                 gate_sel = chan & 0x1f;
 833                                 break;
 834                         }
 835                 }
 836                 if (i <= NI_660X_MAX_RTSI_CHAN)
 837                         break;
 838                 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
 839                         if (chan == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
 840                                 gate_sel = chan & 0x1f;
 841                                 break;
 842                         }
 843                 }
 844                 if (i <= NI_660X_MAX_GATE_PIN)
 845                         break;
 846                 return -EINVAL;
 847         }
 848         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 849                         Gi_Gate_Select_Mask, Gi_Gate_Select_Bits(gate_sel));
 850         return 0;
 851 }
 852
 853 static int ni_m_series_set_first_gate(struct ni_gpct *counter,
 854                                       unsigned int gate_source)
 855 {
 856         unsigned int chan = CR_CHAN(gate_source);
 857         unsigned cidx = counter->counter_index;
 858         unsigned gate_sel;
 859         unsigned i;
 860
 861         switch (chan) {
 862         case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
 863         case NI_GPCT_AI_START2_GATE_SELECT:
 864         case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
 865         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 866         case NI_GPCT_AI_START1_GATE_SELECT:
 867         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 868         case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
 869         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 870                 gate_sel = chan & 0x1f;
 871                 break;
 872         default:
 873                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 874                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 875                                 gate_sel = chan & 0x1f;
 876                                 break;
 877                         }
 878                 }
 879                 if (i <= NI_M_MAX_RTSI_CHAN)
 880                         break;
 881                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 882                         if (chan == NI_GPCT_PFI_GATE_SELECT(i)) {
 883                                 gate_sel = chan & 0x1f;
 884                                 break;
 885                         }
 886                 }
 887                 if (i <= NI_M_MAX_PFI_CHAN)
 888                         break;
 889                 return -EINVAL;
 890         }
 891         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 892                         Gi_Gate_Select_Mask, Gi_Gate_Select_Bits(gate_sel));
 893         return 0;
 894 }
 895
 896 static int ni_660x_set_second_gate(struct ni_gpct *counter,
 897                                    unsigned int gate_source)
 898 {
 899         struct ni_gpct_device *counter_dev = counter->counter_dev;
 900         unsigned cidx = counter->counter_index;
 901         unsigned int chan = CR_CHAN(gate_source);
 902         unsigned gate2_reg = NITIO_GATE2_REG(cidx);
 903         unsigned gate2_sel;
 904         unsigned i;
 905
 906         switch (chan) {
 907         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
 908         case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
 909         case NI_GPCT_SELECTED_GATE_GATE_SELECT:
 910         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 911         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 912                 gate2_sel = chan & 0x1f;
 913                 break;
 914         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 915                 gate2_sel = NI_660X_NEXT_SRC_GATE2_SEL;
 916                 break;
 917         default:
 918                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 919                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 920                                 gate2_sel = chan & 0x1f;
 921                                 break;
 922                         }
 923                 }
 924                 if (i <= NI_660X_MAX_RTSI_CHAN)
 925                         break;
 926                 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
 927                         if (chan == NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
 928                                 gate2_sel = chan & 0x1f;
 929                                 break;
 930                         }
 931                 }
 932                 if (i <= NI_660X_MAX_UP_DOWN_PIN)
 933                         break;
 934                 return -EINVAL;
 935         }
 936         counter_dev->regs[gate2_reg] |= Gi_Second_Gate_Mode_Bit;
 937         counter_dev->regs[gate2_reg] &= ~Gi_Second_Gate_Select_Mask;
 938         counter_dev->regs[gate2_reg] |= Gi_Second_Gate_Select_Bits(gate2_sel);
 939         write_register(counter, counter_dev->regs[gate2_reg], gate2_reg);
 940         return 0;
 941 }
 942
 943 static int ni_m_series_set_second_gate(struct ni_gpct *counter,
 944                                        unsigned int gate_source)
 945 {
 946         struct ni_gpct_device *counter_dev = counter->counter_dev;
 947         unsigned cidx = counter->counter_index;
 948         const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
 949         const unsigned selected_second_gate = CR_CHAN(gate_source);
 950         /* bits of second_gate that may be meaningful to second gate register */
 951         static const unsigned selected_second_gate_mask = 0x1f;
 952         unsigned ni_m_series_second_gate_select;
 953
 954         /*
 955          * FIXME: We don't know what the m-series second gate codes are,
 956          * so we'll just pass the bits through for now.
 957          */
 958         switch (selected_second_gate) {
 959         default:
 960                 ni_m_series_second_gate_select =
 961                     selected_second_gate & selected_second_gate_mask;
 962                 break;
 963         }
 964         counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
 965         counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
 966         counter_dev->regs[second_gate_reg] |=
 967             Gi_Second_Gate_Select_Bits(ni_m_series_second_gate_select);
 968         write_register(counter, counter_dev->regs[second_gate_reg],
 969                        second_gate_reg);
 970         return 0;
 971 }
 972
 973 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
 974                         unsigned int gate_source)
 975 {
 976         struct ni_gpct_device *counter_dev = counter->counter_dev;
 977         unsigned cidx = counter->counter_index;
 978         const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
 979
 980         switch (gate_index) {
 981         case 0:
 982                 if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
 983                         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 984                                         Gi_Gating_Mode_Mask,
 985                                         Gi_Gating_Disabled_Bits);
 986                         return 0;
 987                 }
 988                 ni_tio_set_first_gate_modifiers(counter, gate_source);
 989                 switch (counter_dev->variant) {
 990                 case ni_gpct_variant_e_series:
 991                 case ni_gpct_variant_m_series:
 992                 default:
 993                         return ni_m_series_set_first_gate(counter, gate_source);
 994                 case ni_gpct_variant_660x:
 995                         return ni_660x_set_first_gate(counter, gate_source);
 996                 }
 997                 break;
 998         case 1:
 999                 if (ni_tio_second_gate_registers_present(counter_dev) == 0)
1000                         return -EINVAL;
1001                 if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
1002                         counter_dev->regs[second_gate_reg] &=
1003                             ~Gi_Second_Gate_Mode_Bit;
1004                         write_register(counter,
1005                                        counter_dev->regs[second_gate_reg],
1006                                        second_gate_reg);
1007                         return 0;
1008                 }
1009                 if (gate_source & CR_INVERT) {
1010                         counter_dev->regs[second_gate_reg] |=
1011                             Gi_Second_Gate_Polarity_Bit;
1012                 } else {
1013                         counter_dev->regs[second_gate_reg] &=
1014                             ~Gi_Second_Gate_Polarity_Bit;
1015                 }
1016                 switch (counter_dev->variant) {
1017                 case ni_gpct_variant_m_series:
1018                         return ni_m_series_set_second_gate(counter,
1019                                                            gate_source);
1020                 case ni_gpct_variant_660x:
1021                         return ni_660x_set_second_gate(counter, gate_source);
1022                 default:
1023                         BUG();
1024                         break;
1025                 }
1026                 break;
1027         default:
1028                 return -EINVAL;
1029         }
1030         return 0;
1031 }
1032 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
1033
1034 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned index,
1035                                 unsigned int source)
1036 {
1037         struct ni_gpct_device *counter_dev = counter->counter_dev;
1038         unsigned cidx = counter->counter_index;
1039
1040         if (counter_dev->variant == ni_gpct_variant_m_series) {
1041                 unsigned int abz_reg, shift, mask;
1042
1043                 abz_reg = NITIO_ABZ_REG(cidx);
1044                 switch (index) {
1045                 case NI_GPCT_SOURCE_ENCODER_A:
1046                         shift = 10;
1047                         break;
1048                 case NI_GPCT_SOURCE_ENCODER_B:
1049                         shift = 5;
1050                         break;
1051                 case NI_GPCT_SOURCE_ENCODER_Z:
1052                         shift = 0;
1053                         break;
1054                 default:
1055                         return -EINVAL;
1056                 }
1057                 mask = 0x1f << shift;
1058                 if (source > 0x1f) {
1059                         /* Disable gate */
1060                         source = 0x1f;
1061                 }
1062                 counter_dev->regs[abz_reg] &= ~mask;
1063                 counter_dev->regs[abz_reg] |= (source << shift) & mask;
1064                 write_register(counter, counter_dev->regs[abz_reg], abz_reg);
1065                 return 0;
1066         }
1067         return -EINVAL;
1068 }
1069
1070 static unsigned
1071 ni_660x_first_gate_to_generic_gate_source(unsigned ni_660x_gate_select)
1072 {
1073         unsigned i;
1074
1075         switch (ni_660x_gate_select) {
1076         case NI_660X_SRC_PIN_I_GATE_SEL:
1077                 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1078         case NI_660X_GATE_PIN_I_GATE_SEL:
1079                 return NI_GPCT_GATE_PIN_i_GATE_SELECT;
1080         case NI_660X_NEXT_SRC_GATE_SEL:
1081                 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1082         case NI_660X_NEXT_OUT_GATE_SEL:
1083                 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1084         case NI_660X_LOGIC_LOW_GATE_SEL:
1085                 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1086         default:
1087                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1088                         if (ni_660x_gate_select == NI_660X_RTSI_GATE_SEL(i))
1089                                 return NI_GPCT_RTSI_GATE_SELECT(i);
1090                 }
1091                 if (i <= NI_660X_MAX_RTSI_CHAN)
1092                         break;
1093                 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
1094                         if (ni_660x_gate_select == NI_660X_PIN_GATE_SEL(i))
1095                                 return NI_GPCT_GATE_PIN_GATE_SELECT(i);
1096                 }
1097                 if (i <= NI_660X_MAX_GATE_PIN)
1098                         break;
1099                 BUG();
1100                 break;
1101         }
1102         return 0;
1103 };
1104
1105 static unsigned
1106 ni_m_series_first_gate_to_generic_gate_source(unsigned ni_m_series_gate_select)
1107 {
1108         unsigned i;
1109
1110         switch (ni_m_series_gate_select) {
1111         case NI_M_TIMESTAMP_MUX_GATE_SEL:
1112                 return NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1113         case NI_M_AI_START2_GATE_SEL:
1114                 return NI_GPCT_AI_START2_GATE_SELECT;
1115         case NI_M_PXI_STAR_TRIGGER_GATE_SEL:
1116                 return NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1117         case NI_M_NEXT_OUT_GATE_SEL:
1118                 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1119         case NI_M_AI_START1_GATE_SEL:
1120                 return NI_GPCT_AI_START1_GATE_SELECT;
1121         case NI_M_NEXT_SRC_GATE_SEL:
1122                 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1123         case NI_M_ANALOG_TRIG_OUT_GATE_SEL:
1124                 return NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1125         case NI_M_LOGIC_LOW_GATE_SEL:
1126                 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1127         default:
1128                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
1129                         if (ni_m_series_gate_select == NI_M_RTSI_GATE_SEL(i))
1130                                 return NI_GPCT_RTSI_GATE_SELECT(i);
1131                 }
1132                 if (i <= NI_M_MAX_RTSI_CHAN)
1133                         break;
1134                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
1135                         if (ni_m_series_gate_select == NI_M_PFI_GATE_SEL(i))
1136                                 return NI_GPCT_PFI_GATE_SELECT(i);
1137                 }
1138                 if (i <= NI_M_MAX_PFI_CHAN)
1139                         break;
1140                 BUG();
1141                 break;
1142         }
1143         return 0;
1144 };
1145
1146 static unsigned
1147 ni_660x_second_gate_to_generic_gate_source(unsigned ni_660x_gate_select)
1148 {
1149         unsigned i;
1150
1151         switch (ni_660x_gate_select) {
1152         case NI_660X_SRC_PIN_I_GATE2_SEL:
1153                 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1154         case NI_660X_UD_PIN_I_GATE2_SEL:
1155                 return NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1156         case NI_660X_NEXT_SRC_GATE2_SEL:
1157                 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1158         case NI_660X_NEXT_OUT_GATE2_SEL:
1159                 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1160         case NI_660X_SELECTED_GATE2_SEL:
1161                 return NI_GPCT_SELECTED_GATE_GATE_SELECT;
1162         case NI_660X_LOGIC_LOW_GATE2_SEL:
1163                 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1164         default:
1165                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1166                         if (ni_660x_gate_select == NI_660X_RTSI_GATE2_SEL(i))
1167                                 return NI_GPCT_RTSI_GATE_SELECT(i);
1168                 }
1169                 if (i <= NI_660X_MAX_RTSI_CHAN)
1170                         break;
1171                 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
1172                         if (ni_660x_gate_select == NI_660X_UD_PIN_GATE2_SEL(i))
1173                                 return NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1174                 }
1175                 if (i <= NI_660X_MAX_UP_DOWN_PIN)
1176                         break;
1177                 BUG();
1178                 break;
1179         }
1180         return 0;
1181 };
1182
1183 static unsigned
1184 ni_m_series_second_gate_to_generic_gate_source(unsigned ni_m_series_gate_select)
1185 {
1186         /*
1187          * FIXME: the second gate sources for the m series are undocumented,
1188          * so we just return the raw bits for now.
1189          */
1190         switch (ni_m_series_gate_select) {
1191         default:
1192                 return ni_m_series_gate_select;
1193         }
1194         return 0;
1195 };
1196
1197 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
1198                                unsigned int *gate_source)
1199 {
1200         struct ni_gpct_device *counter_dev = counter->counter_dev;
1201         unsigned cidx = counter->counter_index;
1202         const unsigned mode_bits =
1203                 ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx));
1204         const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
1205         unsigned gate_select_bits;
1206
1207         switch (gate_index) {
1208         case 0:
1209                 if ((mode_bits & Gi_Gating_Mode_Mask) ==
1210                     Gi_Gating_Disabled_Bits) {
1211                         *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1212                         return 0;
1213                 }
1214
1215                 gate_select_bits =
1216                     (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
1217                         Gi_Gate_Select_Mask) >> Gi_Gate_Select_Shift;
1218
1219                 switch (counter_dev->variant) {
1220                 case ni_gpct_variant_e_series:
1221                 case ni_gpct_variant_m_series:
1222                 default:
1223                         *gate_source =
1224                             ni_m_series_first_gate_to_generic_gate_source
1225                             (gate_select_bits);
1226                         break;
1227                 case ni_gpct_variant_660x:
1228                         *gate_source =
1229                             ni_660x_first_gate_to_generic_gate_source
1230                             (gate_select_bits);
1231                         break;
1232                 }
1233                 if (mode_bits & Gi_Gate_Polarity_Bit)
1234                         *gate_source |= CR_INVERT;
1235                 if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
1236                         *gate_source |= CR_EDGE;
1237                 break;
1238         case 1:
1239                 if ((mode_bits & Gi_Gating_Mode_Mask) == Gi_Gating_Disabled_Bits
1240                     || (counter_dev->regs[second_gate_reg] &
1241                         Gi_Second_Gate_Mode_Bit)
1242                     == 0) {
1243                         *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1244                         return 0;
1245                 }
1246
1247                 gate_select_bits = (counter_dev->regs[second_gate_reg] &
1248                                 Gi_Second_Gate_Select_Mask) >>
1249                                 Gi_Second_Gate_Select_Shift;
1250                 switch (counter_dev->variant) {
1251                 case ni_gpct_variant_e_series:
1252                 case ni_gpct_variant_m_series:
1253                 default:
1254                         *gate_source =
1255                             ni_m_series_second_gate_to_generic_gate_source
1256                             (gate_select_bits);
1257                         break;
1258                 case ni_gpct_variant_660x:
1259                         *gate_source =
1260                             ni_660x_second_gate_to_generic_gate_source
1261                             (gate_select_bits);
1262                         break;
1263                 }
1264                 if (counter_dev->regs[second_gate_reg] &
1265                     Gi_Second_Gate_Polarity_Bit) {
1266                         *gate_source |= CR_INVERT;
1267                 }
1268                 /* second gate can't have edge/level mode set independently */
1269                 if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
1270                         *gate_source |= CR_EDGE;
1271                 break;
1272         default:
1273                 return -EINVAL;
1274         }
1275         return 0;
1276 }
1277
1278 int ni_tio_insn_config(struct comedi_device *dev,
1279                        struct comedi_subdevice *s,
1280                        struct comedi_insn *insn,
1281                        unsigned int *data)
1282 {
1283         struct ni_gpct *counter = s->private;
1284
1285         switch (data[0]) {
1286         case INSN_CONFIG_SET_COUNTER_MODE:
1287                 return ni_tio_set_counter_mode(counter, data[1]);
1288         case INSN_CONFIG_ARM:
1289                 return ni_tio_arm(counter, 1, data[1]);
1290         case INSN_CONFIG_DISARM:
1291                 ni_tio_arm(counter, 0, 0);
1292                 return 0;
1293         case INSN_CONFIG_GET_COUNTER_STATUS:
1294                 data[1] = ni_tio_counter_status(counter);
1295                 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
1296                 return 0;
1297         case INSN_CONFIG_SET_CLOCK_SRC:
1298                 return ni_tio_set_clock_src(counter, data[1], data[2]);
1299         case INSN_CONFIG_GET_CLOCK_SRC:
1300                 ni_tio_get_clock_src(counter, &data[1], &data[2]);
1301                 return 0;
1302         case INSN_CONFIG_SET_GATE_SRC:
1303                 return ni_tio_set_gate_src(counter, data[1], data[2]);
1304         case INSN_CONFIG_GET_GATE_SRC:
1305                 return ni_tio_get_gate_src(counter, data[1], &data[2]);
1306         case INSN_CONFIG_SET_OTHER_SRC:
1307                 return ni_tio_set_other_src(counter, data[1], data[2]);
1308         case INSN_CONFIG_RESET:
1309                 ni_tio_reset_count_and_disarm(counter);
1310                 return 0;
1311         default:
1312                 break;
1313         }
1314         return -EINVAL;
1315 }
1316 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1317
1318 static unsigned int ni_tio_read_sw_save_reg(struct comedi_device *dev,
1319                                             struct comedi_subdevice *s)
1320 {
1321         struct ni_gpct *counter = s->private;
1322         unsigned cidx = counter->counter_index;
1323         unsigned int first_read;
1324         unsigned int second_read;
1325         unsigned int correct_read;
1326
1327         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), Gi_Save_Trace_Bit, 0);
1328         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1329                         Gi_Save_Trace_Bit, Gi_Save_Trace_Bit);
1330
1331         /*
1332          * The count doesn't get latched until the next clock edge, so it is
1333          * possible the count may change (once) while we are reading. Since
1334          * the read of the SW_Save_Reg isn't atomic (apparently even when it's
1335          * a 32 bit register according to 660x docs), we need to read twice
1336          * and make sure the reading hasn't changed. If it has, a third read
1337          * will be correct since the count value will definitely have latched
1338          * by then.
1339          */
1340         first_read = read_register(counter, NITIO_SW_SAVE_REG(cidx));
1341         second_read = read_register(counter, NITIO_SW_SAVE_REG(cidx));
1342         if (first_read != second_read)
1343                 correct_read = read_register(counter, NITIO_SW_SAVE_REG(cidx));
1344         else
1345                 correct_read = first_read;
1346
1347         return correct_read;
1348 }
1349
1350 int ni_tio_insn_read(struct comedi_device *dev,
1351                      struct comedi_subdevice *s,
1352                      struct comedi_insn *insn,
1353                      unsigned int *data)
1354 {
1355         struct ni_gpct *counter = s->private;
1356         struct ni_gpct_device *counter_dev = counter->counter_dev;
1357         unsigned int channel = CR_CHAN(insn->chanspec);
1358         unsigned cidx = counter->counter_index;
1359         int i;
1360
1361         for (i = 0; i < insn->n; i++) {
1362                 switch (channel) {
1363                 case 0:
1364                         data[i] = ni_tio_read_sw_save_reg(dev, s);
1365                         break;
1366                 case 1:
1367                         data[i] = counter_dev->regs[NITIO_LOADA_REG(cidx)];
1368                         break;
1369                 case 2:
1370                         data[i] = counter_dev->regs[NITIO_LOADB_REG(cidx)];
1371                         break;
1372                 }
1373         }
1374         return insn->n;
1375 }
1376 EXPORT_SYMBOL_GPL(ni_tio_insn_read);
1377
1378 static unsigned ni_tio_next_load_register(struct ni_gpct *counter)
1379 {
1380         unsigned cidx = counter->counter_index;
1381         const unsigned bits =
1382                 read_register(counter, NITIO_SHARED_STATUS_REG(cidx));
1383
1384         return (bits & Gi_Next_Load_Source_Bit(cidx))
1385                         ? NITIO_LOADB_REG(cidx)
1386                         : NITIO_LOADA_REG(cidx);
1387 }
1388
1389 int ni_tio_insn_write(struct comedi_device *dev,
1390                       struct comedi_subdevice *s,
1391                       struct comedi_insn *insn,
1392                       unsigned int *data)
1393 {
1394         struct ni_gpct *counter = s->private;
1395         struct ni_gpct_device *counter_dev = counter->counter_dev;
1396         const unsigned channel = CR_CHAN(insn->chanspec);
1397         unsigned cidx = counter->counter_index;
1398         unsigned load_reg;
1399
1400         if (insn->n < 1)
1401                 return 0;
1402         switch (channel) {
1403         case 0:
1404                 /*
1405                  * Unsafe if counter is armed.
1406                  * Should probably check status and return -EBUSY if armed.
1407                  */
1408
1409                 /*
1410                  * Don't disturb load source select, just use whichever
1411                  * load register is already selected.
1412                  */
1413                 load_reg = ni_tio_next_load_register(counter);
1414                 write_register(counter, data[0], load_reg);
1415                 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
1416                                           0, 0, Gi_Load_Bit);
1417                 /* restore load reg */
1418                 write_register(counter, counter_dev->regs[load_reg], load_reg);
1419                 break;
1420         case 1:
1421                 counter_dev->regs[NITIO_LOADA_REG(cidx)] = data[0];
1422                 write_register(counter, data[0], NITIO_LOADA_REG(cidx));
1423                 break;
1424         case 2:
1425                 counter_dev->regs[NITIO_LOADB_REG(cidx)] = data[0];
1426                 write_register(counter, data[0], NITIO_LOADB_REG(cidx));
1427                 break;
1428         default:
1429                 return -EINVAL;
1430         }
1431         return 0;
1432 }
1433 EXPORT_SYMBOL_GPL(ni_tio_insn_write);
1434
1435 void ni_tio_init_counter(struct ni_gpct *counter)
1436 {
1437         struct ni_gpct_device *counter_dev = counter->counter_dev;
1438         unsigned cidx = counter->counter_index;
1439
1440         ni_tio_reset_count_and_disarm(counter);
1441
1442         /* initialize counter registers */
1443         counter_dev->regs[NITIO_AUTO_INC_REG(cidx)] = 0x0;
1444         write_register(counter, 0x0, NITIO_AUTO_INC_REG(cidx));
1445
1446         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1447                         ~0, Gi_Synchronize_Gate_Bit);
1448
1449         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ~0, 0);
1450
1451         counter_dev->regs[NITIO_LOADA_REG(cidx)] = 0x0;
1452         write_register(counter, 0x0, NITIO_LOADA_REG(cidx));
1453
1454         counter_dev->regs[NITIO_LOADB_REG(cidx)] = 0x0;
1455         write_register(counter, 0x0, NITIO_LOADB_REG(cidx));
1456
1457         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ~0, 0);
1458
1459         if (ni_tio_counting_mode_registers_present(counter_dev))
1460                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ~0, 0);
1461
1462         if (ni_tio_second_gate_registers_present(counter_dev)) {
1463                 counter_dev->regs[NITIO_GATE2_REG(cidx)] = 0x0;
1464                 write_register(counter, 0x0, NITIO_GATE2_REG(cidx));
1465         }
1466
1467         ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), ~0, 0x0);
1468
1469         ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ~0, 0x0);
1470 }
1471 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
1472
1473 struct ni_gpct_device *
1474 ni_gpct_device_construct(struct comedi_device *dev,
1475                          void (*write_register)(struct ni_gpct *counter,
1476                                                 unsigned bits,
1477                                                 enum ni_gpct_register reg),
1478                          unsigned (*read_register)(struct ni_gpct *counter,
1479                                                    enum ni_gpct_register reg),
1480                          enum ni_gpct_variant variant,
1481                          unsigned num_counters)
1482 {
1483         struct ni_gpct_device *counter_dev;
1484         struct ni_gpct *counter;
1485         unsigned i;
1486
1487         if (num_counters == 0)
1488                 return NULL;
1489
1490         counter_dev = kzalloc(sizeof(*counter_dev), GFP_KERNEL);
1491         if (!counter_dev)
1492                 return NULL;
1493
1494         counter_dev->dev = dev;
1495         counter_dev->write_register = write_register;
1496         counter_dev->read_register = read_register;
1497         counter_dev->variant = variant;
1498
1499         spin_lock_init(&counter_dev->regs_lock);
1500
1501         counter_dev->counters = kcalloc(num_counters, sizeof(*counter),
1502                                         GFP_KERNEL);
1503         if (!counter_dev->counters) {
1504                 kfree(counter_dev);
1505                 return NULL;
1506         }
1507
1508         for (i = 0; i < num_counters; ++i) {
1509                 counter = &counter_dev->counters[i];
1510                 counter->counter_dev = counter_dev;
1511                 spin_lock_init(&counter->lock);
1512         }
1513         counter_dev->num_counters = num_counters;
1514
1515         return counter_dev;
1516 }
1517 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
1518
1519 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
1520 {
1521         if (!counter_dev->counters)
1522                 return;
1523         kfree(counter_dev->counters);
1524         kfree(counter_dev);
1525 }
1526 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
1527
1528 static int __init ni_tio_init_module(void)
1529 {
1530         return 0;
1531 }
1532 module_init(ni_tio_init_module);
1533
1534 static void __exit ni_tio_cleanup_module(void)
1535 {
1536 }
1537 module_exit(ni_tio_cleanup_module);
1538
1539 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
1540 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
1541 MODULE_LICENSE("GPL");