2 comedi/drivers/ni_tio.c
3 Support for NI general purpose counters
5 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
20 Description: National Instruments general purpose counters
22 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
23 Herman.Bruyninckx@mech.kuleuven.ac.be,
24 Wim.Meeussen@mech.kuleuven.ac.be,
25 Klaas.Gadeyne@mech.kuleuven.ac.be,
26 Frank Mori Hess <fmhess@users.sourceforge.net>
27 Updated: Thu Nov 16 09:50:32 EST 2006
30 This module is not used directly by end-users. Rather, it
31 is used by other drivers (for example ni_660x and ni_pcimio)
32 to provide support for NI's general purpose counters. It was
33 originally based on the counter code from ni_660x.c and
37 DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
38 DAQ 6601/6602 User Manual (NI 322137B-01)
39 340934b.pdf DAQ-STC reference manual
44 Support use of both banks X and Y
47 #include <linux/module.h>
48 #include <linux/slab.h>
50 #include "ni_tio_internal.h"
53 * clock sources for ni e and m series boards,
54 * get bits with GI_SRC_SEL()
56 #define NI_M_TIMEBASE_1_CLK 0x0 /* 20MHz */
57 #define NI_M_PFI_CLK(x) (((x) < 10) ? (1 + (x)) : (0xb + (x)))
58 #define NI_M_RTSI_CLK(x) (((x) == 7) ? 0x1b : (0xb + (x)))
59 #define NI_M_TIMEBASE_2_CLK 0x12 /* 100KHz */
60 #define NI_M_NEXT_TC_CLK 0x13
61 #define NI_M_NEXT_GATE_CLK 0x14 /* Gi_Src_SubSelect=0 */
62 #define NI_M_PXI_STAR_TRIGGER_CLK 0x14 /* Gi_Src_SubSelect=1 */
63 #define NI_M_PXI10_CLK 0x1d
64 #define NI_M_TIMEBASE_3_CLK 0x1e /* 80MHz, Gi_Src_SubSelect=0 */
65 #define NI_M_ANALOG_TRIGGER_OUT_CLK 0x1e /* Gi_Src_SubSelect=1 */
66 #define NI_M_LOGIC_LOW_CLK 0x1f
67 #define NI_M_MAX_PFI_CHAN 15
68 #define NI_M_MAX_RTSI_CHAN 7
71 * clock sources for ni_660x boards,
72 * get bits with GI_SRC_SEL()
74 #define NI_660X_TIMEBASE_1_CLK 0x0 /* 20MHz */
75 #define NI_660X_SRC_PIN_I_CLK 0x1
76 #define NI_660X_SRC_PIN_CLK(x) (0x2 + (x))
77 #define NI_660X_NEXT_GATE_CLK 0xa
78 #define NI_660X_RTSI_CLK(x) (0xb + (x))
79 #define NI_660X_TIMEBASE_2_CLK 0x12 /* 100KHz */
80 #define NI_660X_NEXT_TC_CLK 0x13
81 #define NI_660X_TIMEBASE_3_CLK 0x1e /* 80MHz */
82 #define NI_660X_LOGIC_LOW_CLK 0x1f
83 #define NI_660X_MAX_SRC_PIN 7
84 #define NI_660X_MAX_RTSI_CHAN 6
86 /* ni m series gate_select */
87 #define NI_M_TIMESTAMP_MUX_GATE_SEL 0x0
88 #define NI_M_PFI_GATE_SEL(x) (((x) < 10) ? (1 + (x)) : (0xb + (x)))
89 #define NI_M_RTSI_GATE_SEL(x) (((x) == 7) ? 0x1b : (0xb + (x)))
90 #define NI_M_AI_START2_GATE_SEL 0x12
91 #define NI_M_PXI_STAR_TRIGGER_GATE_SEL 0x13
92 #define NI_M_NEXT_OUT_GATE_SEL 0x14
93 #define NI_M_AI_START1_GATE_SEL 0x1c
94 #define NI_M_NEXT_SRC_GATE_SEL 0x1d
95 #define NI_M_ANALOG_TRIG_OUT_GATE_SEL 0x1e
96 #define NI_M_LOGIC_LOW_GATE_SEL 0x1f
98 /* ni_660x gate select */
99 #define NI_660X_SRC_PIN_I_GATE_SEL 0x0
100 #define NI_660X_GATE_PIN_I_GATE_SEL 0x1
101 #define NI_660X_PIN_GATE_SEL(x) (0x2 + (x))
102 #define NI_660X_NEXT_SRC_GATE_SEL 0xa
103 #define NI_660X_RTSI_GATE_SEL(x) (0xb + (x))
104 #define NI_660X_NEXT_OUT_GATE_SEL 0x14
105 #define NI_660X_LOGIC_LOW_GATE_SEL 0x1f
106 #define NI_660X_MAX_GATE_PIN 7
108 /* ni_660x second gate select */
109 #define NI_660X_SRC_PIN_I_GATE2_SEL 0x0
110 #define NI_660X_UD_PIN_I_GATE2_SEL 0x1
111 #define NI_660X_UD_PIN_GATE2_SEL(x) (0x2 + (x))
112 #define NI_660X_NEXT_SRC_GATE2_SEL 0xa
113 #define NI_660X_RTSI_GATE2_SEL(x) (0xb + (x))
114 #define NI_660X_NEXT_OUT_GATE2_SEL 0x14
115 #define NI_660X_SELECTED_GATE2_SEL 0x1e
116 #define NI_660X_LOGIC_LOW_GATE2_SEL 0x1f
117 #define NI_660X_MAX_UP_DOWN_PIN 7
119 static inline unsigned GI_ALT_SYNC(enum ni_gpct_variant variant)
122 case ni_gpct_variant_e_series:
125 case ni_gpct_variant_m_series:
126 return GI_M_ALT_SYNC;
127 case ni_gpct_variant_660x:
128 return GI_660X_ALT_SYNC;
132 static inline unsigned GI_PRESCALE_X2(enum ni_gpct_variant variant)
135 case ni_gpct_variant_e_series:
138 case ni_gpct_variant_m_series:
139 return GI_M_PRESCALE_X2;
140 case ni_gpct_variant_660x:
141 return GI_660X_PRESCALE_X2;
145 static inline unsigned GI_PRESCALE_X8(enum ni_gpct_variant variant)
148 case ni_gpct_variant_e_series:
151 case ni_gpct_variant_m_series:
152 return GI_M_PRESCALE_X8;
153 case ni_gpct_variant_660x:
154 return GI_660X_PRESCALE_X8;
158 static inline unsigned GI_HW_ARM_SEL_MASK(enum ni_gpct_variant variant)
161 case ni_gpct_variant_e_series:
164 case ni_gpct_variant_m_series:
165 return GI_M_HW_ARM_SEL_MASK;
166 case ni_gpct_variant_660x:
167 return GI_660X_HW_ARM_SEL_MASK;
171 static int ni_tio_has_gate2_registers(const struct ni_gpct_device *counter_dev)
173 switch (counter_dev->variant) {
174 case ni_gpct_variant_e_series:
177 case ni_gpct_variant_m_series:
178 case ni_gpct_variant_660x:
183 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
185 unsigned cidx = counter->counter_index;
187 write_register(counter, GI_RESET(cidx), NITIO_RESET_REG(cidx));
190 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
191 unsigned generic_clock_source)
193 uint64_t clock_period_ps;
195 switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
196 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
197 clock_period_ps = 50000;
199 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
200 clock_period_ps = 10000000;
202 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
203 clock_period_ps = 12500;
205 case NI_GPCT_PXI10_CLOCK_SRC_BITS:
206 clock_period_ps = 100000;
210 * clock period is specified by user with prescaling
211 * already taken into account.
213 return counter->clock_period_ps;
216 switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
217 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
219 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
220 clock_period_ps *= 2;
222 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
223 clock_period_ps *= 8;
229 return clock_period_ps;
232 static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
234 struct ni_gpct_device *counter_dev = counter->counter_dev;
235 unsigned cidx = counter->counter_index;
236 const unsigned counting_mode_bits =
237 ni_tio_get_soft_copy(counter, NITIO_CNT_MODE_REG(cidx));
240 if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
242 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
243 if (counting_mode_bits & GI_PRESCALE_X2(counter_dev->variant))
244 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
245 if (counting_mode_bits & GI_PRESCALE_X8(counter_dev->variant))
246 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
250 static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter)
252 struct ni_gpct_device *counter_dev = counter->counter_dev;
253 unsigned cidx = counter->counter_index;
254 const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
255 unsigned clock_source = 0;
259 src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
260 NITIO_INPUT_SEL_REG(cidx)));
263 case NI_M_TIMEBASE_1_CLK:
264 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
266 case NI_M_TIMEBASE_2_CLK:
267 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
269 case NI_M_TIMEBASE_3_CLK:
270 if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL)
272 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
274 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
276 case NI_M_LOGIC_LOW_CLK:
277 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
279 case NI_M_NEXT_GATE_CLK:
280 if (counter_dev->regs[second_gate_reg] & GI_SRC_SUBSEL)
281 clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
283 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
286 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
288 case NI_M_NEXT_TC_CLK:
289 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
292 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
293 if (src == NI_M_RTSI_CLK(i)) {
294 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
298 if (i <= NI_M_MAX_RTSI_CHAN)
300 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
301 if (src == NI_M_PFI_CLK(i)) {
302 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
306 if (i <= NI_M_MAX_PFI_CHAN)
311 clock_source |= ni_tio_clock_src_modifiers(counter);
315 static unsigned ni_660x_clock_src_select(const struct ni_gpct *counter)
317 unsigned clock_source = 0;
318 unsigned cidx = counter->counter_index;
322 src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
323 NITIO_INPUT_SEL_REG(cidx)));
326 case NI_660X_TIMEBASE_1_CLK:
327 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
329 case NI_660X_TIMEBASE_2_CLK:
330 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
332 case NI_660X_TIMEBASE_3_CLK:
333 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
335 case NI_660X_LOGIC_LOW_CLK:
336 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
338 case NI_660X_SRC_PIN_I_CLK:
339 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
341 case NI_660X_NEXT_GATE_CLK:
342 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
344 case NI_660X_NEXT_TC_CLK:
345 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
348 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
349 if (src == NI_660X_RTSI_CLK(i)) {
350 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
354 if (i <= NI_660X_MAX_RTSI_CHAN)
356 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
357 if (src == NI_660X_SRC_PIN_CLK(i)) {
359 NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
363 if (i <= NI_660X_MAX_SRC_PIN)
368 clock_source |= ni_tio_clock_src_modifiers(counter);
372 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter)
374 switch (counter->counter_dev->variant) {
375 case ni_gpct_variant_e_series:
376 case ni_gpct_variant_m_series:
378 return ni_m_series_clock_src_select(counter);
379 case ni_gpct_variant_660x:
380 return ni_660x_clock_src_select(counter);
384 static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync)
386 struct ni_gpct_device *counter_dev = counter->counter_dev;
387 unsigned cidx = counter->counter_index;
388 const unsigned counting_mode_reg = NITIO_CNT_MODE_REG(cidx);
389 static const uint64_t min_normal_sync_period_ps = 25000;
391 uint64_t clock_period_ps;
393 if (ni_tio_counting_mode_registers_present(counter_dev) == 0)
396 mode = ni_tio_get_soft_copy(counter, counting_mode_reg);
397 switch (mode & GI_CNT_MODE_MASK) {
398 case GI_CNT_MODE_QUADX1:
399 case GI_CNT_MODE_QUADX2:
400 case GI_CNT_MODE_QUADX4:
401 case GI_CNT_MODE_SYNC_SRC:
408 clock_period_ps = ni_tio_clock_period_ps(counter,
409 ni_tio_generic_clock_src_select(counter));
412 * It's not clear what we should do if clock_period is unknown, so we
413 * are not using the alt sync bit in that case, but allow the caller
414 * to decide by using the force_alt_sync parameter.
416 if (force_alt_sync ||
417 (clock_period_ps && clock_period_ps < min_normal_sync_period_ps)) {
418 ni_tio_set_bits(counter, counting_mode_reg,
419 GI_ALT_SYNC(counter_dev->variant),
420 GI_ALT_SYNC(counter_dev->variant));
422 ni_tio_set_bits(counter, counting_mode_reg,
423 GI_ALT_SYNC(counter_dev->variant),
428 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode)
430 struct ni_gpct_device *counter_dev = counter->counter_dev;
431 unsigned cidx = counter->counter_index;
432 unsigned mode_reg_mask;
433 unsigned mode_reg_values;
434 unsigned input_select_bits = 0;
435 /* these bits map directly on to the mode register */
436 static const unsigned mode_reg_direct_mask =
437 NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
438 NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
439 NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
440 NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
442 mode_reg_mask = mode_reg_direct_mask | GI_RELOAD_SRC_SWITCHING;
443 mode_reg_values = mode & mode_reg_direct_mask;
444 switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
445 case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
447 case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
448 mode_reg_values |= GI_RELOAD_SRC_SWITCHING;
450 case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
451 input_select_bits |= GI_GATE_SEL_LOAD_SRC;
452 mode_reg_mask |= GI_GATING_MODE_MASK;
453 mode_reg_values |= GI_LEVEL_GATING;
458 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
459 mode_reg_mask, mode_reg_values);
461 if (ni_tio_counting_mode_registers_present(counter_dev)) {
464 bits |= GI_CNT_MODE(mode >> NI_GPCT_COUNTING_MODE_SHIFT);
465 bits |= GI_INDEX_PHASE((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT));
466 if (mode & NI_GPCT_INDEX_ENABLE_BIT)
467 bits |= GI_INDEX_MODE;
468 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
469 GI_CNT_MODE_MASK | GI_INDEX_PHASE_MASK |
470 GI_INDEX_MODE, bits);
471 ni_tio_set_sync_mode(counter, 0);
474 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_CNT_DIR_MASK,
475 GI_CNT_DIR(mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT));
477 if (mode & NI_GPCT_OR_GATE_BIT)
478 input_select_bits |= GI_OR_GATE;
479 if (mode & NI_GPCT_INVERT_OUTPUT_BIT)
480 input_select_bits |= GI_OUTPUT_POL_INVERT;
481 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
482 GI_GATE_SEL_LOAD_SRC | GI_OR_GATE |
483 GI_OUTPUT_POL_INVERT, input_select_bits);
488 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger)
490 struct ni_gpct_device *counter_dev = counter->counter_dev;
491 unsigned cidx = counter->counter_index;
492 unsigned command_transient_bits = 0;
495 switch (start_trigger) {
496 case NI_GPCT_ARM_IMMEDIATE:
497 command_transient_bits |= GI_ARM;
499 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
500 command_transient_bits |= GI_ARM | GI_ARM_COPY;
505 if (ni_tio_counting_mode_registers_present(counter_dev)) {
509 sel_mask = GI_HW_ARM_SEL_MASK(counter_dev->variant);
511 switch (start_trigger) {
512 case NI_GPCT_ARM_IMMEDIATE:
513 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
516 if (start_trigger & NI_GPCT_ARM_UNKNOWN) {
518 * pass-through the least significant
519 * bits so we can figure out what
522 bits |= GI_HW_ARM_ENA |
523 (GI_HW_ARM_SEL(start_trigger) &
530 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
531 GI_HW_ARM_ENA | sel_mask, bits);
534 command_transient_bits |= GI_DISARM;
536 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
537 0, 0, command_transient_bits);
540 EXPORT_SYMBOL_GPL(ni_tio_arm);
542 static unsigned ni_660x_clk_src(unsigned int clock_source)
544 unsigned clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
545 unsigned ni_660x_clock;
549 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
550 ni_660x_clock = NI_660X_TIMEBASE_1_CLK;
552 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
553 ni_660x_clock = NI_660X_TIMEBASE_2_CLK;
555 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
556 ni_660x_clock = NI_660X_TIMEBASE_3_CLK;
558 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
559 ni_660x_clock = NI_660X_LOGIC_LOW_CLK;
561 case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
562 ni_660x_clock = NI_660X_SRC_PIN_I_CLK;
564 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
565 ni_660x_clock = NI_660X_NEXT_GATE_CLK;
567 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
568 ni_660x_clock = NI_660X_NEXT_TC_CLK;
571 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
572 if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
573 ni_660x_clock = NI_660X_RTSI_CLK(i);
577 if (i <= NI_660X_MAX_RTSI_CHAN)
579 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
580 if (clk_src == NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
581 ni_660x_clock = NI_660X_SRC_PIN_CLK(i);
585 if (i <= NI_660X_MAX_SRC_PIN)
591 return GI_SRC_SEL(ni_660x_clock);
594 static unsigned ni_m_clk_src(unsigned int clock_source)
596 unsigned clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
597 unsigned ni_m_series_clock;
601 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
602 ni_m_series_clock = NI_M_TIMEBASE_1_CLK;
604 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
605 ni_m_series_clock = NI_M_TIMEBASE_2_CLK;
607 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
608 ni_m_series_clock = NI_M_TIMEBASE_3_CLK;
610 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
611 ni_m_series_clock = NI_M_LOGIC_LOW_CLK;
613 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
614 ni_m_series_clock = NI_M_NEXT_GATE_CLK;
616 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
617 ni_m_series_clock = NI_M_NEXT_TC_CLK;
619 case NI_GPCT_PXI10_CLOCK_SRC_BITS:
620 ni_m_series_clock = NI_M_PXI10_CLK;
622 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
623 ni_m_series_clock = NI_M_PXI_STAR_TRIGGER_CLK;
625 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
626 ni_m_series_clock = NI_M_ANALOG_TRIGGER_OUT_CLK;
629 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
630 if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
631 ni_m_series_clock = NI_M_RTSI_CLK(i);
635 if (i <= NI_M_MAX_RTSI_CHAN)
637 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
638 if (clk_src == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
639 ni_m_series_clock = NI_M_PFI_CLK(i);
643 if (i <= NI_M_MAX_PFI_CHAN)
645 pr_err("invalid clock source 0x%lx\n",
646 (unsigned long)clock_source);
648 ni_m_series_clock = 0;
651 return GI_SRC_SEL(ni_m_series_clock);
654 static void ni_tio_set_source_subselect(struct ni_gpct *counter,
655 unsigned int clock_source)
657 struct ni_gpct_device *counter_dev = counter->counter_dev;
658 unsigned cidx = counter->counter_index;
659 const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
661 if (counter_dev->variant != ni_gpct_variant_m_series)
663 switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
664 /* Gi_Source_Subselect is zero */
665 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
666 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
667 counter_dev->regs[second_gate_reg] &= ~GI_SRC_SUBSEL;
669 /* Gi_Source_Subselect is one */
670 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
671 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
672 counter_dev->regs[second_gate_reg] |= GI_SRC_SUBSEL;
674 /* Gi_Source_Subselect doesn't matter */
678 write_register(counter, counter_dev->regs[second_gate_reg],
682 static int ni_tio_set_clock_src(struct ni_gpct *counter,
683 unsigned int clock_source,
684 unsigned int period_ns)
686 struct ni_gpct_device *counter_dev = counter->counter_dev;
687 unsigned cidx = counter->counter_index;
690 /* FIXME: validate clock source */
691 switch (counter_dev->variant) {
692 case ni_gpct_variant_660x:
693 bits |= ni_660x_clk_src(clock_source);
695 case ni_gpct_variant_e_series:
696 case ni_gpct_variant_m_series:
698 bits |= ni_m_clk_src(clock_source);
701 if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
702 bits |= GI_SRC_POL_INVERT;
703 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
704 GI_SRC_SEL_MASK | GI_SRC_POL_INVERT, bits);
705 ni_tio_set_source_subselect(counter, clock_source);
707 if (ni_tio_counting_mode_registers_present(counter_dev)) {
709 switch (clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
710 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
712 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
713 bits |= GI_PRESCALE_X2(counter_dev->variant);
715 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
716 bits |= GI_PRESCALE_X8(counter_dev->variant);
721 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
722 GI_PRESCALE_X2(counter_dev->variant) |
723 GI_PRESCALE_X8(counter_dev->variant), bits);
725 counter->clock_period_ps = period_ns * 1000;
726 ni_tio_set_sync_mode(counter, 0);
730 static void ni_tio_get_clock_src(struct ni_gpct *counter,
731 unsigned int *clock_source,
732 unsigned int *period_ns)
736 *clock_source = ni_tio_generic_clock_src_select(counter);
737 temp64 = ni_tio_clock_period_ps(counter, *clock_source);
738 do_div(temp64, 1000); /* ps to ns */
742 static int ni_660x_set_gate(struct ni_gpct *counter, unsigned int gate_source)
744 unsigned int chan = CR_CHAN(gate_source);
745 unsigned cidx = counter->counter_index;
750 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
751 gate_sel = NI_660X_NEXT_SRC_GATE_SEL;
753 case NI_GPCT_NEXT_OUT_GATE_SELECT:
754 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
755 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
756 case NI_GPCT_GATE_PIN_i_GATE_SELECT:
757 gate_sel = chan & 0x1f;
760 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
761 if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
762 gate_sel = chan & 0x1f;
766 if (i <= NI_660X_MAX_RTSI_CHAN)
768 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
769 if (chan == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
770 gate_sel = chan & 0x1f;
774 if (i <= NI_660X_MAX_GATE_PIN)
778 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
779 GI_GATE_SEL_MASK, GI_GATE_SEL(gate_sel));
783 static int ni_m_set_gate(struct ni_gpct *counter, unsigned int gate_source)
785 unsigned int chan = CR_CHAN(gate_source);
786 unsigned cidx = counter->counter_index;
791 case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
792 case NI_GPCT_AI_START2_GATE_SELECT:
793 case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
794 case NI_GPCT_NEXT_OUT_GATE_SELECT:
795 case NI_GPCT_AI_START1_GATE_SELECT:
796 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
797 case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
798 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
799 gate_sel = chan & 0x1f;
802 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
803 if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
804 gate_sel = chan & 0x1f;
808 if (i <= NI_M_MAX_RTSI_CHAN)
810 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
811 if (chan == NI_GPCT_PFI_GATE_SELECT(i)) {
812 gate_sel = chan & 0x1f;
816 if (i <= NI_M_MAX_PFI_CHAN)
820 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
821 GI_GATE_SEL_MASK, GI_GATE_SEL(gate_sel));
825 static int ni_660x_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
827 struct ni_gpct_device *counter_dev = counter->counter_dev;
828 unsigned cidx = counter->counter_index;
829 unsigned int chan = CR_CHAN(gate_source);
830 unsigned gate2_reg = NITIO_GATE2_REG(cidx);
835 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
836 case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
837 case NI_GPCT_SELECTED_GATE_GATE_SELECT:
838 case NI_GPCT_NEXT_OUT_GATE_SELECT:
839 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
840 gate2_sel = chan & 0x1f;
842 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
843 gate2_sel = NI_660X_NEXT_SRC_GATE2_SEL;
846 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
847 if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
848 gate2_sel = chan & 0x1f;
852 if (i <= NI_660X_MAX_RTSI_CHAN)
854 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
855 if (chan == NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
856 gate2_sel = chan & 0x1f;
860 if (i <= NI_660X_MAX_UP_DOWN_PIN)
864 counter_dev->regs[gate2_reg] |= GI_GATE2_MODE;
865 counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK;
866 counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel);
867 write_register(counter, counter_dev->regs[gate2_reg], gate2_reg);
871 static int ni_m_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
873 struct ni_gpct_device *counter_dev = counter->counter_dev;
874 unsigned cidx = counter->counter_index;
875 unsigned int chan = CR_CHAN(gate_source);
876 unsigned gate2_reg = NITIO_GATE2_REG(cidx);
880 * FIXME: We don't know what the m-series second gate codes are,
881 * so we'll just pass the bits through for now.
885 gate2_sel = chan & 0x1f;
888 counter_dev->regs[gate2_reg] |= GI_GATE2_MODE;
889 counter_dev->regs[gate2_reg] &= ~GI_GATE2_SEL_MASK;
890 counter_dev->regs[gate2_reg] |= GI_GATE2_SEL(gate2_sel);
891 write_register(counter, counter_dev->regs[gate2_reg], gate2_reg);
895 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
896 unsigned int gate_source)
898 struct ni_gpct_device *counter_dev = counter->counter_dev;
899 unsigned cidx = counter->counter_index;
900 unsigned int chan = CR_CHAN(gate_source);
901 unsigned gate2_reg = NITIO_GATE2_REG(cidx);
904 switch (gate_index) {
906 if (chan == NI_GPCT_DISABLED_GATE_SELECT) {
907 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
912 if (gate_source & CR_INVERT)
913 mode |= GI_GATE_POL_INVERT;
914 if (gate_source & CR_EDGE)
915 mode |= GI_RISING_EDGE_GATING;
917 mode |= GI_LEVEL_GATING;
918 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
919 GI_GATE_POL_INVERT | GI_GATING_MODE_MASK,
921 switch (counter_dev->variant) {
922 case ni_gpct_variant_e_series:
923 case ni_gpct_variant_m_series:
925 return ni_m_set_gate(counter, gate_source);
926 case ni_gpct_variant_660x:
927 return ni_660x_set_gate(counter, gate_source);
931 if (!ni_tio_has_gate2_registers(counter_dev))
934 if (chan == NI_GPCT_DISABLED_GATE_SELECT) {
935 counter_dev->regs[gate2_reg] &= ~GI_GATE2_MODE;
936 write_register(counter, counter_dev->regs[gate2_reg],
940 if (gate_source & CR_INVERT)
941 counter_dev->regs[gate2_reg] |= GI_GATE2_POL_INVERT;
943 counter_dev->regs[gate2_reg] &= ~GI_GATE2_POL_INVERT;
944 switch (counter_dev->variant) {
945 case ni_gpct_variant_m_series:
946 return ni_m_set_gate2(counter, gate_source);
947 case ni_gpct_variant_660x:
948 return ni_660x_set_gate2(counter, gate_source);
959 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
961 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned index,
964 struct ni_gpct_device *counter_dev = counter->counter_dev;
965 unsigned cidx = counter->counter_index;
966 unsigned int abz_reg, shift, mask;
968 if (counter_dev->variant != ni_gpct_variant_m_series)
971 abz_reg = NITIO_ABZ_REG(cidx);
973 case NI_GPCT_SOURCE_ENCODER_A:
976 case NI_GPCT_SOURCE_ENCODER_B:
979 case NI_GPCT_SOURCE_ENCODER_Z:
985 mask = 0x1f << shift;
987 source = 0x1f; /* Disable gate */
989 counter_dev->regs[abz_reg] &= ~mask;
990 counter_dev->regs[abz_reg] |= (source << shift) & mask;
991 write_register(counter, counter_dev->regs[abz_reg], abz_reg);
995 static unsigned ni_660x_gate_to_generic_gate(unsigned gate)
1000 case NI_660X_SRC_PIN_I_GATE_SEL:
1001 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1002 case NI_660X_GATE_PIN_I_GATE_SEL:
1003 return NI_GPCT_GATE_PIN_i_GATE_SELECT;
1004 case NI_660X_NEXT_SRC_GATE_SEL:
1005 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1006 case NI_660X_NEXT_OUT_GATE_SEL:
1007 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1008 case NI_660X_LOGIC_LOW_GATE_SEL:
1009 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1011 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1012 if (gate == NI_660X_RTSI_GATE_SEL(i))
1013 return NI_GPCT_RTSI_GATE_SELECT(i);
1015 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
1016 if (gate == NI_660X_PIN_GATE_SEL(i))
1017 return NI_GPCT_GATE_PIN_GATE_SELECT(i);
1025 static unsigned ni_m_gate_to_generic_gate(unsigned gate)
1030 case NI_M_TIMESTAMP_MUX_GATE_SEL:
1031 return NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1032 case NI_M_AI_START2_GATE_SEL:
1033 return NI_GPCT_AI_START2_GATE_SELECT;
1034 case NI_M_PXI_STAR_TRIGGER_GATE_SEL:
1035 return NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1036 case NI_M_NEXT_OUT_GATE_SEL:
1037 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1038 case NI_M_AI_START1_GATE_SEL:
1039 return NI_GPCT_AI_START1_GATE_SELECT;
1040 case NI_M_NEXT_SRC_GATE_SEL:
1041 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1042 case NI_M_ANALOG_TRIG_OUT_GATE_SEL:
1043 return NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1044 case NI_M_LOGIC_LOW_GATE_SEL:
1045 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1047 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
1048 if (gate == NI_M_RTSI_GATE_SEL(i))
1049 return NI_GPCT_RTSI_GATE_SELECT(i);
1051 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
1052 if (gate == NI_M_PFI_GATE_SEL(i))
1053 return NI_GPCT_PFI_GATE_SELECT(i);
1061 static unsigned ni_660x_gate2_to_generic_gate(unsigned gate)
1066 case NI_660X_SRC_PIN_I_GATE2_SEL:
1067 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1068 case NI_660X_UD_PIN_I_GATE2_SEL:
1069 return NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1070 case NI_660X_NEXT_SRC_GATE2_SEL:
1071 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1072 case NI_660X_NEXT_OUT_GATE2_SEL:
1073 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1074 case NI_660X_SELECTED_GATE2_SEL:
1075 return NI_GPCT_SELECTED_GATE_GATE_SELECT;
1076 case NI_660X_LOGIC_LOW_GATE2_SEL:
1077 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1079 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1080 if (gate == NI_660X_RTSI_GATE2_SEL(i))
1081 return NI_GPCT_RTSI_GATE_SELECT(i);
1083 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
1084 if (gate == NI_660X_UD_PIN_GATE2_SEL(i))
1085 return NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1093 static unsigned ni_m_gate2_to_generic_gate(unsigned gate)
1096 * FIXME: the second gate sources for the m series are undocumented,
1097 * so we just return the raw bits for now.
1106 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
1107 unsigned int *gate_source)
1109 struct ni_gpct_device *counter_dev = counter->counter_dev;
1110 unsigned cidx = counter->counter_index;
1111 unsigned mode = ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx));
1112 unsigned gate2_reg = NITIO_GATE2_REG(cidx);
1115 switch (gate_index) {
1117 if ((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED) {
1118 *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1122 gate = GI_BITS_TO_GATE(ni_tio_get_soft_copy(counter,
1123 NITIO_INPUT_SEL_REG(cidx)));
1125 switch (counter_dev->variant) {
1126 case ni_gpct_variant_e_series:
1127 case ni_gpct_variant_m_series:
1129 *gate_source = ni_m_gate_to_generic_gate(gate);
1131 case ni_gpct_variant_660x:
1132 *gate_source = ni_660x_gate_to_generic_gate(gate);
1135 if (mode & GI_GATE_POL_INVERT)
1136 *gate_source |= CR_INVERT;
1137 if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)
1138 *gate_source |= CR_EDGE;
1141 if ((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED ||
1142 !(counter_dev->regs[gate2_reg] & GI_GATE2_MODE)) {
1143 *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1147 gate = GI_BITS_TO_GATE2(counter_dev->regs[gate2_reg]);
1149 switch (counter_dev->variant) {
1150 case ni_gpct_variant_e_series:
1151 case ni_gpct_variant_m_series:
1153 *gate_source = ni_m_gate2_to_generic_gate(gate);
1155 case ni_gpct_variant_660x:
1156 *gate_source = ni_660x_gate2_to_generic_gate(gate);
1159 if (counter_dev->regs[gate2_reg] & GI_GATE2_POL_INVERT)
1160 *gate_source |= CR_INVERT;
1161 /* second gate can't have edge/level mode set independently */
1162 if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)
1163 *gate_source |= CR_EDGE;
1171 int ni_tio_insn_config(struct comedi_device *dev,
1172 struct comedi_subdevice *s,
1173 struct comedi_insn *insn,
1176 struct ni_gpct *counter = s->private;
1177 unsigned cidx = counter->counter_index;
1181 case INSN_CONFIG_SET_COUNTER_MODE:
1182 return ni_tio_set_counter_mode(counter, data[1]);
1183 case INSN_CONFIG_ARM:
1184 return ni_tio_arm(counter, 1, data[1]);
1185 case INSN_CONFIG_DISARM:
1186 ni_tio_arm(counter, 0, 0);
1188 case INSN_CONFIG_GET_COUNTER_STATUS:
1190 status = read_register(counter, NITIO_SHARED_STATUS_REG(cidx));
1191 if (status & GI_ARMED(cidx)) {
1192 data[1] |= COMEDI_COUNTER_ARMED;
1193 if (status & GI_COUNTING(cidx))
1194 data[1] |= COMEDI_COUNTER_COUNTING;
1196 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
1198 case INSN_CONFIG_SET_CLOCK_SRC:
1199 return ni_tio_set_clock_src(counter, data[1], data[2]);
1200 case INSN_CONFIG_GET_CLOCK_SRC:
1201 ni_tio_get_clock_src(counter, &data[1], &data[2]);
1203 case INSN_CONFIG_SET_GATE_SRC:
1204 return ni_tio_set_gate_src(counter, data[1], data[2]);
1205 case INSN_CONFIG_GET_GATE_SRC:
1206 return ni_tio_get_gate_src(counter, data[1], &data[2]);
1207 case INSN_CONFIG_SET_OTHER_SRC:
1208 return ni_tio_set_other_src(counter, data[1], data[2]);
1209 case INSN_CONFIG_RESET:
1210 ni_tio_reset_count_and_disarm(counter);
1217 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1219 static unsigned int ni_tio_read_sw_save_reg(struct comedi_device *dev,
1220 struct comedi_subdevice *s)
1222 struct ni_gpct *counter = s->private;
1223 unsigned cidx = counter->counter_index;
1226 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0);
1227 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1228 GI_SAVE_TRACE, GI_SAVE_TRACE);
1231 * The count doesn't get latched until the next clock edge, so it is
1232 * possible the count may change (once) while we are reading. Since
1233 * the read of the SW_Save_Reg isn't atomic (apparently even when it's
1234 * a 32 bit register according to 660x docs), we need to read twice
1235 * and make sure the reading hasn't changed. If it has, a third read
1236 * will be correct since the count value will definitely have latched
1239 val = read_register(counter, NITIO_SW_SAVE_REG(cidx));
1240 if (val != read_register(counter, NITIO_SW_SAVE_REG(cidx)))
1241 val = read_register(counter, NITIO_SW_SAVE_REG(cidx));
1246 int ni_tio_insn_read(struct comedi_device *dev,
1247 struct comedi_subdevice *s,
1248 struct comedi_insn *insn,
1251 struct ni_gpct *counter = s->private;
1252 struct ni_gpct_device *counter_dev = counter->counter_dev;
1253 unsigned int channel = CR_CHAN(insn->chanspec);
1254 unsigned cidx = counter->counter_index;
1257 for (i = 0; i < insn->n; i++) {
1260 data[i] = ni_tio_read_sw_save_reg(dev, s);
1263 data[i] = counter_dev->regs[NITIO_LOADA_REG(cidx)];
1266 data[i] = counter_dev->regs[NITIO_LOADB_REG(cidx)];
1272 EXPORT_SYMBOL_GPL(ni_tio_insn_read);
1274 static unsigned ni_tio_next_load_register(struct ni_gpct *counter)
1276 unsigned cidx = counter->counter_index;
1277 const unsigned bits =
1278 read_register(counter, NITIO_SHARED_STATUS_REG(cidx));
1280 return (bits & GI_NEXT_LOAD_SRC(cidx))
1281 ? NITIO_LOADB_REG(cidx)
1282 : NITIO_LOADA_REG(cidx);
1285 int ni_tio_insn_write(struct comedi_device *dev,
1286 struct comedi_subdevice *s,
1287 struct comedi_insn *insn,
1290 struct ni_gpct *counter = s->private;
1291 struct ni_gpct_device *counter_dev = counter->counter_dev;
1292 const unsigned channel = CR_CHAN(insn->chanspec);
1293 unsigned cidx = counter->counter_index;
1301 * Unsafe if counter is armed.
1302 * Should probably check status and return -EBUSY if armed.
1306 * Don't disturb load source select, just use whichever
1307 * load register is already selected.
1309 load_reg = ni_tio_next_load_register(counter);
1310 write_register(counter, data[0], load_reg);
1311 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
1313 /* restore load reg */
1314 write_register(counter, counter_dev->regs[load_reg], load_reg);
1317 counter_dev->regs[NITIO_LOADA_REG(cidx)] = data[0];
1318 write_register(counter, data[0], NITIO_LOADA_REG(cidx));
1321 counter_dev->regs[NITIO_LOADB_REG(cidx)] = data[0];
1322 write_register(counter, data[0], NITIO_LOADB_REG(cidx));
1329 EXPORT_SYMBOL_GPL(ni_tio_insn_write);
1331 void ni_tio_init_counter(struct ni_gpct *counter)
1333 struct ni_gpct_device *counter_dev = counter->counter_dev;
1334 unsigned cidx = counter->counter_index;
1336 ni_tio_reset_count_and_disarm(counter);
1338 /* initialize counter registers */
1339 counter_dev->regs[NITIO_AUTO_INC_REG(cidx)] = 0x0;
1340 write_register(counter, 0x0, NITIO_AUTO_INC_REG(cidx));
1342 ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1345 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ~0, 0);
1347 counter_dev->regs[NITIO_LOADA_REG(cidx)] = 0x0;
1348 write_register(counter, 0x0, NITIO_LOADA_REG(cidx));
1350 counter_dev->regs[NITIO_LOADB_REG(cidx)] = 0x0;
1351 write_register(counter, 0x0, NITIO_LOADB_REG(cidx));
1353 ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ~0, 0);
1355 if (ni_tio_counting_mode_registers_present(counter_dev))
1356 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ~0, 0);
1358 if (ni_tio_has_gate2_registers(counter_dev)) {
1359 counter_dev->regs[NITIO_GATE2_REG(cidx)] = 0x0;
1360 write_register(counter, 0x0, NITIO_GATE2_REG(cidx));
1363 ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), ~0, 0x0);
1365 ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ~0, 0x0);
1367 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
1369 struct ni_gpct_device *
1370 ni_gpct_device_construct(struct comedi_device *dev,
1371 void (*write_register)(struct ni_gpct *counter,
1373 enum ni_gpct_register reg),
1374 unsigned (*read_register)(struct ni_gpct *counter,
1375 enum ni_gpct_register reg),
1376 enum ni_gpct_variant variant,
1377 unsigned num_counters)
1379 struct ni_gpct_device *counter_dev;
1380 struct ni_gpct *counter;
1383 if (num_counters == 0)
1386 counter_dev = kzalloc(sizeof(*counter_dev), GFP_KERNEL);
1390 counter_dev->dev = dev;
1391 counter_dev->write_register = write_register;
1392 counter_dev->read_register = read_register;
1393 counter_dev->variant = variant;
1395 spin_lock_init(&counter_dev->regs_lock);
1397 counter_dev->counters = kcalloc(num_counters, sizeof(*counter),
1399 if (!counter_dev->counters) {
1404 for (i = 0; i < num_counters; ++i) {
1405 counter = &counter_dev->counters[i];
1406 counter->counter_dev = counter_dev;
1407 spin_lock_init(&counter->lock);
1409 counter_dev->num_counters = num_counters;
1413 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
1415 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
1417 if (!counter_dev->counters)
1419 kfree(counter_dev->counters);
1422 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
1424 static int __init ni_tio_init_module(void)
1428 module_init(ni_tio_init_module);
1430 static void __exit ni_tio_cleanup_module(void)
1433 module_exit(ni_tio_cleanup_module);
1435 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
1436 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
1437 MODULE_LICENSE("GPL");