drivers/staging/comedi/drivers/ni_tio.c

   1 /*
   2   comedi/drivers/ni_tio.c
   3   Support for NI general purpose counters
   4
   5   Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   6
   7   This program is free software; you can redistribute it and/or modify
   8   it under the terms of the GNU General Public License as published by
   9   the Free Software Foundation; either version 2 of the License, or
  10   (at your option) any later version.
  11
  12   This program is distributed in the hope that it will be useful,
  13   but WITHOUT ANY WARRANTY; without even the implied warranty of
  14   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15   GNU General Public License for more details.
  16 */
  17
  18 /*
  19 Driver: ni_tio
  20 Description: National Instruments general purpose counters
  21 Devices:
  22 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  23         Herman.Bruyninckx@mech.kuleuven.ac.be,
  24         Wim.Meeussen@mech.kuleuven.ac.be,
  25         Klaas.Gadeyne@mech.kuleuven.ac.be,
  26         Frank Mori Hess <fmhess@users.sourceforge.net>
  27 Updated: Thu Nov 16 09:50:32 EST 2006
  28 Status: works
  29
  30 This module is not used directly by end-users.  Rather, it
  31 is used by other drivers (for example ni_660x and ni_pcimio)
  32 to provide support for NI's general purpose counters.  It was
  33 originally based on the counter code from ni_660x.c and
  34 ni_mio_common.c.
  35
  36 References:
  37 DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  38 DAQ 6601/6602 User Manual (NI 322137B-01)
  39 340934b.pdf  DAQ-STC reference manual
  40
  41 */
  42 /*
  43 TODO:
  44         Support use of both banks X and Y
  45 */
  46
  47 #include <linux/module.h>
  48 #include <linux/slab.h>
  49
  50 #include "ni_tio_internal.h"
  51
  52 /*
  53  * clock sources for ni e and m series boards,
  54  * get bits with Gi_Source_Select_Bits()
  55  */
  56 #define NI_M_TIMEBASE_1_CLK             0x0     /* 20MHz */
  57 #define NI_M_PFI_CLK(x)                 (((x) < 10) ? (1 + (x)) : (0xb + (x)))
  58 #define NI_M_RTSI_CLK(x)                (((x) == 7) ? 0x1b : (0xb + (x)))
  59 #define NI_M_TIMEBASE_2_CLK             0x12    /* 100KHz */
  60 #define NI_M_NEXT_TC_CLK                0x13
  61 #define NI_M_NEXT_GATE_CLK              0x14    /* Gi_Src_SubSelect=0 */
  62 #define NI_M_PXI_STAR_TRIGGER_CLK       0x14    /* Gi_Src_SubSelect=1 */
  63 #define NI_M_PXI10_CLK                  0x1d
  64 #define NI_M_TIMEBASE_3_CLK             0x1e    /* 80MHz, Gi_Src_SubSelect=0 */
  65 #define NI_M_ANALOG_TRIGGER_OUT_CLK     0x1e    /* Gi_Src_SubSelect=1 */
  66 #define NI_M_LOGIC_LOW_CLK              0x1f
  67 #define NI_M_MAX_PFI_CHAN               15
  68 #define NI_M_MAX_RTSI_CHAN              7
  69
  70 /*
  71  * clock sources for ni_660x boards,
  72  * get bits with Gi_Source_Select_Bits()
  73  */
  74 #define NI_660X_TIMEBASE_1_CLK          0x0     /* 20MHz */
  75 #define NI_660X_SRC_PIN_I_CLK           0x1
  76 #define NI_660X_SRC_PIN_CLK(x)          (0x2 + (x))
  77 #define NI_660X_NEXT_GATE_CLK           0xa
  78 #define NI_660X_RTSI_CLK(x)             (0xb + (x))
  79 #define NI_660X_TIMEBASE_2_CLK          0x12    /* 100KHz */
  80 #define NI_660X_NEXT_TC_CLK             0x13
  81 #define NI_660X_TIMEBASE_3_CLK          0x1e    /* 80MHz */
  82 #define NI_660X_LOGIC_LOW_CLK           0x1f
  83 #define NI_660X_MAX_SRC_PIN             7
  84 #define NI_660X_MAX_RTSI_CHAN           6
  85
  86 /* ni m series gate_select */
  87 #define NI_M_TIMESTAMP_MUX_GATE_SEL     0x0
  88 #define NI_M_PFI_GATE_SEL(x)            (((x) < 10) ? (1 + (x)) : (0xb + (x)))
  89 #define NI_M_RTSI_GATE_SEL(x)           (((x) == 7) ? 0x1b : (0xb + (x)))
  90 #define NI_M_AI_START2_GATE_SEL         0x12
  91 #define NI_M_PXI_STAR_TRIGGER_GATE_SEL  0x13
  92 #define NI_M_NEXT_OUT_GATE_SEL          0x14
  93 #define NI_M_AI_START1_GATE_SEL         0x1c
  94 #define NI_M_NEXT_SRC_GATE_SEL          0x1d
  95 #define NI_M_ANALOG_TRIG_OUT_GATE_SEL   0x1e
  96 #define NI_M_LOGIC_LOW_GATE_SEL         0x1f
  97
  98 /* ni_660x gate select */
  99 #define NI_660X_SRC_PIN_I_GATE_SEL      0x0
 100 #define NI_660X_GATE_PIN_I_GATE_SEL     0x1
 101 #define NI_660X_PIN_GATE_SEL(x)         (0x2 + (x))
 102 #define NI_660X_NEXT_SRC_GATE_SEL       0xa
 103 #define NI_660X_RTSI_GATE_SEL(x)        (0xb + (x))
 104 #define NI_660X_NEXT_OUT_GATE_SEL       0x14
 105 #define NI_660X_LOGIC_LOW_GATE_SEL      0x1f
 106 #define NI_660X_MAX_GATE_PIN            7
 107
 108 /* ni_660x second gate select */
 109 #define NI_660X_SRC_PIN_I_GATE2_SEL     0x0
 110 #define NI_660X_UD_PIN_I_GATE2_SEL      0x1
 111 #define NI_660X_UD_PIN_GATE2_SEL(x)     (0x2 + (x))
 112 #define NI_660X_NEXT_SRC_GATE2_SEL      0xa
 113 #define NI_660X_RTSI_GATE2_SEL(x)       (0xb + (x))
 114 #define NI_660X_NEXT_OUT_GATE2_SEL      0x14
 115 #define NI_660X_SELECTED_GATE2_SEL      0x1e
 116 #define NI_660X_LOGIC_LOW_GATE2_SEL     0x1f
 117 #define NI_660X_MAX_UP_DOWN_PIN         7
 118
 119 static inline unsigned GI_ALT_SYNC(enum ni_gpct_variant variant)
 120 {
 121         switch (variant) {
 122         case ni_gpct_variant_e_series:
 123         default:
 124                 return 0;
 125         case ni_gpct_variant_m_series:
 126                 return GI_M_ALT_SYNC;
 127         case ni_gpct_variant_660x:
 128                 return GI_660X_ALT_SYNC;
 129         }
 130 }
 131
 132 static inline unsigned GI_PRESCALE_X2(enum ni_gpct_variant variant)
 133 {
 134         switch (variant) {
 135         case ni_gpct_variant_e_series:
 136         default:
 137                 return 0;
 138         case ni_gpct_variant_m_series:
 139                 return GI_M_PRESCALE_X2;
 140         case ni_gpct_variant_660x:
 141                 return GI_660X_PRESCALE_X2;
 142         }
 143 }
 144
 145 static inline unsigned GI_PRESCALE_X8(enum ni_gpct_variant variant)
 146 {
 147         switch (variant) {
 148         case ni_gpct_variant_e_series:
 149         default:
 150                 return 0;
 151         case ni_gpct_variant_m_series:
 152                 return GI_M_PRESCALE_X8;
 153         case ni_gpct_variant_660x:
 154                 return GI_660X_PRESCALE_X8;
 155         }
 156 }
 157
 158 static inline unsigned GI_HW_ARM_SEL_MASK(enum ni_gpct_variant variant)
 159 {
 160         switch (variant) {
 161         case ni_gpct_variant_e_series:
 162         default:
 163                 return 0;
 164         case ni_gpct_variant_m_series:
 165                 return GI_M_HW_ARM_SEL_MASK;
 166         case ni_gpct_variant_660x:
 167                 return GI_660X_HW_ARM_SEL_MASK;
 168         }
 169 }
 170
 171 static inline unsigned Gi_Source_Select_Bits(unsigned source)
 172 {
 173         return (source << Gi_Source_Select_Shift) & Gi_Source_Select_Mask;
 174 }
 175
 176 static inline unsigned Gi_Gate_Select_Bits(unsigned gate_select)
 177 {
 178         return (gate_select << Gi_Gate_Select_Shift) & Gi_Gate_Select_Mask;
 179 }
 180
 181 static int ni_tio_has_gate2_registers(const struct ni_gpct_device *counter_dev)
 182 {
 183         switch (counter_dev->variant) {
 184         case ni_gpct_variant_e_series:
 185         default:
 186                 return 0;
 187         case ni_gpct_variant_m_series:
 188         case ni_gpct_variant_660x:
 189                 return 1;
 190         }
 191 }
 192
 193 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
 194 {
 195         unsigned cidx = counter->counter_index;
 196
 197         write_register(counter, Gi_Reset_Bit(cidx), NITIO_RESET_REG(cidx));
 198 }
 199
 200 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
 201                                        unsigned generic_clock_source)
 202 {
 203         uint64_t clock_period_ps;
 204
 205         switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 206         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 207                 clock_period_ps = 50000;
 208                 break;
 209         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 210                 clock_period_ps = 10000000;
 211                 break;
 212         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 213                 clock_period_ps = 12500;
 214                 break;
 215         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 216                 clock_period_ps = 100000;
 217                 break;
 218         default:
 219                 /*
 220                  * clock period is specified by user with prescaling
 221                  * already taken into account.
 222                  */
 223                 return counter->clock_period_ps;
 224         }
 225
 226         switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
 227         case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 228                 break;
 229         case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 230                 clock_period_ps *= 2;
 231                 break;
 232         case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 233                 clock_period_ps *= 8;
 234                 break;
 235         default:
 236                 BUG();
 237                 break;
 238         }
 239         return clock_period_ps;
 240 }
 241
 242 static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
 243 {
 244         struct ni_gpct_device *counter_dev = counter->counter_dev;
 245         unsigned cidx = counter->counter_index;
 246         const unsigned counting_mode_bits =
 247                 ni_tio_get_soft_copy(counter, NITIO_CNT_MODE_REG(cidx));
 248         unsigned bits = 0;
 249
 250         if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
 251             Gi_Source_Polarity_Bit)
 252                 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
 253         if (counting_mode_bits & GI_PRESCALE_X2(counter_dev->variant))
 254                 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
 255         if (counting_mode_bits & GI_PRESCALE_X8(counter_dev->variant))
 256                 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
 257         return bits;
 258 }
 259
 260 static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter)
 261 {
 262         struct ni_gpct_device *counter_dev = counter->counter_dev;
 263         unsigned cidx = counter->counter_index;
 264         const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
 265         unsigned clock_source = 0;
 266         unsigned i;
 267         const unsigned input_select =
 268                 (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
 269                         Gi_Source_Select_Mask) >> Gi_Source_Select_Shift;
 270
 271         switch (input_select) {
 272         case NI_M_TIMEBASE_1_CLK:
 273                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 274                 break;
 275         case NI_M_TIMEBASE_2_CLK:
 276                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 277                 break;
 278         case NI_M_TIMEBASE_3_CLK:
 279                 if (counter_dev->regs[second_gate_reg] &
 280                     Gi_Source_Subselect_Bit)
 281                         clock_source =
 282                             NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
 283                 else
 284                         clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 285                 break;
 286         case NI_M_LOGIC_LOW_CLK:
 287                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 288                 break;
 289         case NI_M_NEXT_GATE_CLK:
 290                 if (counter_dev->regs[second_gate_reg] &
 291                     Gi_Source_Subselect_Bit)
 292                         clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
 293                 else
 294                         clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 295                 break;
 296         case NI_M_PXI10_CLK:
 297                 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
 298                 break;
 299         case NI_M_NEXT_TC_CLK:
 300                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 301                 break;
 302         default:
 303                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 304                         if (input_select == NI_M_RTSI_CLK(i)) {
 305                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 306                                 break;
 307                         }
 308                 }
 309                 if (i <= NI_M_MAX_RTSI_CHAN)
 310                         break;
 311                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 312                         if (input_select == NI_M_PFI_CLK(i)) {
 313                                 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
 314                                 break;
 315                         }
 316                 }
 317                 if (i <= NI_M_MAX_PFI_CHAN)
 318                         break;
 319                 BUG();
 320                 break;
 321         }
 322         clock_source |= ni_tio_clock_src_modifiers(counter);
 323         return clock_source;
 324 }
 325
 326 static unsigned ni_660x_clock_src_select(const struct ni_gpct *counter)
 327 {
 328         unsigned clock_source = 0;
 329         unsigned cidx = counter->counter_index;
 330         const unsigned input_select =
 331                 (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
 332                         Gi_Source_Select_Mask) >> Gi_Source_Select_Shift;
 333         unsigned i;
 334
 335         switch (input_select) {
 336         case NI_660X_TIMEBASE_1_CLK:
 337                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 338                 break;
 339         case NI_660X_TIMEBASE_2_CLK:
 340                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 341                 break;
 342         case NI_660X_TIMEBASE_3_CLK:
 343                 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 344                 break;
 345         case NI_660X_LOGIC_LOW_CLK:
 346                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 347                 break;
 348         case NI_660X_SRC_PIN_I_CLK:
 349                 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
 350                 break;
 351         case NI_660X_NEXT_GATE_CLK:
 352                 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 353                 break;
 354         case NI_660X_NEXT_TC_CLK:
 355                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 356                 break;
 357         default:
 358                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 359                         if (input_select == NI_660X_RTSI_CLK(i)) {
 360                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 361                                 break;
 362                         }
 363                 }
 364                 if (i <= NI_660X_MAX_RTSI_CHAN)
 365                         break;
 366                 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
 367                         if (input_select == NI_660X_SRC_PIN_CLK(i)) {
 368                                 clock_source =
 369                                     NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
 370                                 break;
 371                         }
 372                 }
 373                 if (i <= NI_660X_MAX_SRC_PIN)
 374                         break;
 375                 BUG();
 376                 break;
 377         }
 378         clock_source |= ni_tio_clock_src_modifiers(counter);
 379         return clock_source;
 380 }
 381
 382 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter)
 383 {
 384         switch (counter->counter_dev->variant) {
 385         case ni_gpct_variant_e_series:
 386         case ni_gpct_variant_m_series:
 387         default:
 388                 return ni_m_series_clock_src_select(counter);
 389         case ni_gpct_variant_660x:
 390                 return ni_660x_clock_src_select(counter);
 391         }
 392 }
 393
 394 static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync)
 395 {
 396         struct ni_gpct_device *counter_dev = counter->counter_dev;
 397         unsigned cidx = counter->counter_index;
 398         const unsigned counting_mode_reg = NITIO_CNT_MODE_REG(cidx);
 399         static const uint64_t min_normal_sync_period_ps = 25000;
 400         unsigned mode;
 401         uint64_t clock_period_ps;
 402
 403         if (ni_tio_counting_mode_registers_present(counter_dev) == 0)
 404                 return;
 405
 406         mode = ni_tio_get_soft_copy(counter, counting_mode_reg);
 407         switch (mode & GI_CNT_MODE_MASK) {
 408         case GI_CNT_MODE_QUADX1:
 409         case GI_CNT_MODE_QUADX2:
 410         case GI_CNT_MODE_QUADX4:
 411         case GI_CNT_MODE_SYNC_SRC:
 412                 force_alt_sync = 1;
 413                 break;
 414         default:
 415                 break;
 416         }
 417
 418         clock_period_ps = ni_tio_clock_period_ps(counter,
 419                                 ni_tio_generic_clock_src_select(counter));
 420
 421         /*
 422          * It's not clear what we should do if clock_period is unknown, so we
 423          * are not using the alt sync bit in that case, but allow the caller
 424          * to decide by using the force_alt_sync parameter.
 425          */
 426         if (force_alt_sync ||
 427             (clock_period_ps && clock_period_ps < min_normal_sync_period_ps)) {
 428                 ni_tio_set_bits(counter, counting_mode_reg,
 429                                 GI_ALT_SYNC(counter_dev->variant),
 430                                 GI_ALT_SYNC(counter_dev->variant));
 431         } else {
 432                 ni_tio_set_bits(counter, counting_mode_reg,
 433                                 GI_ALT_SYNC(counter_dev->variant),
 434                                 0x0);
 435         }
 436 }
 437
 438 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode)
 439 {
 440         struct ni_gpct_device *counter_dev = counter->counter_dev;
 441         unsigned cidx = counter->counter_index;
 442         unsigned mode_reg_mask;
 443         unsigned mode_reg_values;
 444         unsigned input_select_bits = 0;
 445         /* these bits map directly on to the mode register */
 446         static const unsigned mode_reg_direct_mask =
 447             NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
 448             NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
 449             NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
 450             NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
 451
 452         mode_reg_mask = mode_reg_direct_mask | Gi_Reload_Source_Switching_Bit;
 453         mode_reg_values = mode & mode_reg_direct_mask;
 454         switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
 455         case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
 456                 break;
 457         case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
 458                 mode_reg_values |= Gi_Reload_Source_Switching_Bit;
 459                 break;
 460         case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
 461                 input_select_bits |= Gi_Gate_Select_Load_Source_Bit;
 462                 mode_reg_mask |= Gi_Gating_Mode_Mask;
 463                 mode_reg_values |= Gi_Level_Gating_Bits;
 464                 break;
 465         default:
 466                 break;
 467         }
 468         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 469                         mode_reg_mask, mode_reg_values);
 470
 471         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 472                 unsigned bits = 0;
 473
 474                 bits |= GI_CNT_MODE(mode >> NI_GPCT_COUNTING_MODE_SHIFT);
 475                 bits |= GI_INDEX_PHASE((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT));
 476                 if (mode & NI_GPCT_INDEX_ENABLE_BIT)
 477                         bits |= GI_INDEX_MODE;
 478                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 479                                 GI_CNT_MODE_MASK | GI_INDEX_PHASE_MASK |
 480                                 GI_INDEX_MODE, bits);
 481                 ni_tio_set_sync_mode(counter, 0);
 482         }
 483
 484         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
 485                         Gi_Up_Down_Mask,
 486                         (mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT) <<
 487                         Gi_Up_Down_Shift);
 488
 489         if (mode & NI_GPCT_OR_GATE_BIT)
 490                 input_select_bits |= Gi_Or_Gate_Bit;
 491         if (mode & NI_GPCT_INVERT_OUTPUT_BIT)
 492                 input_select_bits |= Gi_Output_Polarity_Bit;
 493         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 494                         Gi_Gate_Select_Load_Source_Bit | Gi_Or_Gate_Bit |
 495                         Gi_Output_Polarity_Bit, input_select_bits);
 496
 497         return 0;
 498 }
 499
 500 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger)
 501 {
 502         struct ni_gpct_device *counter_dev = counter->counter_dev;
 503         unsigned cidx = counter->counter_index;
 504         unsigned command_transient_bits = 0;
 505
 506         if (arm) {
 507                 switch (start_trigger) {
 508                 case NI_GPCT_ARM_IMMEDIATE:
 509                         command_transient_bits |= Gi_Arm_Bit;
 510                         break;
 511                 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
 512                         command_transient_bits |= Gi_Arm_Bit | Gi_Arm_Copy_Bit;
 513                         break;
 514                 default:
 515                         break;
 516                 }
 517                 if (ni_tio_counting_mode_registers_present(counter_dev)) {
 518                         unsigned bits = 0;
 519                         unsigned sel_mask;
 520
 521                         sel_mask = GI_HW_ARM_SEL_MASK(counter_dev->variant);
 522
 523                         switch (start_trigger) {
 524                         case NI_GPCT_ARM_IMMEDIATE:
 525                         case NI_GPCT_ARM_PAIRED_IMMEDIATE:
 526                                 break;
 527                         default:
 528                                 if (start_trigger & NI_GPCT_ARM_UNKNOWN) {
 529                                         /*
 530                                          * pass-through the least significant
 531                                          * bits so we can figure out what
 532                                          * select later
 533                                          */
 534                                         bits |= GI_HW_ARM_ENA |
 535                                                 (GI_HW_ARM_SEL(start_trigger) &
 536                                                  sel_mask);
 537                                 } else {
 538                                         return -EINVAL;
 539                                 }
 540                                 break;
 541                         }
 542                         ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 543                                         GI_HW_ARM_ENA | sel_mask, bits);
 544                 }
 545         } else {
 546                 command_transient_bits |= Gi_Disarm_Bit;
 547         }
 548         ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
 549                                   0, 0, command_transient_bits);
 550         return 0;
 551 }
 552 EXPORT_SYMBOL_GPL(ni_tio_arm);
 553
 554 static unsigned ni_660x_clk_src(unsigned int clock_source)
 555 {
 556         unsigned clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 557         unsigned ni_660x_clock;
 558         unsigned i;
 559
 560         switch (clk_src) {
 561         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 562                 ni_660x_clock = NI_660X_TIMEBASE_1_CLK;
 563                 break;
 564         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 565                 ni_660x_clock = NI_660X_TIMEBASE_2_CLK;
 566                 break;
 567         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 568                 ni_660x_clock = NI_660X_TIMEBASE_3_CLK;
 569                 break;
 570         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 571                 ni_660x_clock = NI_660X_LOGIC_LOW_CLK;
 572                 break;
 573         case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
 574                 ni_660x_clock = NI_660X_SRC_PIN_I_CLK;
 575                 break;
 576         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 577                 ni_660x_clock = NI_660X_NEXT_GATE_CLK;
 578                 break;
 579         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 580                 ni_660x_clock = NI_660X_NEXT_TC_CLK;
 581                 break;
 582         default:
 583                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 584                         if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 585                                 ni_660x_clock = NI_660X_RTSI_CLK(i);
 586                                 break;
 587                         }
 588                 }
 589                 if (i <= NI_660X_MAX_RTSI_CHAN)
 590                         break;
 591                 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
 592                         if (clk_src == NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
 593                                 ni_660x_clock = NI_660X_SRC_PIN_CLK(i);
 594                                 break;
 595                         }
 596                 }
 597                 if (i <= NI_660X_MAX_SRC_PIN)
 598                         break;
 599                 ni_660x_clock = 0;
 600                 BUG();
 601                 break;
 602         }
 603         return Gi_Source_Select_Bits(ni_660x_clock);
 604 }
 605
 606 static unsigned ni_m_clk_src(unsigned int clock_source)
 607 {
 608         unsigned clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 609         unsigned ni_m_series_clock;
 610         unsigned i;
 611
 612         switch (clk_src) {
 613         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 614                 ni_m_series_clock = NI_M_TIMEBASE_1_CLK;
 615                 break;
 616         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 617                 ni_m_series_clock = NI_M_TIMEBASE_2_CLK;
 618                 break;
 619         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 620                 ni_m_series_clock = NI_M_TIMEBASE_3_CLK;
 621                 break;
 622         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 623                 ni_m_series_clock = NI_M_LOGIC_LOW_CLK;
 624                 break;
 625         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 626                 ni_m_series_clock = NI_M_NEXT_GATE_CLK;
 627                 break;
 628         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 629                 ni_m_series_clock = NI_M_NEXT_TC_CLK;
 630                 break;
 631         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 632                 ni_m_series_clock = NI_M_PXI10_CLK;
 633                 break;
 634         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 635                 ni_m_series_clock = NI_M_PXI_STAR_TRIGGER_CLK;
 636                 break;
 637         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 638                 ni_m_series_clock = NI_M_ANALOG_TRIGGER_OUT_CLK;
 639                 break;
 640         default:
 641                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 642                         if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 643                                 ni_m_series_clock = NI_M_RTSI_CLK(i);
 644                                 break;
 645                         }
 646                 }
 647                 if (i <= NI_M_MAX_RTSI_CHAN)
 648                         break;
 649                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 650                         if (clk_src == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
 651                                 ni_m_series_clock = NI_M_PFI_CLK(i);
 652                                 break;
 653                         }
 654                 }
 655                 if (i <= NI_M_MAX_PFI_CHAN)
 656                         break;
 657                 pr_err("invalid clock source 0x%lx\n",
 658                        (unsigned long)clock_source);
 659                 BUG();
 660                 ni_m_series_clock = 0;
 661                 break;
 662         }
 663         return Gi_Source_Select_Bits(ni_m_series_clock);
 664 };
 665
 666 static void ni_tio_set_source_subselect(struct ni_gpct *counter,
 667                                         unsigned int clock_source)
 668 {
 669         struct ni_gpct_device *counter_dev = counter->counter_dev;
 670         unsigned cidx = counter->counter_index;
 671         const unsigned second_gate_reg = NITIO_GATE2_REG(cidx);
 672
 673         if (counter_dev->variant != ni_gpct_variant_m_series)
 674                 return;
 675         switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 676                 /* Gi_Source_Subselect is zero */
 677         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 678         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 679                 counter_dev->regs[second_gate_reg] &= ~Gi_Source_Subselect_Bit;
 680                 break;
 681                 /* Gi_Source_Subselect is one */
 682         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 683         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 684                 counter_dev->regs[second_gate_reg] |= Gi_Source_Subselect_Bit;
 685                 break;
 686                 /* Gi_Source_Subselect doesn't matter */
 687         default:
 688                 return;
 689         }
 690         write_register(counter, counter_dev->regs[second_gate_reg],
 691                        second_gate_reg);
 692 }
 693
 694 static int ni_tio_set_clock_src(struct ni_gpct *counter,
 695                                 unsigned int clock_source,
 696                                 unsigned int period_ns)
 697 {
 698         struct ni_gpct_device *counter_dev = counter->counter_dev;
 699         unsigned cidx = counter->counter_index;
 700         unsigned bits = 0;
 701
 702         /* FIXME: validate clock source */
 703         switch (counter_dev->variant) {
 704         case ni_gpct_variant_660x:
 705                 bits |= ni_660x_clk_src(clock_source);
 706                 break;
 707         case ni_gpct_variant_e_series:
 708         case ni_gpct_variant_m_series:
 709         default:
 710                 bits |= ni_m_clk_src(clock_source);
 711                 break;
 712         }
 713         if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
 714                 bits |= Gi_Source_Polarity_Bit;
 715         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 716                         Gi_Source_Select_Mask | Gi_Source_Polarity_Bit, bits);
 717         ni_tio_set_source_subselect(counter, clock_source);
 718
 719         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 720                 bits = 0;
 721                 switch (clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
 722                 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 723                         break;
 724                 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 725                         bits |= GI_PRESCALE_X2(counter_dev->variant);
 726                         break;
 727                 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 728                         bits |= GI_PRESCALE_X8(counter_dev->variant);
 729                         break;
 730                 default:
 731                         return -EINVAL;
 732                 }
 733                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 734                                 GI_PRESCALE_X2(counter_dev->variant) |
 735                                 GI_PRESCALE_X8(counter_dev->variant), bits);
 736         }
 737         counter->clock_period_ps = period_ns * 1000;
 738         ni_tio_set_sync_mode(counter, 0);
 739         return 0;
 740 }
 741
 742 static void ni_tio_get_clock_src(struct ni_gpct *counter,
 743                                  unsigned int *clock_source,
 744                                  unsigned int *period_ns)
 745 {
 746         uint64_t temp64;
 747
 748         *clock_source = ni_tio_generic_clock_src_select(counter);
 749         temp64 = ni_tio_clock_period_ps(counter, *clock_source);
 750         do_div(temp64, 1000);   /* ps to ns */
 751         *period_ns = temp64;
 752 }
 753
 754 static int ni_660x_set_gate(struct ni_gpct *counter, unsigned int gate_source)
 755 {
 756         unsigned int chan = CR_CHAN(gate_source);
 757         unsigned cidx = counter->counter_index;
 758         unsigned gate_sel;
 759         unsigned i;
 760
 761         switch (chan) {
 762         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 763                 gate_sel = NI_660X_NEXT_SRC_GATE_SEL;
 764                 break;
 765         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 766         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 767         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
 768         case NI_GPCT_GATE_PIN_i_GATE_SELECT:
 769                 gate_sel = chan & 0x1f;
 770                 break;
 771         default:
 772                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 773                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 774                                 gate_sel = chan & 0x1f;
 775                                 break;
 776                         }
 777                 }
 778                 if (i <= NI_660X_MAX_RTSI_CHAN)
 779                         break;
 780                 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
 781                         if (chan == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
 782                                 gate_sel = chan & 0x1f;
 783                                 break;
 784                         }
 785                 }
 786                 if (i <= NI_660X_MAX_GATE_PIN)
 787                         break;
 788                 return -EINVAL;
 789         }
 790         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 791                         Gi_Gate_Select_Mask, Gi_Gate_Select_Bits(gate_sel));
 792         return 0;
 793 }
 794
 795 static int ni_m_set_gate(struct ni_gpct *counter, unsigned int gate_source)
 796 {
 797         unsigned int chan = CR_CHAN(gate_source);
 798         unsigned cidx = counter->counter_index;
 799         unsigned gate_sel;
 800         unsigned i;
 801
 802         switch (chan) {
 803         case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
 804         case NI_GPCT_AI_START2_GATE_SELECT:
 805         case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
 806         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 807         case NI_GPCT_AI_START1_GATE_SELECT:
 808         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 809         case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
 810         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 811                 gate_sel = chan & 0x1f;
 812                 break;
 813         default:
 814                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 815                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 816                                 gate_sel = chan & 0x1f;
 817                                 break;
 818                         }
 819                 }
 820                 if (i <= NI_M_MAX_RTSI_CHAN)
 821                         break;
 822                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 823                         if (chan == NI_GPCT_PFI_GATE_SELECT(i)) {
 824                                 gate_sel = chan & 0x1f;
 825                                 break;
 826                         }
 827                 }
 828                 if (i <= NI_M_MAX_PFI_CHAN)
 829                         break;
 830                 return -EINVAL;
 831         }
 832         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 833                         Gi_Gate_Select_Mask, Gi_Gate_Select_Bits(gate_sel));
 834         return 0;
 835 }
 836
 837 static int ni_660x_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
 838 {
 839         struct ni_gpct_device *counter_dev = counter->counter_dev;
 840         unsigned cidx = counter->counter_index;
 841         unsigned int chan = CR_CHAN(gate_source);
 842         unsigned gate2_reg = NITIO_GATE2_REG(cidx);
 843         unsigned gate2_sel;
 844         unsigned i;
 845
 846         switch (chan) {
 847         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
 848         case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
 849         case NI_GPCT_SELECTED_GATE_GATE_SELECT:
 850         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 851         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 852                 gate2_sel = chan & 0x1f;
 853                 break;
 854         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 855                 gate2_sel = NI_660X_NEXT_SRC_GATE2_SEL;
 856                 break;
 857         default:
 858                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 859                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 860                                 gate2_sel = chan & 0x1f;
 861                                 break;
 862                         }
 863                 }
 864                 if (i <= NI_660X_MAX_RTSI_CHAN)
 865                         break;
 866                 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
 867                         if (chan == NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
 868                                 gate2_sel = chan & 0x1f;
 869                                 break;
 870                         }
 871                 }
 872                 if (i <= NI_660X_MAX_UP_DOWN_PIN)
 873                         break;
 874                 return -EINVAL;
 875         }
 876         counter_dev->regs[gate2_reg] |= Gi_Second_Gate_Mode_Bit;
 877         counter_dev->regs[gate2_reg] &= ~Gi_Second_Gate_Select_Mask;
 878         counter_dev->regs[gate2_reg] |= Gi_Second_Gate_Select_Bits(gate2_sel);
 879         write_register(counter, counter_dev->regs[gate2_reg], gate2_reg);
 880         return 0;
 881 }
 882
 883 static int ni_m_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
 884 {
 885         struct ni_gpct_device *counter_dev = counter->counter_dev;
 886         unsigned cidx = counter->counter_index;
 887         unsigned int chan = CR_CHAN(gate_source);
 888         unsigned gate2_reg = NITIO_GATE2_REG(cidx);
 889         unsigned gate2_sel;
 890
 891         /*
 892          * FIXME: We don't know what the m-series second gate codes are,
 893          * so we'll just pass the bits through for now.
 894          */
 895         switch (chan) {
 896         default:
 897                 gate2_sel = chan & 0x1f;
 898                 break;
 899         }
 900         counter_dev->regs[gate2_reg] |= Gi_Second_Gate_Mode_Bit;
 901         counter_dev->regs[gate2_reg] &= ~Gi_Second_Gate_Select_Mask;
 902         counter_dev->regs[gate2_reg] |= Gi_Second_Gate_Select_Bits(gate2_sel);
 903         write_register(counter, counter_dev->regs[gate2_reg], gate2_reg);
 904         return 0;
 905 }
 906
 907 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
 908                         unsigned int gate_source)
 909 {
 910         struct ni_gpct_device *counter_dev = counter->counter_dev;
 911         unsigned cidx = counter->counter_index;
 912         unsigned int chan = CR_CHAN(gate_source);
 913         unsigned gate2_reg = NITIO_GATE2_REG(cidx);
 914         unsigned mode = 0;
 915
 916         switch (gate_index) {
 917         case 0:
 918                 if (chan == NI_GPCT_DISABLED_GATE_SELECT) {
 919                         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 920                                         Gi_Gating_Mode_Mask,
 921                                         Gi_Gating_Disabled_Bits);
 922                         return 0;
 923                 }
 924                 if (gate_source & CR_INVERT)
 925                         mode |= Gi_Gate_Polarity_Bit;
 926                 if (gate_source & CR_EDGE)
 927                         mode |= Gi_Rising_Edge_Gating_Bits;
 928                 else
 929                         mode |= Gi_Level_Gating_Bits;
 930                 ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 931                                 Gi_Gate_Polarity_Bit | Gi_Gating_Mode_Mask,
 932                                 mode);
 933                 switch (counter_dev->variant) {
 934                 case ni_gpct_variant_e_series:
 935                 case ni_gpct_variant_m_series:
 936                 default:
 937                         return ni_m_set_gate(counter, gate_source);
 938                 case ni_gpct_variant_660x:
 939                         return ni_660x_set_gate(counter, gate_source);
 940                 }
 941                 break;
 942         case 1:
 943                 if (!ni_tio_has_gate2_registers(counter_dev))
 944                         return -EINVAL;
 945
 946                 if (chan == NI_GPCT_DISABLED_GATE_SELECT) {
 947                         counter_dev->regs[gate2_reg] &=
 948                                                 ~Gi_Second_Gate_Mode_Bit;
 949                         write_register(counter, counter_dev->regs[gate2_reg],
 950                                        gate2_reg);
 951                         return 0;
 952                 }
 953                 if (gate_source & CR_INVERT) {
 954                         counter_dev->regs[gate2_reg] |=
 955                                                 Gi_Second_Gate_Polarity_Bit;
 956                 } else {
 957                         counter_dev->regs[gate2_reg] &=
 958                                                 ~Gi_Second_Gate_Polarity_Bit;
 959                 }
 960                 switch (counter_dev->variant) {
 961                 case ni_gpct_variant_m_series:
 962                         return ni_m_set_gate2(counter, gate_source);
 963                 case ni_gpct_variant_660x:
 964                         return ni_660x_set_gate2(counter, gate_source);
 965                 default:
 966                         BUG();
 967                         break;
 968                 }
 969                 break;
 970         default:
 971                 return -EINVAL;
 972         }
 973         return 0;
 974 }
 975 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
 976
 977 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned index,
 978                                 unsigned int source)
 979 {
 980         struct ni_gpct_device *counter_dev = counter->counter_dev;
 981         unsigned cidx = counter->counter_index;
 982         unsigned int abz_reg, shift, mask;
 983
 984         if (counter_dev->variant != ni_gpct_variant_m_series)
 985                 return -EINVAL;
 986
 987         abz_reg = NITIO_ABZ_REG(cidx);
 988         switch (index) {
 989         case NI_GPCT_SOURCE_ENCODER_A:
 990                 shift = 10;
 991                 break;
 992         case NI_GPCT_SOURCE_ENCODER_B:
 993                 shift = 5;
 994                 break;
 995         case NI_GPCT_SOURCE_ENCODER_Z:
 996                 shift = 0;
 997                 break;
 998         default:
 999                 return -EINVAL;
1000         }
1001         mask = 0x1f << shift;
1002         if (source > 0x1f)
1003                 source = 0x1f;  /* Disable gate */
1004
1005         counter_dev->regs[abz_reg] &= ~mask;
1006         counter_dev->regs[abz_reg] |= (source << shift) & mask;
1007         write_register(counter, counter_dev->regs[abz_reg], abz_reg);
1008         return 0;
1009 }
1010
1011 static unsigned ni_660x_gate_to_generic_gate(unsigned gate)
1012 {
1013         unsigned i;
1014
1015         switch (gate) {
1016         case NI_660X_SRC_PIN_I_GATE_SEL:
1017                 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1018         case NI_660X_GATE_PIN_I_GATE_SEL:
1019                 return NI_GPCT_GATE_PIN_i_GATE_SELECT;
1020         case NI_660X_NEXT_SRC_GATE_SEL:
1021                 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1022         case NI_660X_NEXT_OUT_GATE_SEL:
1023                 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1024         case NI_660X_LOGIC_LOW_GATE_SEL:
1025                 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1026         default:
1027                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1028                         if (gate == NI_660X_RTSI_GATE_SEL(i))
1029                                 return NI_GPCT_RTSI_GATE_SELECT(i);
1030                 }
1031                 if (i <= NI_660X_MAX_RTSI_CHAN)
1032                         break;
1033                 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
1034                         if (gate == NI_660X_PIN_GATE_SEL(i))
1035                                 return NI_GPCT_GATE_PIN_GATE_SELECT(i);
1036                 }
1037                 if (i <= NI_660X_MAX_GATE_PIN)
1038                         break;
1039                 BUG();
1040                 break;
1041         }
1042         return 0;
1043 };
1044
1045 static unsigned ni_m_gate_to_generic_gate(unsigned gate)
1046 {
1047         unsigned i;
1048
1049         switch (gate) {
1050         case NI_M_TIMESTAMP_MUX_GATE_SEL:
1051                 return NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1052         case NI_M_AI_START2_GATE_SEL:
1053                 return NI_GPCT_AI_START2_GATE_SELECT;
1054         case NI_M_PXI_STAR_TRIGGER_GATE_SEL:
1055                 return NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1056         case NI_M_NEXT_OUT_GATE_SEL:
1057                 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1058         case NI_M_AI_START1_GATE_SEL:
1059                 return NI_GPCT_AI_START1_GATE_SELECT;
1060         case NI_M_NEXT_SRC_GATE_SEL:
1061                 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1062         case NI_M_ANALOG_TRIG_OUT_GATE_SEL:
1063                 return NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1064         case NI_M_LOGIC_LOW_GATE_SEL:
1065                 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1066         default:
1067                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
1068                         if (gate == NI_M_RTSI_GATE_SEL(i))
1069                                 return NI_GPCT_RTSI_GATE_SELECT(i);
1070                 }
1071                 if (i <= NI_M_MAX_RTSI_CHAN)
1072                         break;
1073                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
1074                         if (gate == NI_M_PFI_GATE_SEL(i))
1075                                 return NI_GPCT_PFI_GATE_SELECT(i);
1076                 }
1077                 if (i <= NI_M_MAX_PFI_CHAN)
1078                         break;
1079                 BUG();
1080                 break;
1081         }
1082         return 0;
1083 };
1084
1085 static unsigned ni_660x_gate2_to_generic_gate(unsigned gate)
1086 {
1087         unsigned i;
1088
1089         switch (gate) {
1090         case NI_660X_SRC_PIN_I_GATE2_SEL:
1091                 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1092         case NI_660X_UD_PIN_I_GATE2_SEL:
1093                 return NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1094         case NI_660X_NEXT_SRC_GATE2_SEL:
1095                 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1096         case NI_660X_NEXT_OUT_GATE2_SEL:
1097                 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1098         case NI_660X_SELECTED_GATE2_SEL:
1099                 return NI_GPCT_SELECTED_GATE_GATE_SELECT;
1100         case NI_660X_LOGIC_LOW_GATE2_SEL:
1101                 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1102         default:
1103                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1104                         if (gate == NI_660X_RTSI_GATE2_SEL(i))
1105                                 return NI_GPCT_RTSI_GATE_SELECT(i);
1106                 }
1107                 if (i <= NI_660X_MAX_RTSI_CHAN)
1108                         break;
1109                 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
1110                         if (gate == NI_660X_UD_PIN_GATE2_SEL(i))
1111                                 return NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1112                 }
1113                 if (i <= NI_660X_MAX_UP_DOWN_PIN)
1114                         break;
1115                 BUG();
1116                 break;
1117         }
1118         return 0;
1119 };
1120
1121 static unsigned ni_m_gate2_to_generic_gate(unsigned gate)
1122 {
1123         /*
1124          * FIXME: the second gate sources for the m series are undocumented,
1125          * so we just return the raw bits for now.
1126          */
1127         switch (gate) {
1128         default:
1129                 return gate;
1130         }
1131         return 0;
1132 };
1133
1134 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
1135                                unsigned int *gate_source)
1136 {
1137         struct ni_gpct_device *counter_dev = counter->counter_dev;
1138         unsigned cidx = counter->counter_index;
1139         unsigned mode = ni_tio_get_soft_copy(counter, NITIO_MODE_REG(cidx));
1140         unsigned gate2_reg = NITIO_GATE2_REG(cidx);
1141         unsigned gate_sel;
1142
1143         switch (gate_index) {
1144         case 0:
1145                 if ((mode & Gi_Gating_Mode_Mask) == Gi_Gating_Disabled_Bits) {
1146                         *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1147                         return 0;
1148                 }
1149
1150                 gate_sel = ni_tio_get_soft_copy(counter,
1151                                                 NITIO_INPUT_SEL_REG(cidx));
1152                 gate_sel &= Gi_Gate_Select_Mask;
1153                 gate_sel >>= Gi_Gate_Select_Shift;
1154
1155                 switch (counter_dev->variant) {
1156                 case ni_gpct_variant_e_series:
1157                 case ni_gpct_variant_m_series:
1158                 default:
1159                         *gate_source = ni_m_gate_to_generic_gate(gate_sel);
1160                         break;
1161                 case ni_gpct_variant_660x:
1162                         *gate_source = ni_660x_gate_to_generic_gate(gate_sel);
1163                         break;
1164                 }
1165                 if (mode & Gi_Gate_Polarity_Bit)
1166                         *gate_source |= CR_INVERT;
1167                 if ((mode & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
1168                         *gate_source |= CR_EDGE;
1169                 break;
1170         case 1:
1171                 if ((mode & Gi_Gating_Mode_Mask) == Gi_Gating_Disabled_Bits ||
1172                     !(counter_dev->regs[gate2_reg] & Gi_Second_Gate_Mode_Bit)) {
1173                         *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1174                         return 0;
1175                 }
1176
1177                 gate_sel = counter_dev->regs[gate2_reg];
1178                 gate_sel &= Gi_Second_Gate_Select_Mask;
1179                 gate_sel >>= Gi_Second_Gate_Select_Shift;
1180
1181                 switch (counter_dev->variant) {
1182                 case ni_gpct_variant_e_series:
1183                 case ni_gpct_variant_m_series:
1184                 default:
1185                         *gate_source = ni_m_gate2_to_generic_gate(gate_sel);
1186                         break;
1187                 case ni_gpct_variant_660x:
1188                         *gate_source = ni_660x_gate2_to_generic_gate(gate_sel);
1189                         break;
1190                 }
1191                 if (counter_dev->regs[gate2_reg] & Gi_Second_Gate_Polarity_Bit)
1192                         *gate_source |= CR_INVERT;
1193                 /* second gate can't have edge/level mode set independently */
1194                 if ((mode & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
1195                         *gate_source |= CR_EDGE;
1196                 break;
1197         default:
1198                 return -EINVAL;
1199         }
1200         return 0;
1201 }
1202
1203 int ni_tio_insn_config(struct comedi_device *dev,
1204                        struct comedi_subdevice *s,
1205                        struct comedi_insn *insn,
1206                        unsigned int *data)
1207 {
1208         struct ni_gpct *counter = s->private;
1209         unsigned cidx = counter->counter_index;
1210         unsigned status;
1211
1212         switch (data[0]) {
1213         case INSN_CONFIG_SET_COUNTER_MODE:
1214                 return ni_tio_set_counter_mode(counter, data[1]);
1215         case INSN_CONFIG_ARM:
1216                 return ni_tio_arm(counter, 1, data[1]);
1217         case INSN_CONFIG_DISARM:
1218                 ni_tio_arm(counter, 0, 0);
1219                 return 0;
1220         case INSN_CONFIG_GET_COUNTER_STATUS:
1221                 data[1] = 0;
1222                 status = read_register(counter, NITIO_SHARED_STATUS_REG(cidx));
1223                 if (status & Gi_Armed_Bit(cidx)) {
1224                         data[1] |= COMEDI_COUNTER_ARMED;
1225                         if (status & Gi_Counting_Bit(cidx))
1226                                 data[1] |= COMEDI_COUNTER_COUNTING;
1227                 }
1228                 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
1229                 return 0;
1230         case INSN_CONFIG_SET_CLOCK_SRC:
1231                 return ni_tio_set_clock_src(counter, data[1], data[2]);
1232         case INSN_CONFIG_GET_CLOCK_SRC:
1233                 ni_tio_get_clock_src(counter, &data[1], &data[2]);
1234                 return 0;
1235         case INSN_CONFIG_SET_GATE_SRC:
1236                 return ni_tio_set_gate_src(counter, data[1], data[2]);
1237         case INSN_CONFIG_GET_GATE_SRC:
1238                 return ni_tio_get_gate_src(counter, data[1], &data[2]);
1239         case INSN_CONFIG_SET_OTHER_SRC:
1240                 return ni_tio_set_other_src(counter, data[1], data[2]);
1241         case INSN_CONFIG_RESET:
1242                 ni_tio_reset_count_and_disarm(counter);
1243                 return 0;
1244         default:
1245                 break;
1246         }
1247         return -EINVAL;
1248 }
1249 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1250
1251 static unsigned int ni_tio_read_sw_save_reg(struct comedi_device *dev,
1252                                             struct comedi_subdevice *s)
1253 {
1254         struct ni_gpct *counter = s->private;
1255         unsigned cidx = counter->counter_index;
1256         unsigned int val;
1257
1258         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), Gi_Save_Trace_Bit, 0);
1259         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1260                         Gi_Save_Trace_Bit, Gi_Save_Trace_Bit);
1261
1262         /*
1263          * The count doesn't get latched until the next clock edge, so it is
1264          * possible the count may change (once) while we are reading. Since
1265          * the read of the SW_Save_Reg isn't atomic (apparently even when it's
1266          * a 32 bit register according to 660x docs), we need to read twice
1267          * and make sure the reading hasn't changed. If it has, a third read
1268          * will be correct since the count value will definitely have latched
1269          * by then.
1270          */
1271         val = read_register(counter, NITIO_SW_SAVE_REG(cidx));
1272         if (val != read_register(counter, NITIO_SW_SAVE_REG(cidx)))
1273                 val = read_register(counter, NITIO_SW_SAVE_REG(cidx));
1274
1275         return val;
1276 }
1277
1278 int ni_tio_insn_read(struct comedi_device *dev,
1279                      struct comedi_subdevice *s,
1280                      struct comedi_insn *insn,
1281                      unsigned int *data)
1282 {
1283         struct ni_gpct *counter = s->private;
1284         struct ni_gpct_device *counter_dev = counter->counter_dev;
1285         unsigned int channel = CR_CHAN(insn->chanspec);
1286         unsigned cidx = counter->counter_index;
1287         int i;
1288
1289         for (i = 0; i < insn->n; i++) {
1290                 switch (channel) {
1291                 case 0:
1292                         data[i] = ni_tio_read_sw_save_reg(dev, s);
1293                         break;
1294                 case 1:
1295                         data[i] = counter_dev->regs[NITIO_LOADA_REG(cidx)];
1296                         break;
1297                 case 2:
1298                         data[i] = counter_dev->regs[NITIO_LOADB_REG(cidx)];
1299                         break;
1300                 }
1301         }
1302         return insn->n;
1303 }
1304 EXPORT_SYMBOL_GPL(ni_tio_insn_read);
1305
1306 static unsigned ni_tio_next_load_register(struct ni_gpct *counter)
1307 {
1308         unsigned cidx = counter->counter_index;
1309         const unsigned bits =
1310                 read_register(counter, NITIO_SHARED_STATUS_REG(cidx));
1311
1312         return (bits & Gi_Next_Load_Source_Bit(cidx))
1313                         ? NITIO_LOADB_REG(cidx)
1314                         : NITIO_LOADA_REG(cidx);
1315 }
1316
1317 int ni_tio_insn_write(struct comedi_device *dev,
1318                       struct comedi_subdevice *s,
1319                       struct comedi_insn *insn,
1320                       unsigned int *data)
1321 {
1322         struct ni_gpct *counter = s->private;
1323         struct ni_gpct_device *counter_dev = counter->counter_dev;
1324         const unsigned channel = CR_CHAN(insn->chanspec);
1325         unsigned cidx = counter->counter_index;
1326         unsigned load_reg;
1327
1328         if (insn->n < 1)
1329                 return 0;
1330         switch (channel) {
1331         case 0:
1332                 /*
1333                  * Unsafe if counter is armed.
1334                  * Should probably check status and return -EBUSY if armed.
1335                  */
1336
1337                 /*
1338                  * Don't disturb load source select, just use whichever
1339                  * load register is already selected.
1340                  */
1341                 load_reg = ni_tio_next_load_register(counter);
1342                 write_register(counter, data[0], load_reg);
1343                 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
1344                                           0, 0, Gi_Load_Bit);
1345                 /* restore load reg */
1346                 write_register(counter, counter_dev->regs[load_reg], load_reg);
1347                 break;
1348         case 1:
1349                 counter_dev->regs[NITIO_LOADA_REG(cidx)] = data[0];
1350                 write_register(counter, data[0], NITIO_LOADA_REG(cidx));
1351                 break;
1352         case 2:
1353                 counter_dev->regs[NITIO_LOADB_REG(cidx)] = data[0];
1354                 write_register(counter, data[0], NITIO_LOADB_REG(cidx));
1355                 break;
1356         default:
1357                 return -EINVAL;
1358         }
1359         return 0;
1360 }
1361 EXPORT_SYMBOL_GPL(ni_tio_insn_write);
1362
1363 void ni_tio_init_counter(struct ni_gpct *counter)
1364 {
1365         struct ni_gpct_device *counter_dev = counter->counter_dev;
1366         unsigned cidx = counter->counter_index;
1367
1368         ni_tio_reset_count_and_disarm(counter);
1369
1370         /* initialize counter registers */
1371         counter_dev->regs[NITIO_AUTO_INC_REG(cidx)] = 0x0;
1372         write_register(counter, 0x0, NITIO_AUTO_INC_REG(cidx));
1373
1374         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1375                         ~0, Gi_Synchronize_Gate_Bit);
1376
1377         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ~0, 0);
1378
1379         counter_dev->regs[NITIO_LOADA_REG(cidx)] = 0x0;
1380         write_register(counter, 0x0, NITIO_LOADA_REG(cidx));
1381
1382         counter_dev->regs[NITIO_LOADB_REG(cidx)] = 0x0;
1383         write_register(counter, 0x0, NITIO_LOADB_REG(cidx));
1384
1385         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ~0, 0);
1386
1387         if (ni_tio_counting_mode_registers_present(counter_dev))
1388                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ~0, 0);
1389
1390         if (ni_tio_has_gate2_registers(counter_dev)) {
1391                 counter_dev->regs[NITIO_GATE2_REG(cidx)] = 0x0;
1392                 write_register(counter, 0x0, NITIO_GATE2_REG(cidx));
1393         }
1394
1395         ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), ~0, 0x0);
1396
1397         ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ~0, 0x0);
1398 }
1399 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
1400
1401 struct ni_gpct_device *
1402 ni_gpct_device_construct(struct comedi_device *dev,
1403                          void (*write_register)(struct ni_gpct *counter,
1404                                                 unsigned bits,
1405                                                 enum ni_gpct_register reg),
1406                          unsigned (*read_register)(struct ni_gpct *counter,
1407                                                    enum ni_gpct_register reg),
1408                          enum ni_gpct_variant variant,
1409                          unsigned num_counters)
1410 {
1411         struct ni_gpct_device *counter_dev;
1412         struct ni_gpct *counter;
1413         unsigned i;
1414
1415         if (num_counters == 0)
1416                 return NULL;
1417
1418         counter_dev = kzalloc(sizeof(*counter_dev), GFP_KERNEL);
1419         if (!counter_dev)
1420                 return NULL;
1421
1422         counter_dev->dev = dev;
1423         counter_dev->write_register = write_register;
1424         counter_dev->read_register = read_register;
1425         counter_dev->variant = variant;
1426
1427         spin_lock_init(&counter_dev->regs_lock);
1428
1429         counter_dev->counters = kcalloc(num_counters, sizeof(*counter),
1430                                         GFP_KERNEL);
1431         if (!counter_dev->counters) {
1432                 kfree(counter_dev);
1433                 return NULL;
1434         }
1435
1436         for (i = 0; i < num_counters; ++i) {
1437                 counter = &counter_dev->counters[i];
1438                 counter->counter_dev = counter_dev;
1439                 spin_lock_init(&counter->lock);
1440         }
1441         counter_dev->num_counters = num_counters;
1442
1443         return counter_dev;
1444 }
1445 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
1446
1447 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
1448 {
1449         if (!counter_dev->counters)
1450                 return;
1451         kfree(counter_dev->counters);
1452         kfree(counter_dev);
1453 }
1454 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
1455
1456 static int __init ni_tio_init_module(void)
1457 {
1458         return 0;
1459 }
1460 module_init(ni_tio_init_module);
1461
1462 static void __exit ni_tio_cleanup_module(void)
1463 {
1464 }
1465 module_exit(ni_tio_cleanup_module);
1466
1467 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
1468 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
1469 MODULE_LICENSE("GPL");