2 * comedi/drivers/rtd520.c
3 * Comedi driver for Real Time Devices (RTD) PCI4520/DM7520
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 2001 David A. Schleef <ds@schleef.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
21 * Description: Real Time Devices PCI4520/DM7520
22 * Devices: (Real Time Devices) DM7520HR-1 [DM7520]
23 * (Real Time Devices) DM7520HR-8 [DM7520]
24 * (Real Time Devices) PCI4520 [PCI4520]
25 * (Real Time Devices) PCI4520-8 [PCI4520]
26 * Author: Dan Christian
27 * Status: Works. Only tested on DM7520-8. Not SMP safe.
29 * Configuration options: not applicable, uses PCI auto config
33 * Created by Dan Christian, NASA Ames Research Center.
35 * The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
37 * 8/16 12 bit ADC with FIFO and channel gain table
38 * 8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
39 * 8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
40 * 2 12 bit DACs with FIFOs
44 * timers: ADC sample, pacer, burst, about, delay, DA1, DA2
46 * 3 user timer/counters (8254)
49 * The DM7520 has slightly fewer features (fewer gain steps).
51 * These boards can support external multiplexors and multi-board
52 * synchronization, but this driver doesn't support that.
54 * Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
55 * Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
56 * Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
57 * Call them and ask for the register level manual.
58 * PCI chip: http://www.plxtech.com/products/io/pci9080
61 * This board is memory mapped. There is some IO stuff, but it isn't needed.
63 * I use a pretty loose naming style within the driver (rtd_blah).
64 * All externally visible names should be rtd520_blah.
65 * I use camelCase for structures (and inside them).
66 * I may also use upper CamelCase for function names (old habit).
68 * This board is somewhat related to the RTD PCI4400 board.
70 * I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
71 * das1800, since they have the best documented code. Driver cb_pcidas64.c
72 * uses the same DMA controller.
74 * As far as I can tell, the About interrupt doesn't work if Sample is
75 * also enabled. It turns out that About really isn't needed, since
76 * we always count down samples read.
78 * There was some timer/counter code, but it didn't follow the right API.
84 * Analog-In supports instruction and command mode.
86 * With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
87 * (single channel, 64K read buffer). I get random system lockups when
88 * using DMA with ALI-15xx based systems. I haven't been able to test
89 * any other chipsets. The lockups happen soon after the start of an
90 * acquistion, not in the middle of a long run.
92 * Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
93 * (with a 256K read buffer).
95 * Digital-IO and Analog-Out only support instruction mode.
98 #include <linux/module.h>
99 #include <linux/pci.h>
100 #include <linux/delay.h>
101 #include <linux/interrupt.h>
103 #include "../comedidev.h"
105 #include "comedi_fc.h"
109 * Local Address Space 0 Offsets
111 #define LAS0_USER_IO 0x0008 /* User I/O */
112 #define LAS0_ADC 0x0010 /* FIFO Status/Software A/D Start */
113 #define FS_DAC1_NOT_EMPTY (1 << 0) /* DAC1 FIFO not empty */
114 #define FS_DAC1_HEMPTY (1 << 1) /* DAC1 FIFO half empty */
115 #define FS_DAC1_NOT_FULL (1 << 2) /* DAC1 FIFO not full */
116 #define FS_DAC2_NOT_EMPTY (1 << 4) /* DAC2 FIFO not empty */
117 #define FS_DAC2_HEMPTY (1 << 5) /* DAC2 FIFO half empty */
118 #define FS_DAC2_NOT_FULL (1 << 6) /* DAC2 FIFO not full */
119 #define FS_ADC_NOT_EMPTY (1 << 8) /* ADC FIFO not empty */
120 #define FS_ADC_HEMPTY (1 << 9) /* ADC FIFO half empty */
121 #define FS_ADC_NOT_FULL (1 << 10) /* ADC FIFO not full */
122 #define FS_DIN_NOT_EMPTY (1 << 12) /* DIN FIFO not empty */
123 #define FS_DIN_HEMPTY (1 << 13) /* DIN FIFO half empty */
124 #define FS_DIN_NOT_FULL (1 << 14) /* DIN FIFO not full */
125 #define LAS0_DAC1 0x0014 /* Software D/A1 Update (w) */
126 #define LAS0_DAC2 0x0018 /* Software D/A2 Update (w) */
127 #define LAS0_DAC 0x0024 /* Software Simultaneous Update (w) */
128 #define LAS0_PACER 0x0028 /* Software Pacer Start/Stop */
129 #define LAS0_TIMER 0x002c /* Timer Status/HDIN Software Trig. */
130 #define LAS0_IT 0x0030 /* Interrupt Status/Enable */
131 #define IRQM_ADC_FIFO_WRITE (1 << 0) /* ADC FIFO Write */
132 #define IRQM_CGT_RESET (1 << 1) /* Reset CGT */
133 #define IRQM_CGT_PAUSE (1 << 3) /* Pause CGT */
134 #define IRQM_ADC_ABOUT_CNT (1 << 4) /* About Counter out */
135 #define IRQM_ADC_DELAY_CNT (1 << 5) /* Delay Counter out */
136 #define IRQM_ADC_SAMPLE_CNT (1 << 6) /* ADC Sample Counter */
137 #define IRQM_DAC1_UCNT (1 << 7) /* DAC1 Update Counter */
138 #define IRQM_DAC2_UCNT (1 << 8) /* DAC2 Update Counter */
139 #define IRQM_UTC1 (1 << 9) /* User TC1 out */
140 #define IRQM_UTC1_INV (1 << 10) /* User TC1 out, inverted */
141 #define IRQM_UTC2 (1 << 11) /* User TC2 out */
142 #define IRQM_DIGITAL_IT (1 << 12) /* Digital Interrupt */
143 #define IRQM_EXTERNAL_IT (1 << 13) /* External Interrupt */
144 #define IRQM_ETRIG_RISING (1 << 14) /* Ext Trigger rising-edge */
145 #define IRQM_ETRIG_FALLING (1 << 15) /* Ext Trigger falling-edge */
146 #define LAS0_CLEAR 0x0034 /* Clear/Set Interrupt Clear Mask */
147 #define LAS0_OVERRUN 0x0038 /* Pending interrupts/Clear Overrun */
148 #define LAS0_PCLK 0x0040 /* Pacer Clock (24bit) */
149 #define LAS0_BCLK 0x0044 /* Burst Clock (10bit) */
150 #define LAS0_ADC_SCNT 0x0048 /* A/D Sample counter (10bit) */
151 #define LAS0_DAC1_UCNT 0x004c /* D/A1 Update counter (10 bit) */
152 #define LAS0_DAC2_UCNT 0x0050 /* D/A2 Update counter (10 bit) */
153 #define LAS0_DCNT 0x0054 /* Delay counter (16 bit) */
154 #define LAS0_ACNT 0x0058 /* About counter (16 bit) */
155 #define LAS0_DAC_CLK 0x005c /* DAC clock (16bit) */
156 #define LAS0_UTC0 0x0060 /* 8254 TC Counter 0 */
157 #define LAS0_UTC1 0x0064 /* 8254 TC Counter 1 */
158 #define LAS0_UTC2 0x0068 /* 8254 TC Counter 2 */
159 #define LAS0_UTC_CTRL 0x006c /* 8254 TC Control */
160 #define LAS0_DIO0 0x0070 /* Digital I/O Port 0 */
161 #define LAS0_DIO1 0x0074 /* Digital I/O Port 1 */
162 #define LAS0_DIO0_CTRL 0x0078 /* Digital I/O Control */
163 #define LAS0_DIO_STATUS 0x007c /* Digital I/O Status */
164 #define LAS0_BOARD_RESET 0x0100 /* Board reset */
165 #define LAS0_DMA0_SRC 0x0104 /* DMA 0 Sources select */
166 #define LAS0_DMA1_SRC 0x0108 /* DMA 1 Sources select */
167 #define LAS0_ADC_CONVERSION 0x010c /* A/D Conversion Signal select */
168 #define LAS0_BURST_START 0x0110 /* Burst Clock Start Trigger select */
169 #define LAS0_PACER_START 0x0114 /* Pacer Clock Start Trigger select */
170 #define LAS0_PACER_STOP 0x0118 /* Pacer Clock Stop Trigger select */
171 #define LAS0_ACNT_STOP_ENABLE 0x011c /* About Counter Stop Enable */
172 #define LAS0_PACER_REPEAT 0x0120 /* Pacer Start Trigger Mode select */
173 #define LAS0_DIN_START 0x0124 /* HiSpd DI Sampling Signal select */
174 #define LAS0_DIN_FIFO_CLEAR 0x0128 /* Digital Input FIFO Clear */
175 #define LAS0_ADC_FIFO_CLEAR 0x012c /* A/D FIFO Clear */
176 #define LAS0_CGT_WRITE 0x0130 /* Channel Gain Table Write */
177 #define LAS0_CGL_WRITE 0x0134 /* Channel Gain Latch Write */
178 #define LAS0_CG_DATA 0x0138 /* Digital Table Write */
179 #define LAS0_CGT_ENABLE 0x013c /* Channel Gain Table Enable */
180 #define LAS0_CG_ENABLE 0x0140 /* Digital Table Enable */
181 #define LAS0_CGT_PAUSE 0x0144 /* Table Pause Enable */
182 #define LAS0_CGT_RESET 0x0148 /* Reset Channel Gain Table */
183 #define LAS0_CGT_CLEAR 0x014c /* Clear Channel Gain Table */
184 #define LAS0_DAC1_CTRL 0x0150 /* D/A1 output type/range */
185 #define LAS0_DAC1_SRC 0x0154 /* D/A1 update source */
186 #define LAS0_DAC1_CYCLE 0x0158 /* D/A1 cycle mode */
187 #define LAS0_DAC1_RESET 0x015c /* D/A1 FIFO reset */
188 #define LAS0_DAC1_FIFO_CLEAR 0x0160 /* D/A1 FIFO clear */
189 #define LAS0_DAC2_CTRL 0x0164 /* D/A2 output type/range */
190 #define LAS0_DAC2_SRC 0x0168 /* D/A2 update source */
191 #define LAS0_DAC2_CYCLE 0x016c /* D/A2 cycle mode */
192 #define LAS0_DAC2_RESET 0x0170 /* D/A2 FIFO reset */
193 #define LAS0_DAC2_FIFO_CLEAR 0x0174 /* D/A2 FIFO clear */
194 #define LAS0_ADC_SCNT_SRC 0x0178 /* A/D Sample Counter Source select */
195 #define LAS0_PACER_SELECT 0x0180 /* Pacer Clock select */
196 #define LAS0_SBUS0_SRC 0x0184 /* SyncBus 0 Source select */
197 #define LAS0_SBUS0_ENABLE 0x0188 /* SyncBus 0 enable */
198 #define LAS0_SBUS1_SRC 0x018c /* SyncBus 1 Source select */
199 #define LAS0_SBUS1_ENABLE 0x0190 /* SyncBus 1 enable */
200 #define LAS0_SBUS2_SRC 0x0198 /* SyncBus 2 Source select */
201 #define LAS0_SBUS2_ENABLE 0x019c /* SyncBus 2 enable */
202 #define LAS0_ETRG_POLARITY 0x01a4 /* Ext. Trigger polarity select */
203 #define LAS0_EINT_POLARITY 0x01a8 /* Ext. Interrupt polarity select */
204 #define LAS0_UTC0_CLOCK 0x01ac /* UTC0 Clock select */
205 #define LAS0_UTC0_GATE 0x01b0 /* UTC0 Gate select */
206 #define LAS0_UTC1_CLOCK 0x01b4 /* UTC1 Clock select */
207 #define LAS0_UTC1_GATE 0x01b8 /* UTC1 Gate select */
208 #define LAS0_UTC2_CLOCK 0x01bc /* UTC2 Clock select */
209 #define LAS0_UTC2_GATE 0x01c0 /* UTC2 Gate select */
210 #define LAS0_UOUT0_SELECT 0x01c4 /* User Output 0 source select */
211 #define LAS0_UOUT1_SELECT 0x01c8 /* User Output 1 source select */
212 #define LAS0_DMA0_RESET 0x01cc /* DMA0 Request state machine reset */
213 #define LAS0_DMA1_RESET 0x01d0 /* DMA1 Request state machine reset */
216 * Local Address Space 1 Offsets
218 #define LAS1_ADC_FIFO 0x0000 /* A/D FIFO (16bit) */
219 #define LAS1_HDIO_FIFO 0x0004 /* HiSpd DI FIFO (16bit) */
220 #define LAS1_DAC1_FIFO 0x0008 /* D/A1 FIFO (16bit) */
221 #define LAS1_DAC2_FIFO 0x000c /* D/A2 FIFO (16bit) */
223 /*======================================================================
224 Driver specific stuff (tunable)
225 ======================================================================*/
227 /* We really only need 2 buffers. More than that means being much
228 smarter about knowing which ones are full. */
229 #define DMA_CHAIN_COUNT 2 /* max DMA segments/buffers in a ring (min 2) */
231 /* Target period for periodic transfers. This sets the user read latency. */
232 /* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
233 /* If this is too low, efficiency is poor */
234 #define TRANS_TARGET_PERIOD 10000000 /* 10 ms (in nanoseconds) */
236 /* Set a practical limit on how long a list to support (affects memory use) */
237 /* The board support a channel list up to the FIFO length (1K or 8K) */
238 #define RTD_MAX_CHANLIST 128 /* max channel list that we allow */
240 /*======================================================================
242 ======================================================================*/
244 #define RTD_CLOCK_RATE 8000000 /* 8Mhz onboard clock */
245 #define RTD_CLOCK_BASE 125 /* clock period in ns */
247 /* Note: these speed are slower than the spec, but fit the counter resolution*/
248 #define RTD_MAX_SPEED 1625 /* when sampling, in nanoseconds */
249 /* max speed if we don't have to wait for settling */
250 #define RTD_MAX_SPEED_1 875 /* if single channel, in nanoseconds */
252 #define RTD_MIN_SPEED 2097151875 /* (24bit counter) in nanoseconds */
253 /* min speed when only 1 channel (no burst counter) */
254 #define RTD_MIN_SPEED_1 5000000 /* 200Hz, in nanoseconds */
256 /* Setup continuous ring of 1/2 FIFO transfers. See RTD manual p91 */
257 #define DMA_MODE_BITS (\
258 PLX_LOCAL_BUS_16_WIDE_BITS \
259 | PLX_DMA_EN_READYIN_BIT \
260 | PLX_DMA_LOCAL_BURST_EN_BIT \
262 | PLX_DMA_INTR_PCI_BIT \
263 | PLX_LOCAL_ADDR_CONST_BIT \
264 | PLX_DEMAND_MODE_BIT)
266 #define DMA_TRANSFER_BITS (\
267 /* descriptors in PCI memory*/ PLX_DESC_IN_PCI_BIT \
268 /* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
269 /* from board to PCI */ | PLX_XFER_LOCAL_TO_PCI)
271 /*======================================================================
272 Comedi specific stuff
273 ======================================================================*/
276 * The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
278 static const struct comedi_lrange rtd_ai_7520_range = {
280 /* +-5V input range gain steps */
287 /* +-10V input range gain steps */
292 BIP_RANGE(10.0 / 16),
293 BIP_RANGE(10.0 / 32),
294 /* +10V input range gain steps */
299 UNI_RANGE(10.0 / 16),
300 UNI_RANGE(10.0 / 32),
304 /* PCI4520 has two more gains (6 more entries) */
305 static const struct comedi_lrange rtd_ai_4520_range = {
307 /* +-5V input range gain steps */
315 BIP_RANGE(5.0 / 128),
316 /* +-10V input range gain steps */
321 BIP_RANGE(10.0 / 16),
322 BIP_RANGE(10.0 / 32),
323 BIP_RANGE(10.0 / 64),
324 BIP_RANGE(10.0 / 128),
325 /* +10V input range gain steps */
330 UNI_RANGE(10.0 / 16),
331 UNI_RANGE(10.0 / 32),
332 UNI_RANGE(10.0 / 64),
333 UNI_RANGE(10.0 / 128),
337 /* Table order matches range values */
338 static const struct comedi_lrange rtd_ao_range = {
352 struct rtd_boardinfo {
354 int range_bip10; /* start of +-10V range */
355 int range_uni10; /* start of +10V range */
356 const struct comedi_lrange *ai_range;
359 static const struct rtd_boardinfo rtd520Boards[] = {
364 .ai_range = &rtd_ai_7520_range,
370 .ai_range = &rtd_ai_4520_range,
375 /* memory mapped board structures */
380 long ai_count; /* total transfer size (samples) */
381 int xfer_count; /* # to transfer data. 0->1/2FIFO */
382 int flags; /* flag event modes */
383 DECLARE_BITMAP(chan_is_bipolar, RTD_MAX_CHANLIST);
384 unsigned int ao_readback[2];
388 /* bit defines for "flags" */
389 #define SEND_EOS 0x01 /* send End Of Scan events */
390 #define DMA0_ACTIVE 0x02 /* DMA0 is active */
391 #define DMA1_ACTIVE 0x04 /* DMA1 is active */
394 Given a desired period and the clock period (both in ns),
395 return the proper counter value (divider-1).
396 Sets the original period to be the true value.
397 Note: you have to check if the value is larger than the counter range!
399 static int rtd_ns_to_timer_base(unsigned int *nanosec,
400 int round_mode, int base)
404 switch (round_mode) {
405 case TRIG_ROUND_NEAREST:
407 divider = (*nanosec + base / 2) / base;
409 case TRIG_ROUND_DOWN:
410 divider = (*nanosec) / base;
413 divider = (*nanosec + base - 1) / base;
417 divider = 2; /* min is divide by 2 */
419 /* Note: we don't check for max, because different timers
420 have different ranges */
422 *nanosec = base * divider;
423 return divider - 1; /* countdown is divisor+1 */
427 Given a desired period (in ns),
428 return the proper counter value (divider-1) for the internal clock.
429 Sets the original period to be the true value.
431 static int rtd_ns_to_timer(unsigned int *ns, int round_mode)
433 return rtd_ns_to_timer_base(ns, round_mode, RTD_CLOCK_BASE);
437 Convert a single comedi channel-gain entry to a RTD520 table entry
439 static unsigned short rtd_convert_chan_gain(struct comedi_device *dev,
440 unsigned int chanspec, int index)
442 const struct rtd_boardinfo *board = comedi_board(dev);
443 struct rtd_private *devpriv = dev->private;
444 unsigned int chan = CR_CHAN(chanspec);
445 unsigned int range = CR_RANGE(chanspec);
446 unsigned int aref = CR_AREF(chanspec);
447 unsigned short r = 0;
451 /* Note: we also setup the channel list bipolar flag array */
452 if (range < board->range_bip10) {
455 r |= (range & 0x7) << 4;
456 __set_bit(index, devpriv->chan_is_bipolar);
457 } else if (range < board->range_uni10) {
460 r |= ((range - board->range_bip10) & 0x7) << 4;
461 __set_bit(index, devpriv->chan_is_bipolar);
465 r |= ((range - board->range_uni10) & 0x7) << 4;
466 __clear_bit(index, devpriv->chan_is_bipolar);
470 case AREF_GROUND: /* on-board ground */
474 r |= 0x80; /* ref external analog common */
478 r |= 0x400; /* differential inputs */
481 case AREF_OTHER: /* ??? */
488 Setup the channel-gain table from a comedi list
490 static void rtd_load_channelgain_list(struct comedi_device *dev,
491 unsigned int n_chan, unsigned int *list)
493 struct rtd_private *devpriv = dev->private;
495 if (n_chan > 1) { /* setup channel gain table */
498 writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
499 writel(1, devpriv->las0 + LAS0_CGT_ENABLE);
500 for (ii = 0; ii < n_chan; ii++) {
501 writel(rtd_convert_chan_gain(dev, list[ii], ii),
502 devpriv->las0 + LAS0_CGT_WRITE);
504 } else { /* just use the channel gain latch */
505 writel(0, devpriv->las0 + LAS0_CGT_ENABLE);
506 writel(rtd_convert_chan_gain(dev, list[0], 0),
507 devpriv->las0 + LAS0_CGL_WRITE);
511 /* determine fifo size by doing adc conversions until the fifo half
512 empty status flag clears */
513 static int rtd520_probe_fifo_depth(struct comedi_device *dev)
515 struct rtd_private *devpriv = dev->private;
516 unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
518 static const unsigned limit = 0x2000;
519 unsigned fifo_size = 0;
521 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
522 rtd_load_channelgain_list(dev, 1, &chanspec);
523 /* ADC conversion trigger source: SOFTWARE */
524 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
525 /* convert samples */
526 for (i = 0; i < limit; ++i) {
527 unsigned fifo_status;
528 /* trigger conversion */
529 writew(0, devpriv->las0 + LAS0_ADC);
531 fifo_status = readl(devpriv->las0 + LAS0_ADC);
532 if ((fifo_status & FS_ADC_HEMPTY) == 0) {
538 dev_info(dev->class_dev, "failed to probe fifo size.\n");
541 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
542 if (fifo_size != 0x400 && fifo_size != 0x2000) {
543 dev_info(dev->class_dev,
544 "unexpected fifo size of %i, expected 1024 or 8192.\n",
551 static int rtd_ai_eoc(struct comedi_device *dev,
552 struct comedi_subdevice *s,
553 struct comedi_insn *insn,
554 unsigned long context)
556 struct rtd_private *devpriv = dev->private;
559 status = readl(devpriv->las0 + LAS0_ADC);
560 if (status & FS_ADC_NOT_EMPTY)
565 static int rtd_ai_rinsn(struct comedi_device *dev,
566 struct comedi_subdevice *s, struct comedi_insn *insn,
569 struct rtd_private *devpriv = dev->private;
573 /* clear any old fifo data */
574 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
576 /* write channel to multiplexer and clear channel gain table */
577 rtd_load_channelgain_list(dev, 1, &insn->chanspec);
579 /* ADC conversion trigger source: SOFTWARE */
580 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
582 /* convert n samples */
583 for (n = 0; n < insn->n; n++) {
585 /* trigger conversion */
586 writew(0, devpriv->las0 + LAS0_ADC);
588 ret = comedi_timeout(dev, s, insn, rtd_ai_eoc, 0);
593 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
594 d = d >> 3; /* low 3 bits are marker lines */
595 if (test_bit(0, devpriv->chan_is_bipolar))
596 /* convert to comedi unsigned data */
597 d = comedi_offset_munge(s, d);
598 data[n] = d & s->maxdata;
601 /* return the number of samples read/written */
606 Get what we know is there.... Fast!
607 This uses 1/2 the bus cycles of read_dregs (below).
609 The manual claims that we can do a lword read, but it doesn't work here.
611 static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
614 struct rtd_private *devpriv = dev->private;
617 for (ii = 0; ii < count; ii++) {
620 if (0 == devpriv->ai_count) { /* done */
621 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
625 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
626 d = d >> 3; /* low 3 bits are marker lines */
627 if (test_bit(s->async->cur_chan, devpriv->chan_is_bipolar))
628 /* convert to comedi unsigned data */
629 d = comedi_offset_munge(s, d);
632 if (!comedi_buf_put(s, d))
635 if (devpriv->ai_count > 0) /* < 0, means read forever */
642 unknown amout of data is waiting in fifo.
644 static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
646 struct rtd_private *devpriv = dev->private;
648 while (readl(devpriv->las0 + LAS0_ADC) & FS_ADC_NOT_EMPTY) {
649 unsigned short d = readw(devpriv->las1 + LAS1_ADC_FIFO);
651 if (0 == devpriv->ai_count) { /* done */
652 continue; /* read rest */
655 d = d >> 3; /* low 3 bits are marker lines */
656 if (test_bit(s->async->cur_chan, devpriv->chan_is_bipolar))
657 /* convert to comedi unsigned data */
658 d = comedi_offset_munge(s, d);
661 if (!comedi_buf_put(s, d))
664 if (devpriv->ai_count > 0) /* < 0, means read forever */
671 Handle all rtd520 interrupts.
672 Runs atomically and is never re-entered.
673 This is a "slow handler"; other interrupts may be active.
674 The data conversion may someday happen in a "bottom half".
676 static irqreturn_t rtd_interrupt(int irq, void *d)
678 struct comedi_device *dev = d;
679 struct comedi_subdevice *s = dev->read_subdev;
680 struct rtd_private *devpriv = dev->private;
688 fifo_status = readl(devpriv->las0 + LAS0_ADC);
689 /* check for FIFO full, this automatically halts the ADC! */
690 if (!(fifo_status & FS_ADC_NOT_FULL)) /* 0 -> full */
693 status = readw(devpriv->las0 + LAS0_IT);
694 /* if interrupt was not caused by our board, or handled above */
698 if (status & IRQM_ADC_ABOUT_CNT) { /* sample count -> read FIFO */
700 * since the priority interrupt controller may have queued
701 * a sample counter interrupt, even though we have already
702 * finished, we must handle the possibility that there is
705 if (!(fifo_status & FS_ADC_HEMPTY)) {
707 if (ai_read_n(dev, s, devpriv->fifosz / 2) < 0)
710 if (0 == devpriv->ai_count)
713 comedi_event(dev, s);
714 } else if (devpriv->xfer_count > 0) {
715 if (fifo_status & FS_ADC_NOT_EMPTY) {
717 if (ai_read_n(dev, s, devpriv->xfer_count) < 0)
720 if (0 == devpriv->ai_count)
723 comedi_event(dev, s);
728 overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
732 /* clear the interrupt */
733 writew(status, devpriv->las0 + LAS0_CLEAR);
734 readw(devpriv->las0 + LAS0_CLEAR);
738 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
739 s->async->events |= COMEDI_CB_ERROR;
740 devpriv->ai_count = 0; /* stop and don't transfer any more */
741 /* fall into xfer_done */
744 /* pacer stop source: SOFTWARE */
745 writel(0, devpriv->las0 + LAS0_PACER_STOP);
746 writel(0, devpriv->las0 + LAS0_PACER); /* stop pacer */
747 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
748 writew(0, devpriv->las0 + LAS0_IT);
750 if (devpriv->ai_count > 0) { /* there shouldn't be anything left */
751 fifo_status = readl(devpriv->las0 + LAS0_ADC);
752 ai_read_dregs(dev, s); /* read anything left in FIFO */
755 s->async->events |= COMEDI_CB_EOA; /* signal end to comedi */
756 comedi_event(dev, s);
758 /* clear the interrupt */
759 status = readw(devpriv->las0 + LAS0_IT);
760 writew(status, devpriv->las0 + LAS0_CLEAR);
761 readw(devpriv->las0 + LAS0_CLEAR);
763 fifo_status = readl(devpriv->las0 + LAS0_ADC);
764 overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
770 cmdtest tests a particular command to see if it is valid.
771 Using the cmdtest ioctl, a user can create a valid cmd
772 and then have it executed by the cmd ioctl (asynchronously).
774 cmdtest returns 1,2,3,4 or 0, depending on which tests
778 static int rtd_ai_cmdtest(struct comedi_device *dev,
779 struct comedi_subdevice *s, struct comedi_cmd *cmd)
784 /* Step 1 : check if triggers are trivially valid */
786 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
787 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
788 TRIG_TIMER | TRIG_EXT);
789 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
790 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
791 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
796 /* Step 2a : make sure trigger sources are unique */
798 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
799 err |= cfc_check_trigger_is_unique(cmd->convert_src);
800 err |= cfc_check_trigger_is_unique(cmd->stop_src);
802 /* Step 2b : and mutually compatible */
807 /* Step 3: check if arguments are trivially valid */
809 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
811 if (cmd->scan_begin_src == TRIG_TIMER) {
812 /* Note: these are time periods, not actual rates */
813 if (1 == cmd->chanlist_len) { /* no scanning */
814 if (cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
816 rtd_ns_to_timer(&cmd->scan_begin_arg,
820 if (cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
822 rtd_ns_to_timer(&cmd->scan_begin_arg,
827 if (cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
829 rtd_ns_to_timer(&cmd->scan_begin_arg,
833 if (cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
835 rtd_ns_to_timer(&cmd->scan_begin_arg,
841 /* external trigger */
842 /* should be level/edge, hi/lo specification here */
843 /* should specify multiple external triggers */
844 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
847 if (cmd->convert_src == TRIG_TIMER) {
848 if (1 == cmd->chanlist_len) { /* no scanning */
849 if (cfc_check_trigger_arg_min(&cmd->convert_arg,
851 rtd_ns_to_timer(&cmd->convert_arg,
855 if (cfc_check_trigger_arg_max(&cmd->convert_arg,
857 rtd_ns_to_timer(&cmd->convert_arg,
862 if (cfc_check_trigger_arg_min(&cmd->convert_arg,
864 rtd_ns_to_timer(&cmd->convert_arg,
868 if (cfc_check_trigger_arg_max(&cmd->convert_arg,
870 rtd_ns_to_timer(&cmd->convert_arg,
876 /* external trigger */
878 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 9);
881 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
883 if (cmd->stop_src == TRIG_COUNT) {
884 /* TODO check for rounding error due to counter wrap */
887 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
894 /* step 4: fix up any arguments */
896 if (cmd->scan_begin_src == TRIG_TIMER) {
897 arg = cmd->scan_begin_arg;
898 rtd_ns_to_timer(&arg, cmd->flags & TRIG_ROUND_MASK);
899 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
902 if (cmd->convert_src == TRIG_TIMER) {
903 arg = cmd->convert_arg;
904 rtd_ns_to_timer(&arg, cmd->flags & TRIG_ROUND_MASK);
905 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, arg);
907 if (cmd->scan_begin_src == TRIG_TIMER) {
908 arg = cmd->convert_arg * cmd->scan_end_arg;
909 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
921 Execute a analog in command with many possible triggering options.
922 The data get stored in the async structure of the subdevice.
923 This is usually done by an interrupt handler.
924 Userland gets to the data using read calls.
926 static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
928 struct rtd_private *devpriv = dev->private;
929 struct comedi_cmd *cmd = &s->async->cmd;
932 /* stop anything currently running */
933 /* pacer stop source: SOFTWARE */
934 writel(0, devpriv->las0 + LAS0_PACER_STOP);
935 writel(0, devpriv->las0 + LAS0_PACER); /* stop pacer */
936 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
937 writew(0, devpriv->las0 + LAS0_IT);
938 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
939 writel(0, devpriv->las0 + LAS0_OVERRUN);
941 /* start configuration */
942 /* load channel list and reset CGT */
943 rtd_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
945 /* setup the common case and override if needed */
946 if (cmd->chanlist_len > 1) {
947 /* pacer start source: SOFTWARE */
948 writel(0, devpriv->las0 + LAS0_PACER_START);
949 /* burst trigger source: PACER */
950 writel(1, devpriv->las0 + LAS0_BURST_START);
951 /* ADC conversion trigger source: BURST */
952 writel(2, devpriv->las0 + LAS0_ADC_CONVERSION);
953 } else { /* single channel */
954 /* pacer start source: SOFTWARE */
955 writel(0, devpriv->las0 + LAS0_PACER_START);
956 /* ADC conversion trigger source: PACER */
957 writel(1, devpriv->las0 + LAS0_ADC_CONVERSION);
959 writel((devpriv->fifosz / 2 - 1) & 0xffff, devpriv->las0 + LAS0_ACNT);
961 if (TRIG_TIMER == cmd->scan_begin_src) {
962 /* scan_begin_arg is in nanoseconds */
963 /* find out how many samples to wait before transferring */
964 if (cmd->flags & TRIG_WAKE_EOS) {
966 * this may generate un-sustainable interrupt rates
967 * the application is responsible for doing the
970 devpriv->xfer_count = cmd->chanlist_len;
971 devpriv->flags |= SEND_EOS;
973 /* arrange to transfer data periodically */
974 devpriv->xfer_count =
975 (TRANS_TARGET_PERIOD * cmd->chanlist_len) /
977 if (devpriv->xfer_count < cmd->chanlist_len) {
978 /* transfer after each scan (and avoid 0) */
979 devpriv->xfer_count = cmd->chanlist_len;
980 } else { /* make a multiple of scan length */
981 devpriv->xfer_count =
982 (devpriv->xfer_count +
983 cmd->chanlist_len - 1)
985 devpriv->xfer_count *= cmd->chanlist_len;
987 devpriv->flags |= SEND_EOS;
989 if (devpriv->xfer_count >= (devpriv->fifosz / 2)) {
990 /* out of counter range, use 1/2 fifo instead */
991 devpriv->xfer_count = 0;
992 devpriv->flags &= ~SEND_EOS;
994 /* interrupt for each transfer */
995 writel((devpriv->xfer_count - 1) & 0xffff,
996 devpriv->las0 + LAS0_ACNT);
998 } else { /* unknown timing, just use 1/2 FIFO */
999 devpriv->xfer_count = 0;
1000 devpriv->flags &= ~SEND_EOS;
1002 /* pacer clock source: INTERNAL 8MHz */
1003 writel(1, devpriv->las0 + LAS0_PACER_SELECT);
1004 /* just interrupt, don't stop */
1005 writel(1, devpriv->las0 + LAS0_ACNT_STOP_ENABLE);
1007 /* BUG??? these look like enumerated values, but they are bit fields */
1009 /* First, setup when to stop */
1010 switch (cmd->stop_src) {
1011 case TRIG_COUNT: /* stop after N scans */
1012 devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len;
1013 if ((devpriv->xfer_count > 0)
1014 && (devpriv->xfer_count > devpriv->ai_count)) {
1015 devpriv->xfer_count = devpriv->ai_count;
1019 case TRIG_NONE: /* stop when cancel is called */
1020 devpriv->ai_count = -1; /* read forever */
1025 switch (cmd->scan_begin_src) {
1026 case TRIG_TIMER: /* periodic scanning */
1027 timer = rtd_ns_to_timer(&cmd->scan_begin_arg,
1028 TRIG_ROUND_NEAREST);
1029 /* set PACER clock */
1030 writel(timer & 0xffffff, devpriv->las0 + LAS0_PCLK);
1035 /* pacer start source: EXTERNAL */
1036 writel(1, devpriv->las0 + LAS0_PACER_START);
1040 /* Sample timing within a scan */
1041 switch (cmd->convert_src) {
1042 case TRIG_TIMER: /* periodic */
1043 if (cmd->chanlist_len > 1) {
1044 /* only needed for multi-channel */
1045 timer = rtd_ns_to_timer(&cmd->convert_arg,
1046 TRIG_ROUND_NEAREST);
1047 /* setup BURST clock */
1048 writel(timer & 0x3ff, devpriv->las0 + LAS0_BCLK);
1053 case TRIG_EXT: /* external */
1054 /* burst trigger source: EXTERNAL */
1055 writel(2, devpriv->las0 + LAS0_BURST_START);
1058 /* end configuration */
1060 /* This doesn't seem to work. There is no way to clear an interrupt
1061 that the priority controller has queued! */
1062 writew(~0, devpriv->las0 + LAS0_CLEAR);
1063 readw(devpriv->las0 + LAS0_CLEAR);
1065 /* TODO: allow multiple interrupt sources */
1066 if (devpriv->xfer_count > 0) { /* transfer every N samples */
1067 writew(IRQM_ADC_ABOUT_CNT, devpriv->las0 + LAS0_IT);
1068 } else { /* 1/2 FIFO transfers */
1069 writew(IRQM_ADC_ABOUT_CNT, devpriv->las0 + LAS0_IT);
1072 /* BUG: start_src is ASSUMED to be TRIG_NOW */
1073 /* BUG? it seems like things are running before the "start" */
1074 readl(devpriv->las0 + LAS0_PACER); /* start pacer */
1079 Stop a running data acquisition.
1081 static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1083 struct rtd_private *devpriv = dev->private;
1087 /* pacer stop source: SOFTWARE */
1088 writel(0, devpriv->las0 + LAS0_PACER_STOP);
1089 writel(0, devpriv->las0 + LAS0_PACER); /* stop pacer */
1090 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1091 writew(0, devpriv->las0 + LAS0_IT);
1092 devpriv->ai_count = 0; /* stop and don't transfer any more */
1093 status = readw(devpriv->las0 + LAS0_IT);
1094 overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
1098 static int rtd_ao_eoc(struct comedi_device *dev,
1099 struct comedi_subdevice *s,
1100 struct comedi_insn *insn,
1101 unsigned long context)
1103 struct rtd_private *devpriv = dev->private;
1104 unsigned int chan = CR_CHAN(insn->chanspec);
1105 unsigned int bit = (chan == 0) ? FS_DAC1_NOT_EMPTY : FS_DAC2_NOT_EMPTY;
1106 unsigned int status;
1108 status = readl(devpriv->las0 + LAS0_ADC);
1114 static int rtd_ao_winsn(struct comedi_device *dev,
1115 struct comedi_subdevice *s, struct comedi_insn *insn,
1118 struct rtd_private *devpriv = dev->private;
1120 int chan = CR_CHAN(insn->chanspec);
1121 int range = CR_RANGE(insn->chanspec);
1124 /* Configure the output range (table index matches the range values) */
1125 writew(range & 7, devpriv->las0 +
1126 ((chan == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL));
1128 /* Writing a list of values to an AO channel is probably not
1129 * very useful, but that's how the interface is defined. */
1130 for (i = 0; i < insn->n; ++i) {
1131 int val = data[i] << 3;
1133 /* VERIFY: comedi range and offset conversions */
1135 if ((range > 1) /* bipolar */
1136 && (data[i] < 2048)) {
1137 /* offset and sign extend */
1138 val = (((int)data[i]) - 2048) << 3;
1139 } else { /* unipolor */
1143 /* a typical programming sequence */
1144 writew(val, devpriv->las1 +
1145 ((chan == 0) ? LAS1_DAC1_FIFO : LAS1_DAC2_FIFO));
1146 writew(0, devpriv->las0 +
1147 ((chan == 0) ? LAS0_DAC1 : LAS0_DAC2));
1149 devpriv->ao_readback[chan] = data[i];
1151 ret = comedi_timeout(dev, s, insn, rtd_ao_eoc, 0);
1156 /* return the number of samples read/written */
1160 /* AO subdevices should have a read insn as well as a write insn.
1161 * Usually this means copying a value stored in devpriv. */
1162 static int rtd_ao_rinsn(struct comedi_device *dev,
1163 struct comedi_subdevice *s, struct comedi_insn *insn,
1166 struct rtd_private *devpriv = dev->private;
1168 int chan = CR_CHAN(insn->chanspec);
1170 for (i = 0; i < insn->n; i++)
1171 data[i] = devpriv->ao_readback[chan];
1177 static int rtd_dio_insn_bits(struct comedi_device *dev,
1178 struct comedi_subdevice *s,
1179 struct comedi_insn *insn,
1182 struct rtd_private *devpriv = dev->private;
1184 if (comedi_dio_update_state(s, data))
1185 writew(s->state & 0xff, devpriv->las0 + LAS0_DIO0);
1187 data[1] = readw(devpriv->las0 + LAS0_DIO0) & 0xff;
1192 static int rtd_dio_insn_config(struct comedi_device *dev,
1193 struct comedi_subdevice *s,
1194 struct comedi_insn *insn,
1197 struct rtd_private *devpriv = dev->private;
1200 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
1204 /* TODO support digital match interrupts and strobes */
1207 writew(0x01, devpriv->las0 + LAS0_DIO_STATUS);
1208 writew(s->io_bits & 0xff, devpriv->las0 + LAS0_DIO0_CTRL);
1210 /* clear interrupts */
1211 writew(0x00, devpriv->las0 + LAS0_DIO_STATUS);
1213 /* port1 can only be all input or all output */
1215 /* there are also 2 user input lines and 2 user output lines */
1220 static void rtd_reset(struct comedi_device *dev)
1222 struct rtd_private *devpriv = dev->private;
1224 writel(0, devpriv->las0 + LAS0_BOARD_RESET);
1225 udelay(100); /* needed? */
1226 writel(0, devpriv->lcfg + PLX_INTRCS_REG);
1227 writew(0, devpriv->las0 + LAS0_IT);
1228 writew(~0, devpriv->las0 + LAS0_CLEAR);
1229 readw(devpriv->las0 + LAS0_CLEAR);
1233 * initialize board, per RTD spec
1234 * also, initialize shadow registers
1236 static void rtd_init_board(struct comedi_device *dev)
1238 struct rtd_private *devpriv = dev->private;
1242 writel(0, devpriv->las0 + LAS0_OVERRUN);
1243 writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
1244 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
1245 writel(0, devpriv->las0 + LAS0_DAC1_RESET);
1246 writel(0, devpriv->las0 + LAS0_DAC2_RESET);
1247 /* clear digital IO fifo */
1248 writew(0, devpriv->las0 + LAS0_DIO_STATUS);
1249 writeb((0 << 6) | 0x30, devpriv->las0 + LAS0_UTC_CTRL);
1250 writeb((1 << 6) | 0x30, devpriv->las0 + LAS0_UTC_CTRL);
1251 writeb((2 << 6) | 0x30, devpriv->las0 + LAS0_UTC_CTRL);
1252 writeb((3 << 6) | 0x00, devpriv->las0 + LAS0_UTC_CTRL);
1253 /* TODO: set user out source ??? */
1256 /* The RTD driver does this */
1257 static void rtd_pci_latency_quirk(struct comedi_device *dev,
1258 struct pci_dev *pcidev)
1260 unsigned char pci_latency;
1262 pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency);
1263 if (pci_latency < 32) {
1264 dev_info(dev->class_dev,
1265 "PCI latency changed from %d to %d\n",
1267 pci_write_config_byte(pcidev, PCI_LATENCY_TIMER, 32);
1271 static int rtd_auto_attach(struct comedi_device *dev,
1272 unsigned long context)
1274 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1275 const struct rtd_boardinfo *board = NULL;
1276 struct rtd_private *devpriv;
1277 struct comedi_subdevice *s;
1280 if (context < ARRAY_SIZE(rtd520Boards))
1281 board = &rtd520Boards[context];
1284 dev->board_ptr = board;
1285 dev->board_name = board->name;
1287 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
1291 ret = comedi_pci_enable(dev);
1295 devpriv->las0 = pci_ioremap_bar(pcidev, 2);
1296 devpriv->las1 = pci_ioremap_bar(pcidev, 3);
1297 devpriv->lcfg = pci_ioremap_bar(pcidev, 0);
1298 if (!devpriv->las0 || !devpriv->las1 || !devpriv->lcfg)
1301 rtd_pci_latency_quirk(dev, pcidev);
1304 ret = request_irq(pcidev->irq, rtd_interrupt, IRQF_SHARED,
1305 dev->board_name, dev);
1307 dev->irq = pcidev->irq;
1310 ret = comedi_alloc_subdevices(dev, 4);
1314 s = &dev->subdevices[0];
1315 /* analog input subdevice */
1316 s->type = COMEDI_SUBD_AI;
1317 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF;
1319 s->maxdata = 0x0fff;
1320 s->range_table = board->ai_range;
1321 s->len_chanlist = RTD_MAX_CHANLIST;
1322 s->insn_read = rtd_ai_rinsn;
1324 dev->read_subdev = s;
1325 s->subdev_flags |= SDF_CMD_READ;
1326 s->do_cmd = rtd_ai_cmd;
1327 s->do_cmdtest = rtd_ai_cmdtest;
1328 s->cancel = rtd_ai_cancel;
1331 s = &dev->subdevices[1];
1332 /* analog output subdevice */
1333 s->type = COMEDI_SUBD_AO;
1334 s->subdev_flags = SDF_WRITABLE;
1336 s->maxdata = 0x0fff;
1337 s->range_table = &rtd_ao_range;
1338 s->insn_write = rtd_ao_winsn;
1339 s->insn_read = rtd_ao_rinsn;
1341 s = &dev->subdevices[2];
1342 /* digital i/o subdevice */
1343 s->type = COMEDI_SUBD_DIO;
1344 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1345 /* we only support port 0 right now. Ignoring port 1 and user IO */
1348 s->range_table = &range_digital;
1349 s->insn_bits = rtd_dio_insn_bits;
1350 s->insn_config = rtd_dio_insn_config;
1352 /* timer/counter subdevices (not currently supported) */
1353 s = &dev->subdevices[3];
1354 s->type = COMEDI_SUBD_COUNTER;
1355 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1357 s->maxdata = 0xffff;
1359 rtd_init_board(dev);
1361 ret = rtd520_probe_fifo_depth(dev);
1364 devpriv->fifosz = ret;
1367 writel(ICS_PIE | ICS_PLIE, devpriv->lcfg + PLX_INTRCS_REG);
1372 static void rtd_detach(struct comedi_device *dev)
1374 struct rtd_private *devpriv = dev->private;
1377 /* Shut down any board ops by resetting it */
1378 if (devpriv->las0 && devpriv->lcfg)
1381 writel(readl(devpriv->lcfg + PLX_INTRCS_REG) &
1382 ~(ICS_PLIE | ICS_DMA0_E | ICS_DMA1_E),
1383 devpriv->lcfg + PLX_INTRCS_REG);
1384 free_irq(dev->irq, dev);
1387 iounmap(devpriv->las0);
1389 iounmap(devpriv->las1);
1391 iounmap(devpriv->lcfg);
1393 comedi_pci_disable(dev);
1396 static struct comedi_driver rtd520_driver = {
1397 .driver_name = "rtd520",
1398 .module = THIS_MODULE,
1399 .auto_attach = rtd_auto_attach,
1400 .detach = rtd_detach,
1403 static int rtd520_pci_probe(struct pci_dev *dev,
1404 const struct pci_device_id *id)
1406 return comedi_pci_auto_config(dev, &rtd520_driver, id->driver_data);
1409 static const struct pci_device_id rtd520_pci_table[] = {
1410 { PCI_VDEVICE(RTD, 0x7520), BOARD_DM7520 },
1411 { PCI_VDEVICE(RTD, 0x4520), BOARD_PCI4520 },
1414 MODULE_DEVICE_TABLE(pci, rtd520_pci_table);
1416 static struct pci_driver rtd520_pci_driver = {
1418 .id_table = rtd520_pci_table,
1419 .probe = rtd520_pci_probe,
1420 .remove = comedi_pci_auto_unconfig,
1422 module_comedi_pci_driver(rtd520_driver, rtd520_pci_driver);
1424 MODULE_AUTHOR("Comedi http://www.comedi.org");
1425 MODULE_DESCRIPTION("Comedi low-level driver");
1426 MODULE_LICENSE("GPL");