2 comedi/drivers/rtd520.c
3 Comedi driver for Real Time Devices (RTD) PCI4520/DM7520
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2001 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: Real Time Devices PCI4520/DM7520
26 Devices: [Real Time Devices] DM7520HR-1 (rtd520), DM7520HR-8,
28 Status: Works. Only tested on DM7520-8. Not SMP safe.
30 Configuration options:
31 [0] - PCI bus of device (optional)
32 If bus / slot is not specified, the first available PCI
34 [1] - PCI slot of device (optional)
37 Created by Dan Christian, NASA Ames Research Center.
39 The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
41 8/16 12 bit ADC with FIFO and channel gain table
42 8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
43 8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
44 2 12 bit DACs with FIFOs
48 timers: ADC sample, pacer, burst, about, delay, DA1, DA2
50 3 user timer/counters (8254)
53 The DM7520 has slightly fewer features (fewer gain steps).
55 These boards can support external multiplexors and multi-board
56 synchronization, but this driver doesn't support that.
58 Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
59 Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
60 Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
61 Call them and ask for the register level manual.
62 PCI chip: http://www.plxtech.com/products/io/pci9080
65 This board is memory mapped. There is some IO stuff, but it isn't needed.
67 I use a pretty loose naming style within the driver (rtd_blah).
68 All externally visible names should be rtd520_blah.
69 I use camelCase for structures (and inside them).
70 I may also use upper CamelCase for function names (old habit).
72 This board is somewhat related to the RTD PCI4400 board.
74 I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
75 das1800, since they have the best documented code. Driver
76 cb_pcidas64.c uses the same DMA controller.
78 As far as I can tell, the About interrupt doesn't work if Sample is
79 also enabled. It turns out that About really isn't needed, since
80 we always count down samples read.
82 There was some timer/counter code, but it didn't follow the right API.
89 Analog-In supports instruction and command mode.
91 With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
92 (single channel, 64K read buffer). I get random system lockups when
93 using DMA with ALI-15xx based systems. I haven't been able to test
94 any other chipsets. The lockups happen soon after the start of an
95 acquistion, not in the middle of a long run.
97 Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
98 (with a 256K read buffer).
100 Digital-IO and Analog-Out only support instruction mode.
104 #include <linux/interrupt.h>
105 #include <linux/delay.h>
107 #include "../comedidev.h"
109 #define DRV_NAME "rtd520"
111 /*======================================================================
112 Driver specific stuff (tunable)
113 ======================================================================*/
114 /* Enable this to test the new DMA support. You may get hard lock ups */
117 /* We really only need 2 buffers. More than that means being much
118 smarter about knowing which ones are full. */
119 #define DMA_CHAIN_COUNT 2 /* max DMA segments/buffers in a ring (min 2) */
121 /* Target period for periodic transfers. This sets the user read latency. */
122 /* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
123 /* If this is too low, efficiency is poor */
124 #define TRANS_TARGET_PERIOD 10000000 /* 10 ms (in nanoseconds) */
126 /* Set a practical limit on how long a list to support (affects memory use) */
127 /* The board support a channel list up to the FIFO length (1K or 8K) */
128 #define RTD_MAX_CHANLIST 128 /* max channel list that we allow */
130 /* tuning for ai/ao instruction done polling */
132 #define WAIT_QUIETLY /* as nothing, spin on done bit */
133 #define RTD_ADC_TIMEOUT 66000 /* 2 msec at 33mhz bus rate */
134 #define RTD_DAC_TIMEOUT 66000
135 #define RTD_DMA_TIMEOUT 33000 /* 1 msec */
137 /* by delaying, power and electrical noise are reduced somewhat */
138 #define WAIT_QUIETLY udelay(1)
139 #define RTD_ADC_TIMEOUT 2000 /* in usec */
140 #define RTD_DAC_TIMEOUT 2000 /* in usec */
141 #define RTD_DMA_TIMEOUT 1000 /* in usec */
144 /*======================================================================
146 ======================================================================*/
149 #define PCI_VENDOR_ID_RTD 0x1435
151 The board has three memory windows: las0, las1, and lcfg (the PCI chip)
152 Las1 has the data and can be burst DMAed 32bits at a time.
154 #define LCFG_PCIINDEX 0
155 /* PCI region 1 is a 256 byte IO space mapping. Use??? */
156 #define LAS0_PCIINDEX 2 /* PCI memory resources */
157 #define LAS1_PCIINDEX 3
158 #define LCFG_PCISIZE 0x100
159 #define LAS0_PCISIZE 0x200
160 #define LAS1_PCISIZE 0x10
162 #define RTD_CLOCK_RATE 8000000 /* 8Mhz onboard clock */
163 #define RTD_CLOCK_BASE 125 /* clock period in ns */
165 /* Note: these speed are slower than the spec, but fit the counter resolution*/
166 #define RTD_MAX_SPEED 1625 /* when sampling, in nanoseconds */
167 /* max speed if we don't have to wait for settling */
168 #define RTD_MAX_SPEED_1 875 /* if single channel, in nanoseconds */
170 #define RTD_MIN_SPEED 2097151875 /* (24bit counter) in nanoseconds */
171 /* min speed when only 1 channel (no burst counter) */
172 #define RTD_MIN_SPEED_1 5000000 /* 200Hz, in nanoseconds */
177 /* Setup continuous ring of 1/2 FIFO transfers. See RTD manual p91 */
178 #define DMA_MODE_BITS (\
179 PLX_LOCAL_BUS_16_WIDE_BITS \
180 | PLX_DMA_EN_READYIN_BIT \
181 | PLX_DMA_LOCAL_BURST_EN_BIT \
183 | PLX_DMA_INTR_PCI_BIT \
184 | PLX_LOCAL_ADDR_CONST_BIT \
185 | PLX_DEMAND_MODE_BIT)
187 #define DMA_TRANSFER_BITS (\
188 /* descriptors in PCI memory*/ PLX_DESC_IN_PCI_BIT \
189 /* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
190 /* from board to PCI */ | PLX_XFER_LOCAL_TO_PCI)
192 /*======================================================================
193 Comedi specific stuff
194 ======================================================================*/
197 The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
199 static const struct comedi_lrange rtd_ai_7520_range = { 18, {
200 /* +-5V input range gain steps */
209 /* +-10V input range gain steps */
221 /* +10V input range gain steps */
237 /* PCI4520 has two more gains (6 more entries) */
238 static const struct comedi_lrange rtd_ai_4520_range = { 24, {
239 /* +-5V input range gain steps */
252 /* +-10V input range gain steps */
268 /* +10V input range gain steps */
287 /* Table order matches range values */
288 static const struct comedi_lrange rtd_ao_range = { 4, {
300 const char *name; /* must be first */
305 int range10Start; /* start of +-10V range */
306 int rangeUniStart; /* start of +10V range */
309 static const struct rtdBoard rtd520Boards[] = {
331 * Useful for shorthand access to the particular board structure
333 #define thisboard ((const struct rtdBoard *)dev->board_ptr)
336 This structure is for data unique to this hardware driver.
337 This is also unique for each board in the system.
340 /* memory mapped board structures */
345 unsigned long intCount; /* interrupt count */
346 long aiCount; /* total transfer size (samples) */
347 int transCount; /* # to transfer data. 0->1/2FIFO */
348 int flags; /* flag event modes */
350 /* PCI device info */
351 struct pci_dev *pci_dev;
352 int got_regions; /* non-zero if PCI regions owned */
354 /* channel list info */
355 /* chanBipolar tracks whether a channel is bipolar (and needs +2048) */
356 unsigned char chanBipolar[RTD_MAX_CHANLIST / 8]; /* bit array */
359 unsigned int aoValue[2]; /* Used for AO read back */
361 /* timer gate (when enabled) */
362 u8 utcGate[4]; /* 1 extra allows simple range check */
364 /* shadow registers affect other registers, but can't be read back */
365 /* The macros below update these on writes */
366 u16 intMask; /* interrupt mask */
367 u16 intClearMask; /* interrupt clear mask */
368 u8 utcCtrl[4]; /* crtl mode for 3 utc + read back */
369 u8 dioStatus; /* could be read back (dio0Ctrl) */
372 * Always DMA 1/2 FIFO. Buffer (dmaBuff?) is (at least) twice that
373 * size. After transferring, interrupt processes 1/2 FIFO and
376 s16 dma0Offset; /* current processing offset (0, 1/2) */
377 uint16_t *dma0Buff[DMA_CHAIN_COUNT]; /* DMA buffers (for ADC) */
378 dma_addr_t dma0BuffPhysAddr[DMA_CHAIN_COUNT]; /* physical addresses */
379 struct plx_dma_desc *dma0Chain; /* DMA descriptor ring for dmaBuff */
380 dma_addr_t dma0ChainPhysAddr; /* physical addresses */
381 /* shadow registers */
388 /* bit defines for "flags" */
389 #define SEND_EOS 0x01 /* send End Of Scan events */
390 #define DMA0_ACTIVE 0x02 /* DMA0 is active */
391 #define DMA1_ACTIVE 0x04 /* DMA1 is active */
393 /* Macros for accessing channel list bit array */
394 #define CHAN_ARRAY_TEST(array, index) \
395 (((array)[(index)/8] >> ((index) & 0x7)) & 0x1)
396 #define CHAN_ARRAY_SET(array, index) \
397 (((array)[(index)/8] |= 1 << ((index) & 0x7)))
398 #define CHAN_ARRAY_CLEAR(array, index) \
399 (((array)[(index)/8] &= ~(1 << ((index) & 0x7))))
402 * most drivers define the following macro to make it easy to
403 * access the private structure.
405 #define devpriv ((struct rtdPrivate *)dev->private)
407 /* Macros to access registers */
410 #define RtdDio0Read(dev) \
411 (readw(devpriv->las0+LAS0_DIO0) & 0xff)
412 #define RtdDio0Write(dev, v) \
413 writew((v) & 0xff, devpriv->las0+LAS0_DIO0)
415 #define RtdDio1Read(dev) \
416 (readw(devpriv->las0+LAS0_DIO1) & 0xff)
417 #define RtdDio1Write(dev, v) \
418 writew((v) & 0xff, devpriv->las0+LAS0_DIO1)
420 #define RtdDioStatusRead(dev) \
421 (readw(devpriv->las0+LAS0_DIO_STATUS) & 0xff)
422 #define RtdDioStatusWrite(dev, v) \
423 writew((devpriv->dioStatus = (v)), devpriv->las0+LAS0_DIO_STATUS)
425 #define RtdDio0CtrlRead(dev) \
426 (readw(devpriv->las0+LAS0_DIO0_CTRL) & 0xff)
427 #define RtdDio0CtrlWrite(dev, v) \
428 writew((v) & 0xff, devpriv->las0+LAS0_DIO0_CTRL)
430 /* Digital to Analog converter */
431 /* Write one data value (sign + 12bit + marker bits) */
432 /* Note: matches what DMA would put. Actual value << 3 */
433 #define RtdDacFifoPut(dev, n, v) \
434 writew((v), devpriv->las1 + (((n) == 0) ? LAS1_DAC1_FIFO : \
437 /* Start single DAC conversion */
438 #define RtdDacUpdate(dev, n) \
439 writew(0, devpriv->las0 + (((n) == 0) ? LAS0_DAC1 : LAS0_DAC2))
441 /* Start single DAC conversion on both DACs */
442 #define RtdDacBothUpdate(dev) \
443 writew(0, devpriv->las0+LAS0_DAC)
445 /* Set DAC output type and range */
446 #define RtdDacRange(dev, n, v) \
447 writew((v) & 7, devpriv->las0 \
448 +(((n) == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL))
451 #define RtdDacClearFifo(dev, n) \
452 writel(0, devpriv->las0+(((n) == 0) ? LAS0_DAC1_RESET : \
455 /* Set source for DMA 0 (write only, shadow?) */
456 #define RtdDma0Source(dev, n) \
457 writel((n) & 0xf, devpriv->las0+LAS0_DMA0_SRC)
459 /* Set source for DMA 1 (write only, shadow?) */
460 #define RtdDma1Source(dev, n) \
461 writel((n) & 0xf, devpriv->las0+LAS0_DMA1_SRC)
463 /* Reset board state for DMA 0 */
464 #define RtdDma0Reset(dev) \
465 writel(0, devpriv->las0+LAS0_DMA0_RESET)
467 /* Reset board state for DMA 1 */
468 #define RtdDma1Reset(dev) \
469 writel(0, devpriv->las0+LAS0_DMA1_SRC)
471 /* PLX9080 interrupt mask and status */
472 #define RtdPlxInterruptRead(dev) \
473 readl(devpriv->lcfg+LCFG_ITCSR)
474 #define RtdPlxInterruptWrite(dev, v) \
475 writel(v, devpriv->lcfg+LCFG_ITCSR)
477 /* Set mode for DMA 0 */
478 #define RtdDma0Mode(dev, m) \
479 writel((m), devpriv->lcfg+LCFG_DMAMODE0)
481 /* Set PCI address for DMA 0 */
482 #define RtdDma0PciAddr(dev, a) \
483 writel((a), devpriv->lcfg+LCFG_DMAPADR0)
485 /* Set local address for DMA 0 */
486 #define RtdDma0LocalAddr(dev, a) \
487 writel((a), devpriv->lcfg+LCFG_DMALADR0)
489 /* Set byte count for DMA 0 */
490 #define RtdDma0Count(dev, c) \
491 writel((c), devpriv->lcfg+LCFG_DMASIZ0)
493 /* Set next descriptor for DMA 0 */
494 #define RtdDma0Next(dev, a) \
495 writel((a), devpriv->lcfg+LCFG_DMADPR0)
497 /* Set mode for DMA 1 */
498 #define RtdDma1Mode(dev, m) \
499 writel((m), devpriv->lcfg+LCFG_DMAMODE1)
501 /* Set PCI address for DMA 1 */
502 #define RtdDma1PciAddr(dev, a) \
503 writel((a), devpriv->lcfg+LCFG_DMAADR1)
505 /* Set local address for DMA 1 */
506 #define RtdDma1LocalAddr(dev, a) \
507 writel((a), devpriv->lcfg+LCFG_DMALADR1)
509 /* Set byte count for DMA 1 */
510 #define RtdDma1Count(dev, c) \
511 writel((c), devpriv->lcfg+LCFG_DMASIZ1)
513 /* Set next descriptor for DMA 1 */
514 #define RtdDma1Next(dev, a) \
515 writel((a), devpriv->lcfg+LCFG_DMADPR1)
517 /* Set control for DMA 0 (write only, shadow?) */
518 #define RtdDma0Control(dev, n) \
519 writeb(devpriv->dma0Control = (n), devpriv->lcfg+LCFG_DMACSR0)
521 /* Get status for DMA 0 */
522 #define RtdDma0Status(dev) \
523 readb(devpriv->lcfg+LCFG_DMACSR0)
525 /* Set control for DMA 1 (write only, shadow?) */
526 #define RtdDma1Control(dev, n) \
527 writeb(devpriv->dma1Control = (n), devpriv->lcfg+LCFG_DMACSR1)
529 /* Get status for DMA 1 */
530 #define RtdDma1Status(dev) \
531 readb(devpriv->lcfg+LCFG_DMACSR1)
534 Given a desired period and the clock period (both in ns),
535 return the proper counter value (divider-1).
536 Sets the original period to be the true value.
537 Note: you have to check if the value is larger than the counter range!
539 static int rtd_ns_to_timer_base(unsigned int *nanosec, /* desired period (in ns) */
540 int round_mode, int base)
541 { /* clock period (in ns) */
544 switch (round_mode) {
545 case TRIG_ROUND_NEAREST:
547 divider = (*nanosec + base / 2) / base;
549 case TRIG_ROUND_DOWN:
550 divider = (*nanosec) / base;
553 divider = (*nanosec + base - 1) / base;
557 divider = 2; /* min is divide by 2 */
559 /* Note: we don't check for max, because different timers
560 have different ranges */
562 *nanosec = base * divider;
563 return divider - 1; /* countdown is divisor+1 */
567 Given a desired period (in ns),
568 return the proper counter value (divider-1) for the internal clock.
569 Sets the original period to be the true value.
571 static int rtd_ns_to_timer(unsigned int *ns, int round_mode)
573 return rtd_ns_to_timer_base(ns, round_mode, RTD_CLOCK_BASE);
577 Convert a single comedi channel-gain entry to a RTD520 table entry
579 static unsigned short rtdConvertChanGain(struct comedi_device *dev,
580 unsigned int comediChan, int chanIndex)
581 { /* index in channel list */
582 unsigned int chan, range, aref;
583 unsigned short r = 0;
585 chan = CR_CHAN(comediChan);
586 range = CR_RANGE(comediChan);
587 aref = CR_AREF(comediChan);
591 /* Note: we also setup the channel list bipolar flag array */
592 if (range < thisboard->range10Start) { /* first batch are +-5 */
593 r |= 0x000; /* +-5 range */
594 r |= (range & 0x7) << 4; /* gain */
595 CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
596 } else if (range < thisboard->rangeUniStart) { /* second batch are +-10 */
597 r |= 0x100; /* +-10 range */
599 r |= ((range - thisboard->range10Start) & 0x7) << 4;
600 CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
601 } else { /* last batch is +10 */
602 r |= 0x200; /* +10 range */
604 r |= ((range - thisboard->rangeUniStart) & 0x7) << 4;
605 CHAN_ARRAY_CLEAR(devpriv->chanBipolar, chanIndex);
609 case AREF_GROUND: /* on-board ground */
613 r |= 0x80; /* ref external analog common */
617 r |= 0x400; /* differential inputs */
620 case AREF_OTHER: /* ??? */
623 /*printk ("chan=%d r=%d a=%d -> 0x%x\n",
624 chan, range, aref, r); */
629 Setup the channel-gain table from a comedi list
631 static void rtd_load_channelgain_list(struct comedi_device *dev,
632 unsigned int n_chan, unsigned int *list)
634 if (n_chan > 1) { /* setup channel gain table */
637 writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
638 writel(1, devpriv->las0 + LAS0_CGT_ENABLE);
639 for (ii = 0; ii < n_chan; ii++) {
640 writel(rtdConvertChanGain(dev, list[ii], ii),
641 devpriv->las0 + LAS0_CGT_WRITE);
643 } else { /* just use the channel gain latch */
644 writel(0, devpriv->las0 + LAS0_CGT_ENABLE);
645 writel(rtdConvertChanGain(dev, list[0], 0),
646 devpriv->las0 + LAS0_CGL_WRITE);
650 /* determine fifo size by doing adc conversions until the fifo half
651 empty status flag clears */
652 static int rtd520_probe_fifo_depth(struct comedi_device *dev)
654 unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
656 static const unsigned limit = 0x2000;
657 unsigned fifo_size = 0;
659 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
660 rtd_load_channelgain_list(dev, 1, &chanspec);
661 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
662 /* convert samples */
663 for (i = 0; i < limit; ++i) {
664 unsigned fifo_status;
665 /* trigger conversion */
666 writew(0, devpriv->las0 + LAS0_ADC);
668 fifo_status = readl(devpriv->las0 + LAS0_ADC);
669 if ((fifo_status & FS_ADC_HEMPTY) == 0) {
675 printk(KERN_INFO "\ncomedi: %s: failed to probe fifo size.\n",
679 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
680 if (fifo_size != 0x400 && fifo_size != 0x2000) {
682 (KERN_INFO "\ncomedi: %s: unexpected fifo size of %i, expected 1024 or 8192.\n",
683 DRV_NAME, fifo_size);
690 "instructions" read/write data in "one-shot" or "software-triggered"
691 mode (simplest case).
692 This doesn't use interrupts.
694 Note, we don't do any settling delays. Use a instruction list to
695 select, delay, then read.
697 static int rtd_ai_rinsn(struct comedi_device *dev,
698 struct comedi_subdevice *s, struct comedi_insn *insn,
704 /* clear any old fifo data */
705 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
707 /* write channel to multiplexer and clear channel gain table */
708 rtd_load_channelgain_list(dev, 1, &insn->chanspec);
710 /* set conversion source */
711 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
713 /* convert n samples */
714 for (n = 0; n < insn->n; n++) {
716 /* trigger conversion */
717 writew(0, devpriv->las0 + LAS0_ADC);
719 for (ii = 0; ii < RTD_ADC_TIMEOUT; ++ii) {
720 stat = readl(devpriv->las0 + LAS0_ADC);
721 if (stat & FS_ADC_NOT_EMPTY) /* 1 -> not empty */
725 if (ii >= RTD_ADC_TIMEOUT) {
727 ("rtd520: Error: ADC never finished! FifoStatus=0x%x\n",
733 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
734 /*printk ("rtd520: Got 0x%x after %d usec\n", d, ii+1); */
735 d = d >> 3; /* low 3 bits are marker lines */
736 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, 0))
737 /* convert to comedi unsigned data */
743 /* return the number of samples read/written */
748 Get what we know is there.... Fast!
749 This uses 1/2 the bus cycles of read_dregs (below).
751 The manual claims that we can do a lword read, but it doesn't work here.
753 static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
758 for (ii = 0; ii < count; ii++) {
762 if (0 == devpriv->aiCount) { /* done */
763 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
767 if (!(readl(devpriv->las0 + LAS0_ADC) & FS_ADC_NOT_EMPTY)) {
768 DPRINTK("comedi: READ OOPS on %d of %d\n", ii + 1,
773 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
775 d = d >> 3; /* low 3 bits are marker lines */
776 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
777 /* convert to comedi unsigned data */
782 if (!comedi_buf_put(s->async, sample))
785 if (devpriv->aiCount > 0) /* < 0, means read forever */
792 unknown amout of data is waiting in fifo.
794 static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
796 while (readl(devpriv->las0 + LAS0_ADC) & FS_ADC_NOT_EMPTY) {
798 s16 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
800 if (0 == devpriv->aiCount) { /* done */
801 continue; /* read rest */
804 d = d >> 3; /* low 3 bits are marker lines */
805 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
806 /* convert to comedi unsigned data */
811 if (!comedi_buf_put(s->async, sample))
814 if (devpriv->aiCount > 0) /* < 0, means read forever */
822 Terminate a DMA transfer and wait for everything to quiet down
824 void abort_dma(struct comedi_device *dev, unsigned int channel)
825 { /* DMA channel 0, 1 */
826 unsigned long dma_cs_addr; /* the control/status register */
829 /* unsigned long flags; */
831 dma_cs_addr = (unsigned long)devpriv->lcfg
832 + ((channel == 0) ? LCFG_DMACSR0 : LCFG_DMACSR1);
834 /* spinlock for plx dma control/status reg */
835 /* spin_lock_irqsave( &dev->spinlock, flags ); */
837 /* abort dma transfer if necessary */
838 status = readb(dma_cs_addr);
839 if ((status & PLX_DMA_EN_BIT) == 0) { /* not enabled (Error?) */
840 DPRINTK("rtd520: AbortDma on non-active channel %d (0x%x)\n",
845 /* wait to make sure done bit is zero (needed?) */
846 for (ii = 0; (status & PLX_DMA_DONE_BIT) && ii < RTD_DMA_TIMEOUT; ii++) {
848 status = readb(dma_cs_addr);
850 if (status & PLX_DMA_DONE_BIT) {
851 printk("rtd520: Timeout waiting for dma %i done clear\n",
856 /* disable channel (required) */
857 writeb(0, dma_cs_addr);
858 udelay(1); /* needed?? */
859 /* set abort bit for channel */
860 writeb(PLX_DMA_ABORT_BIT, dma_cs_addr);
862 /* wait for dma done bit to be set */
863 status = readb(dma_cs_addr);
865 (status & PLX_DMA_DONE_BIT) == 0 && ii < RTD_DMA_TIMEOUT; ii++) {
866 status = readb(dma_cs_addr);
869 if ((status & PLX_DMA_DONE_BIT) == 0) {
870 printk("rtd520: Timeout waiting for dma %i done set\n",
875 /* spin_unlock_irqrestore( &dev->spinlock, flags ); */
879 Process what is in the DMA transfer buffer and pass to comedi
880 Note: this is not re-entrant
882 static int ai_process_dma(struct comedi_device *dev, struct comedi_subdevice *s)
887 if (devpriv->aiCount == 0) /* transfer already complete */
890 dp = devpriv->dma0Buff[devpriv->dma0Offset];
891 for (ii = 0; ii < devpriv->fifoLen / 2;) { /* convert samples */
894 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
895 sample = (*dp >> 3) + 2048; /* convert to comedi unsigned data */
897 sample = *dp >> 3; /* low 3 bits are marker lines */
899 *dp++ = sample; /* put processed value back */
901 if (++s->async->cur_chan >= s->async->cmd.chanlist_len)
902 s->async->cur_chan = 0;
904 ++ii; /* number ready to transfer */
905 if (devpriv->aiCount > 0) { /* < 0, means read forever */
906 if (--devpriv->aiCount == 0) { /* done */
907 /*DPRINTK ("rtd520: Final %d samples\n", ii); */
913 /* now pass the whole array to the comedi buffer */
914 dp = devpriv->dma0Buff[devpriv->dma0Offset];
915 n = comedi_buf_write_alloc(s->async, ii * sizeof(s16));
916 if (n < (ii * sizeof(s16))) { /* any residual is an error */
917 DPRINTK("rtd520:ai_process_dma buffer overflow %d samples!\n",
918 ii - (n / sizeof(s16)));
919 s->async->events |= COMEDI_CB_ERROR;
922 comedi_buf_memcpy_to(s->async, 0, dp, n);
923 comedi_buf_write_free(s->async, n);
926 * always at least 1 scan -- 1/2 FIFO is larger than our max scan list
928 s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOS;
930 if (++devpriv->dma0Offset >= DMA_CHAIN_COUNT) { /* next buffer */
931 devpriv->dma0Offset = 0;
938 Handle all rtd520 interrupts.
939 Runs atomically and is never re-entered.
940 This is a "slow handler"; other interrupts may be active.
941 The data conversion may someday happen in a "bottom half".
943 static irqreturn_t rtd_interrupt(int irq, /* interrupt number (ignored) */
945 { /* our data *//* cpu context (ignored) */
946 struct comedi_device *dev = d; /* must be called "dev" for devpriv */
947 struct comedi_subdevice *s = dev->subdevices + 0; /* analog in subdevice */
955 devpriv->intCount++; /* DEBUG statistics */
957 fifoStatus = readl(devpriv->las0 + LAS0_ADC);
958 /* check for FIFO full, this automatically halts the ADC! */
959 if (!(fifoStatus & FS_ADC_NOT_FULL)) { /* 0 -> full */
960 DPRINTK("rtd520: FIFO full! fifo_status=0x%x\n", (fifoStatus ^ 0x6666) & 0x7777); /* should be all 0s */
964 if (devpriv->flags & DMA0_ACTIVE) { /* Check DMA */
965 u32 istatus = RtdPlxInterruptRead(dev);
967 if (istatus & ICS_DMA0_A) {
968 if (ai_process_dma(dev, s) < 0) {
970 ("rtd520: comedi read buffer overflow (DMA) with %ld to go!\n",
973 (devpriv->dma0Control &
975 | PLX_CLEAR_DMA_INTR_BIT);
979 /*DPRINTK ("rtd520: DMA transfer: %ld to go, istatus %x\n",
980 devpriv->aiCount, istatus); */
983 dma0Control & ~PLX_DMA_START_BIT)
984 | PLX_CLEAR_DMA_INTR_BIT);
985 if (0 == devpriv->aiCount) { /* counted down */
986 DPRINTK("rtd520: Samples Done (DMA).\n");
989 comedi_event(dev, s);
991 /*DPRINTK ("rtd520: No DMA ready: istatus %x\n", istatus); */
994 /* Fall through and check for other interrupt sources */
997 status = readw(devpriv->las0 + LAS0_IT);
998 /* if interrupt was not caused by our board, or handled above */
1002 if (status & IRQM_ADC_ABOUT_CNT) { /* sample count -> read FIFO */
1003 /* since the priority interrupt controller may have queued a sample
1004 counter interrupt, even though we have already finished,
1005 we must handle the possibility that there is no data here */
1006 if (!(fifoStatus & FS_ADC_HEMPTY)) { /* 0 -> 1/2 full */
1007 /*DPRINTK("rtd520: Sample int, reading 1/2FIFO. fifo_status 0x%x\n",
1008 (fifoStatus ^ 0x6666) & 0x7777); */
1009 if (ai_read_n(dev, s, devpriv->fifoLen / 2) < 0) {
1011 ("rtd520: comedi read buffer overflow (1/2FIFO) with %ld to go!\n",
1015 if (0 == devpriv->aiCount) { /* counted down */
1016 DPRINTK("rtd520: Samples Done (1/2). fifo_status was 0x%x\n", (fifoStatus ^ 0x6666) & 0x7777); /* should be all 0s */
1019 comedi_event(dev, s);
1020 } else if (devpriv->transCount > 0) { /* read often */
1021 /*DPRINTK("rtd520: Sample int, reading %d fifo_status 0x%x\n",
1022 devpriv->transCount, (fifoStatus ^ 0x6666) & 0x7777); */
1023 if (fifoStatus & FS_ADC_NOT_EMPTY) { /* 1 -> not empty */
1024 if (ai_read_n(dev, s, devpriv->transCount) < 0) {
1026 ("rtd520: comedi read buffer overflow (N) with %ld to go!\n",
1030 if (0 == devpriv->aiCount) { /* counted down */
1032 ("rtd520: Samples Done (N). fifo_status was 0x%x\n",
1033 (fifoStatus ^ 0x6666) & 0x7777);
1036 comedi_event(dev, s);
1038 } else { /* wait for 1/2 FIFO (old) */
1040 ("rtd520: Sample int. Wait for 1/2. fifo_status 0x%x\n",
1041 (fifoStatus ^ 0x6666) & 0x7777);
1044 DPRINTK("rtd520: unknown interrupt source!\n");
1047 overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
1050 ("rtd520: Interrupt overrun with %ld to go! over_status=0x%x\n",
1051 devpriv->aiCount, overrun);
1055 /* clear the interrupt */
1056 devpriv->intClearMask = status;
1057 writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
1058 readw(devpriv->las0 + LAS0_CLEAR);
1062 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
1063 s->async->events |= COMEDI_CB_ERROR;
1064 devpriv->aiCount = 0; /* stop and don't transfer any more */
1065 /* fall into transferDone */
1068 writel(0, devpriv->las0 + LAS0_PACER_STOP);
1069 writel(0, devpriv->las0 + LAS0_PACER);
1070 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1071 devpriv->intMask = 0;
1072 writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
1074 if (devpriv->flags & DMA0_ACTIVE) {
1075 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1076 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1078 devpriv->flags &= ~DMA0_ACTIVE;
1079 /* if Using DMA, then we should have read everything by now */
1080 if (devpriv->aiCount > 0) {
1081 DPRINTK("rtd520: Lost DMA data! %ld remain\n",
1085 #endif /* USE_DMA */
1087 if (devpriv->aiCount > 0) { /* there shouldn't be anything left */
1088 fifoStatus = readl(devpriv->las0 + LAS0_ADC);
1089 DPRINTK("rtd520: Finishing up. %ld remain, fifoStat=%x\n", devpriv->aiCount, (fifoStatus ^ 0x6666) & 0x7777); /* should read all 0s */
1090 ai_read_dregs(dev, s); /* read anything left in FIFO */
1093 s->async->events |= COMEDI_CB_EOA; /* signal end to comedi */
1094 comedi_event(dev, s);
1096 /* clear the interrupt */
1097 status = readw(devpriv->las0 + LAS0_IT);
1098 devpriv->intClearMask = status;
1099 writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
1100 readw(devpriv->las0 + LAS0_CLEAR);
1102 fifoStatus = readl(devpriv->las0 + LAS0_ADC);
1103 overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
1105 ("rtd520: Acquisition complete. %ld ints, intStat=%x, overStat=%x\n",
1106 devpriv->intCount, status, overrun);
1113 return the number of samples available
1115 static int rtd_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1117 /* TODO: This needs to mask interrupts, read_dregs, and then re-enable */
1118 /* Not sure what to do if DMA is active */
1119 return s->async->buf_write_count - s->async->buf_read_count;
1124 cmdtest tests a particular command to see if it is valid.
1125 Using the cmdtest ioctl, a user can create a valid cmd
1126 and then have it executed by the cmd ioctl (asyncronously).
1128 cmdtest returns 1,2,3,4 or 0, depending on which tests
1132 static int rtd_ai_cmdtest(struct comedi_device *dev,
1133 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1138 /* step 1: make sure trigger sources are trivially valid */
1140 tmp = cmd->start_src;
1141 cmd->start_src &= TRIG_NOW;
1142 if (!cmd->start_src || tmp != cmd->start_src)
1145 tmp = cmd->scan_begin_src;
1146 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
1147 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1151 tmp = cmd->convert_src;
1152 cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
1153 if (!cmd->convert_src || tmp != cmd->convert_src)
1157 tmp = cmd->scan_end_src;
1158 cmd->scan_end_src &= TRIG_COUNT;
1159 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1163 tmp = cmd->stop_src;
1164 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
1165 if (!cmd->stop_src || tmp != cmd->stop_src)
1172 /* step 2: make sure trigger sources are unique
1173 and mutually compatible */
1174 /* note that mutual compatibility is not an issue here */
1175 if (cmd->scan_begin_src != TRIG_TIMER &&
1176 cmd->scan_begin_src != TRIG_EXT) {
1179 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
1182 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
1188 /* step 3: make sure arguments are trivially compatible */
1190 if (cmd->start_arg != 0) {
1195 if (cmd->scan_begin_src == TRIG_TIMER) {
1196 /* Note: these are time periods, not actual rates */
1197 if (1 == cmd->chanlist_len) { /* no scanning */
1198 if (cmd->scan_begin_arg < RTD_MAX_SPEED_1) {
1199 cmd->scan_begin_arg = RTD_MAX_SPEED_1;
1200 rtd_ns_to_timer(&cmd->scan_begin_arg,
1204 if (cmd->scan_begin_arg > RTD_MIN_SPEED_1) {
1205 cmd->scan_begin_arg = RTD_MIN_SPEED_1;
1206 rtd_ns_to_timer(&cmd->scan_begin_arg,
1211 if (cmd->scan_begin_arg < RTD_MAX_SPEED) {
1212 cmd->scan_begin_arg = RTD_MAX_SPEED;
1213 rtd_ns_to_timer(&cmd->scan_begin_arg,
1217 if (cmd->scan_begin_arg > RTD_MIN_SPEED) {
1218 cmd->scan_begin_arg = RTD_MIN_SPEED;
1219 rtd_ns_to_timer(&cmd->scan_begin_arg,
1225 /* external trigger */
1226 /* should be level/edge, hi/lo specification here */
1227 /* should specify multiple external triggers */
1228 if (cmd->scan_begin_arg > 9) {
1229 cmd->scan_begin_arg = 9;
1233 if (cmd->convert_src == TRIG_TIMER) {
1234 if (1 == cmd->chanlist_len) { /* no scanning */
1235 if (cmd->convert_arg < RTD_MAX_SPEED_1) {
1236 cmd->convert_arg = RTD_MAX_SPEED_1;
1237 rtd_ns_to_timer(&cmd->convert_arg,
1241 if (cmd->convert_arg > RTD_MIN_SPEED_1) {
1242 cmd->convert_arg = RTD_MIN_SPEED_1;
1243 rtd_ns_to_timer(&cmd->convert_arg,
1248 if (cmd->convert_arg < RTD_MAX_SPEED) {
1249 cmd->convert_arg = RTD_MAX_SPEED;
1250 rtd_ns_to_timer(&cmd->convert_arg,
1254 if (cmd->convert_arg > RTD_MIN_SPEED) {
1255 cmd->convert_arg = RTD_MIN_SPEED;
1256 rtd_ns_to_timer(&cmd->convert_arg,
1262 /* external trigger */
1264 if (cmd->convert_arg > 9) {
1265 cmd->convert_arg = 9;
1271 if (cmd->scan_end_arg != cmd->chanlist_len) {
1272 cmd->scan_end_arg = cmd->chanlist_len;
1276 if (cmd->stop_src == TRIG_COUNT) {
1277 /* TODO check for rounding error due to counter wrap */
1281 if (cmd->stop_arg != 0) {
1291 /* step 4: fix up any arguments */
1293 if (cmd->chanlist_len > RTD_MAX_CHANLIST) {
1294 cmd->chanlist_len = RTD_MAX_CHANLIST;
1297 if (cmd->scan_begin_src == TRIG_TIMER) {
1298 tmp = cmd->scan_begin_arg;
1299 rtd_ns_to_timer(&cmd->scan_begin_arg,
1300 cmd->flags & TRIG_ROUND_MASK);
1301 if (tmp != cmd->scan_begin_arg)
1305 if (cmd->convert_src == TRIG_TIMER) {
1306 tmp = cmd->convert_arg;
1307 rtd_ns_to_timer(&cmd->convert_arg,
1308 cmd->flags & TRIG_ROUND_MASK);
1309 if (tmp != cmd->convert_arg)
1312 if (cmd->scan_begin_src == TRIG_TIMER
1313 && (cmd->scan_begin_arg
1314 < (cmd->convert_arg * cmd->scan_end_arg))) {
1315 cmd->scan_begin_arg =
1316 cmd->convert_arg * cmd->scan_end_arg;
1328 Execute a analog in command with many possible triggering options.
1329 The data get stored in the async structure of the subdevice.
1330 This is usually done by an interrupt handler.
1331 Userland gets to the data using read calls.
1333 static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1335 struct comedi_cmd *cmd = &s->async->cmd;
1338 /* stop anything currently running */
1339 writel(0, devpriv->las0 + LAS0_PACER_STOP);
1340 writel(0, devpriv->las0 + LAS0_PACER);
1341 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1342 devpriv->intMask = 0;
1343 writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
1345 if (devpriv->flags & DMA0_ACTIVE) { /* cancel anything running */
1346 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1347 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1349 devpriv->flags &= ~DMA0_ACTIVE;
1350 if (RtdPlxInterruptRead(dev) & ICS_DMA0_A) { /*clear pending int */
1351 RtdDma0Control(dev, PLX_CLEAR_DMA_INTR_BIT);
1354 RtdDma0Reset(dev); /* reset onboard state */
1355 #endif /* USE_DMA */
1356 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
1357 writel(0, devpriv->las0 + LAS0_OVERRUN);
1358 devpriv->intCount = 0;
1360 if (!dev->irq) { /* we need interrupts for this */
1361 DPRINTK("rtd520: ERROR! No interrupt available!\n");
1365 /* start configuration */
1366 /* load channel list and reset CGT */
1367 rtd_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
1369 /* setup the common case and override if needed */
1370 if (cmd->chanlist_len > 1) {
1371 /*DPRINTK ("rtd520: Multi channel setup\n"); */
1372 writel(0, devpriv->las0 + LAS0_PACER_START);
1373 writel(1, devpriv->las0 + LAS0_BURST_START);
1374 writel(2, devpriv->las0 + LAS0_ADC_CONVERSION);
1375 } else { /* single channel */
1376 /*DPRINTK ("rtd520: single channel setup\n"); */
1377 writel(0, devpriv->las0 + LAS0_PACER_START);
1378 writel(1, devpriv->las0 + LAS0_ADC_CONVERSION);
1380 writel((devpriv->fifoLen / 2 - 1) & 0xffff, devpriv->las0 + LAS0_ACNT);
1382 if (TRIG_TIMER == cmd->scan_begin_src) {
1383 /* scan_begin_arg is in nanoseconds */
1384 /* find out how many samples to wait before transferring */
1385 if (cmd->flags & TRIG_WAKE_EOS) {
1386 /* this may generate un-sustainable interrupt rates */
1387 /* the application is responsible for doing the right thing */
1388 devpriv->transCount = cmd->chanlist_len;
1389 devpriv->flags |= SEND_EOS;
1391 /* arrange to transfer data periodically */
1394 (TRANS_TARGET_PERIOD * cmd->chanlist_len) /
1395 cmd->scan_begin_arg;
1396 if (devpriv->transCount < cmd->chanlist_len) {
1397 /* transfer after each scan (and avoid 0) */
1398 devpriv->transCount = cmd->chanlist_len;
1399 } else { /* make a multiple of scan length */
1400 devpriv->transCount =
1401 (devpriv->transCount +
1402 cmd->chanlist_len - 1)
1403 / cmd->chanlist_len;
1404 devpriv->transCount *= cmd->chanlist_len;
1406 devpriv->flags |= SEND_EOS;
1408 if (devpriv->transCount >= (devpriv->fifoLen / 2)) {
1409 /* out of counter range, use 1/2 fifo instead */
1410 devpriv->transCount = 0;
1411 devpriv->flags &= ~SEND_EOS;
1413 /* interrupt for each transfer */
1414 writel((devpriv->transCount - 1) & 0xffff,
1415 devpriv->las0 + LAS0_ACNT);
1419 ("rtd520: scanLen=%d transferCount=%d fifoLen=%d\n scanTime(ns)=%d flags=0x%x\n",
1420 cmd->chanlist_len, devpriv->transCount, devpriv->fifoLen,
1421 cmd->scan_begin_arg, devpriv->flags);
1422 } else { /* unknown timing, just use 1/2 FIFO */
1423 devpriv->transCount = 0;
1424 devpriv->flags &= ~SEND_EOS;
1426 writel(1, devpriv->las0 + LAS0_PACER_SELECT);
1427 writel(1, devpriv->las0 + LAS0_ACNT_STOP_ENABLE);
1429 /* BUG??? these look like enumerated values, but they are bit fields */
1431 /* First, setup when to stop */
1432 switch (cmd->stop_src) {
1433 case TRIG_COUNT: /* stop after N scans */
1434 devpriv->aiCount = cmd->stop_arg * cmd->chanlist_len;
1435 if ((devpriv->transCount > 0)
1436 && (devpriv->transCount > devpriv->aiCount)) {
1437 devpriv->transCount = devpriv->aiCount;
1441 case TRIG_NONE: /* stop when cancel is called */
1442 devpriv->aiCount = -1; /* read forever */
1446 DPRINTK("rtd520: Warning! ignoring stop_src mode %d\n",
1451 switch (cmd->scan_begin_src) {
1452 case TRIG_TIMER: /* periodic scanning */
1453 timer = rtd_ns_to_timer(&cmd->scan_begin_arg,
1454 TRIG_ROUND_NEAREST);
1455 /* set PACER clock */
1456 /*DPRINTK ("rtd520: loading %d into pacer\n", timer); */
1457 writel(timer & 0xffffff, devpriv->las0 + LAS0_PCLK);
1462 writel(1, devpriv->las0 + LAS0_PACER_START);
1466 DPRINTK("rtd520: Warning! ignoring scan_begin_src mode %d\n",
1467 cmd->scan_begin_src);
1470 /* Sample timing within a scan */
1471 switch (cmd->convert_src) {
1472 case TRIG_TIMER: /* periodic */
1473 if (cmd->chanlist_len > 1) { /* only needed for multi-channel */
1474 timer = rtd_ns_to_timer(&cmd->convert_arg,
1475 TRIG_ROUND_NEAREST);
1476 /* setup BURST clock */
1477 /*DPRINTK ("rtd520: loading %d into burst\n", timer); */
1478 writel(timer & 0x3ff, devpriv->las0 + LAS0_BCLK);
1483 case TRIG_EXT: /* external */
1484 writel(2, devpriv->las0 + LAS0_BURST_START);
1488 DPRINTK("rtd520: Warning! ignoring convert_src mode %d\n",
1491 /* end configuration */
1493 /* This doesn't seem to work. There is no way to clear an interrupt
1494 that the priority controller has queued! */
1495 devpriv->intClearMask = ~0;
1496 writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
1497 readw(devpriv->las0 + LAS0_CLEAR);
1499 /* TODO: allow multiple interrupt sources */
1500 if (devpriv->transCount > 0) { /* transfer every N samples */
1501 devpriv->intMask = IRQM_ADC_ABOUT_CNT;
1502 writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
1503 DPRINTK("rtd520: Transferring every %d\n", devpriv->transCount);
1504 } else { /* 1/2 FIFO transfers */
1506 devpriv->flags |= DMA0_ACTIVE;
1508 /* point to first transfer in ring */
1509 devpriv->dma0Offset = 0;
1510 RtdDma0Mode(dev, DMA_MODE_BITS);
1511 RtdDma0Next(dev, /* point to first block */
1512 devpriv->dma0Chain[DMA_CHAIN_COUNT - 1].next);
1513 RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL); /* set DMA trigger source */
1515 RtdPlxInterruptWrite(dev, /* enable interrupt */
1516 RtdPlxInterruptRead(dev) | ICS_DMA0_E);
1517 /* Must be 2 steps. See PLX app note about "Starting a DMA transfer" */
1518 RtdDma0Control(dev, PLX_DMA_EN_BIT); /* enable DMA (clear INTR?) */
1519 RtdDma0Control(dev, PLX_DMA_EN_BIT | PLX_DMA_START_BIT); /*start DMA */
1520 DPRINTK("rtd520: Using DMA0 transfers. plxInt %x RtdInt %x\n",
1521 RtdPlxInterruptRead(dev), devpriv->intMask);
1523 devpriv->intMask = IRQM_ADC_ABOUT_CNT;
1524 writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
1525 DPRINTK("rtd520: Transferring every 1/2 FIFO\n");
1526 #endif /* USE_DMA */
1529 /* BUG: start_src is ASSUMED to be TRIG_NOW */
1530 /* BUG? it seems like things are running before the "start" */
1531 readl(devpriv->las0 + LAS0_PACER);
1536 Stop a running data acquisition.
1538 static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1543 writel(0, devpriv->las0 + LAS0_PACER_STOP);
1544 writel(0, devpriv->las0 + LAS0_PACER);
1545 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1546 devpriv->intMask = 0;
1547 writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
1548 devpriv->aiCount = 0; /* stop and don't transfer any more */
1550 if (devpriv->flags & DMA0_ACTIVE) {
1551 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1552 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1554 devpriv->flags &= ~DMA0_ACTIVE;
1556 #endif /* USE_DMA */
1557 status = readw(devpriv->las0 + LAS0_IT);
1558 overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
1560 ("rtd520: Acquisition canceled. %ld ints, intStat=%x, overStat=%x\n",
1561 devpriv->intCount, status, overrun);
1566 Output one (or more) analog values to a single port as fast as possible.
1568 static int rtd_ao_winsn(struct comedi_device *dev,
1569 struct comedi_subdevice *s, struct comedi_insn *insn,
1573 int chan = CR_CHAN(insn->chanspec);
1574 int range = CR_RANGE(insn->chanspec);
1576 /* Configure the output range (table index matches the range values) */
1577 RtdDacRange(dev, chan, range);
1579 /* Writing a list of values to an AO channel is probably not
1580 * very useful, but that's how the interface is defined. */
1581 for (i = 0; i < insn->n; ++i) {
1582 int val = data[i] << 3;
1583 int stat = 0; /* initialize to avoid bogus warning */
1586 /* VERIFY: comedi range and offset conversions */
1588 if ((range > 1) /* bipolar */
1589 && (data[i] < 2048)) {
1590 /* offset and sign extend */
1591 val = (((int)data[i]) - 2048) << 3;
1592 } else { /* unipolor */
1597 ("comedi: rtd520 DAC chan=%d range=%d writing %d as 0x%x\n",
1598 chan, range, data[i], val);
1600 /* a typical programming sequence */
1601 RtdDacFifoPut(dev, chan, val); /* put the value in */
1602 RtdDacUpdate(dev, chan); /* trigger the conversion */
1604 devpriv->aoValue[chan] = data[i]; /* save for read back */
1606 for (ii = 0; ii < RTD_DAC_TIMEOUT; ++ii) {
1607 stat = readl(devpriv->las0 + LAS0_ADC);
1608 /* 1 -> not empty */
1609 if (stat & ((0 == chan) ? FS_DAC1_NOT_EMPTY :
1614 if (ii >= RTD_DAC_TIMEOUT) {
1616 ("rtd520: Error: DAC never finished! FifoStatus=0x%x\n",
1622 /* return the number of samples read/written */
1626 /* AO subdevices should have a read insn as well as a write insn.
1627 * Usually this means copying a value stored in devpriv. */
1628 static int rtd_ao_rinsn(struct comedi_device *dev,
1629 struct comedi_subdevice *s, struct comedi_insn *insn,
1633 int chan = CR_CHAN(insn->chanspec);
1635 for (i = 0; i < insn->n; i++)
1636 data[i] = devpriv->aoValue[chan];
1643 Write a masked set of bits and the read back the port.
1644 We track what the bits should be (i.e. we don't read the port first).
1646 DIO devices are slightly special. Although it is possible to
1647 * implement the insn_read/insn_write interface, it is much more
1648 * useful to applications if you implement the insn_bits interface.
1649 * This allows packed reading/writing of the DIO channels. The
1650 * comedi core can convert between insn_bits and insn_read/write
1652 static int rtd_dio_insn_bits(struct comedi_device *dev,
1653 struct comedi_subdevice *s,
1654 struct comedi_insn *insn, unsigned int *data)
1656 /* The insn data is a mask in data[0] and the new data
1657 * in data[1], each channel cooresponding to a bit. */
1659 s->state &= ~data[0];
1660 s->state |= data[0] & data[1];
1662 /* Write out the new digital output lines */
1663 RtdDio0Write(dev, s->state);
1665 /* on return, data[1] contains the value of the digital
1667 data[1] = RtdDio0Read(dev);
1669 /*DPRINTK("rtd520:port_0 wrote: 0x%x read: 0x%x\n", s->state, data[1]); */
1675 Configure one bit on a IO port as Input or Output (hence the name :-).
1677 static int rtd_dio_insn_config(struct comedi_device *dev,
1678 struct comedi_subdevice *s,
1679 struct comedi_insn *insn, unsigned int *data)
1681 int chan = CR_CHAN(insn->chanspec);
1683 /* The input or output configuration of each digital line is
1684 * configured by a special insn_config instruction. chanspec
1685 * contains the channel to be changed, and data[0] contains the
1686 * value COMEDI_INPUT or COMEDI_OUTPUT. */
1688 case INSN_CONFIG_DIO_OUTPUT:
1689 s->io_bits |= 1 << chan; /* 1 means Out */
1691 case INSN_CONFIG_DIO_INPUT:
1692 s->io_bits &= ~(1 << chan);
1694 case INSN_CONFIG_DIO_QUERY:
1696 (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
1703 DPRINTK("rtd520: port_0_direction=0x%x (1 means out)\n", s->io_bits);
1704 /* TODO support digital match interrupts and strobes */
1705 RtdDioStatusWrite(dev, 0x01); /* make Dio0Ctrl point to direction */
1706 RtdDio0CtrlWrite(dev, s->io_bits); /* set direction 1 means Out */
1707 RtdDioStatusWrite(dev, 0); /* make Dio0Ctrl clear interrupts */
1709 /* port1 can only be all input or all output */
1711 /* there are also 2 user input lines and 2 user output lines */
1716 static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1717 { /* board name and options flags */
1718 struct comedi_subdevice *s;
1719 struct pci_dev *pcidev;
1721 resource_size_t physLas0; /* configuration */
1722 resource_size_t physLas1; /* data area */
1723 resource_size_t physLcfg; /* PLX9080 */
1728 printk(KERN_INFO "comedi%d: rtd520 attaching.\n", dev->minor);
1730 #if defined(CONFIG_COMEDI_DEBUG) && defined(USE_DMA)
1731 /* You can set this a load time: modprobe comedi comedi_debug=1 */
1732 if (0 == comedi_debug) /* force DMA debug printks */
1737 * Allocate the private structure area. alloc_private() is a
1738 * convenient macro defined in comedidev.h.
1740 if (alloc_private(dev, sizeof(struct rtdPrivate)) < 0)
1744 * Probe the device to determine what device in the series it is.
1746 for (pcidev = pci_get_device(PCI_VENDOR_ID_RTD, PCI_ANY_ID, NULL);
1748 pcidev = pci_get_device(PCI_VENDOR_ID_RTD, PCI_ANY_ID, pcidev)) {
1751 if (it->options[0] || it->options[1]) {
1752 if (pcidev->bus->number != it->options[0]
1753 || PCI_SLOT(pcidev->devfn) != it->options[1]) {
1757 for (i = 0; i < ARRAY_SIZE(rtd520Boards); ++i) {
1758 if (pcidev->device == rtd520Boards[i].device_id) {
1759 dev->board_ptr = &rtd520Boards[i];
1764 break; /* found one */
1767 if (it->options[0] && it->options[1]) {
1768 printk(KERN_INFO "No RTD card at bus=%d slot=%d.\n",
1769 it->options[0], it->options[1]);
1771 printk(KERN_INFO "No RTD card found.\n");
1775 devpriv->pci_dev = pcidev;
1776 dev->board_name = thisboard->name;
1778 ret = comedi_pci_enable(pcidev, DRV_NAME);
1780 printk(KERN_INFO "Failed to enable PCI device and request regions.\n");
1783 devpriv->got_regions = 1;
1786 * Initialize base addresses
1788 /* Get the physical address from PCI config */
1789 physLas0 = pci_resource_start(devpriv->pci_dev, LAS0_PCIINDEX);
1790 physLas1 = pci_resource_start(devpriv->pci_dev, LAS1_PCIINDEX);
1791 physLcfg = pci_resource_start(devpriv->pci_dev, LCFG_PCIINDEX);
1792 /* Now have the kernel map this into memory */
1793 /* ASSUME page aligned */
1794 devpriv->las0 = ioremap_nocache(physLas0, LAS0_PCISIZE);
1795 devpriv->las1 = ioremap_nocache(physLas1, LAS1_PCISIZE);
1796 devpriv->lcfg = ioremap_nocache(physLcfg, LCFG_PCISIZE);
1798 if (!devpriv->las0 || !devpriv->las1 || !devpriv->lcfg)
1802 DPRINTK("%s: LAS0=%llx, LAS1=%llx, CFG=%llx.\n", dev->board_name,
1803 (unsigned long long)physLas0, (unsigned long long)physLas1,
1804 (unsigned long long)physLcfg);
1805 { /* The RTD driver does this */
1806 unsigned char pci_latency;
1808 /*uint32_t epld_version; */
1810 pci_read_config_word(devpriv->pci_dev, PCI_REVISION_ID,
1812 DPRINTK("%s: PCI revision %d.\n", dev->board_name, revision);
1814 pci_read_config_byte(devpriv->pci_dev,
1815 PCI_LATENCY_TIMER, &pci_latency);
1816 if (pci_latency < 32) {
1817 printk(KERN_INFO "%s: PCI latency changed from %d to %d\n",
1818 dev->board_name, pci_latency, 32);
1819 pci_write_config_byte(devpriv->pci_dev,
1820 PCI_LATENCY_TIMER, 32);
1822 DPRINTK("rtd520: PCI latency = %d\n", pci_latency);
1826 * Undocumented EPLD version (doesn't match RTD driver results)
1828 /*DPRINTK ("rtd520: Reading epld from %p\n",
1830 epld_version = readl (devpriv->las0+0);
1831 if ((epld_version & 0xF0) >> 4 == 0x0F) {
1832 DPRINTK("rtd520: pre-v8 EPLD. (%x)\n", epld_version);
1834 DPRINTK("rtd520: EPLD version %x.\n", epld_version >> 4);
1838 /* Show board configuration */
1839 printk(KERN_INFO "%s:", dev->board_name);
1841 ret = comedi_alloc_subdevices(dev, 4);
1845 s = dev->subdevices + 0;
1846 dev->read_subdev = s;
1847 /* analog input subdevice */
1848 s->type = COMEDI_SUBD_AI;
1850 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
1851 s->n_chan = thisboard->aiChans;
1852 s->maxdata = (1 << thisboard->aiBits) - 1;
1853 if (thisboard->aiMaxGain <= 32)
1854 s->range_table = &rtd_ai_7520_range;
1856 s->range_table = &rtd_ai_4520_range;
1858 s->len_chanlist = RTD_MAX_CHANLIST; /* devpriv->fifoLen */
1859 s->insn_read = rtd_ai_rinsn;
1860 s->do_cmd = rtd_ai_cmd;
1861 s->do_cmdtest = rtd_ai_cmdtest;
1862 s->cancel = rtd_ai_cancel;
1863 /* s->poll = rtd_ai_poll; *//* not ready yet */
1865 s = dev->subdevices + 1;
1866 /* analog output subdevice */
1867 s->type = COMEDI_SUBD_AO;
1868 s->subdev_flags = SDF_WRITABLE;
1870 s->maxdata = (1 << thisboard->aiBits) - 1;
1871 s->range_table = &rtd_ao_range;
1872 s->insn_write = rtd_ao_winsn;
1873 s->insn_read = rtd_ao_rinsn;
1875 s = dev->subdevices + 2;
1876 /* digital i/o subdevice */
1877 s->type = COMEDI_SUBD_DIO;
1878 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1879 /* we only support port 0 right now. Ignoring port 1 and user IO */
1882 s->range_table = &range_digital;
1883 s->insn_bits = rtd_dio_insn_bits;
1884 s->insn_config = rtd_dio_insn_config;
1886 /* timer/counter subdevices (not currently supported) */
1887 s = dev->subdevices + 3;
1888 s->type = COMEDI_SUBD_COUNTER;
1889 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1891 s->maxdata = 0xffff;
1893 /* initialize board, per RTD spec */
1894 /* also, initialize shadow registers */
1895 writel(0, devpriv->las0 + LAS0_BOARD_RESET);
1896 udelay(100); /* needed? */
1897 RtdPlxInterruptWrite(dev, 0);
1898 devpriv->intMask = 0;
1899 writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
1900 devpriv->intClearMask = ~0;
1901 writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
1902 readw(devpriv->las0 + LAS0_CLEAR);
1903 writel(0, devpriv->las0 + LAS0_OVERRUN);
1904 writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
1905 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
1906 RtdDacClearFifo(dev, 0);
1907 RtdDacClearFifo(dev, 1);
1908 /* clear digital IO fifo */
1909 RtdDioStatusWrite(dev, 0); /* safe state, set shadow */
1910 devpriv->utcCtrl[0] = (0 << 6) | 0x30;
1911 devpriv->utcCtrl[1] = (1 << 6) | 0x30;
1912 devpriv->utcCtrl[2] = (2 << 6) | 0x30;
1913 devpriv->utcCtrl[3] = (3 << 6) | 0x00;
1914 writeb(devpriv->utcCtrl[0], devpriv->las0 + LAS0_UTC_CTRL);
1915 writeb(devpriv->utcCtrl[1], devpriv->las0 + LAS0_UTC_CTRL);
1916 writeb(devpriv->utcCtrl[2], devpriv->las0 + LAS0_UTC_CTRL);
1917 writeb(devpriv->utcCtrl[3], devpriv->las0 + LAS0_UTC_CTRL);
1918 /* TODO: set user out source ??? */
1920 /* check if our interrupt is available and get it */
1921 ret = request_irq(devpriv->pci_dev->irq, rtd_interrupt,
1922 IRQF_SHARED, DRV_NAME, dev);
1925 printk("Could not get interrupt! (%u)\n",
1926 devpriv->pci_dev->irq);
1929 dev->irq = devpriv->pci_dev->irq;
1930 printk(KERN_INFO "( irq=%u )", dev->irq);
1932 ret = rtd520_probe_fifo_depth(dev);
1936 devpriv->fifoLen = ret;
1937 printk("( fifoLen=%d )", devpriv->fifoLen);
1941 printk("( DMA buff=%d )\n", DMA_CHAIN_COUNT);
1943 * The PLX9080 has 2 DMA controllers, but there could be
1944 * 4 sources: ADC, digital, DAC1, and DAC2. Since only the
1945 * ADC supports cmd mode right now, this isn't an issue (yet)
1947 devpriv->dma0Offset = 0;
1949 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
1950 devpriv->dma0Buff[index] =
1951 pci_alloc_consistent(devpriv->pci_dev,
1953 devpriv->fifoLen / 2,
1955 dma0BuffPhysAddr[index]);
1956 if (devpriv->dma0Buff[index] == NULL) {
1958 goto rtd_attach_die_error;
1960 /*DPRINTK ("buff[%d] @ %p virtual, %x PCI\n",
1962 devpriv->dma0Buff[index],
1963 devpriv->dma0BuffPhysAddr[index]); */
1967 * setup DMA descriptor ring (use cpu_to_le32 for byte
1970 devpriv->dma0Chain =
1971 pci_alloc_consistent(devpriv->pci_dev,
1972 sizeof(struct plx_dma_desc) *
1974 &devpriv->dma0ChainPhysAddr);
1975 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
1976 devpriv->dma0Chain[index].pci_start_addr =
1977 devpriv->dma0BuffPhysAddr[index];
1978 devpriv->dma0Chain[index].local_start_addr =
1980 devpriv->dma0Chain[index].transfer_size =
1981 sizeof(u16) * devpriv->fifoLen / 2;
1982 devpriv->dma0Chain[index].next =
1983 (devpriv->dma0ChainPhysAddr + ((index +
1986 * sizeof(devpriv->dma0Chain[0]))
1987 | DMA_TRANSFER_BITS;
1988 /*DPRINTK ("ring[%d] @%lx PCI: %x, local: %x, N: 0x%x, next: %x\n",
1990 ((long)devpriv->dma0ChainPhysAddr
1991 + (index * sizeof(devpriv->dma0Chain[0]))),
1992 devpriv->dma0Chain[index].pci_start_addr,
1993 devpriv->dma0Chain[index].local_start_addr,
1994 devpriv->dma0Chain[index].transfer_size,
1995 devpriv->dma0Chain[index].next); */
1998 if (devpriv->dma0Chain == NULL) {
2000 goto rtd_attach_die_error;
2003 RtdDma0Mode(dev, DMA_MODE_BITS);
2004 /* set DMA trigger source */
2005 RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL);
2007 printk(KERN_INFO "( no IRQ->no DMA )");
2009 #endif /* USE_DMA */
2011 if (dev->irq) { /* enable plx9080 interrupts */
2012 RtdPlxInterruptWrite(dev, ICS_PIE | ICS_PLIE);
2015 printk("\ncomedi%d: rtd520 driver attached.\n", dev->minor);
2020 /* hit an error, clean up memory and return ret */
2021 /* rtd_attach_die_error: */
2023 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2024 if (NULL != devpriv->dma0Buff[index]) { /* free buffer memory */
2025 pci_free_consistent(devpriv->pci_dev,
2026 sizeof(u16) * devpriv->fifoLen / 2,
2027 devpriv->dma0Buff[index],
2028 devpriv->dma0BuffPhysAddr[index]);
2029 devpriv->dma0Buff[index] = NULL;
2032 if (NULL != devpriv->dma0Chain) {
2033 pci_free_consistent(devpriv->pci_dev,
2034 sizeof(struct plx_dma_desc)
2037 devpriv->dma0ChainPhysAddr);
2038 devpriv->dma0Chain = NULL;
2040 #endif /* USE_DMA */
2041 /* subdevices and priv are freed by the core */
2043 /* disable interrupt controller */
2044 RtdPlxInterruptWrite(dev, RtdPlxInterruptRead(dev)
2045 & ~(ICS_PLIE | ICS_DMA0_E | ICS_DMA1_E));
2046 free_irq(dev->irq, dev);
2049 /* release all regions that were allocated */
2051 iounmap(devpriv->las0);
2054 iounmap(devpriv->las1);
2057 iounmap(devpriv->lcfg);
2059 if (devpriv->pci_dev)
2060 pci_dev_put(devpriv->pci_dev);
2066 static void rtd_detach(struct comedi_device *dev)
2073 /* Shut down any board ops by resetting it */
2075 if (devpriv->lcfg) {
2076 RtdDma0Control(dev, 0); /* disable DMA */
2077 RtdDma1Control(dev, 0); /* disable DMA */
2078 RtdPlxInterruptWrite(dev, ICS_PIE | ICS_PLIE);
2080 #endif /* USE_DMA */
2081 if (devpriv->las0) {
2082 writel(0, devpriv->las0 + LAS0_BOARD_RESET);
2083 devpriv->intMask = 0;
2084 writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
2085 devpriv->intClearMask = ~0;
2086 writew(devpriv->intClearMask,
2087 devpriv->las0 + LAS0_CLEAR);
2088 readw(devpriv->las0 + LAS0_CLEAR);
2092 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2093 if (NULL != devpriv->dma0Buff[index]) {
2094 pci_free_consistent(devpriv->pci_dev,
2096 devpriv->fifoLen / 2,
2097 devpriv->dma0Buff[index],
2099 dma0BuffPhysAddr[index]);
2100 devpriv->dma0Buff[index] = NULL;
2103 if (NULL != devpriv->dma0Chain) {
2104 pci_free_consistent(devpriv->pci_dev,
2105 sizeof(struct plx_dma_desc) *
2106 DMA_CHAIN_COUNT, devpriv->dma0Chain,
2107 devpriv->dma0ChainPhysAddr);
2108 devpriv->dma0Chain = NULL;
2110 #endif /* USE_DMA */
2112 RtdPlxInterruptWrite(dev, RtdPlxInterruptRead(dev)
2113 & ~(ICS_PLIE | ICS_DMA0_E |
2115 free_irq(dev->irq, dev);
2118 iounmap(devpriv->las0);
2120 iounmap(devpriv->las1);
2122 iounmap(devpriv->lcfg);
2123 if (devpriv->pci_dev) {
2124 if (devpriv->got_regions)
2125 comedi_pci_disable(devpriv->pci_dev);
2126 pci_dev_put(devpriv->pci_dev);
2131 static struct comedi_driver rtd520_driver = {
2132 .driver_name = "rtd520",
2133 .module = THIS_MODULE,
2134 .attach = rtd_attach,
2135 .detach = rtd_detach,
2138 static int __devinit rtd520_pci_probe(struct pci_dev *dev,
2139 const struct pci_device_id *ent)
2141 return comedi_pci_auto_config(dev, &rtd520_driver);
2144 static void __devexit rtd520_pci_remove(struct pci_dev *dev)
2146 comedi_pci_auto_unconfig(dev);
2149 static DEFINE_PCI_DEVICE_TABLE(rtd520_pci_table) = {
2150 { PCI_DEVICE(PCI_VENDOR_ID_RTD, 0x7520) },
2151 { PCI_DEVICE(PCI_VENDOR_ID_RTD, 0x4520) },
2154 MODULE_DEVICE_TABLE(pci, rtd520_pci_table);
2156 static struct pci_driver rtd520_pci_driver = {
2158 .id_table = rtd520_pci_table,
2159 .probe = rtd520_pci_probe,
2160 .remove = __devexit_p(rtd520_pci_remove),
2162 module_comedi_pci_driver(rtd520_driver, rtd520_pci_driver);
2164 MODULE_AUTHOR("Comedi http://www.comedi.org");
2165 MODULE_DESCRIPTION("Comedi low-level driver");
2166 MODULE_LICENSE("GPL");