2 comedi/drivers/rtd520.c
3 Comedi driver for Real Time Devices (RTD) PCI4520/DM7520
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2001 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: Real Time Devices PCI4520/DM7520
26 Devices: [Real Time Devices] DM7520HR-1 (rtd520), DM7520HR-8,
28 Status: Works. Only tested on DM7520-8. Not SMP safe.
30 Configuration options:
31 [0] - PCI bus of device (optional)
32 If bus / slot is not specified, the first available PCI
34 [1] - PCI slot of device (optional)
37 Created by Dan Christian, NASA Ames Research Center.
39 The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
41 8/16 12 bit ADC with FIFO and channel gain table
42 8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
43 8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
44 2 12 bit DACs with FIFOs
48 timers: ADC sample, pacer, burst, about, delay, DA1, DA2
50 3 user timer/counters (8254)
53 The DM7520 has slightly fewer features (fewer gain steps).
55 These boards can support external multiplexors and multi-board
56 synchronization, but this driver doesn't support that.
58 Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
59 Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
60 Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
61 Call them and ask for the register level manual.
62 PCI chip: http://www.plxtech.com/products/io/pci9080
65 This board is memory mapped. There is some IO stuff, but it isn't needed.
67 I use a pretty loose naming style within the driver (rtd_blah).
68 All externally visible names should be rtd520_blah.
69 I use camelCase for structures (and inside them).
70 I may also use upper CamelCase for function names (old habit).
72 This board is somewhat related to the RTD PCI4400 board.
74 I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
75 das1800, since they have the best documented code. Driver
76 cb_pcidas64.c uses the same DMA controller.
78 As far as I can tell, the About interrupt doesn't work if Sample is
79 also enabled. It turns out that About really isn't needed, since
80 we always count down samples read.
82 There was some timer/counter code, but it didn't follow the right API.
89 Analog-In supports instruction and command mode.
91 With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
92 (single channel, 64K read buffer). I get random system lockups when
93 using DMA with ALI-15xx based systems. I haven't been able to test
94 any other chipsets. The lockups happen soon after the start of an
95 acquistion, not in the middle of a long run.
97 Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
98 (with a 256K read buffer).
100 Digital-IO and Analog-Out only support instruction mode.
104 #include <linux/interrupt.h>
105 #include <linux/delay.h>
107 #include "../comedidev.h"
109 #define DRV_NAME "rtd520"
111 /*======================================================================
112 Driver specific stuff (tunable)
113 ======================================================================*/
114 /* Enable this to test the new DMA support. You may get hard lock ups */
117 /* We really only need 2 buffers. More than that means being much
118 smarter about knowing which ones are full. */
119 #define DMA_CHAIN_COUNT 2 /* max DMA segments/buffers in a ring (min 2) */
121 /* Target period for periodic transfers. This sets the user read latency. */
122 /* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
123 /* If this is too low, efficiency is poor */
124 #define TRANS_TARGET_PERIOD 10000000 /* 10 ms (in nanoseconds) */
126 /* Set a practical limit on how long a list to support (affects memory use) */
127 /* The board support a channel list up to the FIFO length (1K or 8K) */
128 #define RTD_MAX_CHANLIST 128 /* max channel list that we allow */
130 /* tuning for ai/ao instruction done polling */
132 #define WAIT_QUIETLY /* as nothing, spin on done bit */
133 #define RTD_ADC_TIMEOUT 66000 /* 2 msec at 33mhz bus rate */
134 #define RTD_DAC_TIMEOUT 66000
135 #define RTD_DMA_TIMEOUT 33000 /* 1 msec */
137 /* by delaying, power and electrical noise are reduced somewhat */
138 #define WAIT_QUIETLY udelay(1)
139 #define RTD_ADC_TIMEOUT 2000 /* in usec */
140 #define RTD_DAC_TIMEOUT 2000 /* in usec */
141 #define RTD_DMA_TIMEOUT 1000 /* in usec */
144 /*======================================================================
146 ======================================================================*/
149 #define PCI_VENDOR_ID_RTD 0x1435
151 The board has three memory windows: las0, las1, and lcfg (the PCI chip)
152 Las1 has the data and can be burst DMAed 32bits at a time.
154 #define LCFG_PCIINDEX 0
155 /* PCI region 1 is a 256 byte IO space mapping. Use??? */
156 #define LAS0_PCIINDEX 2 /* PCI memory resources */
157 #define LAS1_PCIINDEX 3
158 #define LCFG_PCISIZE 0x100
159 #define LAS0_PCISIZE 0x200
160 #define LAS1_PCISIZE 0x10
162 #define RTD_CLOCK_RATE 8000000 /* 8Mhz onboard clock */
163 #define RTD_CLOCK_BASE 125 /* clock period in ns */
165 /* Note: these speed are slower than the spec, but fit the counter resolution*/
166 #define RTD_MAX_SPEED 1625 /* when sampling, in nanoseconds */
167 /* max speed if we don't have to wait for settling */
168 #define RTD_MAX_SPEED_1 875 /* if single channel, in nanoseconds */
170 #define RTD_MIN_SPEED 2097151875 /* (24bit counter) in nanoseconds */
171 /* min speed when only 1 channel (no burst counter) */
172 #define RTD_MIN_SPEED_1 5000000 /* 200Hz, in nanoseconds */
177 /* Setup continuous ring of 1/2 FIFO transfers. See RTD manual p91 */
178 #define DMA_MODE_BITS (\
179 PLX_LOCAL_BUS_16_WIDE_BITS \
180 | PLX_DMA_EN_READYIN_BIT \
181 | PLX_DMA_LOCAL_BURST_EN_BIT \
183 | PLX_DMA_INTR_PCI_BIT \
184 | PLX_LOCAL_ADDR_CONST_BIT \
185 | PLX_DEMAND_MODE_BIT)
187 #define DMA_TRANSFER_BITS (\
188 /* descriptors in PCI memory*/ PLX_DESC_IN_PCI_BIT \
189 /* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
190 /* from board to PCI */ | PLX_XFER_LOCAL_TO_PCI)
192 /*======================================================================
193 Comedi specific stuff
194 ======================================================================*/
197 The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
199 static const struct comedi_lrange rtd_ai_7520_range = { 18, {
200 /* +-5V input range gain steps */
209 /* +-10V input range gain steps */
221 /* +10V input range gain steps */
237 /* PCI4520 has two more gains (6 more entries) */
238 static const struct comedi_lrange rtd_ai_4520_range = { 24, {
239 /* +-5V input range gain steps */
252 /* +-10V input range gain steps */
268 /* +10V input range gain steps */
287 /* Table order matches range values */
288 static const struct comedi_lrange rtd_ao_range = { 4, {
300 const char *name; /* must be first */
305 int range10Start; /* start of +-10V range */
306 int rangeUniStart; /* start of +10V range */
309 static const struct rtdBoard rtd520Boards[] = {
331 * Useful for shorthand access to the particular board structure
333 #define thisboard ((const struct rtdBoard *)dev->board_ptr)
336 This structure is for data unique to this hardware driver.
337 This is also unique for each board in the system.
340 /* memory mapped board structures */
345 unsigned long intCount; /* interrupt count */
346 long aiCount; /* total transfer size (samples) */
347 int transCount; /* # to transfer data. 0->1/2FIFO */
348 int flags; /* flag event modes */
350 /* PCI device info */
351 struct pci_dev *pci_dev;
352 int got_regions; /* non-zero if PCI regions owned */
354 /* channel list info */
355 /* chanBipolar tracks whether a channel is bipolar (and needs +2048) */
356 unsigned char chanBipolar[RTD_MAX_CHANLIST / 8]; /* bit array */
359 unsigned int aoValue[2]; /* Used for AO read back */
361 /* timer gate (when enabled) */
362 u8 utcGate[4]; /* 1 extra allows simple range check */
364 /* shadow registers affect other registers, but can't be read back */
365 /* The macros below update these on writes */
366 u16 intMask; /* interrupt mask */
367 u16 intClearMask; /* interrupt clear mask */
368 u8 utcCtrl[4]; /* crtl mode for 3 utc + read back */
369 u8 dioStatus; /* could be read back (dio0Ctrl) */
372 * Always DMA 1/2 FIFO. Buffer (dmaBuff?) is (at least) twice that
373 * size. After transferring, interrupt processes 1/2 FIFO and
376 s16 dma0Offset; /* current processing offset (0, 1/2) */
377 uint16_t *dma0Buff[DMA_CHAIN_COUNT]; /* DMA buffers (for ADC) */
378 dma_addr_t dma0BuffPhysAddr[DMA_CHAIN_COUNT]; /* physical addresses */
379 struct plx_dma_desc *dma0Chain; /* DMA descriptor ring for dmaBuff */
380 dma_addr_t dma0ChainPhysAddr; /* physical addresses */
381 /* shadow registers */
388 /* bit defines for "flags" */
389 #define SEND_EOS 0x01 /* send End Of Scan events */
390 #define DMA0_ACTIVE 0x02 /* DMA0 is active */
391 #define DMA1_ACTIVE 0x04 /* DMA1 is active */
393 /* Macros for accessing channel list bit array */
394 #define CHAN_ARRAY_TEST(array, index) \
395 (((array)[(index)/8] >> ((index) & 0x7)) & 0x1)
396 #define CHAN_ARRAY_SET(array, index) \
397 (((array)[(index)/8] |= 1 << ((index) & 0x7)))
398 #define CHAN_ARRAY_CLEAR(array, index) \
399 (((array)[(index)/8] &= ~(1 << ((index) & 0x7))))
402 * most drivers define the following macro to make it easy to
403 * access the private structure.
405 #define devpriv ((struct rtdPrivate *)dev->private)
407 /* Macros to access registers */
409 /* Set external trigger polarity (write only) 0=positive edge, 1=negative */
410 #define RtdTriggerPolarity(dev, v) \
411 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_ETRG_POLARITY)
413 /* Start single ADC conversion */
414 #define RtdAdcStart(dev) \
415 writew(0, devpriv->las0+LAS0_ADC)
417 /* Read one ADC data value (12bit (with sign extend) as 16bit) */
418 /* Note: matches what DMA would get. Actual value >> 3 */
419 #define RtdAdcFifoGet(dev) \
420 readw(devpriv->las1+LAS1_ADC_FIFO)
422 /* Read two ADC data values (DOESN'T WORK) */
423 #define RtdAdcFifoGet2(dev) \
424 readl(devpriv->las1+LAS1_ADC_FIFO)
427 #define RtdFifoStatus(dev) \
428 readl(devpriv->las0+LAS0_ADC)
430 /* pacer start/stop read=start, write=stop*/
431 #define RtdPacerStart(dev) \
432 readl(devpriv->las0+LAS0_PACER)
433 #define RtdPacerStop(dev) \
434 writel(0, devpriv->las0+LAS0_PACER)
436 /* Interrupt status */
437 #define RtdInterruptStatus(dev) \
438 readw(devpriv->las0+LAS0_IT)
441 #define RtdInterruptMask(dev, v) \
442 writew((devpriv->intMask = (v)), devpriv->las0+LAS0_IT)
444 /* Interrupt status clear (only bits set in mask) */
445 #define RtdInterruptClear(dev) \
446 readw(devpriv->las0+LAS0_CLEAR)
448 /* Interrupt clear mask */
449 #define RtdInterruptClearMask(dev, v) \
450 writew((devpriv->intClearMask = (v)), devpriv->las0+LAS0_CLEAR)
452 /* Interrupt overrun status */
453 #define RtdInterruptOverrunStatus(dev) \
454 readl(devpriv->las0+LAS0_OVERRUN)
456 /* Interrupt overrun clear */
457 #define RtdInterruptOverrunClear(dev) \
458 writel(0, devpriv->las0+LAS0_OVERRUN)
460 /* Pacer counter, 24bit */
461 #define RtdPacerCount(dev) \
462 readl(devpriv->las0+LAS0_PCLK)
463 #define RtdPacerCounter(dev, v) \
464 writel((v) & 0xffffff, devpriv->las0+LAS0_PCLK)
466 /* Burst counter, 10bit */
467 #define RtdBurstCount(dev) \
468 readl(devpriv->las0+LAS0_BCLK)
469 #define RtdBurstCounter(dev, v) \
470 writel((v) & 0x3ff, devpriv->las0+LAS0_BCLK)
472 /* Delay counter, 16bit */
473 #define RtdDelayCount(dev) \
474 readl(devpriv->las0+LAS0_DCLK)
475 #define RtdDelayCounter(dev, v) \
476 writel((v) & 0xffff, devpriv->las0+LAS0_DCLK)
478 /* About counter, 16bit */
479 #define RtdAboutCount(dev) \
480 readl(devpriv->las0+LAS0_ACNT)
481 #define RtdAboutCounter(dev, v) \
482 writel((v) & 0xffff, devpriv->las0+LAS0_ACNT)
484 /* ADC sample counter, 10bit */
485 #define RtdAdcSampleCount(dev) \
486 readl(devpriv->las0+LAS0_ADC_SCNT)
487 #define RtdAdcSampleCounter(dev, v) \
488 writel((v) & 0x3ff, devpriv->las0+LAS0_ADC_SCNT)
490 /* User Timer/Counter (8254) */
491 #define RtdUtcCounterGet(dev, n) \
492 readb(devpriv->las0 \
493 + ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
495 #define RtdUtcCounterPut(dev, n, v) \
496 writeb((v) & 0xff, devpriv->las0 \
497 + ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
499 /* Set UTC (8254) control byte */
500 #define RtdUtcCtrlPut(dev, n, v) \
501 writeb(devpriv->utcCtrl[(n) & 3] = (((n) & 3) << 6) | ((v) & 0x3f), \
502 devpriv->las0 + LAS0_UTC_CTRL)
504 /* Set UTCn clock source (write only) */
505 #define RtdUtcClockSource(dev, n, v) \
506 writew(v, devpriv->las0 \
507 + ((n <= 0) ? LAS0_UTC0_CLOCK : \
508 ((1 == n) ? LAS0_UTC1_CLOCK : LAS0_UTC2_CLOCK)))
510 /* Set UTCn gate source (write only) */
511 #define RtdUtcGateSource(dev, n, v) \
512 writew(v, devpriv->las0 \
513 + ((n <= 0) ? LAS0_UTC0_GATE : \
514 ((1 == n) ? LAS0_UTC1_GATE : LAS0_UTC2_GATE)))
516 /* User output N source select (write only) */
517 #define RtdUsrOutSource(dev, n, v) \
518 writel(v, devpriv->las0+((n <= 0) ? LAS0_UOUT0_SELECT : \
522 #define RtdDio0Read(dev) \
523 (readw(devpriv->las0+LAS0_DIO0) & 0xff)
524 #define RtdDio0Write(dev, v) \
525 writew((v) & 0xff, devpriv->las0+LAS0_DIO0)
527 #define RtdDio1Read(dev) \
528 (readw(devpriv->las0+LAS0_DIO1) & 0xff)
529 #define RtdDio1Write(dev, v) \
530 writew((v) & 0xff, devpriv->las0+LAS0_DIO1)
532 #define RtdDioStatusRead(dev) \
533 (readw(devpriv->las0+LAS0_DIO_STATUS) & 0xff)
534 #define RtdDioStatusWrite(dev, v) \
535 writew((devpriv->dioStatus = (v)), devpriv->las0+LAS0_DIO_STATUS)
537 #define RtdDio0CtrlRead(dev) \
538 (readw(devpriv->las0+LAS0_DIO0_CTRL) & 0xff)
539 #define RtdDio0CtrlWrite(dev, v) \
540 writew((v) & 0xff, devpriv->las0+LAS0_DIO0_CTRL)
542 /* Digital to Analog converter */
543 /* Write one data value (sign + 12bit + marker bits) */
544 /* Note: matches what DMA would put. Actual value << 3 */
545 #define RtdDacFifoPut(dev, n, v) \
546 writew((v), devpriv->las1 + (((n) == 0) ? LAS1_DAC1_FIFO : \
549 /* Start single DAC conversion */
550 #define RtdDacUpdate(dev, n) \
551 writew(0, devpriv->las0 + (((n) == 0) ? LAS0_DAC1 : LAS0_DAC2))
553 /* Start single DAC conversion on both DACs */
554 #define RtdDacBothUpdate(dev) \
555 writew(0, devpriv->las0+LAS0_DAC)
557 /* Set DAC output type and range */
558 #define RtdDacRange(dev, n, v) \
559 writew((v) & 7, devpriv->las0 \
560 +(((n) == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL))
563 #define RtdDacClearFifo(dev, n) \
564 writel(0, devpriv->las0+(((n) == 0) ? LAS0_DAC1_RESET : \
567 /* Set source for DMA 0 (write only, shadow?) */
568 #define RtdDma0Source(dev, n) \
569 writel((n) & 0xf, devpriv->las0+LAS0_DMA0_SRC)
571 /* Set source for DMA 1 (write only, shadow?) */
572 #define RtdDma1Source(dev, n) \
573 writel((n) & 0xf, devpriv->las0+LAS0_DMA1_SRC)
575 /* Reset board state for DMA 0 */
576 #define RtdDma0Reset(dev) \
577 writel(0, devpriv->las0+LAS0_DMA0_RESET)
579 /* Reset board state for DMA 1 */
580 #define RtdDma1Reset(dev) \
581 writel(0, devpriv->las0+LAS0_DMA1_SRC)
583 /* PLX9080 interrupt mask and status */
584 #define RtdPlxInterruptRead(dev) \
585 readl(devpriv->lcfg+LCFG_ITCSR)
586 #define RtdPlxInterruptWrite(dev, v) \
587 writel(v, devpriv->lcfg+LCFG_ITCSR)
589 /* Set mode for DMA 0 */
590 #define RtdDma0Mode(dev, m) \
591 writel((m), devpriv->lcfg+LCFG_DMAMODE0)
593 /* Set PCI address for DMA 0 */
594 #define RtdDma0PciAddr(dev, a) \
595 writel((a), devpriv->lcfg+LCFG_DMAPADR0)
597 /* Set local address for DMA 0 */
598 #define RtdDma0LocalAddr(dev, a) \
599 writel((a), devpriv->lcfg+LCFG_DMALADR0)
601 /* Set byte count for DMA 0 */
602 #define RtdDma0Count(dev, c) \
603 writel((c), devpriv->lcfg+LCFG_DMASIZ0)
605 /* Set next descriptor for DMA 0 */
606 #define RtdDma0Next(dev, a) \
607 writel((a), devpriv->lcfg+LCFG_DMADPR0)
609 /* Set mode for DMA 1 */
610 #define RtdDma1Mode(dev, m) \
611 writel((m), devpriv->lcfg+LCFG_DMAMODE1)
613 /* Set PCI address for DMA 1 */
614 #define RtdDma1PciAddr(dev, a) \
615 writel((a), devpriv->lcfg+LCFG_DMAADR1)
617 /* Set local address for DMA 1 */
618 #define RtdDma1LocalAddr(dev, a) \
619 writel((a), devpriv->lcfg+LCFG_DMALADR1)
621 /* Set byte count for DMA 1 */
622 #define RtdDma1Count(dev, c) \
623 writel((c), devpriv->lcfg+LCFG_DMASIZ1)
625 /* Set next descriptor for DMA 1 */
626 #define RtdDma1Next(dev, a) \
627 writel((a), devpriv->lcfg+LCFG_DMADPR1)
629 /* Set control for DMA 0 (write only, shadow?) */
630 #define RtdDma0Control(dev, n) \
631 writeb(devpriv->dma0Control = (n), devpriv->lcfg+LCFG_DMACSR0)
633 /* Get status for DMA 0 */
634 #define RtdDma0Status(dev) \
635 readb(devpriv->lcfg+LCFG_DMACSR0)
637 /* Set control for DMA 1 (write only, shadow?) */
638 #define RtdDma1Control(dev, n) \
639 writeb(devpriv->dma1Control = (n), devpriv->lcfg+LCFG_DMACSR1)
641 /* Get status for DMA 1 */
642 #define RtdDma1Status(dev) \
643 readb(devpriv->lcfg+LCFG_DMACSR1)
646 Given a desired period and the clock period (both in ns),
647 return the proper counter value (divider-1).
648 Sets the original period to be the true value.
649 Note: you have to check if the value is larger than the counter range!
651 static int rtd_ns_to_timer_base(unsigned int *nanosec, /* desired period (in ns) */
652 int round_mode, int base)
653 { /* clock period (in ns) */
656 switch (round_mode) {
657 case TRIG_ROUND_NEAREST:
659 divider = (*nanosec + base / 2) / base;
661 case TRIG_ROUND_DOWN:
662 divider = (*nanosec) / base;
665 divider = (*nanosec + base - 1) / base;
669 divider = 2; /* min is divide by 2 */
671 /* Note: we don't check for max, because different timers
672 have different ranges */
674 *nanosec = base * divider;
675 return divider - 1; /* countdown is divisor+1 */
679 Given a desired period (in ns),
680 return the proper counter value (divider-1) for the internal clock.
681 Sets the original period to be the true value.
683 static int rtd_ns_to_timer(unsigned int *ns, int round_mode)
685 return rtd_ns_to_timer_base(ns, round_mode, RTD_CLOCK_BASE);
689 Convert a single comedi channel-gain entry to a RTD520 table entry
691 static unsigned short rtdConvertChanGain(struct comedi_device *dev,
692 unsigned int comediChan, int chanIndex)
693 { /* index in channel list */
694 unsigned int chan, range, aref;
695 unsigned short r = 0;
697 chan = CR_CHAN(comediChan);
698 range = CR_RANGE(comediChan);
699 aref = CR_AREF(comediChan);
703 /* Note: we also setup the channel list bipolar flag array */
704 if (range < thisboard->range10Start) { /* first batch are +-5 */
705 r |= 0x000; /* +-5 range */
706 r |= (range & 0x7) << 4; /* gain */
707 CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
708 } else if (range < thisboard->rangeUniStart) { /* second batch are +-10 */
709 r |= 0x100; /* +-10 range */
711 r |= ((range - thisboard->range10Start) & 0x7) << 4;
712 CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
713 } else { /* last batch is +10 */
714 r |= 0x200; /* +10 range */
716 r |= ((range - thisboard->rangeUniStart) & 0x7) << 4;
717 CHAN_ARRAY_CLEAR(devpriv->chanBipolar, chanIndex);
721 case AREF_GROUND: /* on-board ground */
725 r |= 0x80; /* ref external analog common */
729 r |= 0x400; /* differential inputs */
732 case AREF_OTHER: /* ??? */
735 /*printk ("chan=%d r=%d a=%d -> 0x%x\n",
736 chan, range, aref, r); */
741 Setup the channel-gain table from a comedi list
743 static void rtd_load_channelgain_list(struct comedi_device *dev,
744 unsigned int n_chan, unsigned int *list)
746 if (n_chan > 1) { /* setup channel gain table */
749 writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
750 writel(1, devpriv->las0 + LAS0_CGT_ENABLE);
751 for (ii = 0; ii < n_chan; ii++) {
752 writel(rtdConvertChanGain(dev, list[ii], ii),
753 devpriv->las0 + LAS0_CGT_WRITE);
755 } else { /* just use the channel gain latch */
756 writel(0, devpriv->las0 + LAS0_CGT_ENABLE);
757 writel(rtdConvertChanGain(dev, list[0], 0),
758 devpriv->las0 + LAS0_CGL_WRITE);
762 /* determine fifo size by doing adc conversions until the fifo half
763 empty status flag clears */
764 static int rtd520_probe_fifo_depth(struct comedi_device *dev)
766 unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
768 static const unsigned limit = 0x2000;
769 unsigned fifo_size = 0;
771 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
772 rtd_load_channelgain_list(dev, 1, &chanspec);
773 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
774 /* convert samples */
775 for (i = 0; i < limit; ++i) {
776 unsigned fifo_status;
777 /* trigger conversion */
780 fifo_status = RtdFifoStatus(dev);
781 if ((fifo_status & FS_ADC_HEMPTY) == 0) {
787 printk(KERN_INFO "\ncomedi: %s: failed to probe fifo size.\n",
791 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
792 if (fifo_size != 0x400 && fifo_size != 0x2000) {
794 (KERN_INFO "\ncomedi: %s: unexpected fifo size of %i, expected 1024 or 8192.\n",
795 DRV_NAME, fifo_size);
802 "instructions" read/write data in "one-shot" or "software-triggered"
803 mode (simplest case).
804 This doesn't use interrupts.
806 Note, we don't do any settling delays. Use a instruction list to
807 select, delay, then read.
809 static int rtd_ai_rinsn(struct comedi_device *dev,
810 struct comedi_subdevice *s, struct comedi_insn *insn,
816 /* clear any old fifo data */
817 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
819 /* write channel to multiplexer and clear channel gain table */
820 rtd_load_channelgain_list(dev, 1, &insn->chanspec);
822 /* set conversion source */
823 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
825 /* convert n samples */
826 for (n = 0; n < insn->n; n++) {
828 /* trigger conversion */
831 for (ii = 0; ii < RTD_ADC_TIMEOUT; ++ii) {
832 stat = RtdFifoStatus(dev);
833 if (stat & FS_ADC_NOT_EMPTY) /* 1 -> not empty */
837 if (ii >= RTD_ADC_TIMEOUT) {
839 ("rtd520: Error: ADC never finished! FifoStatus=0x%x\n",
845 d = RtdAdcFifoGet(dev); /* get 2s comp value */
846 /*printk ("rtd520: Got 0x%x after %d usec\n", d, ii+1); */
847 d = d >> 3; /* low 3 bits are marker lines */
848 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, 0))
849 /* convert to comedi unsigned data */
855 /* return the number of samples read/written */
860 Get what we know is there.... Fast!
861 This uses 1/2 the bus cycles of read_dregs (below).
863 The manual claims that we can do a lword read, but it doesn't work here.
865 static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
870 for (ii = 0; ii < count; ii++) {
874 if (0 == devpriv->aiCount) { /* done */
875 d = RtdAdcFifoGet(dev); /* Read N and discard */
879 if (0 == (RtdFifoStatus(dev) & FS_ADC_NOT_EMPTY)) { /* DEBUG */
880 DPRINTK("comedi: READ OOPS on %d of %d\n", ii + 1,
885 d = RtdAdcFifoGet(dev); /* get 2s comp value */
887 d = d >> 3; /* low 3 bits are marker lines */
888 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
889 /* convert to comedi unsigned data */
894 if (!comedi_buf_put(s->async, sample))
897 if (devpriv->aiCount > 0) /* < 0, means read forever */
904 unknown amout of data is waiting in fifo.
906 static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
908 while (RtdFifoStatus(dev) & FS_ADC_NOT_EMPTY) { /* 1 -> not empty */
910 s16 d = RtdAdcFifoGet(dev); /* get 2s comp value */
912 if (0 == devpriv->aiCount) { /* done */
913 continue; /* read rest */
916 d = d >> 3; /* low 3 bits are marker lines */
917 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
918 /* convert to comedi unsigned data */
923 if (!comedi_buf_put(s->async, sample))
926 if (devpriv->aiCount > 0) /* < 0, means read forever */
934 Terminate a DMA transfer and wait for everything to quiet down
936 void abort_dma(struct comedi_device *dev, unsigned int channel)
937 { /* DMA channel 0, 1 */
938 unsigned long dma_cs_addr; /* the control/status register */
941 /* unsigned long flags; */
943 dma_cs_addr = (unsigned long)devpriv->lcfg
944 + ((channel == 0) ? LCFG_DMACSR0 : LCFG_DMACSR1);
946 /* spinlock for plx dma control/status reg */
947 /* spin_lock_irqsave( &dev->spinlock, flags ); */
949 /* abort dma transfer if necessary */
950 status = readb(dma_cs_addr);
951 if ((status & PLX_DMA_EN_BIT) == 0) { /* not enabled (Error?) */
952 DPRINTK("rtd520: AbortDma on non-active channel %d (0x%x)\n",
957 /* wait to make sure done bit is zero (needed?) */
958 for (ii = 0; (status & PLX_DMA_DONE_BIT) && ii < RTD_DMA_TIMEOUT; ii++) {
960 status = readb(dma_cs_addr);
962 if (status & PLX_DMA_DONE_BIT) {
963 printk("rtd520: Timeout waiting for dma %i done clear\n",
968 /* disable channel (required) */
969 writeb(0, dma_cs_addr);
970 udelay(1); /* needed?? */
971 /* set abort bit for channel */
972 writeb(PLX_DMA_ABORT_BIT, dma_cs_addr);
974 /* wait for dma done bit to be set */
975 status = readb(dma_cs_addr);
977 (status & PLX_DMA_DONE_BIT) == 0 && ii < RTD_DMA_TIMEOUT; ii++) {
978 status = readb(dma_cs_addr);
981 if ((status & PLX_DMA_DONE_BIT) == 0) {
982 printk("rtd520: Timeout waiting for dma %i done set\n",
987 /* spin_unlock_irqrestore( &dev->spinlock, flags ); */
991 Process what is in the DMA transfer buffer and pass to comedi
992 Note: this is not re-entrant
994 static int ai_process_dma(struct comedi_device *dev, struct comedi_subdevice *s)
999 if (devpriv->aiCount == 0) /* transfer already complete */
1002 dp = devpriv->dma0Buff[devpriv->dma0Offset];
1003 for (ii = 0; ii < devpriv->fifoLen / 2;) { /* convert samples */
1006 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
1007 sample = (*dp >> 3) + 2048; /* convert to comedi unsigned data */
1009 sample = *dp >> 3; /* low 3 bits are marker lines */
1011 *dp++ = sample; /* put processed value back */
1013 if (++s->async->cur_chan >= s->async->cmd.chanlist_len)
1014 s->async->cur_chan = 0;
1016 ++ii; /* number ready to transfer */
1017 if (devpriv->aiCount > 0) { /* < 0, means read forever */
1018 if (--devpriv->aiCount == 0) { /* done */
1019 /*DPRINTK ("rtd520: Final %d samples\n", ii); */
1025 /* now pass the whole array to the comedi buffer */
1026 dp = devpriv->dma0Buff[devpriv->dma0Offset];
1027 n = comedi_buf_write_alloc(s->async, ii * sizeof(s16));
1028 if (n < (ii * sizeof(s16))) { /* any residual is an error */
1029 DPRINTK("rtd520:ai_process_dma buffer overflow %d samples!\n",
1030 ii - (n / sizeof(s16)));
1031 s->async->events |= COMEDI_CB_ERROR;
1034 comedi_buf_memcpy_to(s->async, 0, dp, n);
1035 comedi_buf_write_free(s->async, n);
1038 * always at least 1 scan -- 1/2 FIFO is larger than our max scan list
1040 s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOS;
1042 if (++devpriv->dma0Offset >= DMA_CHAIN_COUNT) { /* next buffer */
1043 devpriv->dma0Offset = 0;
1047 #endif /* USE_DMA */
1050 Handle all rtd520 interrupts.
1051 Runs atomically and is never re-entered.
1052 This is a "slow handler"; other interrupts may be active.
1053 The data conversion may someday happen in a "bottom half".
1055 static irqreturn_t rtd_interrupt(int irq, /* interrupt number (ignored) */
1057 { /* our data *//* cpu context (ignored) */
1058 struct comedi_device *dev = d; /* must be called "dev" for devpriv */
1061 struct comedi_subdevice *s = dev->subdevices + 0; /* analog in subdevice */
1066 devpriv->intCount++; /* DEBUG statistics */
1068 fifoStatus = RtdFifoStatus(dev);
1069 /* check for FIFO full, this automatically halts the ADC! */
1070 if (!(fifoStatus & FS_ADC_NOT_FULL)) { /* 0 -> full */
1071 DPRINTK("rtd520: FIFO full! fifo_status=0x%x\n", (fifoStatus ^ 0x6666) & 0x7777); /* should be all 0s */
1075 if (devpriv->flags & DMA0_ACTIVE) { /* Check DMA */
1076 u32 istatus = RtdPlxInterruptRead(dev);
1078 if (istatus & ICS_DMA0_A) {
1079 if (ai_process_dma(dev, s) < 0) {
1081 ("rtd520: comedi read buffer overflow (DMA) with %ld to go!\n",
1084 (devpriv->dma0Control &
1086 | PLX_CLEAR_DMA_INTR_BIT);
1090 /*DPRINTK ("rtd520: DMA transfer: %ld to go, istatus %x\n",
1091 devpriv->aiCount, istatus); */
1094 dma0Control & ~PLX_DMA_START_BIT)
1095 | PLX_CLEAR_DMA_INTR_BIT);
1096 if (0 == devpriv->aiCount) { /* counted down */
1097 DPRINTK("rtd520: Samples Done (DMA).\n");
1100 comedi_event(dev, s);
1102 /*DPRINTK ("rtd520: No DMA ready: istatus %x\n", istatus); */
1105 /* Fall through and check for other interrupt sources */
1106 #endif /* USE_DMA */
1108 status = RtdInterruptStatus(dev);
1109 /* if interrupt was not caused by our board, or handled above */
1113 if (status & IRQM_ADC_ABOUT_CNT) { /* sample count -> read FIFO */
1114 /* since the priority interrupt controller may have queued a sample
1115 counter interrupt, even though we have already finished,
1116 we must handle the possibility that there is no data here */
1117 if (!(fifoStatus & FS_ADC_HEMPTY)) { /* 0 -> 1/2 full */
1118 /*DPRINTK("rtd520: Sample int, reading 1/2FIFO. fifo_status 0x%x\n",
1119 (fifoStatus ^ 0x6666) & 0x7777); */
1120 if (ai_read_n(dev, s, devpriv->fifoLen / 2) < 0) {
1122 ("rtd520: comedi read buffer overflow (1/2FIFO) with %ld to go!\n",
1126 if (0 == devpriv->aiCount) { /* counted down */
1127 DPRINTK("rtd520: Samples Done (1/2). fifo_status was 0x%x\n", (fifoStatus ^ 0x6666) & 0x7777); /* should be all 0s */
1130 comedi_event(dev, s);
1131 } else if (devpriv->transCount > 0) { /* read often */
1132 /*DPRINTK("rtd520: Sample int, reading %d fifo_status 0x%x\n",
1133 devpriv->transCount, (fifoStatus ^ 0x6666) & 0x7777); */
1134 if (fifoStatus & FS_ADC_NOT_EMPTY) { /* 1 -> not empty */
1135 if (ai_read_n(dev, s, devpriv->transCount) < 0) {
1137 ("rtd520: comedi read buffer overflow (N) with %ld to go!\n",
1141 if (0 == devpriv->aiCount) { /* counted down */
1143 ("rtd520: Samples Done (N). fifo_status was 0x%x\n",
1144 (fifoStatus ^ 0x6666) & 0x7777);
1147 comedi_event(dev, s);
1149 } else { /* wait for 1/2 FIFO (old) */
1151 ("rtd520: Sample int. Wait for 1/2. fifo_status 0x%x\n",
1152 (fifoStatus ^ 0x6666) & 0x7777);
1155 DPRINTK("rtd520: unknown interrupt source!\n");
1158 if (0xffff & RtdInterruptOverrunStatus(dev)) { /* interrupt overrun */
1160 ("rtd520: Interrupt overrun with %ld to go! over_status=0x%x\n",
1161 devpriv->aiCount, 0xffff & RtdInterruptOverrunStatus(dev));
1165 /* clear the interrupt */
1166 RtdInterruptClearMask(dev, status);
1167 RtdInterruptClear(dev);
1171 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
1172 s->async->events |= COMEDI_CB_ERROR;
1173 devpriv->aiCount = 0; /* stop and don't transfer any more */
1174 /* fall into transferDone */
1177 writel(0, devpriv->las0 + LAS0_PACER_STOP);
1178 RtdPacerStop(dev); /* Stop PACER */
1179 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1180 RtdInterruptMask(dev, 0); /* mask out SAMPLE */
1182 if (devpriv->flags & DMA0_ACTIVE) {
1183 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1184 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1186 devpriv->flags &= ~DMA0_ACTIVE;
1187 /* if Using DMA, then we should have read everything by now */
1188 if (devpriv->aiCount > 0) {
1189 DPRINTK("rtd520: Lost DMA data! %ld remain\n",
1193 #endif /* USE_DMA */
1195 if (devpriv->aiCount > 0) { /* there shouldn't be anything left */
1196 fifoStatus = RtdFifoStatus(dev);
1197 DPRINTK("rtd520: Finishing up. %ld remain, fifoStat=%x\n", devpriv->aiCount, (fifoStatus ^ 0x6666) & 0x7777); /* should read all 0s */
1198 ai_read_dregs(dev, s); /* read anything left in FIFO */
1201 s->async->events |= COMEDI_CB_EOA; /* signal end to comedi */
1202 comedi_event(dev, s);
1204 /* clear the interrupt */
1205 status = RtdInterruptStatus(dev);
1206 RtdInterruptClearMask(dev, status);
1207 RtdInterruptClear(dev);
1209 fifoStatus = RtdFifoStatus(dev); /* DEBUG */
1211 ("rtd520: Acquisition complete. %ld ints, intStat=%x, overStat=%x\n",
1212 devpriv->intCount, status,
1213 0xffff & RtdInterruptOverrunStatus(dev));
1220 return the number of samples available
1222 static int rtd_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1224 /* TODO: This needs to mask interrupts, read_dregs, and then re-enable */
1225 /* Not sure what to do if DMA is active */
1226 return s->async->buf_write_count - s->async->buf_read_count;
1231 cmdtest tests a particular command to see if it is valid.
1232 Using the cmdtest ioctl, a user can create a valid cmd
1233 and then have it executed by the cmd ioctl (asyncronously).
1235 cmdtest returns 1,2,3,4 or 0, depending on which tests
1239 static int rtd_ai_cmdtest(struct comedi_device *dev,
1240 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1245 /* step 1: make sure trigger sources are trivially valid */
1247 tmp = cmd->start_src;
1248 cmd->start_src &= TRIG_NOW;
1249 if (!cmd->start_src || tmp != cmd->start_src)
1252 tmp = cmd->scan_begin_src;
1253 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
1254 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1258 tmp = cmd->convert_src;
1259 cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
1260 if (!cmd->convert_src || tmp != cmd->convert_src)
1264 tmp = cmd->scan_end_src;
1265 cmd->scan_end_src &= TRIG_COUNT;
1266 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1270 tmp = cmd->stop_src;
1271 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
1272 if (!cmd->stop_src || tmp != cmd->stop_src)
1279 /* step 2: make sure trigger sources are unique
1280 and mutually compatible */
1281 /* note that mutual compatibility is not an issue here */
1282 if (cmd->scan_begin_src != TRIG_TIMER &&
1283 cmd->scan_begin_src != TRIG_EXT) {
1286 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
1289 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
1295 /* step 3: make sure arguments are trivially compatible */
1297 if (cmd->start_arg != 0) {
1302 if (cmd->scan_begin_src == TRIG_TIMER) {
1303 /* Note: these are time periods, not actual rates */
1304 if (1 == cmd->chanlist_len) { /* no scanning */
1305 if (cmd->scan_begin_arg < RTD_MAX_SPEED_1) {
1306 cmd->scan_begin_arg = RTD_MAX_SPEED_1;
1307 rtd_ns_to_timer(&cmd->scan_begin_arg,
1311 if (cmd->scan_begin_arg > RTD_MIN_SPEED_1) {
1312 cmd->scan_begin_arg = RTD_MIN_SPEED_1;
1313 rtd_ns_to_timer(&cmd->scan_begin_arg,
1318 if (cmd->scan_begin_arg < RTD_MAX_SPEED) {
1319 cmd->scan_begin_arg = RTD_MAX_SPEED;
1320 rtd_ns_to_timer(&cmd->scan_begin_arg,
1324 if (cmd->scan_begin_arg > RTD_MIN_SPEED) {
1325 cmd->scan_begin_arg = RTD_MIN_SPEED;
1326 rtd_ns_to_timer(&cmd->scan_begin_arg,
1332 /* external trigger */
1333 /* should be level/edge, hi/lo specification here */
1334 /* should specify multiple external triggers */
1335 if (cmd->scan_begin_arg > 9) {
1336 cmd->scan_begin_arg = 9;
1340 if (cmd->convert_src == TRIG_TIMER) {
1341 if (1 == cmd->chanlist_len) { /* no scanning */
1342 if (cmd->convert_arg < RTD_MAX_SPEED_1) {
1343 cmd->convert_arg = RTD_MAX_SPEED_1;
1344 rtd_ns_to_timer(&cmd->convert_arg,
1348 if (cmd->convert_arg > RTD_MIN_SPEED_1) {
1349 cmd->convert_arg = RTD_MIN_SPEED_1;
1350 rtd_ns_to_timer(&cmd->convert_arg,
1355 if (cmd->convert_arg < RTD_MAX_SPEED) {
1356 cmd->convert_arg = RTD_MAX_SPEED;
1357 rtd_ns_to_timer(&cmd->convert_arg,
1361 if (cmd->convert_arg > RTD_MIN_SPEED) {
1362 cmd->convert_arg = RTD_MIN_SPEED;
1363 rtd_ns_to_timer(&cmd->convert_arg,
1369 /* external trigger */
1371 if (cmd->convert_arg > 9) {
1372 cmd->convert_arg = 9;
1378 if (cmd->scan_end_arg != cmd->chanlist_len) {
1379 cmd->scan_end_arg = cmd->chanlist_len;
1383 if (cmd->stop_src == TRIG_COUNT) {
1384 /* TODO check for rounding error due to counter wrap */
1388 if (cmd->stop_arg != 0) {
1398 /* step 4: fix up any arguments */
1400 if (cmd->chanlist_len > RTD_MAX_CHANLIST) {
1401 cmd->chanlist_len = RTD_MAX_CHANLIST;
1404 if (cmd->scan_begin_src == TRIG_TIMER) {
1405 tmp = cmd->scan_begin_arg;
1406 rtd_ns_to_timer(&cmd->scan_begin_arg,
1407 cmd->flags & TRIG_ROUND_MASK);
1408 if (tmp != cmd->scan_begin_arg)
1412 if (cmd->convert_src == TRIG_TIMER) {
1413 tmp = cmd->convert_arg;
1414 rtd_ns_to_timer(&cmd->convert_arg,
1415 cmd->flags & TRIG_ROUND_MASK);
1416 if (tmp != cmd->convert_arg)
1419 if (cmd->scan_begin_src == TRIG_TIMER
1420 && (cmd->scan_begin_arg
1421 < (cmd->convert_arg * cmd->scan_end_arg))) {
1422 cmd->scan_begin_arg =
1423 cmd->convert_arg * cmd->scan_end_arg;
1435 Execute a analog in command with many possible triggering options.
1436 The data get stored in the async structure of the subdevice.
1437 This is usually done by an interrupt handler.
1438 Userland gets to the data using read calls.
1440 static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1442 struct comedi_cmd *cmd = &s->async->cmd;
1445 /* stop anything currently running */
1446 writel(0, devpriv->las0 + LAS0_PACER_STOP);
1447 RtdPacerStop(dev); /* make sure PACER is stopped */
1448 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1449 RtdInterruptMask(dev, 0);
1451 if (devpriv->flags & DMA0_ACTIVE) { /* cancel anything running */
1452 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1453 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1455 devpriv->flags &= ~DMA0_ACTIVE;
1456 if (RtdPlxInterruptRead(dev) & ICS_DMA0_A) { /*clear pending int */
1457 RtdDma0Control(dev, PLX_CLEAR_DMA_INTR_BIT);
1460 RtdDma0Reset(dev); /* reset onboard state */
1461 #endif /* USE_DMA */
1462 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
1463 RtdInterruptOverrunClear(dev);
1464 devpriv->intCount = 0;
1466 if (!dev->irq) { /* we need interrupts for this */
1467 DPRINTK("rtd520: ERROR! No interrupt available!\n");
1471 /* start configuration */
1472 /* load channel list and reset CGT */
1473 rtd_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
1475 /* setup the common case and override if needed */
1476 if (cmd->chanlist_len > 1) {
1477 /*DPRINTK ("rtd520: Multi channel setup\n"); */
1478 writel(0, devpriv->las0 + LAS0_PACER_START);
1479 writel(1, devpriv->las0 + LAS0_BURST_START);
1480 writel(2, devpriv->las0 + LAS0_ADC_CONVERSION);
1481 } else { /* single channel */
1482 /*DPRINTK ("rtd520: single channel setup\n"); */
1483 writel(0, devpriv->las0 + LAS0_PACER_START);
1484 writel(1, devpriv->las0 + LAS0_ADC_CONVERSION);
1486 RtdAboutCounter(dev, devpriv->fifoLen / 2 - 1); /* 1/2 FIFO */
1488 if (TRIG_TIMER == cmd->scan_begin_src) {
1489 /* scan_begin_arg is in nanoseconds */
1490 /* find out how many samples to wait before transferring */
1491 if (cmd->flags & TRIG_WAKE_EOS) {
1492 /* this may generate un-sustainable interrupt rates */
1493 /* the application is responsible for doing the right thing */
1494 devpriv->transCount = cmd->chanlist_len;
1495 devpriv->flags |= SEND_EOS;
1497 /* arrange to transfer data periodically */
1500 (TRANS_TARGET_PERIOD * cmd->chanlist_len) /
1501 cmd->scan_begin_arg;
1502 if (devpriv->transCount < cmd->chanlist_len) {
1503 /* transfer after each scan (and avoid 0) */
1504 devpriv->transCount = cmd->chanlist_len;
1505 } else { /* make a multiple of scan length */
1506 devpriv->transCount =
1507 (devpriv->transCount +
1508 cmd->chanlist_len - 1)
1509 / cmd->chanlist_len;
1510 devpriv->transCount *= cmd->chanlist_len;
1512 devpriv->flags |= SEND_EOS;
1514 if (devpriv->transCount >= (devpriv->fifoLen / 2)) {
1515 /* out of counter range, use 1/2 fifo instead */
1516 devpriv->transCount = 0;
1517 devpriv->flags &= ~SEND_EOS;
1519 /* interrupt for each transfer */
1520 RtdAboutCounter(dev, devpriv->transCount - 1);
1524 ("rtd520: scanLen=%d transferCount=%d fifoLen=%d\n scanTime(ns)=%d flags=0x%x\n",
1525 cmd->chanlist_len, devpriv->transCount, devpriv->fifoLen,
1526 cmd->scan_begin_arg, devpriv->flags);
1527 } else { /* unknown timing, just use 1/2 FIFO */
1528 devpriv->transCount = 0;
1529 devpriv->flags &= ~SEND_EOS;
1531 writel(1, devpriv->las0 + LAS0_PACER_SELECT);
1532 writel(1, devpriv->las0 + LAS0_ACNT_STOP_ENABLE);
1534 /* BUG??? these look like enumerated values, but they are bit fields */
1536 /* First, setup when to stop */
1537 switch (cmd->stop_src) {
1538 case TRIG_COUNT: /* stop after N scans */
1539 devpriv->aiCount = cmd->stop_arg * cmd->chanlist_len;
1540 if ((devpriv->transCount > 0)
1541 && (devpriv->transCount > devpriv->aiCount)) {
1542 devpriv->transCount = devpriv->aiCount;
1546 case TRIG_NONE: /* stop when cancel is called */
1547 devpriv->aiCount = -1; /* read forever */
1551 DPRINTK("rtd520: Warning! ignoring stop_src mode %d\n",
1556 switch (cmd->scan_begin_src) {
1557 case TRIG_TIMER: /* periodic scanning */
1558 timer = rtd_ns_to_timer(&cmd->scan_begin_arg,
1559 TRIG_ROUND_NEAREST);
1560 /* set PACER clock */
1561 /*DPRINTK ("rtd520: loading %d into pacer\n", timer); */
1562 RtdPacerCounter(dev, timer);
1567 writel(1, devpriv->las0 + LAS0_PACER_START);
1571 DPRINTK("rtd520: Warning! ignoring scan_begin_src mode %d\n",
1572 cmd->scan_begin_src);
1575 /* Sample timing within a scan */
1576 switch (cmd->convert_src) {
1577 case TRIG_TIMER: /* periodic */
1578 if (cmd->chanlist_len > 1) { /* only needed for multi-channel */
1579 timer = rtd_ns_to_timer(&cmd->convert_arg,
1580 TRIG_ROUND_NEAREST);
1581 /* setup BURST clock */
1582 /*DPRINTK ("rtd520: loading %d into burst\n", timer); */
1583 RtdBurstCounter(dev, timer);
1588 case TRIG_EXT: /* external */
1589 writel(2, devpriv->las0 + LAS0_BURST_START);
1593 DPRINTK("rtd520: Warning! ignoring convert_src mode %d\n",
1596 /* end configuration */
1598 /* This doesn't seem to work. There is no way to clear an interrupt
1599 that the priority controller has queued! */
1600 RtdInterruptClearMask(dev, ~0); /* clear any existing flags */
1601 RtdInterruptClear(dev);
1603 /* TODO: allow multiple interrupt sources */
1604 if (devpriv->transCount > 0) { /* transfer every N samples */
1605 RtdInterruptMask(dev, IRQM_ADC_ABOUT_CNT);
1606 DPRINTK("rtd520: Transferring every %d\n", devpriv->transCount);
1607 } else { /* 1/2 FIFO transfers */
1609 devpriv->flags |= DMA0_ACTIVE;
1611 /* point to first transfer in ring */
1612 devpriv->dma0Offset = 0;
1613 RtdDma0Mode(dev, DMA_MODE_BITS);
1614 RtdDma0Next(dev, /* point to first block */
1615 devpriv->dma0Chain[DMA_CHAIN_COUNT - 1].next);
1616 RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL); /* set DMA trigger source */
1618 RtdPlxInterruptWrite(dev, /* enable interrupt */
1619 RtdPlxInterruptRead(dev) | ICS_DMA0_E);
1620 /* Must be 2 steps. See PLX app note about "Starting a DMA transfer" */
1621 RtdDma0Control(dev, PLX_DMA_EN_BIT); /* enable DMA (clear INTR?) */
1622 RtdDma0Control(dev, PLX_DMA_EN_BIT | PLX_DMA_START_BIT); /*start DMA */
1623 DPRINTK("rtd520: Using DMA0 transfers. plxInt %x RtdInt %x\n",
1624 RtdPlxInterruptRead(dev), devpriv->intMask);
1626 RtdInterruptMask(dev, IRQM_ADC_ABOUT_CNT);
1627 DPRINTK("rtd520: Transferring every 1/2 FIFO\n");
1628 #endif /* USE_DMA */
1631 /* BUG: start_src is ASSUMED to be TRIG_NOW */
1632 /* BUG? it seems like things are running before the "start" */
1633 RtdPacerStart(dev); /* Start PACER */
1638 Stop a running data acquisition.
1640 static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1644 writel(0, devpriv->las0 + LAS0_PACER_STOP);
1645 RtdPacerStop(dev); /* Stop PACER */
1646 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1647 RtdInterruptMask(dev, 0);
1648 devpriv->aiCount = 0; /* stop and don't transfer any more */
1650 if (devpriv->flags & DMA0_ACTIVE) {
1651 RtdPlxInterruptWrite(dev, /* disable any more interrupts */
1652 RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
1654 devpriv->flags &= ~DMA0_ACTIVE;
1656 #endif /* USE_DMA */
1657 status = RtdInterruptStatus(dev);
1659 ("rtd520: Acquisition canceled. %ld ints, intStat=%x, overStat=%x\n",
1660 devpriv->intCount, status,
1661 0xffff & RtdInterruptOverrunStatus(dev));
1666 Output one (or more) analog values to a single port as fast as possible.
1668 static int rtd_ao_winsn(struct comedi_device *dev,
1669 struct comedi_subdevice *s, struct comedi_insn *insn,
1673 int chan = CR_CHAN(insn->chanspec);
1674 int range = CR_RANGE(insn->chanspec);
1676 /* Configure the output range (table index matches the range values) */
1677 RtdDacRange(dev, chan, range);
1679 /* Writing a list of values to an AO channel is probably not
1680 * very useful, but that's how the interface is defined. */
1681 for (i = 0; i < insn->n; ++i) {
1682 int val = data[i] << 3;
1683 int stat = 0; /* initialize to avoid bogus warning */
1686 /* VERIFY: comedi range and offset conversions */
1688 if ((range > 1) /* bipolar */
1689 && (data[i] < 2048)) {
1690 /* offset and sign extend */
1691 val = (((int)data[i]) - 2048) << 3;
1692 } else { /* unipolor */
1697 ("comedi: rtd520 DAC chan=%d range=%d writing %d as 0x%x\n",
1698 chan, range, data[i], val);
1700 /* a typical programming sequence */
1701 RtdDacFifoPut(dev, chan, val); /* put the value in */
1702 RtdDacUpdate(dev, chan); /* trigger the conversion */
1704 devpriv->aoValue[chan] = data[i]; /* save for read back */
1706 for (ii = 0; ii < RTD_DAC_TIMEOUT; ++ii) {
1707 stat = RtdFifoStatus(dev);
1708 /* 1 -> not empty */
1709 if (stat & ((0 == chan) ? FS_DAC1_NOT_EMPTY :
1714 if (ii >= RTD_DAC_TIMEOUT) {
1716 ("rtd520: Error: DAC never finished! FifoStatus=0x%x\n",
1722 /* return the number of samples read/written */
1726 /* AO subdevices should have a read insn as well as a write insn.
1727 * Usually this means copying a value stored in devpriv. */
1728 static int rtd_ao_rinsn(struct comedi_device *dev,
1729 struct comedi_subdevice *s, struct comedi_insn *insn,
1733 int chan = CR_CHAN(insn->chanspec);
1735 for (i = 0; i < insn->n; i++)
1736 data[i] = devpriv->aoValue[chan];
1743 Write a masked set of bits and the read back the port.
1744 We track what the bits should be (i.e. we don't read the port first).
1746 DIO devices are slightly special. Although it is possible to
1747 * implement the insn_read/insn_write interface, it is much more
1748 * useful to applications if you implement the insn_bits interface.
1749 * This allows packed reading/writing of the DIO channels. The
1750 * comedi core can convert between insn_bits and insn_read/write
1752 static int rtd_dio_insn_bits(struct comedi_device *dev,
1753 struct comedi_subdevice *s,
1754 struct comedi_insn *insn, unsigned int *data)
1756 /* The insn data is a mask in data[0] and the new data
1757 * in data[1], each channel cooresponding to a bit. */
1759 s->state &= ~data[0];
1760 s->state |= data[0] & data[1];
1762 /* Write out the new digital output lines */
1763 RtdDio0Write(dev, s->state);
1765 /* on return, data[1] contains the value of the digital
1767 data[1] = RtdDio0Read(dev);
1769 /*DPRINTK("rtd520:port_0 wrote: 0x%x read: 0x%x\n", s->state, data[1]); */
1775 Configure one bit on a IO port as Input or Output (hence the name :-).
1777 static int rtd_dio_insn_config(struct comedi_device *dev,
1778 struct comedi_subdevice *s,
1779 struct comedi_insn *insn, unsigned int *data)
1781 int chan = CR_CHAN(insn->chanspec);
1783 /* The input or output configuration of each digital line is
1784 * configured by a special insn_config instruction. chanspec
1785 * contains the channel to be changed, and data[0] contains the
1786 * value COMEDI_INPUT or COMEDI_OUTPUT. */
1788 case INSN_CONFIG_DIO_OUTPUT:
1789 s->io_bits |= 1 << chan; /* 1 means Out */
1791 case INSN_CONFIG_DIO_INPUT:
1792 s->io_bits &= ~(1 << chan);
1794 case INSN_CONFIG_DIO_QUERY:
1796 (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
1803 DPRINTK("rtd520: port_0_direction=0x%x (1 means out)\n", s->io_bits);
1804 /* TODO support digital match interrupts and strobes */
1805 RtdDioStatusWrite(dev, 0x01); /* make Dio0Ctrl point to direction */
1806 RtdDio0CtrlWrite(dev, s->io_bits); /* set direction 1 means Out */
1807 RtdDioStatusWrite(dev, 0); /* make Dio0Ctrl clear interrupts */
1809 /* port1 can only be all input or all output */
1811 /* there are also 2 user input lines and 2 user output lines */
1816 static int rtd_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1817 { /* board name and options flags */
1818 struct comedi_subdevice *s;
1819 struct pci_dev *pcidev;
1821 resource_size_t physLas0; /* configuration */
1822 resource_size_t physLas1; /* data area */
1823 resource_size_t physLcfg; /* PLX9080 */
1828 printk(KERN_INFO "comedi%d: rtd520 attaching.\n", dev->minor);
1830 #if defined(CONFIG_COMEDI_DEBUG) && defined(USE_DMA)
1831 /* You can set this a load time: modprobe comedi comedi_debug=1 */
1832 if (0 == comedi_debug) /* force DMA debug printks */
1837 * Allocate the private structure area. alloc_private() is a
1838 * convenient macro defined in comedidev.h.
1840 if (alloc_private(dev, sizeof(struct rtdPrivate)) < 0)
1844 * Probe the device to determine what device in the series it is.
1846 for (pcidev = pci_get_device(PCI_VENDOR_ID_RTD, PCI_ANY_ID, NULL);
1848 pcidev = pci_get_device(PCI_VENDOR_ID_RTD, PCI_ANY_ID, pcidev)) {
1851 if (it->options[0] || it->options[1]) {
1852 if (pcidev->bus->number != it->options[0]
1853 || PCI_SLOT(pcidev->devfn) != it->options[1]) {
1857 for (i = 0; i < ARRAY_SIZE(rtd520Boards); ++i) {
1858 if (pcidev->device == rtd520Boards[i].device_id) {
1859 dev->board_ptr = &rtd520Boards[i];
1864 break; /* found one */
1867 if (it->options[0] && it->options[1]) {
1868 printk(KERN_INFO "No RTD card at bus=%d slot=%d.\n",
1869 it->options[0], it->options[1]);
1871 printk(KERN_INFO "No RTD card found.\n");
1875 devpriv->pci_dev = pcidev;
1876 dev->board_name = thisboard->name;
1878 ret = comedi_pci_enable(pcidev, DRV_NAME);
1880 printk(KERN_INFO "Failed to enable PCI device and request regions.\n");
1883 devpriv->got_regions = 1;
1886 * Initialize base addresses
1888 /* Get the physical address from PCI config */
1889 physLas0 = pci_resource_start(devpriv->pci_dev, LAS0_PCIINDEX);
1890 physLas1 = pci_resource_start(devpriv->pci_dev, LAS1_PCIINDEX);
1891 physLcfg = pci_resource_start(devpriv->pci_dev, LCFG_PCIINDEX);
1892 /* Now have the kernel map this into memory */
1893 /* ASSUME page aligned */
1894 devpriv->las0 = ioremap_nocache(physLas0, LAS0_PCISIZE);
1895 devpriv->las1 = ioremap_nocache(physLas1, LAS1_PCISIZE);
1896 devpriv->lcfg = ioremap_nocache(physLcfg, LCFG_PCISIZE);
1898 if (!devpriv->las0 || !devpriv->las1 || !devpriv->lcfg)
1902 DPRINTK("%s: LAS0=%llx, LAS1=%llx, CFG=%llx.\n", dev->board_name,
1903 (unsigned long long)physLas0, (unsigned long long)physLas1,
1904 (unsigned long long)physLcfg);
1905 { /* The RTD driver does this */
1906 unsigned char pci_latency;
1908 /*uint32_t epld_version; */
1910 pci_read_config_word(devpriv->pci_dev, PCI_REVISION_ID,
1912 DPRINTK("%s: PCI revision %d.\n", dev->board_name, revision);
1914 pci_read_config_byte(devpriv->pci_dev,
1915 PCI_LATENCY_TIMER, &pci_latency);
1916 if (pci_latency < 32) {
1917 printk(KERN_INFO "%s: PCI latency changed from %d to %d\n",
1918 dev->board_name, pci_latency, 32);
1919 pci_write_config_byte(devpriv->pci_dev,
1920 PCI_LATENCY_TIMER, 32);
1922 DPRINTK("rtd520: PCI latency = %d\n", pci_latency);
1926 * Undocumented EPLD version (doesn't match RTD driver results)
1928 /*DPRINTK ("rtd520: Reading epld from %p\n",
1930 epld_version = readl (devpriv->las0+0);
1931 if ((epld_version & 0xF0) >> 4 == 0x0F) {
1932 DPRINTK("rtd520: pre-v8 EPLD. (%x)\n", epld_version);
1934 DPRINTK("rtd520: EPLD version %x.\n", epld_version >> 4);
1938 /* Show board configuration */
1939 printk(KERN_INFO "%s:", dev->board_name);
1941 ret = comedi_alloc_subdevices(dev, 4);
1945 s = dev->subdevices + 0;
1946 dev->read_subdev = s;
1947 /* analog input subdevice */
1948 s->type = COMEDI_SUBD_AI;
1950 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
1951 s->n_chan = thisboard->aiChans;
1952 s->maxdata = (1 << thisboard->aiBits) - 1;
1953 if (thisboard->aiMaxGain <= 32)
1954 s->range_table = &rtd_ai_7520_range;
1956 s->range_table = &rtd_ai_4520_range;
1958 s->len_chanlist = RTD_MAX_CHANLIST; /* devpriv->fifoLen */
1959 s->insn_read = rtd_ai_rinsn;
1960 s->do_cmd = rtd_ai_cmd;
1961 s->do_cmdtest = rtd_ai_cmdtest;
1962 s->cancel = rtd_ai_cancel;
1963 /* s->poll = rtd_ai_poll; *//* not ready yet */
1965 s = dev->subdevices + 1;
1966 /* analog output subdevice */
1967 s->type = COMEDI_SUBD_AO;
1968 s->subdev_flags = SDF_WRITABLE;
1970 s->maxdata = (1 << thisboard->aiBits) - 1;
1971 s->range_table = &rtd_ao_range;
1972 s->insn_write = rtd_ao_winsn;
1973 s->insn_read = rtd_ao_rinsn;
1975 s = dev->subdevices + 2;
1976 /* digital i/o subdevice */
1977 s->type = COMEDI_SUBD_DIO;
1978 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1979 /* we only support port 0 right now. Ignoring port 1 and user IO */
1982 s->range_table = &range_digital;
1983 s->insn_bits = rtd_dio_insn_bits;
1984 s->insn_config = rtd_dio_insn_config;
1986 /* timer/counter subdevices (not currently supported) */
1987 s = dev->subdevices + 3;
1988 s->type = COMEDI_SUBD_COUNTER;
1989 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1991 s->maxdata = 0xffff;
1993 /* initialize board, per RTD spec */
1994 /* also, initialize shadow registers */
1995 writel(0, devpriv->las0 + LAS0_BOARD_RESET);
1996 udelay(100); /* needed? */
1997 RtdPlxInterruptWrite(dev, 0);
1998 RtdInterruptMask(dev, 0); /* and sets shadow */
1999 RtdInterruptClearMask(dev, ~0); /* and sets shadow */
2000 RtdInterruptClear(dev); /* clears bits set by mask */
2001 RtdInterruptOverrunClear(dev);
2002 writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
2003 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
2004 RtdDacClearFifo(dev, 0);
2005 RtdDacClearFifo(dev, 1);
2006 /* clear digital IO fifo */
2007 RtdDioStatusWrite(dev, 0); /* safe state, set shadow */
2008 RtdUtcCtrlPut(dev, 0, 0x30); /* safe state, set shadow */
2009 RtdUtcCtrlPut(dev, 1, 0x30); /* safe state, set shadow */
2010 RtdUtcCtrlPut(dev, 2, 0x30); /* safe state, set shadow */
2011 RtdUtcCtrlPut(dev, 3, 0); /* safe state, set shadow */
2012 /* TODO: set user out source ??? */
2014 /* check if our interrupt is available and get it */
2015 ret = request_irq(devpriv->pci_dev->irq, rtd_interrupt,
2016 IRQF_SHARED, DRV_NAME, dev);
2019 printk("Could not get interrupt! (%u)\n",
2020 devpriv->pci_dev->irq);
2023 dev->irq = devpriv->pci_dev->irq;
2024 printk(KERN_INFO "( irq=%u )", dev->irq);
2026 ret = rtd520_probe_fifo_depth(dev);
2030 devpriv->fifoLen = ret;
2031 printk("( fifoLen=%d )", devpriv->fifoLen);
2035 printk("( DMA buff=%d )\n", DMA_CHAIN_COUNT);
2037 * The PLX9080 has 2 DMA controllers, but there could be
2038 * 4 sources: ADC, digital, DAC1, and DAC2. Since only the
2039 * ADC supports cmd mode right now, this isn't an issue (yet)
2041 devpriv->dma0Offset = 0;
2043 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2044 devpriv->dma0Buff[index] =
2045 pci_alloc_consistent(devpriv->pci_dev,
2047 devpriv->fifoLen / 2,
2049 dma0BuffPhysAddr[index]);
2050 if (devpriv->dma0Buff[index] == NULL) {
2052 goto rtd_attach_die_error;
2054 /*DPRINTK ("buff[%d] @ %p virtual, %x PCI\n",
2056 devpriv->dma0Buff[index],
2057 devpriv->dma0BuffPhysAddr[index]); */
2061 * setup DMA descriptor ring (use cpu_to_le32 for byte
2064 devpriv->dma0Chain =
2065 pci_alloc_consistent(devpriv->pci_dev,
2066 sizeof(struct plx_dma_desc) *
2068 &devpriv->dma0ChainPhysAddr);
2069 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2070 devpriv->dma0Chain[index].pci_start_addr =
2071 devpriv->dma0BuffPhysAddr[index];
2072 devpriv->dma0Chain[index].local_start_addr =
2074 devpriv->dma0Chain[index].transfer_size =
2075 sizeof(u16) * devpriv->fifoLen / 2;
2076 devpriv->dma0Chain[index].next =
2077 (devpriv->dma0ChainPhysAddr + ((index +
2080 * sizeof(devpriv->dma0Chain[0]))
2081 | DMA_TRANSFER_BITS;
2082 /*DPRINTK ("ring[%d] @%lx PCI: %x, local: %x, N: 0x%x, next: %x\n",
2084 ((long)devpriv->dma0ChainPhysAddr
2085 + (index * sizeof(devpriv->dma0Chain[0]))),
2086 devpriv->dma0Chain[index].pci_start_addr,
2087 devpriv->dma0Chain[index].local_start_addr,
2088 devpriv->dma0Chain[index].transfer_size,
2089 devpriv->dma0Chain[index].next); */
2092 if (devpriv->dma0Chain == NULL) {
2094 goto rtd_attach_die_error;
2097 RtdDma0Mode(dev, DMA_MODE_BITS);
2098 /* set DMA trigger source */
2099 RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL);
2101 printk(KERN_INFO "( no IRQ->no DMA )");
2103 #endif /* USE_DMA */
2105 if (dev->irq) { /* enable plx9080 interrupts */
2106 RtdPlxInterruptWrite(dev, ICS_PIE | ICS_PLIE);
2109 printk("\ncomedi%d: rtd520 driver attached.\n", dev->minor);
2114 /* hit an error, clean up memory and return ret */
2115 /* rtd_attach_die_error: */
2117 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2118 if (NULL != devpriv->dma0Buff[index]) { /* free buffer memory */
2119 pci_free_consistent(devpriv->pci_dev,
2120 sizeof(u16) * devpriv->fifoLen / 2,
2121 devpriv->dma0Buff[index],
2122 devpriv->dma0BuffPhysAddr[index]);
2123 devpriv->dma0Buff[index] = NULL;
2126 if (NULL != devpriv->dma0Chain) {
2127 pci_free_consistent(devpriv->pci_dev,
2128 sizeof(struct plx_dma_desc)
2131 devpriv->dma0ChainPhysAddr);
2132 devpriv->dma0Chain = NULL;
2134 #endif /* USE_DMA */
2135 /* subdevices and priv are freed by the core */
2137 /* disable interrupt controller */
2138 RtdPlxInterruptWrite(dev, RtdPlxInterruptRead(dev)
2139 & ~(ICS_PLIE | ICS_DMA0_E | ICS_DMA1_E));
2140 free_irq(dev->irq, dev);
2143 /* release all regions that were allocated */
2145 iounmap(devpriv->las0);
2148 iounmap(devpriv->las1);
2151 iounmap(devpriv->lcfg);
2153 if (devpriv->pci_dev)
2154 pci_dev_put(devpriv->pci_dev);
2160 static void rtd_detach(struct comedi_device *dev)
2167 /* Shut down any board ops by resetting it */
2169 if (devpriv->lcfg) {
2170 RtdDma0Control(dev, 0); /* disable DMA */
2171 RtdDma1Control(dev, 0); /* disable DMA */
2172 RtdPlxInterruptWrite(dev, ICS_PIE | ICS_PLIE);
2174 #endif /* USE_DMA */
2175 if (devpriv->las0) {
2176 writel(0, devpriv->las0 + LAS0_BOARD_RESET);
2177 RtdInterruptMask(dev, 0);
2178 RtdInterruptClearMask(dev, ~0);
2179 RtdInterruptClear(dev); /* clears bits set by mask */
2183 for (index = 0; index < DMA_CHAIN_COUNT; index++) {
2184 if (NULL != devpriv->dma0Buff[index]) {
2185 pci_free_consistent(devpriv->pci_dev,
2187 devpriv->fifoLen / 2,
2188 devpriv->dma0Buff[index],
2190 dma0BuffPhysAddr[index]);
2191 devpriv->dma0Buff[index] = NULL;
2194 if (NULL != devpriv->dma0Chain) {
2195 pci_free_consistent(devpriv->pci_dev,
2196 sizeof(struct plx_dma_desc) *
2197 DMA_CHAIN_COUNT, devpriv->dma0Chain,
2198 devpriv->dma0ChainPhysAddr);
2199 devpriv->dma0Chain = NULL;
2201 #endif /* USE_DMA */
2203 RtdPlxInterruptWrite(dev, RtdPlxInterruptRead(dev)
2204 & ~(ICS_PLIE | ICS_DMA0_E |
2206 free_irq(dev->irq, dev);
2209 iounmap(devpriv->las0);
2211 iounmap(devpriv->las1);
2213 iounmap(devpriv->lcfg);
2214 if (devpriv->pci_dev) {
2215 if (devpriv->got_regions)
2216 comedi_pci_disable(devpriv->pci_dev);
2217 pci_dev_put(devpriv->pci_dev);
2222 static struct comedi_driver rtd520_driver = {
2223 .driver_name = "rtd520",
2224 .module = THIS_MODULE,
2225 .attach = rtd_attach,
2226 .detach = rtd_detach,
2229 static int __devinit rtd520_pci_probe(struct pci_dev *dev,
2230 const struct pci_device_id *ent)
2232 return comedi_pci_auto_config(dev, &rtd520_driver);
2235 static void __devexit rtd520_pci_remove(struct pci_dev *dev)
2237 comedi_pci_auto_unconfig(dev);
2240 static DEFINE_PCI_DEVICE_TABLE(rtd520_pci_table) = {
2241 { PCI_DEVICE(PCI_VENDOR_ID_RTD, 0x7520) },
2242 { PCI_DEVICE(PCI_VENDOR_ID_RTD, 0x4520) },
2245 MODULE_DEVICE_TABLE(pci, rtd520_pci_table);
2247 static struct pci_driver rtd520_pci_driver = {
2249 .id_table = rtd520_pci_table,
2250 .probe = rtd520_pci_probe,
2251 .remove = __devexit_p(rtd520_pci_remove),
2253 module_comedi_pci_driver(rtd520_driver, rtd520_pci_driver);
2255 MODULE_AUTHOR("Comedi http://www.comedi.org");
2256 MODULE_DESCRIPTION("Comedi low-level driver");
2257 MODULE_LICENSE("GPL");