2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include "cx25821-video.h"
24 #include "cx25821-video-upstream-ch2.h"
27 #include <linux/errno.h>
28 #include <linux/kernel.h>
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/syscalls.h>
32 #include <linux/file.h>
33 #include <linux/fcntl.h>
34 #include <asm/uaccess.h>
36 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
37 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
38 MODULE_LICENSE("GPL");
40 static int _intr_msk =
41 FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
43 static __le32 *cx25821_update_riscprogram_ch2(struct cx25821_dev *dev,
44 __le32 * rp, unsigned int offset,
45 unsigned int bpl, u32 sync_line,
47 int fifo_enable, int field_type)
50 int dist_betwn_starts = bpl * 2;
52 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
54 if (USE_RISC_NOOP_VIDEO) {
55 for (i = 0; i < NUM_NO_OPS; i++) {
56 *(rp++) = cpu_to_le32(RISC_NOOP);
61 for (line = 0; line < lines; line++) {
62 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
63 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr_ch2 + offset);
64 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
66 if ((lines <= NTSC_FIELD_HEIGHT)
67 || (line < (NTSC_FIELD_HEIGHT - 1))
68 || !(dev->_isNTSC_ch2)) {
69 offset += dist_betwn_starts;
76 static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev,
78 dma_addr_t databuf_phys_addr,
80 u32 sync_line, unsigned int bpl,
82 int fifo_enable, int field_type)
85 struct sram_channel *sram_ch =
86 &dev->sram_channels[dev->_channel2_upstream_select];
87 int dist_betwn_starts = bpl * 2;
89 /* sync instruction */
90 if (sync_line != NO_SYNC_LINE) {
91 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
94 if (USE_RISC_NOOP_VIDEO) {
95 for (i = 0; i < NUM_NO_OPS; i++) {
96 *(rp++) = cpu_to_le32(RISC_NOOP);
101 for (line = 0; line < lines; line++) {
102 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
103 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
104 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
106 if ((lines <= NTSC_FIELD_HEIGHT)
107 || (line < (NTSC_FIELD_HEIGHT - 1))
108 || !(dev->_isNTSC_ch2)) {
109 offset += dist_betwn_starts;
112 // check if we need to enable the FIFO after the first 4 lines
113 // For the upstream video channel, the risc engine will enable the FIFO.
114 if (fifo_enable && line == 3) {
115 *(rp++) = RISC_WRITECR;
116 *(rp++) = sram_ch->dma_ctl;
117 *(rp++) = FLD_VID_FIFO_EN;
118 *(rp++) = 0x00000001;
125 int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev,
127 unsigned int top_offset, unsigned int bpl,
132 int singlefield_lines = lines >> 1; //get line count for single field
133 int odd_num_lines = singlefield_lines;
136 int databuf_offset = 0;
137 int risc_program_size = 0;
138 int risc_flag = RISC_CNT_RESET;
139 unsigned int bottom_offset = bpl;
140 dma_addr_t risc_phys_jump_addr;
142 if (dev->_isNTSC_ch2) {
143 odd_num_lines = singlefield_lines + 1;
144 risc_program_size = FRAME1_VID_PROG_SIZE;
147 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
148 FRAME_SIZE_NTSC_Y422;
150 risc_program_size = PAL_VID_PROG_SIZE;
153 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
156 /* Virtual address of Risc buffer program */
157 rp = dev->_dma_virt_addr_ch2;
159 for (frame = 0; frame < NUM_FRAMES; frame++) {
160 databuf_offset = frame_size * frame;
162 if (UNSET != top_offset) {
163 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
164 rp = cx25821_risc_field_upstream_ch2(dev, rp,
166 _data_buf_phys_addr_ch2
174 fifo_enable = FIFO_DISABLE;
177 rp = cx25821_risc_field_upstream_ch2(dev, rp,
179 _data_buf_phys_addr_ch2 +
181 bottom_offset, 0x200, bpl,
183 fifo_enable, EVEN_FIELD);
186 risc_flag = RISC_CNT_RESET;
187 risc_phys_jump_addr =
188 dev->_dma_phys_start_addr_ch2 + risc_program_size;
190 risc_flag = RISC_CNT_INC;
191 risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2;
194 // Loop to 2ndFrameRISC or to Start of Risc program & generate IRQ
195 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
196 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
197 *(rp++) = cpu_to_le32(0);
203 void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev)
205 struct sram_channel *sram_ch =
206 &dev->sram_channels[VID_UPSTREAM_SRAM_CHANNEL_J];
209 if (!dev->_is_running_ch2) {
211 ("cx25821: No video file is currently running so return!\n");
214 //Disable RISC interrupts
215 tmp = cx_read(sram_ch->int_msk);
216 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
218 //Turn OFF risc and fifo
219 tmp = cx_read(sram_ch->dma_ctl);
220 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
222 //Clear data buffer memory
223 if (dev->_data_buf_virt_addr_ch2)
224 memset(dev->_data_buf_virt_addr_ch2, 0,
225 dev->_data_buf_size_ch2);
227 dev->_is_running_ch2 = 0;
228 dev->_is_first_frame_ch2 = 0;
229 dev->_frame_count_ch2 = 0;
230 dev->_file_status_ch2 = END_OF_FILE;
232 if (dev->_irq_queues_ch2) {
233 kfree(dev->_irq_queues_ch2);
234 dev->_irq_queues_ch2 = NULL;
237 if (dev->_filename_ch2 != NULL)
238 kfree(dev->_filename_ch2);
240 tmp = cx_read(VID_CH_MODE_SEL);
241 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
244 void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev)
246 if (dev->_is_running_ch2) {
247 cx25821_stop_upstream_video_ch2(dev);
250 if (dev->_dma_virt_addr_ch2) {
251 pci_free_consistent(dev->pci, dev->_risc_size_ch2,
252 dev->_dma_virt_addr_ch2,
253 dev->_dma_phys_addr_ch2);
254 dev->_dma_virt_addr_ch2 = NULL;
257 if (dev->_data_buf_virt_addr_ch2) {
258 pci_free_consistent(dev->pci, dev->_data_buf_size_ch2,
259 dev->_data_buf_virt_addr_ch2,
260 dev->_data_buf_phys_addr_ch2);
261 dev->_data_buf_virt_addr_ch2 = NULL;
265 int cx25821_get_frame_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
268 int frame_index_temp = dev->_frame_index_ch2;
271 (dev->_pixel_format_ch2 ==
272 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
274 int frame_offset = 0;
275 ssize_t vfs_read_retval = 0;
276 char mybuf[line_size];
281 if (dev->_file_status_ch2 == END_OF_FILE)
284 if (dev->_isNTSC_ch2) {
287 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
288 FRAME_SIZE_NTSC_Y422;
292 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
295 frame_offset = (frame_index_temp > 0) ? frame_size : 0;
296 file_offset = dev->_frame_count_ch2 * frame_size;
298 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
300 if (IS_ERR(myfile)) {
301 const int open_errno = -PTR_ERR(myfile);
302 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
303 __func__, dev->_filename_ch2, open_errno);
304 return PTR_ERR(myfile);
306 if (!(myfile->f_op)) {
307 printk("%s: File has no file operations registered!",
309 filp_close(myfile, NULL);
313 if (!myfile->f_op->read) {
314 printk("%s: File has no READ operations registered!",
316 filp_close(myfile, NULL);
324 for (i = 0; i < dev->_lines_count_ch2; i++) {
328 vfs_read(myfile, mybuf, line_size, &pos);
330 if (vfs_read_retval > 0 && vfs_read_retval == line_size
331 && dev->_data_buf_virt_addr_ch2 != NULL) {
332 memcpy((void *)(dev->_data_buf_virt_addr_ch2 +
333 frame_offset / 4), mybuf,
337 file_offset += vfs_read_retval;
338 frame_offset += vfs_read_retval;
340 if (vfs_read_retval < line_size) {
342 "Done: exit %s() since no more bytes to read from Video file.\n",
349 dev->_frame_count_ch2++;
351 dev->_file_status_ch2 =
352 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
355 filp_close(myfile, NULL);
361 static void cx25821_vidups_handler_ch2(struct work_struct *work)
363 struct cx25821_dev *dev =
364 container_of(work, struct cx25821_dev, _irq_work_entry_ch2);
367 printk("ERROR %s(): since container_of(work_struct) FAILED! \n",
372 cx25821_get_frame_ch2(dev,
373 &dev->sram_channels[dev->
374 _channel2_upstream_select]);
377 int cx25821_openfile_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
382 (dev->_pixel_format_ch2 ==
383 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
384 ssize_t vfs_read_retval = 0;
385 char mybuf[line_size];
387 loff_t offset = (unsigned long)0;
390 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
392 if (IS_ERR(myfile)) {
393 const int open_errno = -PTR_ERR(myfile);
394 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
395 __func__, dev->_filename_ch2, open_errno);
396 return PTR_ERR(myfile);
398 if (!(myfile->f_op)) {
399 printk("%s: File has no file operations registered!",
401 filp_close(myfile, NULL);
405 if (!myfile->f_op->read) {
407 ("%s: File has no READ operations registered! Returning.",
409 filp_close(myfile, NULL);
417 for (j = 0; j < NUM_FRAMES; j++) {
418 for (i = 0; i < dev->_lines_count_ch2; i++) {
422 vfs_read(myfile, mybuf, line_size, &pos);
424 if (vfs_read_retval > 0
425 && vfs_read_retval == line_size
426 && dev->_data_buf_virt_addr_ch2 != NULL) {
427 memcpy((void *)(dev->
428 _data_buf_virt_addr_ch2
429 + offset / 4), mybuf,
433 offset += vfs_read_retval;
435 if (vfs_read_retval < line_size) {
437 "Done: exit %s() since no more bytes to read from Video file.\n",
444 dev->_frame_count_ch2++;
446 if (vfs_read_retval < line_size) {
451 dev->_file_status_ch2 =
452 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
456 filp_close(myfile, NULL);
462 static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev,
463 struct sram_channel *sram_ch,
468 dma_addr_t data_dma_addr;
470 if (dev->_dma_virt_addr_ch2 != NULL) {
471 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
472 dev->_dma_virt_addr_ch2,
473 dev->_dma_phys_addr_ch2);
476 dev->_dma_virt_addr_ch2 =
477 pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
479 dev->_dma_virt_start_addr_ch2 = dev->_dma_virt_addr_ch2;
480 dev->_dma_phys_start_addr_ch2 = dma_addr;
481 dev->_dma_phys_addr_ch2 = dma_addr;
482 dev->_risc_size_ch2 = dev->upstream_riscbuf_size_ch2;
484 if (!dev->_dma_virt_addr_ch2) {
486 ("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n");
490 //Iniitize at this address until n bytes to 0
491 memset(dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2);
493 if (dev->_data_buf_virt_addr_ch2 != NULL) {
494 pci_free_consistent(dev->pci, dev->upstream_databuf_size_ch2,
495 dev->_data_buf_virt_addr_ch2,
496 dev->_data_buf_phys_addr_ch2);
498 //For Video Data buffer allocation
499 dev->_data_buf_virt_addr_ch2 =
500 pci_alloc_consistent(dev->pci, dev->upstream_databuf_size_ch2,
502 dev->_data_buf_phys_addr_ch2 = data_dma_addr;
503 dev->_data_buf_size_ch2 = dev->upstream_databuf_size_ch2;
505 if (!dev->_data_buf_virt_addr_ch2) {
507 ("cx25821: FAILED to allocate memory for data buffer! Returning.\n");
511 //Initialize at this address until n bytes to 0
512 memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2);
514 ret = cx25821_openfile_ch2(dev, sram_ch);
518 //Creating RISC programs
520 cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl,
521 dev->_lines_count_ch2);
524 "cx25821: Failed creating Video Upstream Risc programs! \n");
534 int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num,
538 struct sram_channel *channel = &dev->sram_channels[chan_num];
539 int singlefield_lines = NTSC_FIELD_HEIGHT;
540 int line_size_in_bytes = Y422_LINE_SZ;
541 int odd_risc_prog_size = 0;
542 dma_addr_t risc_phys_jump_addr;
545 if (status & FLD_VID_SRC_RISC1) {
546 // We should only process one program per call
547 u32 prog_cnt = cx_read(channel->gpcnt);
549 //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers
550 int_msk_tmp = cx_read(channel->int_msk);
551 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
552 cx_write(channel->int_stat, _intr_msk);
554 spin_lock(&dev->slock);
556 dev->_frame_index_ch2 = prog_cnt;
558 queue_work(dev->_irq_queues_ch2, &dev->_irq_work_entry_ch2);
560 if (dev->_is_first_frame_ch2) {
561 dev->_is_first_frame_ch2 = 0;
563 if (dev->_isNTSC_ch2) {
564 singlefield_lines += 1;
565 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
567 singlefield_lines = PAL_FIELD_HEIGHT;
568 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
571 if (dev->_dma_virt_start_addr_ch2 != NULL) {
573 (dev->_pixel_format_ch2 ==
574 PIXEL_FRMT_411) ? Y411_LINE_SZ :
576 risc_phys_jump_addr =
577 dev->_dma_phys_start_addr_ch2 +
580 rp = cx25821_update_riscprogram_ch2(dev,
582 _dma_virt_start_addr_ch2,
590 // Jump to Even Risc program of 1st Frame
591 *(rp++) = cpu_to_le32(RISC_JUMP);
592 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
593 *(rp++) = cpu_to_le32(0);
597 spin_unlock(&dev->slock);
600 if (dev->_file_status_ch2 == END_OF_FILE) {
601 printk("cx25821: EOF Channel 2 Framecount = %d\n",
602 dev->_frame_count_ch2);
605 //ElSE, set the interrupt mask register, re-enable irq.
606 int_msk_tmp = cx_read(channel->int_msk);
607 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
612 static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id)
614 struct cx25821_dev *dev = dev_id;
615 u32 msk_stat, vid_status;
618 struct sram_channel *sram_ch;
623 channel_num = VID_UPSTREAM_SRAM_CHANNEL_J;
625 sram_ch = &dev->sram_channels[channel_num];
627 msk_stat = cx_read(sram_ch->int_mstat);
628 vid_status = cx_read(sram_ch->int_stat);
630 // Only deal with our interrupt
633 cx25821_video_upstream_irq_ch2(dev, channel_num,
638 cx25821_stop_upstream_video_ch2(dev);
643 return IRQ_RETVAL(handled);
646 static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev,
647 struct sram_channel *ch, int pix_format)
649 int width = WIDTH_D1;
650 int height = dev->_lines_count_ch2;
651 int num_lines, odd_num_lines;
653 int vip_mode = PIXEL_ENGINE_VIP1;
655 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
657 value |= dev->_isNTSC_ch2 ? 0 : 0x10;
658 cx_write(ch->vid_fmt_ctl, value);
660 // set number of active pixels in each line. Default is 720 pixels in both NTSC and PAL format
661 cx_write(ch->vid_active_ctl1, width);
663 num_lines = (height / 2) & 0x3FF;
664 odd_num_lines = num_lines;
666 if (dev->_isNTSC_ch2) {
670 value = (num_lines << 16) | odd_num_lines;
672 // set number of active lines in field 0 (top) and field 1 (bottom)
673 cx_write(ch->vid_active_ctl2, value);
675 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
678 int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev,
679 struct sram_channel *sram_ch)
684 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
685 tmp = cx_read(VID_CH_MODE_SEL);
686 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
688 // Set the physical start address of the RISC program in the initial program counter(IPC) member of the cmds.
689 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2);
690 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
693 cx_write(sram_ch->gpcnt_ctl, 3);
695 // Clear our bits from the interrupt status register.
696 cx_write(sram_ch->int_stat, _intr_msk);
698 //Set the interrupt mask register, enable irq.
699 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
700 tmp = cx_read(sram_ch->int_msk);
701 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
704 request_irq(dev->pci->irq, cx25821_upstream_irq_ch2,
705 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
707 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name,
711 // Start the DMA engine
712 tmp = cx_read(sram_ch->dma_ctl);
713 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
715 dev->_is_running_ch2 = 1;
716 dev->_is_first_frame_ch2 = 1;
721 cx25821_dev_unregister(dev);
725 int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select,
728 struct sram_channel *sram_ch;
732 int data_frame_size = 0;
733 int risc_buffer_size = 0;
736 if (dev->_is_running_ch2) {
737 printk("Video Channel is still running so return!\n");
741 dev->_channel2_upstream_select = channel_select;
742 sram_ch = &dev->sram_channels[channel_select];
744 INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2);
745 dev->_irq_queues_ch2 =
746 create_singlethread_workqueue("cx25821_workqueue2");
748 if (!dev->_irq_queues_ch2) {
750 ("cx25821: create_singlethread_workqueue() for Video FAILED!\n");
753 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
754 tmp = cx_read(VID_CH_MODE_SEL);
755 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
757 dev->_is_running_ch2 = 0;
758 dev->_frame_count_ch2 = 0;
759 dev->_file_status_ch2 = RESET_STATUS;
760 dev->_lines_count_ch2 = dev->_isNTSC_ch2 ? 480 : 576;
761 dev->_pixel_format_ch2 = pixel_format;
762 dev->_line_size_ch2 =
763 (dev->_pixel_format_ch2 ==
764 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
765 data_frame_size = dev->_isNTSC_ch2 ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
767 dev->_isNTSC_ch2 ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
769 if (dev->input_filename_ch2) {
770 str_length = strlen(dev->input_filename_ch2);
772 (char *)kmalloc(str_length + 1, GFP_KERNEL);
774 if (!dev->_filename_ch2)
777 memcpy(dev->_filename_ch2, dev->input_filename_ch2,
780 str_length = strlen(dev->_defaultname_ch2);
782 (char *)kmalloc(str_length + 1, GFP_KERNEL);
784 if (!dev->_filename_ch2)
787 memcpy(dev->_filename_ch2, dev->_defaultname_ch2,
791 //Default if filename is empty string
792 if (strcmp(dev->input_filename_ch2, "") == 0) {
793 if (dev->_isNTSC_ch2) {
795 (dev->_pixel_format_ch2 ==
796 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
800 (dev->_pixel_format_ch2 ==
801 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
807 cx25821_sram_channel_setup_upstream(dev, sram_ch,
808 dev->_line_size_ch2, 0);
810 /* setup fifo + format */
811 cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2);
813 dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2;
814 dev->upstream_databuf_size_ch2 = data_frame_size * 2;
816 //Allocating buffers and prepare RISC program
818 cx25821_upstream_buffer_prepare_ch2(dev, sram_ch,
819 dev->_line_size_ch2);
822 "%s: Failed to set up Video upstream buffers!\n",
827 cx25821_start_video_dma_upstream_ch2(dev, sram_ch);
832 cx25821_dev_unregister(dev);