drivers/staging/cxt1e1/comet.c

   1 /* Copyright (C) 2003-2005  SBE, Inc.
   2  *
   3  *   This program is free software; you can redistribute it and/or modify
   4  *   it under the terms of the GNU General Public License as published by
   5  *   the Free Software Foundation; either version 2 of the License, or
   6  *   (at your option) any later version.
   7  *
   8  *   This program is distributed in the hope that it will be useful,
   9  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *   GNU General Public License for more details.
  12  */
  13
  14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  15
  16 #include <linux/io.h>
  17 #include <linux/hdlc.h>
  18 #include "pmcc4_sysdep.h"
  19 #include "sbecom_inline_linux.h"
  20 #include "libsbew.h"
  21 #include "pmcc4.h"
  22 #include "comet.h"
  23 #include "comet_tables.h"
  24
  25 extern int  cxt1e1_log_level;
  26
  27 #define COMET_NUM_SAMPLES   24  /* Number of entries in the waveform table */
  28 #define COMET_NUM_UNITS     5   /* Number of points per entry in table */
  29
  30 /* forward references */
  31 static void SetPwrLevel(struct s_comet_reg *comet);
  32 static void WrtRcvEqualizerTbl(ci_t *ci, struct s_comet_reg *comet,
  33                                 u_int32_t *table);
  34 static void WrtXmtWaveformTbl(ci_t *ci, struct s_comet_reg *comet,
  35                                 u_int8_t table[COMET_NUM_SAMPLES]
  36                                 [COMET_NUM_UNITS]);
  37
  38
  39 static void *TWV_table[12] = {
  40         TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB,
  41         TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3,
  42         TWVShortHaul4, TWVShortHaul5,
  43         /** PORT POINT - 75 Ohm not supported **/
  44         TWV_E1_75Ohm,
  45         TWV_E1_120Ohm
  46 };
  47
  48
  49 static int
  50 lbo_tbl_lkup(int t1, int lbo) {
  51         /* error switches to default */
  52         if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) {
  53                 if (t1)
  54                         /* default T1 waveform table */
  55                         lbo = CFG_LBO_LH0;
  56
  57                 else
  58                         /* default E1 waveform table */
  59                         lbo = CFG_LBO_E120;
  60         }
  61         /* make index ZERO relative */
  62         return lbo - 1;
  63 }
  64
  65 void init_comet(void *ci, struct s_comet_reg *comet, u_int32_t port_mode,
  66                 int clockmaster, u_int8_t moreParams)
  67 {
  68         u_int8_t isT1mode;
  69         /* T1 default */
  70         u_int8_t    tix = CFG_LBO_LH0;
  71         isT1mode = IS_FRAME_ANY_T1(port_mode);
  72         /* T1 or E1 */
  73         if (isT1mode) {
  74                 /* Select T1 Mode & PIO output enabled */
  75                 pci_write_32((u_int32_t *) &comet->gbl_cfg, 0xa0);
  76                 /* default T1 waveform table */
  77                 tix = lbo_tbl_lkup(isT1mode, CFG_LBO_LH0);
  78         } else {
  79                 /* Select E1 Mode & PIO output enabled */
  80                 pci_write_32((u_int32_t *) &comet->gbl_cfg, 0x81);
  81                 /* default E1 waveform table */
  82                 tix = lbo_tbl_lkup(isT1mode, CFG_LBO_E120);
  83         }
  84
  85         if (moreParams & CFG_LBO_MASK)
  86                 /* dial-in requested waveform table */
  87                 tix = lbo_tbl_lkup(isT1mode, moreParams & CFG_LBO_MASK);
  88         /* Tx line Intfc cfg Set for analog & no special patterns */
  89         /* Transmit Line Interface Config. */
  90         pci_write_32((u_int32_t *) &comet->tx_line_cfg, 0x00);
  91         /* master test Ignore Test settings for now */
  92         /* making sure it's Default value */
  93         pci_write_32((u_int32_t *) &comet->mtest, 0x00);
  94         /* Turn on Center (CENT) and everything else off */
  95         /* RJAT cfg */
  96         pci_write_32((u_int32_t *) &comet->rjat_cfg, 0x10);
  97         /* Set Jitter Attenuation to recommend T1 values */
  98         if (isT1mode) {
  99                 /* RJAT Divider N1 Control */
 100                 pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0x2F);
 101                 /* RJAT Divider N2 Control */
 102                 pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0x2F);
 103         } else {
 104                 /* RJAT Divider N1 Control */
 105                 pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0xFF);
 106                 /* RJAT Divider N2 Control */
 107                 pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0xFF);
 108         }
 109
 110         /* Turn on Center (CENT) and everything else off */
 111         /* TJAT Config. */
 112         pci_write_32((u_int32_t *) &comet->tjat_cfg, 0x10);
 113
 114         /* Do not bypass jitter attenuation and bypass elastic store */
 115         /* rx opts */
 116         pci_write_32((u_int32_t *) &comet->rx_opt, 0x00);
 117
 118         /* TJAT ctrl & TJAT divider ctrl */
 119         /* Set Jitter Attenuation to recommended T1 values */
 120         if (isT1mode) {
 121                 /* TJAT Divider N1 Control */
 122                 pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0x2F);
 123                 /* TJAT Divider N2  Control */
 124                 pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0x2F);
 125         } else {
 126                 /* TJAT Divider N1 Control */
 127                 pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0xFF);
 128                 /* TJAT Divider N2 Control */
 129                 pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0xFF);
 130         }
 131
 132         /* 1c: rx ELST cfg   20: tx ELST cfg  28&38: rx&tx data link ctrl */
 133
 134         /* Select 193-bit frame format */
 135         if (isT1mode) {
 136                 pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x00);
 137                 pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x00);
 138         } else {
 139                 /* Select 256-bit frame format */
 140                 pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x03);
 141                 pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x03);
 142                 /* disable T1 data link receive */
 143                 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x00);
 144                 /* disable T1 data link transmit */
 145                 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x00);
 146         }
 147
 148     /* the following is a default value */
 149     /* Enable 8 out of 10 validation */
 150          /* t1RBOC enable(BOC:BitOriented Code) */
 151         pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
 152         if (isT1mode) {
 153                 /* IBCD cfg: aka Inband Code Detection ** loopback code length
 154                  * set to
 155                  */
 156                 /* 6 bit down, 5 bit up (assert) */
 157                 pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04);
 158                 /* line loopback activate pattern */
 159                 pci_write_32((u_int32_t *) &comet->ibcd_act, 0x08);
 160                 /* deactivate code pattern (i.e.001) */
 161                 pci_write_32((u_int32_t *) &comet->ibcd_deact, 0x24);
 162         }
 163     /* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg  */
 164     /* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg  */
 165     /* 60: t1 ALMI cfg */
 166     /* Configure Line Coding */
 167
 168         switch (port_mode) {
 169         /* 1 - T1 B8ZS */
 170         case CFG_FRAME_SF:
 171                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 172                 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
 173                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 174                 /* 5:B8ZS */
 175                 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x20);
 176                 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
 177                 break;
 178         /* 2 - T1 B8ZS */
 179         case CFG_FRAME_ESF:
 180                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 181                 /* Bit 5: T1 DataLink Enable */
 182                 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
 183                 /* 5: T1 DataLink Enable */
 184                 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
 185                 /* 4:ESF  5:ESFFA */
 186                 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
 187                 /* 2:ESF */
 188                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
 189                 /* 4:ESF  5:B8ZS */
 190                 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x30);
 191                 /* 4:ESF */
 192                 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
 193                 break;
 194         /* 3 - HDB3 */
 195         case CFG_FRAME_E1PLAIN:
 196                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 197                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 198                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0);
 199                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
 200                 break;
 201         /* 4 - HDB3 */
 202         case CFG_FRAME_E1CAS:
 203                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 204                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 205                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x60);
 206                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
 207                 break;
 208         /* 5 - HDB3 */
 209         case CFG_FRAME_E1CRC:
 210                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 211                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 212                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x10);
 213                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
 214                 break;
 215         /* 6 - HDB3 */
 216         case CFG_FRAME_E1CRC_CAS:
 217                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 218                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 219                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x70);
 220                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
 221                 break;
 222         /* 7 - T1 AMI */
 223         case CFG_FRAME_SF_AMI:
 224                 /* Enable AMI Line Decoding */
 225                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 226                 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
 227                 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0);
 228                 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
 229                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 230                 break;
 231         /* 8 - T1 AMI */
 232         case CFG_FRAME_ESF_AMI:
 233                 /* Enable AMI Line Decoding */
 234                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 235                 /* 5: T1 DataLink Enable */
 236                 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
 237                 /* 5: T1 DataLink Enable */
 238                 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
 239                 /* Bit 4:ESF  5:ESFFA */
 240                 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
 241                 /* 2:ESF */
 242                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
 243                 /* 4:ESF */
 244                 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x10);
 245                 /* 4:ESF */
 246                 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
 247                 break;
 248         /* 9 - AMI */
 249         case CFG_FRAME_E1PLAIN_AMI:
 250                 /* Enable AMI Line Decoding */
 251                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 252                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 253                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x80);
 254                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
 255                 break;
 256         /* 10 - AMI */
 257         case CFG_FRAME_E1CAS_AMI:
 258                 /* Enable AMI Line Decoding */
 259                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 260                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 261                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xe0);
 262                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
 263                 break;
 264         /* 11 - AMI */
 265         case CFG_FRAME_E1CRC_AMI:
 266                 /* Enable AMI Line Decoding */
 267                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 268                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 269                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x90);
 270                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
 271                 break;
 272         /* 12 - AMI */
 273         case CFG_FRAME_E1CRC_CAS_AMI:
 274                 /* Enable AMI Line Decoding */
 275                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 276                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 277                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xf0);
 278                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
 279                 break;
 280         }       /* end switch */
 281
 282     /***
 283      * Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0)
 284      * CMODE=1: Clock slave mode with BRCLK as an input,
 285      * DE=0: Use falling edge of BRCLK for data,
 286      * FE=0: Use falling edge of BRCLK for frame,
 287      * CMS=0: Use backplane freq,
 288      * RATE[1:0]=0,0: T1
 289      ***/
 290
 291
 292     /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
 293     /* note "rate bits can only be set once after reset" */
 294         if (clockmaster) {
 295                 /* CMODE == clockMode, 0=clock master
 296                  * (so all 3 others should be slave)
 297                  */
 298                 /* rate = 1.544 Mb/s */
 299                 if (isT1mode)
 300                         /* Comet 0 Master Mode(CMODE=0) */
 301                         pci_write_32((u_int32_t *) &comet->brif_cfg, 0x00);
 302                 /* rate = 2.048 Mb/s */
 303                 else
 304                         /* Comet 0 Master Mode(CMODE=0) */
 305                         pci_write_32((u_int32_t *) &comet->brif_cfg, 0x01);
 306
 307                 /* 31: BRIF frame pulse cfg  06: tx timing options */
 308
 309                 /* Master Mode i.e.FPMODE=0 (@0x20) */
 310                 pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
 311                 if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL) {
 312                         if (cxt1e1_log_level >= LOG_SBEBUG12)
 313                                 pr_info(">> %s: clockmaster internal clock\n",
 314                                         __func__);
 315                         /* internal oscillator */
 316                         pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
 317                 } else {
 318                         /* external clock source */
 319                         if (cxt1e1_log_level >= LOG_SBEBUG12)
 320                                 pr_info(">> %s: clockmaster external clock\n",
 321                                         __func__);
 322                         /* loop timing(external) */
 323                         pci_write_32((u_int32_t *) &comet->tx_time, 0x09);
 324                 }
 325
 326         } else  {
 327                 /* slave */
 328                 if (isT1mode)
 329                         /* Slave Mode(CMODE=1, see above) */
 330                         pci_write_32((u_int32_t *) &comet->brif_cfg, 0x20);
 331                 else
 332                         /* Slave Mode(CMODE=1)*/
 333                         pci_write_32((u_int32_t *) &comet->brif_cfg, 0x21);
 334                 /* Slave Mode i.e. FPMODE=1 (@0x20) */
 335                 pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x20);
 336         if (cxt1e1_log_level >= LOG_SBEBUG12)
 337                 pr_info(">> %s: clockslave internal clock\n", __func__);
 338         /* oscillator timing */
 339         pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
 340         }
 341
 342         /* 32: BRIF parity F-bit cfg */
 343         /* Totem-pole operation */
 344         /* Receive Backplane Parity/F-bit */
 345         pci_write_32((u_int32_t *) &comet->brif_pfcfg, 0x01);
 346
 347     /* dc: RLPS equalizer V ref */
 348     /* Configuration */
 349         if (isT1mode)
 350                 /* RLPS Equalizer Voltage  */
 351                 pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x2c);
 352         else
 353                 /* RLPS Equalizer Voltage  */
 354                 pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x34);
 355
 356     /* Reserved bit set and SQUELCH enabled */
 357     /* f8: RLPS cfg & status  f9: RLPS ALOS detect/clear threshold */
 358         /* RLPS Configuration Status */
 359         pci_write_32((u_int32_t *) &comet->rlps_cfgsts, 0x11);
 360         if (isT1mode)
 361                 /* ? */
 362                 pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x55);
 363         else
 364                 /* ? */
 365                 pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x22);
 366
 367
 368     /* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */
 369     /* CMODE=0: Clock slave mode with BTCLK as an input, DE=1: Use rising */
 370     /* edge of BTCLK for data, FE=1: Use rising edge of BTCLK for frame, */
 371     /* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */
 372     /***    Transmit side is always an Input, Slave Clock*/
 373     /* 40: BTIF cfg  41: loop timing(external) */
 374         /*BTIF frame pulse cfg */
 375         if (isT1mode)
 376                 /* BTIF Configuration  Reg. */
 377                 pci_write_32((u_int32_t *) &comet->btif_cfg, 0x38);
 378         else
 379                 /* BTIF Configuration  Reg. */
 380                 pci_write_32((u_int32_t *) &comet->btif_cfg, 0x39);
 381         /* BTIF Frame Pulse Config. */
 382         pci_write_32((u_int32_t *) &comet->btif_fpcfg, 0x01);
 383
 384     /* 0a: master diag  06: tx timing options */
 385     /* if set Comet to loop back */
 386
 387     /* Comets set to normal */
 388         pci_write_32((u_int32_t *) &comet->mdiag, 0x00);
 389
 390     /* BTCLK driven by TCLKI internally (crystal driven) and Xmt Elasted  */
 391     /* Store is enabled. */
 392
 393         WrtXmtWaveformTbl(ci, comet, TWV_table[tix]);
 394         if (isT1mode)
 395                 WrtRcvEqualizerTbl((ci_t *) ci, comet, &T1_Equalizer[0]);
 396         else
 397                 WrtRcvEqualizerTbl((ci_t *) ci, comet, &E1_Equalizer[0]);
 398         SetPwrLevel(comet);
 399 }
 400
 401 /*
 402 ** Name:        WrtXmtWaveform
 403 ** Description: Formulate the Data for the Pulse Waveform Storage
 404 **                Write register, (F2), from the sample and unit inputs.
 405 **                Write the data to the Pulse Waveform Storage Data register.
 406 ** Returns:     Nothing
 407 */
 408 static void
 409 WrtXmtWaveform(ci_t *ci, struct s_comet_reg *comet, u_int32_t sample,
 410                 u_int32_t unit, u_int8_t data)
 411 {
 412         u_int8_t    WaveformAddr;
 413
 414         WaveformAddr = (sample << 3) + (unit & 7);
 415         pci_write_32((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr);
 416         /* for write order preservation when Optimizing driver */
 417         pci_flush_write(ci);
 418         pci_write_32((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data);
 419 }
 420
 421 /*
 422 ** Name:        WrtXmtWaveformTbl
 423 ** Description: Fill in the Transmit Waveform Values
 424 **                for driving the transmitter DAC.
 425 ** Returns:     Nothing
 426 */
 427 static void
 428 WrtXmtWaveformTbl(ci_t *ci, struct s_comet_reg *comet,
 429                   u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS])
 430 {
 431         u_int32_t sample, unit;
 432
 433         for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) {
 434                 for (unit = 0; unit < COMET_NUM_UNITS; unit++)
 435                         WrtXmtWaveform(ci, comet, sample, unit,
 436                                         table[sample][unit]);
 437                 }
 438
 439     /* Enable transmitter and set output amplitude */
 440         pci_write_32((u_int32_t *) &comet->xlpg_cfg,
 441                         table[COMET_NUM_SAMPLES][0]);
 442 }
 443
 444
 445 /*
 446 ** Name:        WrtXmtWaveform
 447 ** Description: Fill in the Receive Equalizer RAM from the desired
 448 **                table.
 449 ** Returns:     Nothing
 450 **
 451 ** Remarks:  Per PM4351 Device Errata, Receive Equalizer RAM Initialization
 452 **           is coded with early setup of indirect address.
 453 */
 454
 455 static void
 456 WrtRcvEqualizerTbl(ci_t *ci, struct s_comet_reg *comet, u_int32_t *table)
 457 {
 458         u_int32_t   ramaddr;
 459         volatile u_int32_t value;
 460
 461         for (ramaddr = 0; ramaddr < 256; ramaddr++) {
 462                 /*** the following lines are per Errata 7, 2.5 ***/
 463                 {
 464                 /* Set up for a read operation */
 465                 pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0x80);
 466                 /* for write order preservation when Optimizing driver */
 467                 pci_flush_write(ci);
 468                 /* write the addr, initiate a read */
 469                 pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
 470                                 (u_int8_t) ramaddr);
 471                 /* for write order preservation when Optimizing driver */
 472                 pci_flush_write(ci);
 473                 /*
 474                 * wait 3 line rate clock cycles to ensure address bits are
 475                 * captured by T1/E1 clock
 476                 */
 477
 478                 /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
 479                 OS_uwait(4, "wret");
 480         }
 481
 482         value = *table++;
 483         pci_write_32((u_int32_t *) &comet->rlps_idata3,
 484                         (u_int8_t) (value >> 24));
 485         pci_write_32((u_int32_t *) &comet->rlps_idata2,
 486                         (u_int8_t) (value >> 16));
 487         pci_write_32((u_int32_t *) &comet->rlps_idata1,
 488                         (u_int8_t) (value >> 8));
 489         pci_write_32((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
 490          /* for write order preservation when Optimizing driver */
 491         pci_flush_write(ci);
 492
 493         /* Storing RAM address, causes RAM to be updated */
 494
 495                 /* Set up for a write operation */
 496                 pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0);
 497                 /* for write order preservation when optimizing driver */
 498                 pci_flush_write(ci);
 499                 /* write the addr, initiate a read */
 500                 pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
 501                                 (u_int8_t) ramaddr);
 502                  /* for write order preservation when optimizing driver */
 503                 pci_flush_write(ci);
 504
 505         /*
 506         * wait 3 line rate clock cycles to ensure address bits are captured
 507         * by T1/E1 clock
 508         */
 509                 /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
 510                 OS_uwait(4, "wret");
 511         }
 512
 513         /* Enable Equalizer & set it to use 256 periods */
 514         pci_write_32((u_int32_t *) &comet->rlps_eq_cfg, 0xCB);
 515 }
 516
 517
 518 /*
 519 ** Name:        SetPwrLevel
 520 ** Description: Implement power level setting algorithm described below
 521 ** Returns:     Nothing
 522 */
 523
 524 static void
 525 SetPwrLevel(struct s_comet_reg *comet)
 526 {
 527         volatile u_int32_t temp;
 528
 529 /*
 530 **    Algorithm to Balance the Power Distribution of Ttip Tring
 531 **
 532 **    Zero register F6
 533 **    Write 0x01 to register F4
 534 **    Write another 0x01 to register F4
 535 **    Read register F4
 536 **    Remove the 0x01 bit by Anding register F4 with 0xFE
 537 **    Write the resultant value to register F4
 538 **    Repeat these steps for register F5
 539 **    Write 0x01 to register F6
 540 */
 541         /* XLPG Fuse Data Select */
 542         pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x00);
 543         /* XLPG Analog Test Positive control */
 544         pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
 545         pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
 546         temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe;
 547         pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, temp);
 548         pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
 549         pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
 550         /* XLPG Analog Test Negative control */
 551         temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe;
 552         pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, temp);
 553         /* XLPG */
 554         pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x01);
 555 }
 556
 557
 558 /*
 559 ** Name:        SetCometOps
 560 ** Description: Set up the selected Comet's clock edge drive for both
 561 **                the transmit out the analog side and receive to the
 562 **                backplane side.
 563 ** Returns:     Nothing
 564 */
 565 #if 0
 566 static void
 567 SetCometOps(struct s_comet_reg *comet)
 568 {
 569         volatile u_int8_t rd_value;
 570
 571         if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) {
 572                 /* read the BRIF Configuration */
 573                 rd_value = (u_int8_t) pci_read_32((u_int32_t *)
 574                                 &comet->brif_cfg);
 575                 rd_value &= ~0x20;
 576                 pci_write_32((u_int32_t *) &comet->brif_cfg,
 577                                 (u_int32_t) rd_value);
 578                 /* read the BRIF Frame Pulse Configuration */
 579                 rd_value = (u_int8_t) pci_read_32((u_int32_t *)
 580                                 &comet->brif_fpcfg);
 581                 rd_value &= ~0x20;
 582                 pci_write_32((u_int32_t *) &comet->brif_fpcfg,
 583                                 (u_int8_t) rd_value);
 584         } else {
 585         /* read the BRIF Configuration */
 586         rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
 587         rd_value |= 0x20;
 588         pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
 589         /* read the BRIF Frame Pulse Configuration */
 590         rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
 591         rd_value |= 0x20;
 592         pci_write_32(u_int32_t *) & comet->brif_fpcfg, (u_int8_t) rd_value);
 593         }
 594 }
 595 #endif
 596
 597 /***  End-of-File  ***/