2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 * NOTE TO LINUX KERNEL HACKERS: DO NOT REFORMAT THIS CODE!
22 * This is shared code between Digi's CVS archive and the
23 * Linux Kernel sources.
24 * Changing the source just for reformatting needlessly breaks
25 * our CVS diff history.
27 * Send any bug fixes/changes to: Eng.Linux at digi dot com.
32 #include <linux/kernel.h>
33 #include <linux/sched.h> /* For jiffies, task states */
34 #include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */
35 #include <linux/delay.h> /* For udelay */
36 #include <linux/io.h> /* For read[bwl]/write[bwl] */
37 #include <linux/serial.h> /* For struct async_serial */
38 #include <linux/serial_reg.h> /* For the various UART offsets */
39 #include <linux/pci.h>
41 #include "dgnc_driver.h" /* Driver main header file */
45 static inline void cls_parse_isr(struct dgnc_board *brd, uint port);
46 static inline void cls_clear_break(struct channel_t *ch, int force);
47 static inline void cls_set_cts_flow_control(struct channel_t *ch);
48 static inline void cls_set_rts_flow_control(struct channel_t *ch);
49 static inline void cls_set_ixon_flow_control(struct channel_t *ch);
50 static inline void cls_set_ixoff_flow_control(struct channel_t *ch);
51 static inline void cls_set_no_output_flow_control(struct channel_t *ch);
52 static inline void cls_set_no_input_flow_control(struct channel_t *ch);
53 static void cls_parse_modem(struct channel_t *ch, unsigned char signals);
54 static void cls_tasklet(unsigned long data);
55 static void cls_vpd(struct dgnc_board *brd);
56 static void cls_uart_init(struct channel_t *ch);
57 static void cls_uart_off(struct channel_t *ch);
58 static int cls_drain(struct tty_struct *tty, uint seconds);
59 static void cls_param(struct tty_struct *tty);
60 static void cls_assert_modem_signals(struct channel_t *ch);
61 static void cls_flush_uart_write(struct channel_t *ch);
62 static void cls_flush_uart_read(struct channel_t *ch);
63 static void cls_disable_receiver(struct channel_t *ch);
64 static void cls_enable_receiver(struct channel_t *ch);
65 static void cls_send_break(struct channel_t *ch, int msecs);
66 static void cls_send_start_character(struct channel_t *ch);
67 static void cls_send_stop_character(struct channel_t *ch);
68 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch);
69 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch);
70 static uint cls_get_uart_bytes_left(struct channel_t *ch);
71 static void cls_send_immediate_char(struct channel_t *ch, unsigned char);
72 static irqreturn_t cls_intr(int irq, void *voidbrd);
74 struct board_ops dgnc_cls_ops = {
75 .tasklet = cls_tasklet,
77 .uart_init = cls_uart_init,
78 .uart_off = cls_uart_off,
82 .assert_modem_signals = cls_assert_modem_signals,
83 .flush_uart_write = cls_flush_uart_write,
84 .flush_uart_read = cls_flush_uart_read,
85 .disable_receiver = cls_disable_receiver,
86 .enable_receiver = cls_enable_receiver,
87 .send_break = cls_send_break,
88 .send_start_character = cls_send_start_character,
89 .send_stop_character = cls_send_stop_character,
90 .copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
91 .get_uart_bytes_left = cls_get_uart_bytes_left,
92 .send_immediate_char = cls_send_immediate_char
96 static inline void cls_set_cts_flow_control(struct channel_t *ch)
98 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
99 unsigned char ier = readb(&ch->ch_cls_uart->ier);
100 unsigned char isr_fcr = 0;
104 * The Enhanced Register Set may only be accessed when
105 * the Line Control Register is set to 0xBFh.
107 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
109 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
111 /* Turn on CTS flow control, turn off IXON flow control */
112 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR);
113 isr_fcr &= ~(UART_EXAR654_EFR_IXON);
115 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
117 /* Write old LCR value back out, which turns enhanced access off */
118 writeb(lcrb, &ch->ch_cls_uart->lcr);
121 * Enable interrupts for CTS flow, turn off interrupts for
122 * received XOFF chars
124 ier |= (UART_EXAR654_IER_CTSDSR);
125 ier &= ~(UART_EXAR654_IER_XOFF);
126 writeb(ier, &ch->ch_cls_uart->ier);
128 /* Set the usual FIFO values */
129 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
131 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
132 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
133 &ch->ch_cls_uart->isr_fcr);
135 ch->ch_t_tlevel = 16;
140 static inline void cls_set_ixon_flow_control(struct channel_t *ch)
142 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
143 unsigned char ier = readb(&ch->ch_cls_uart->ier);
144 unsigned char isr_fcr = 0;
148 * The Enhanced Register Set may only be accessed when
149 * the Line Control Register is set to 0xBFh.
151 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
153 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
155 /* Turn on IXON flow control, turn off CTS flow control */
156 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON);
157 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR);
159 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
161 /* Now set our current start/stop chars while in enhanced mode */
162 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
163 writeb(0, &ch->ch_cls_uart->lsr);
164 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
165 writeb(0, &ch->ch_cls_uart->spr);
167 /* Write old LCR value back out, which turns enhanced access off */
168 writeb(lcrb, &ch->ch_cls_uart->lcr);
171 * Disable interrupts for CTS flow, turn on interrupts for
172 * received XOFF chars
174 ier &= ~(UART_EXAR654_IER_CTSDSR);
175 ier |= (UART_EXAR654_IER_XOFF);
176 writeb(ier, &ch->ch_cls_uart->ier);
178 /* Set the usual FIFO values */
179 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
181 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
182 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
183 &ch->ch_cls_uart->isr_fcr);
188 static inline void cls_set_no_output_flow_control(struct channel_t *ch)
190 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
191 unsigned char ier = readb(&ch->ch_cls_uart->ier);
192 unsigned char isr_fcr = 0;
196 * The Enhanced Register Set may only be accessed when
197 * the Line Control Register is set to 0xBFh.
199 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
201 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
203 /* Turn off IXON flow control, turn off CTS flow control */
204 isr_fcr |= (UART_EXAR654_EFR_ECB);
205 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON);
207 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
209 /* Write old LCR value back out, which turns enhanced access off */
210 writeb(lcrb, &ch->ch_cls_uart->lcr);
213 * Disable interrupts for CTS flow, turn off interrupts for
214 * received XOFF chars
216 ier &= ~(UART_EXAR654_IER_CTSDSR);
217 ier &= ~(UART_EXAR654_IER_XOFF);
218 writeb(ier, &ch->ch_cls_uart->ier);
220 /* Set the usual FIFO values */
221 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
223 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
224 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
225 &ch->ch_cls_uart->isr_fcr);
227 ch->ch_r_watermark = 0;
228 ch->ch_t_tlevel = 16;
229 ch->ch_r_tlevel = 16;
234 static inline void cls_set_rts_flow_control(struct channel_t *ch)
236 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
237 unsigned char ier = readb(&ch->ch_cls_uart->ier);
238 unsigned char isr_fcr = 0;
242 * The Enhanced Register Set may only be accessed when
243 * the Line Control Register is set to 0xBFh.
245 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
247 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
249 /* Turn on RTS flow control, turn off IXOFF flow control */
250 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR);
251 isr_fcr &= ~(UART_EXAR654_EFR_IXOFF);
253 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
255 /* Write old LCR value back out, which turns enhanced access off */
256 writeb(lcrb, &ch->ch_cls_uart->lcr);
258 /* Enable interrupts for RTS flow */
259 ier |= (UART_EXAR654_IER_RTSDTR);
260 writeb(ier, &ch->ch_cls_uart->ier);
262 /* Set the usual FIFO values */
263 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
265 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
266 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
267 &ch->ch_cls_uart->isr_fcr);
270 ch->ch_r_watermark = 4;
276 static inline void cls_set_ixoff_flow_control(struct channel_t *ch)
278 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
279 unsigned char ier = readb(&ch->ch_cls_uart->ier);
280 unsigned char isr_fcr = 0;
284 * The Enhanced Register Set may only be accessed when
285 * the Line Control Register is set to 0xBFh.
287 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
289 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
291 /* Turn on IXOFF flow control, turn off RTS flow control */
292 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF);
293 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR);
295 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
297 /* Now set our current start/stop chars while in enhanced mode */
298 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
299 writeb(0, &ch->ch_cls_uart->lsr);
300 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
301 writeb(0, &ch->ch_cls_uart->spr);
303 /* Write old LCR value back out, which turns enhanced access off */
304 writeb(lcrb, &ch->ch_cls_uart->lcr);
306 /* Disable interrupts for RTS flow */
307 ier &= ~(UART_EXAR654_IER_RTSDTR);
308 writeb(ier, &ch->ch_cls_uart->ier);
310 /* Set the usual FIFO values */
311 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
313 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
314 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
315 &ch->ch_cls_uart->isr_fcr);
320 static inline void cls_set_no_input_flow_control(struct channel_t *ch)
322 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
323 unsigned char ier = readb(&ch->ch_cls_uart->ier);
324 unsigned char isr_fcr = 0;
328 * The Enhanced Register Set may only be accessed when
329 * the Line Control Register is set to 0xBFh.
331 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
333 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
335 /* Turn off IXOFF flow control, turn off RTS flow control */
336 isr_fcr |= (UART_EXAR654_EFR_ECB);
337 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF);
339 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
341 /* Write old LCR value back out, which turns enhanced access off */
342 writeb(lcrb, &ch->ch_cls_uart->lcr);
344 /* Disable interrupts for RTS flow */
345 ier &= ~(UART_EXAR654_IER_RTSDTR);
346 writeb(ier, &ch->ch_cls_uart->ier);
348 /* Set the usual FIFO values */
349 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
351 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
352 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
353 &ch->ch_cls_uart->isr_fcr);
355 ch->ch_t_tlevel = 16;
356 ch->ch_r_tlevel = 16;
363 * Determines whether its time to shut off break condition.
365 * No locks are assumed to be held when calling this function.
366 * channel lock is held and released in this function.
368 static inline void cls_clear_break(struct channel_t *ch, int force)
372 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
375 spin_lock_irqsave(&ch->ch_lock, flags);
377 /* Bail if we aren't currently sending a break. */
378 if (!ch->ch_stop_sending_break) {
379 spin_unlock_irqrestore(&ch->ch_lock, flags);
383 /* Turn break off, and unset some variables */
384 if (ch->ch_flags & CH_BREAK_SENDING) {
385 if (time_after(jiffies, ch->ch_stop_sending_break) || force) {
386 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
388 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
389 ch->ch_flags &= ~(CH_BREAK_SENDING);
390 ch->ch_stop_sending_break = 0;
393 spin_unlock_irqrestore(&ch->ch_lock, flags);
397 /* Parse the ISR register for the specific port */
398 static inline void cls_parse_isr(struct dgnc_board *brd, uint port)
400 struct channel_t *ch;
401 unsigned char isr = 0;
405 * No need to verify board pointer, it was already
406 * verified in the interrupt routine.
409 if (port > brd->nasync)
412 ch = brd->channels[port];
413 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
416 /* Here we try to figure out what caused the interrupt to happen */
419 isr = readb(&ch->ch_cls_uart->isr_fcr);
421 /* Bail if no pending interrupt on port */
422 if (isr & UART_IIR_NO_INT)
425 /* Receive Interrupt pending */
426 if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) {
427 /* Read data from uart -> queue */
430 cls_copy_data_from_uart_to_queue(ch);
431 dgnc_check_queue_flow_control(ch);
434 /* Transmit Hold register empty pending */
435 if (isr & UART_IIR_THRI) {
436 /* Transfer data (if any) from Write Queue -> UART. */
437 spin_lock_irqsave(&ch->ch_lock, flags);
438 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
441 spin_unlock_irqrestore(&ch->ch_lock, flags);
442 cls_copy_data_from_queue_to_uart(ch);
445 /* CTS/RTS change of state */
446 if (isr & UART_IIR_CTSRTS) {
450 * Don't need to do anything, the cls_parse_modem
451 * below will grab the updated modem signals.
455 /* Parse any modem signal changes */
456 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
463 * Send any/all changes to the line to the UART.
465 static void cls_param(struct tty_struct *tty)
467 unsigned char lcr = 0;
468 unsigned char uart_lcr = 0;
469 unsigned char ier = 0;
470 unsigned char uart_ier = 0;
473 struct dgnc_board *bd;
474 struct channel_t *ch;
477 if (!tty || tty->magic != TTY_MAGIC)
480 un = (struct un_t *) tty->driver_data;
481 if (!un || un->magic != DGNC_UNIT_MAGIC)
485 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
489 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
493 * If baud rate is zero, flush queues, and set mval to drop DTR.
495 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
503 cls_flush_uart_write(ch);
504 cls_flush_uart_read(ch);
506 /* The baudrate is B0 so all modem lines are to be dropped. */
507 ch->ch_flags |= (CH_BAUD0);
508 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
509 cls_assert_modem_signals(ch);
512 } else if (ch->ch_custom_speed) {
514 baud = ch->ch_custom_speed;
515 /* Handle transition from B0 */
516 if (ch->ch_flags & CH_BAUD0) {
517 ch->ch_flags &= ~(CH_BAUD0);
520 * Bring back up RTS and DTR...
521 * Also handle RTS or DTR toggle if set.
523 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
524 ch->ch_mostat |= (UART_MCR_RTS);
525 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
526 ch->ch_mostat |= (UART_MCR_DTR);
533 ulong bauds[4][16] = {
537 600, 1200, 1800, 2400,
538 4800, 9600, 19200, 38400 },
539 { /* slowbaud & CBAUDEX */
540 0, 57600, 115200, 230400,
541 460800, 150, 200, 921600,
542 600, 1200, 1800, 2400,
543 4800, 9600, 19200, 38400 },
545 0, 57600, 76800, 115200,
546 131657, 153600, 230400, 460800,
547 921600, 1200, 1800, 2400,
548 4800, 9600, 19200, 38400 },
549 { /* fastbaud & CBAUDEX */
550 0, 57600, 115200, 230400,
551 460800, 150, 200, 921600,
552 600, 1200, 1800, 2400,
553 4800, 9600, 19200, 38400 }
557 * Only use the TXPrint baud rate if the terminal
560 if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
561 (un->un_type == DGNC_PRINT))
562 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
564 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
566 if (ch->ch_c_cflag & CBAUDEX)
569 if (ch->ch_digi.digi_flags & DIGI_FAST)
574 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) &&
576 baud = bauds[iindex][jindex];
584 /* Handle transition from B0 */
585 if (ch->ch_flags & CH_BAUD0) {
586 ch->ch_flags &= ~(CH_BAUD0);
589 * Bring back up RTS and DTR...
590 * Also handle RTS or DTR toggle if set.
592 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
593 ch->ch_mostat |= (UART_MCR_RTS);
594 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
595 ch->ch_mostat |= (UART_MCR_DTR);
599 if (ch->ch_c_cflag & PARENB)
600 lcr |= UART_LCR_PARITY;
602 if (!(ch->ch_c_cflag & PARODD))
603 lcr |= UART_LCR_EPAR;
606 * Not all platforms support mark/space parity,
607 * so this will hide behind an ifdef.
610 if (ch->ch_c_cflag & CMSPAR)
611 lcr |= UART_LCR_SPAR;
614 if (ch->ch_c_cflag & CSTOPB)
615 lcr |= UART_LCR_STOP;
617 switch (ch->ch_c_cflag & CSIZE) {
619 lcr |= UART_LCR_WLEN5;
622 lcr |= UART_LCR_WLEN6;
625 lcr |= UART_LCR_WLEN7;
629 lcr |= UART_LCR_WLEN8;
633 uart_ier = readb(&ch->ch_cls_uart->ier);
635 uart_lcr = readb(&ch->ch_cls_uart->lcr);
640 quot = ch->ch_bd->bd_dividend / baud;
642 if (quot != 0 && ch->ch_old_baud != baud) {
643 ch->ch_old_baud = baud;
644 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
645 writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
646 writeb((quot >> 8), &ch->ch_cls_uart->ier);
647 writeb(lcr, &ch->ch_cls_uart->lcr);
651 writeb(lcr, &ch->ch_cls_uart->lcr);
653 if (ch->ch_c_cflag & CREAD)
654 ier |= (UART_IER_RDI | UART_IER_RLSI);
656 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
659 * Have the UART interrupt on modem signal changes ONLY when
660 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
662 if ((ch->ch_digi.digi_flags & CTSPACE) ||
663 (ch->ch_digi.digi_flags & RTSPACE) ||
664 (ch->ch_c_cflag & CRTSCTS) ||
665 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
666 !(ch->ch_c_cflag & CLOCAL))
669 ier &= ~UART_IER_MSI;
671 ier |= UART_IER_THRI;
674 writeb(ier, &ch->ch_cls_uart->ier);
676 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
677 cls_set_cts_flow_control(ch);
678 } else if (ch->ch_c_iflag & IXON) {
680 * If start/stop is set to disable, then we should
681 * disable flow control
683 if ((ch->ch_startc == _POSIX_VDISABLE) ||
684 (ch->ch_stopc == _POSIX_VDISABLE))
685 cls_set_no_output_flow_control(ch);
687 cls_set_ixon_flow_control(ch);
689 cls_set_no_output_flow_control(ch);
692 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
693 cls_set_rts_flow_control(ch);
694 } else if (ch->ch_c_iflag & IXOFF) {
696 * If start/stop is set to disable, then we should disable
699 if ((ch->ch_startc == _POSIX_VDISABLE) ||
700 (ch->ch_stopc == _POSIX_VDISABLE))
701 cls_set_no_input_flow_control(ch);
703 cls_set_ixoff_flow_control(ch);
705 cls_set_no_input_flow_control(ch);
708 cls_assert_modem_signals(ch);
710 /* Get current status of the modem signals now */
711 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
716 * Our board poller function.
718 static void cls_tasklet(unsigned long data)
720 struct dgnc_board *bd = (struct dgnc_board *) data;
721 struct channel_t *ch;
727 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
730 /* Cache a couple board values */
731 spin_lock_irqsave(&bd->bd_lock, flags);
734 spin_unlock_irqrestore(&bd->bd_lock, flags);
737 * Do NOT allow the interrupt routine to read the intr registers
738 * Until we release this lock.
740 spin_lock_irqsave(&bd->bd_intr_lock, flags);
743 * If board is ready, parse deeper to see if there is anything to do.
745 if ((state == BOARD_READY) && (ports > 0)) {
747 /* Loop on each port */
748 for (i = 0; i < ports; i++) {
749 ch = bd->channels[i];
754 * NOTE: Remember you CANNOT hold any channel
755 * locks when calling input.
756 * During input processing, its possible we
757 * will call ld, which might do callbacks back
763 * Channel lock is grabbed and then released
764 * inside this routine.
766 cls_copy_data_from_queue_to_uart(ch);
767 dgnc_wakeup_writes(ch);
770 * Check carrier function.
775 * The timing check of turning off the break is done
776 * inside clear_break()
778 if (ch->ch_stop_sending_break)
779 cls_clear_break(ch, 0);
783 spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
791 * Classic specific interrupt handler.
793 static irqreturn_t cls_intr(int irq, void *voidbrd)
795 struct dgnc_board *brd = voidbrd;
797 unsigned char poll_reg;
801 * Check to make sure it didn't receive interrupt with a null board
802 * associated or a board pointer that wasn't ours.
804 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
807 spin_lock_irqsave(&brd->bd_intr_lock, flags);
812 * Check the board's global interrupt offset to see if we
813 * we actually do have an interrupt pending for us.
815 poll_reg = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);
817 /* If 0, no interrupts pending */
819 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
823 /* Parse each port to find out what caused the interrupt */
824 for (i = 0; i < brd->nasync; i++)
825 cls_parse_isr(brd, i);
828 * Schedule tasklet to more in-depth servicing at a better time.
830 tasklet_schedule(&brd->helper_tasklet);
832 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
838 static void cls_disable_receiver(struct channel_t *ch)
840 unsigned char tmp = readb(&ch->ch_cls_uart->ier);
842 tmp &= ~(UART_IER_RDI);
843 writeb(tmp, &ch->ch_cls_uart->ier);
847 static void cls_enable_receiver(struct channel_t *ch)
849 unsigned char tmp = readb(&ch->ch_cls_uart->ier);
851 tmp |= (UART_IER_RDI);
852 writeb(tmp, &ch->ch_cls_uart->ier);
856 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch)
859 unsigned char linestatus = 0;
860 unsigned char error_mask = 0;
865 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
868 spin_lock_irqsave(&ch->ch_lock, flags);
870 /* cache head and tail of queue */
871 head = ch->ch_r_head;
872 tail = ch->ch_r_tail;
874 /* Store how much space we have left in the queue */
875 qleft = (tail - head - 1);
877 qleft += RQUEUEMASK + 1;
880 * Create a mask to determine whether we should
881 * insert the character (if any) into our queue.
883 if (ch->ch_c_iflag & IGNBRK)
884 error_mask |= UART_LSR_BI;
887 linestatus = readb(&ch->ch_cls_uart->lsr);
889 if (!(linestatus & (UART_LSR_DR)))
893 * Discard character if we are ignoring the error mask.
895 if (linestatus & error_mask) {
896 unsigned char discard;
899 discard = readb(&ch->ch_cls_uart->txrx);
904 * If our queue is full, we have no choice but to drop some
905 * data. The assumption is that HWFLOW or SWFLOW should have
906 * stopped things way way before we got to this point.
908 * I decided that I wanted to ditch the oldest data first,
909 * I hope thats okay with everyone? Yes? Good.
912 tail = (tail + 1) & RQUEUEMASK;
913 ch->ch_r_tail = tail;
914 ch->ch_err_overrun++;
918 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
920 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
924 if (ch->ch_equeue[head] & UART_LSR_PE)
926 if (ch->ch_equeue[head] & UART_LSR_BI)
928 if (ch->ch_equeue[head] & UART_LSR_FE)
931 /* Add to, and flip head if needed */
932 head = (head + 1) & RQUEUEMASK;
937 * Write new final heads to channel structure.
939 ch->ch_r_head = head & RQUEUEMASK;
940 ch->ch_e_head = head & EQUEUEMASK;
942 spin_unlock_irqrestore(&ch->ch_lock, flags);
947 * This function basically goes to sleep for secs, or until
948 * it gets signalled that the port has fully drained.
950 static int cls_drain(struct tty_struct *tty, uint seconds)
953 struct channel_t *ch;
956 if (!tty || tty->magic != TTY_MAGIC)
959 un = (struct un_t *) tty->driver_data;
960 if (!un || un->magic != DGNC_UNIT_MAGIC)
964 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
967 spin_lock_irqsave(&ch->ch_lock, flags);
968 un->un_flags |= UN_EMPTY;
969 spin_unlock_irqrestore(&ch->ch_lock, flags);
972 * NOTE: Do something with time passed in.
975 /* If ret is non-zero, user ctrl-c'ed us */
977 return wait_event_interruptible(un->un_flags_wait,
978 ((un->un_flags & UN_EMPTY) == 0));
982 /* Channel lock MUST be held before calling this function! */
983 static void cls_flush_uart_write(struct channel_t *ch)
985 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
988 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
989 &ch->ch_cls_uart->isr_fcr);
992 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
996 /* Channel lock MUST be held before calling this function! */
997 static void cls_flush_uart_read(struct channel_t *ch)
999 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1003 * For complete POSIX compatibility, we should be purging the
1004 * read FIFO in the UART here.
1006 * However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also
1007 * incorrectly flushes write data as well as just basically trashing the
1010 * Presumably, this is a bug in this UART.
1017 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch)
1023 uint len_written = 0;
1024 unsigned long flags;
1026 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1029 spin_lock_irqsave(&ch->ch_lock, flags);
1031 /* No data to write to the UART */
1032 if (ch->ch_w_tail == ch->ch_w_head) {
1033 spin_unlock_irqrestore(&ch->ch_lock, flags);
1037 /* If port is "stopped", don't send any data to the UART */
1038 if ((ch->ch_flags & CH_FORCED_STOP) ||
1039 (ch->ch_flags & CH_BREAK_SENDING)) {
1040 spin_unlock_irqrestore(&ch->ch_lock, flags);
1044 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) {
1045 spin_unlock_irqrestore(&ch->ch_lock, flags);
1051 /* cache head and tail of queue */
1052 head = ch->ch_w_head & WQUEUEMASK;
1053 tail = ch->ch_w_tail & WQUEUEMASK;
1054 qlen = (head - tail) & WQUEUEMASK;
1056 /* Find minimum of the FIFO space, versus queue length */
1062 * If RTS Toggle mode is on, turn on RTS now if not already set,
1063 * and make sure we get an event when the data transfer has
1066 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1067 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1068 ch->ch_mostat |= (UART_MCR_RTS);
1069 cls_assert_modem_signals(ch);
1071 ch->ch_tun.un_flags |= (UN_EMPTY);
1075 * If DTR Toggle mode is on, turn on DTR now if not already set,
1076 * and make sure we get an event when the data transfer has
1079 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1080 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1081 ch->ch_mostat |= (UART_MCR_DTR);
1082 cls_assert_modem_signals(ch);
1084 ch->ch_tun.un_flags |= (UN_EMPTY);
1086 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_cls_uart->txrx);
1088 ch->ch_w_tail &= WQUEUEMASK;
1094 if (len_written > 0)
1095 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1097 spin_unlock_irqrestore(&ch->ch_lock, flags);
1101 static void cls_parse_modem(struct channel_t *ch, unsigned char signals)
1103 unsigned char msignals = signals;
1104 unsigned long flags;
1106 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1110 * Do altpin switching. Altpin switches DCD and DSR.
1111 * This prolly breaks DSRPACE, so we should be more clever here.
1113 spin_lock_irqsave(&ch->ch_lock, flags);
1114 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1115 unsigned char mswap = signals;
1117 if (mswap & UART_MSR_DDCD) {
1118 msignals &= ~UART_MSR_DDCD;
1119 msignals |= UART_MSR_DDSR;
1121 if (mswap & UART_MSR_DDSR) {
1122 msignals &= ~UART_MSR_DDSR;
1123 msignals |= UART_MSR_DDCD;
1125 if (mswap & UART_MSR_DCD) {
1126 msignals &= ~UART_MSR_DCD;
1127 msignals |= UART_MSR_DSR;
1129 if (mswap & UART_MSR_DSR) {
1130 msignals &= ~UART_MSR_DSR;
1131 msignals |= UART_MSR_DCD;
1134 spin_unlock_irqrestore(&ch->ch_lock, flags);
1137 * Scrub off lower bits. They signify delta's, which I don't
1142 spin_lock_irqsave(&ch->ch_lock, flags);
1143 if (msignals & UART_MSR_DCD)
1144 ch->ch_mistat |= UART_MSR_DCD;
1146 ch->ch_mistat &= ~UART_MSR_DCD;
1148 if (msignals & UART_MSR_DSR)
1149 ch->ch_mistat |= UART_MSR_DSR;
1151 ch->ch_mistat &= ~UART_MSR_DSR;
1153 if (msignals & UART_MSR_RI)
1154 ch->ch_mistat |= UART_MSR_RI;
1156 ch->ch_mistat &= ~UART_MSR_RI;
1158 if (msignals & UART_MSR_CTS)
1159 ch->ch_mistat |= UART_MSR_CTS;
1161 ch->ch_mistat &= ~UART_MSR_CTS;
1162 spin_unlock_irqrestore(&ch->ch_lock, flags);
1166 /* Make the UART raise any of the output signals we want up */
1167 static void cls_assert_modem_signals(struct channel_t *ch)
1171 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1174 out = ch->ch_mostat;
1176 if (ch->ch_flags & CH_LOOPBACK)
1177 out |= UART_MCR_LOOP;
1179 writeb(out, &ch->ch_cls_uart->mcr);
1181 /* Give time for the UART to actually drop the signals */
1186 static void cls_send_start_character(struct channel_t *ch)
1188 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1191 if (ch->ch_startc != _POSIX_VDISABLE) {
1193 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
1198 static void cls_send_stop_character(struct channel_t *ch)
1200 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1203 if (ch->ch_stopc != _POSIX_VDISABLE) {
1204 ch->ch_xoff_sends++;
1205 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
1211 static void cls_uart_init(struct channel_t *ch)
1213 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
1214 unsigned char isr_fcr = 0;
1216 writeb(0, &ch->ch_cls_uart->ier);
1219 * The Enhanced Register Set may only be accessed when
1220 * the Line Control Register is set to 0xBFh.
1222 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
1224 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
1226 /* Turn on Enhanced/Extended controls */
1227 isr_fcr |= (UART_EXAR654_EFR_ECB);
1229 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
1231 /* Write old LCR value back out, which turns enhanced access off */
1232 writeb(lcrb, &ch->ch_cls_uart->lcr);
1234 /* Clear out UART and FIFO */
1235 readb(&ch->ch_cls_uart->txrx);
1237 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT),
1238 &ch->ch_cls_uart->isr_fcr);
1241 ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1243 readb(&ch->ch_cls_uart->lsr);
1244 readb(&ch->ch_cls_uart->msr);
1251 static void cls_uart_off(struct channel_t *ch)
1253 writeb(0, &ch->ch_cls_uart->ier);
1258 * cls_get_uarts_bytes_left.
1259 * Returns 0 is nothing left in the FIFO, returns 1 otherwise.
1261 * The channel lock MUST be held by the calling function.
1263 static uint cls_get_uart_bytes_left(struct channel_t *ch)
1265 unsigned char left = 0;
1266 unsigned char lsr = 0;
1268 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1271 lsr = readb(&ch->ch_cls_uart->lsr);
1273 /* Determine whether the Transmitter is empty or not */
1274 if (!(lsr & UART_LSR_TEMT)) {
1275 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1276 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1279 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1289 * Starts sending a break thru the UART.
1291 * The channel lock MUST be held by the calling function.
1293 static void cls_send_break(struct channel_t *ch, int msecs)
1295 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1299 * If we receive a time of 0, this means turn off the break.
1302 /* Turn break off, and unset some variables */
1303 if (ch->ch_flags & CH_BREAK_SENDING) {
1304 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
1306 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1307 ch->ch_flags &= ~(CH_BREAK_SENDING);
1308 ch->ch_stop_sending_break = 0;
1314 * Set the time we should stop sending the break.
1315 * If we are already sending a break, toss away the existing
1316 * time to stop, and use this new value instead.
1318 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1320 /* Tell the UART to start sending the break */
1321 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1322 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
1324 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1325 ch->ch_flags |= (CH_BREAK_SENDING);
1331 * cls_send_immediate_char.
1332 * Sends a specific character as soon as possible to the UART,
1333 * jumping over any bytes that might be in the write queue.
1335 * The channel lock MUST be held by the calling function.
1337 static void cls_send_immediate_char(struct channel_t *ch, unsigned char c)
1339 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1342 writeb(c, &ch->ch_cls_uart->txrx);
1345 static void cls_vpd(struct dgnc_board *brd)
1347 ulong vpdbase; /* Start of io base of the card */
1348 u8 __iomem *re_map_vpdbase;/* Remapped memory of the card */
1352 vpdbase = pci_resource_start(brd->pdev, 3);
1358 re_map_vpdbase = ioremap(vpdbase, 0x400);
1360 if (!re_map_vpdbase)
1363 /* Store the VPD into our buffer */
1364 for (i = 0; i < 0x40; i++) {
1365 brd->vpd[i] = readb(re_map_vpdbase + i);
1366 pr_info("%x ", brd->vpd[i]);
1371 iounmap(re_map_vpdbase);