drivers/staging/dgnc/dgnc_cls.c

   1 /*
   2  * Copyright 2003 Digi International (www.digi.com)
   3  *      Scott H Kilau <Scott_Kilau at digi dot com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2, or (at your option)
   8  * any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
  12  * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
  13  * PURPOSE.  See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  *
  20  *      NOTE TO LINUX KERNEL HACKERS:  DO NOT REFORMAT THIS CODE!
  21  *
  22  *      This is shared code between Digi's CVS archive and the
  23  *      Linux Kernel sources.
  24  *      Changing the source just for reformatting needlessly breaks
  25  *      our CVS diff history.
  26  *
  27  *      Send any bug fixes/changes to:  Eng.Linux at digi dot com.
  28  *      Thank you.
  29  *
  30  */
  31
  32 #include <linux/kernel.h>
  33 #include <linux/sched.h>        /* For jiffies, task states */
  34 #include <linux/interrupt.h>    /* For tasklet and interrupt structs/defines */
  35 #include <linux/delay.h>        /* For udelay */
  36 #include <linux/io.h>           /* For read[bwl]/write[bwl] */
  37 #include <linux/serial.h>       /* For struct async_serial */
  38 #include <linux/serial_reg.h>   /* For the various UART offsets */
  39 #include <linux/pci.h>
  40
  41 #include "dgnc_driver.h"        /* Driver main header file */
  42 #include "dgnc_cls.h"
  43 #include "dgnc_tty.h"
  44
  45 static inline void cls_parse_isr(struct dgnc_board *brd, uint port);
  46 static inline void cls_clear_break(struct channel_t *ch, int force);
  47 static inline void cls_set_cts_flow_control(struct channel_t *ch);
  48 static inline void cls_set_rts_flow_control(struct channel_t *ch);
  49 static inline void cls_set_ixon_flow_control(struct channel_t *ch);
  50 static inline void cls_set_ixoff_flow_control(struct channel_t *ch);
  51 static inline void cls_set_no_output_flow_control(struct channel_t *ch);
  52 static inline void cls_set_no_input_flow_control(struct channel_t *ch);
  53 static void cls_parse_modem(struct channel_t *ch, uchar signals);
  54 static void cls_tasklet(unsigned long data);
  55 static void cls_vpd(struct dgnc_board *brd);
  56 static void cls_uart_init(struct channel_t *ch);
  57 static void cls_uart_off(struct channel_t *ch);
  58 static int cls_drain(struct tty_struct *tty, uint seconds);
  59 static void cls_param(struct tty_struct *tty);
  60 static void cls_assert_modem_signals(struct channel_t *ch);
  61 static void cls_flush_uart_write(struct channel_t *ch);
  62 static void cls_flush_uart_read(struct channel_t *ch);
  63 static void cls_disable_receiver(struct channel_t *ch);
  64 static void cls_enable_receiver(struct channel_t *ch);
  65 static void cls_send_break(struct channel_t *ch, int msecs);
  66 static void cls_send_start_character(struct channel_t *ch);
  67 static void cls_send_stop_character(struct channel_t *ch);
  68 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch);
  69 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch);
  70 static uint cls_get_uart_bytes_left(struct channel_t *ch);
  71 static void cls_send_immediate_char(struct channel_t *ch, unsigned char);
  72 static irqreturn_t cls_intr(int irq, void *voidbrd);
  73
  74 struct board_ops dgnc_cls_ops = {
  75         .tasklet =                      cls_tasklet,
  76         .intr =                         cls_intr,
  77         .uart_init =                    cls_uart_init,
  78         .uart_off =                     cls_uart_off,
  79         .drain =                        cls_drain,
  80         .param =                        cls_param,
  81         .vpd =                          cls_vpd,
  82         .assert_modem_signals =         cls_assert_modem_signals,
  83         .flush_uart_write =             cls_flush_uart_write,
  84         .flush_uart_read =              cls_flush_uart_read,
  85         .disable_receiver =             cls_disable_receiver,
  86         .enable_receiver =              cls_enable_receiver,
  87         .send_break =                   cls_send_break,
  88         .send_start_character =         cls_send_start_character,
  89         .send_stop_character =          cls_send_stop_character,
  90         .copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
  91         .get_uart_bytes_left =          cls_get_uart_bytes_left,
  92         .send_immediate_char =          cls_send_immediate_char
  93 };
  94
  95
  96 static inline void cls_set_cts_flow_control(struct channel_t *ch)
  97 {
  98         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
  99         uchar ier = readb(&ch->ch_cls_uart->ier);
 100         uchar isr_fcr = 0;
 101
 102         DPR_PARAM(("Setting CTSFLOW\n"));
 103
 104         /*
 105          * The Enhanced Register Set may only be accessed when
 106          * the Line Control Register is set to 0xBFh.
 107          */
 108         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 109
 110         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 111
 112         /* Turn on CTS flow control, turn off IXON flow control */
 113         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR);
 114         isr_fcr &= ~(UART_EXAR654_EFR_IXON);
 115
 116         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 117
 118         /* Write old LCR value back out, which turns enhanced access off */
 119         writeb(lcrb, &ch->ch_cls_uart->lcr);
 120
 121         /*
 122          * Enable interrupts for CTS flow, turn off interrupts for
 123          * received XOFF chars
 124          */
 125         ier |= (UART_EXAR654_IER_CTSDSR);
 126         ier &= ~(UART_EXAR654_IER_XOFF);
 127         writeb(ier, &ch->ch_cls_uart->ier);
 128
 129         /* Set the usual FIFO values */
 130         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 131
 132         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
 133                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 134                 &ch->ch_cls_uart->isr_fcr);
 135
 136         ch->ch_t_tlevel = 16;
 137
 138 }
 139
 140
 141 static inline void cls_set_ixon_flow_control(struct channel_t *ch)
 142 {
 143         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 144         uchar ier = readb(&ch->ch_cls_uart->ier);
 145         uchar isr_fcr = 0;
 146
 147         DPR_PARAM(("Setting IXON FLOW\n"));
 148
 149         /*
 150          * The Enhanced Register Set may only be accessed when
 151          * the Line Control Register is set to 0xBFh.
 152          */
 153         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 154
 155         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 156
 157         /* Turn on IXON flow control, turn off CTS flow control */
 158         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON);
 159         isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR);
 160
 161         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 162
 163         /* Now set our current start/stop chars while in enhanced mode */
 164         writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
 165         writeb(0, &ch->ch_cls_uart->lsr);
 166         writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
 167         writeb(0, &ch->ch_cls_uart->spr);
 168
 169         /* Write old LCR value back out, which turns enhanced access off */
 170         writeb(lcrb, &ch->ch_cls_uart->lcr);
 171
 172         /*
 173          * Disable interrupts for CTS flow, turn on interrupts for
 174          * received XOFF chars
 175          */
 176         ier &= ~(UART_EXAR654_IER_CTSDSR);
 177         ier |= (UART_EXAR654_IER_XOFF);
 178         writeb(ier, &ch->ch_cls_uart->ier);
 179
 180         /* Set the usual FIFO values */
 181         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 182
 183         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 184                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 185                 &ch->ch_cls_uart->isr_fcr);
 186
 187 }
 188
 189
 190 static inline void cls_set_no_output_flow_control(struct channel_t *ch)
 191 {
 192         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 193         uchar ier = readb(&ch->ch_cls_uart->ier);
 194         uchar isr_fcr = 0;
 195
 196         DPR_PARAM(("Unsetting Output FLOW\n"));
 197
 198         /*
 199          * The Enhanced Register Set may only be accessed when
 200          * the Line Control Register is set to 0xBFh.
 201          */
 202         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 203
 204         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 205
 206         /* Turn off IXON flow control, turn off CTS flow control */
 207         isr_fcr |= (UART_EXAR654_EFR_ECB);
 208         isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON);
 209
 210         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 211
 212         /* Write old LCR value back out, which turns enhanced access off */
 213         writeb(lcrb, &ch->ch_cls_uart->lcr);
 214
 215         /*
 216          * Disable interrupts for CTS flow, turn off interrupts for
 217          * received XOFF chars
 218          */
 219         ier &= ~(UART_EXAR654_IER_CTSDSR);
 220         ier &= ~(UART_EXAR654_IER_XOFF);
 221         writeb(ier, &ch->ch_cls_uart->ier);
 222
 223         /* Set the usual FIFO values */
 224         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 225
 226         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 227                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 228                 &ch->ch_cls_uart->isr_fcr);
 229
 230         ch->ch_r_watermark = 0;
 231         ch->ch_t_tlevel = 16;
 232         ch->ch_r_tlevel = 16;
 233
 234 }
 235
 236
 237 static inline void cls_set_rts_flow_control(struct channel_t *ch)
 238 {
 239         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 240         uchar ier = readb(&ch->ch_cls_uart->ier);
 241         uchar isr_fcr = 0;
 242
 243         DPR_PARAM(("Setting RTSFLOW\n"));
 244
 245         /*
 246          * The Enhanced Register Set may only be accessed when
 247          * the Line Control Register is set to 0xBFh.
 248          */
 249         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 250
 251         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 252
 253         /* Turn on RTS flow control, turn off IXOFF flow control */
 254         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR);
 255         isr_fcr &= ~(UART_EXAR654_EFR_IXOFF);
 256
 257         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 258
 259         /* Write old LCR value back out, which turns enhanced access off */
 260         writeb(lcrb, &ch->ch_cls_uart->lcr);
 261
 262         /* Enable interrupts for RTS flow */
 263         ier |= (UART_EXAR654_IER_RTSDTR);
 264         writeb(ier, &ch->ch_cls_uart->ier);
 265
 266         /* Set the usual FIFO values */
 267         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 268
 269         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
 270                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 271                 &ch->ch_cls_uart->isr_fcr);
 272
 273
 274         ch->ch_r_watermark = 4;
 275         ch->ch_r_tlevel = 8;
 276
 277 }
 278
 279
 280 static inline void cls_set_ixoff_flow_control(struct channel_t *ch)
 281 {
 282         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 283         uchar ier = readb(&ch->ch_cls_uart->ier);
 284         uchar isr_fcr = 0;
 285
 286         DPR_PARAM(("Setting IXOFF FLOW\n"));
 287
 288         /*
 289          * The Enhanced Register Set may only be accessed when
 290          * the Line Control Register is set to 0xBFh.
 291          */
 292         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 293
 294         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 295
 296         /* Turn on IXOFF flow control, turn off RTS flow control */
 297         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF);
 298         isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR);
 299
 300         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 301
 302         /* Now set our current start/stop chars while in enhanced mode */
 303         writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
 304         writeb(0, &ch->ch_cls_uart->lsr);
 305         writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
 306         writeb(0, &ch->ch_cls_uart->spr);
 307
 308         /* Write old LCR value back out, which turns enhanced access off */
 309         writeb(lcrb, &ch->ch_cls_uart->lcr);
 310
 311         /* Disable interrupts for RTS flow */
 312         ier &= ~(UART_EXAR654_IER_RTSDTR);
 313         writeb(ier, &ch->ch_cls_uart->ier);
 314
 315         /* Set the usual FIFO values */
 316         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 317
 318         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 319                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 320                 &ch->ch_cls_uart->isr_fcr);
 321
 322 }
 323
 324
 325 static inline void cls_set_no_input_flow_control(struct channel_t *ch)
 326 {
 327         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 328         uchar ier = readb(&ch->ch_cls_uart->ier);
 329         uchar isr_fcr = 0;
 330
 331         DPR_PARAM(("Unsetting Input FLOW\n"));
 332
 333         /*
 334          * The Enhanced Register Set may only be accessed when
 335          * the Line Control Register is set to 0xBFh.
 336          */
 337         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 338
 339         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 340
 341         /* Turn off IXOFF flow control, turn off RTS flow control */
 342         isr_fcr |= (UART_EXAR654_EFR_ECB);
 343         isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF);
 344
 345         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 346
 347         /* Write old LCR value back out, which turns enhanced access off */
 348         writeb(lcrb, &ch->ch_cls_uart->lcr);
 349
 350         /* Disable interrupts for RTS flow */
 351         ier &= ~(UART_EXAR654_IER_RTSDTR);
 352         writeb(ier, &ch->ch_cls_uart->ier);
 353
 354         /* Set the usual FIFO values */
 355         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 356
 357         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 358                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 359                 &ch->ch_cls_uart->isr_fcr);
 360
 361         ch->ch_t_tlevel = 16;
 362         ch->ch_r_tlevel = 16;
 363
 364 }
 365
 366
 367 /*
 368  * cls_clear_break.
 369  * Determines whether its time to shut off break condition.
 370  *
 371  * No locks are assumed to be held when calling this function.
 372  * channel lock is held and released in this function.
 373  */
 374 static inline void cls_clear_break(struct channel_t *ch, int force)
 375 {
 376         ulong lock_flags;
 377
 378         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 379                 return;
 380
 381         DGNC_LOCK(ch->ch_lock, lock_flags);
 382
 383         /* Bail if we aren't currently sending a break. */
 384         if (!ch->ch_stop_sending_break) {
 385                 DGNC_UNLOCK(ch->ch_lock, lock_flags);
 386                 return;
 387         }
 388
 389         /* Turn break off, and unset some variables */
 390         if (ch->ch_flags & CH_BREAK_SENDING) {
 391                 if (time_after(jiffies, ch->ch_stop_sending_break) || force) {
 392                         uchar temp = readb(&ch->ch_cls_uart->lcr);
 393                         writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
 394                         ch->ch_flags &= ~(CH_BREAK_SENDING);
 395                         ch->ch_stop_sending_break = 0;
 396                         DPR_IOCTL(("Finishing UART_LCR_SBC! finished: %lx\n",
 397                                                                 jiffies));
 398                 }
 399         }
 400         DGNC_UNLOCK(ch->ch_lock, lock_flags);
 401 }
 402
 403
 404 /* Parse the ISR register for the specific port */
 405 static inline void cls_parse_isr(struct dgnc_board *brd, uint port)
 406 {
 407         struct channel_t *ch;
 408         uchar isr = 0;
 409         ulong lock_flags;
 410
 411         /*
 412          * No need to verify board pointer, it was already
 413          * verified in the interrupt routine.
 414          */
 415
 416         if (port > brd->nasync)
 417                 return;
 418
 419         ch = brd->channels[port];
 420         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 421                 return;
 422
 423         /* Here we try to figure out what caused the interrupt to happen */
 424         while (1) {
 425
 426                 isr = readb(&ch->ch_cls_uart->isr_fcr);
 427
 428                 /* Bail if no pending interrupt on port */
 429                 if (isr & UART_IIR_NO_INT)
 430                         break;
 431
 432                 DPR_INTR(("%s:%d port: %x isr: %x\n", __FILE__, __LINE__,
 433                                                                  port, isr));
 434
 435                 /* Receive Interrupt pending */
 436                 if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) {
 437                         /* Read data from uart -> queue */
 438                         brd->intr_rx++;
 439                         ch->ch_intr_rx++;
 440                         cls_copy_data_from_uart_to_queue(ch);
 441                         dgnc_check_queue_flow_control(ch);
 442                 }
 443
 444                 /* Transmit Hold register empty pending */
 445                 if (isr & UART_IIR_THRI) {
 446                         /* Transfer data (if any) from Write Queue -> UART. */
 447                         DGNC_LOCK(ch->ch_lock, lock_flags);
 448                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 449                         brd->intr_tx++;
 450                         ch->ch_intr_tx++;
 451                         DGNC_UNLOCK(ch->ch_lock, lock_flags);
 452                         cls_copy_data_from_queue_to_uart(ch);
 453                 }
 454
 455                 /* CTS/RTS change of state */
 456                 if (isr & UART_IIR_CTSRTS) {
 457                         brd->intr_modem++;
 458                         ch->ch_intr_modem++;
 459                         /*
 460                          * Don't need to do anything, the cls_parse_modem
 461                          * below will grab the updated modem signals.
 462                          */
 463                 }
 464
 465                 /* Parse any modem signal changes */
 466                 DPR_INTR(("MOD_STAT: sending to parse_modem_sigs\n"));
 467                 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
 468         }
 469 }
 470
 471
 472 /*
 473  * cls_param()
 474  * Send any/all changes to the line to the UART.
 475  */
 476 static void cls_param(struct tty_struct *tty)
 477 {
 478         uchar lcr = 0;
 479         uchar uart_lcr = 0;
 480         uchar ier = 0;
 481         uchar uart_ier = 0;
 482         uint baud = 9600;
 483         int quot = 0;
 484         struct dgnc_board *bd;
 485         struct channel_t *ch;
 486         struct un_t   *un;
 487
 488         if (!tty || tty->magic != TTY_MAGIC)
 489                 return;
 490
 491         un = (struct un_t *) tty->driver_data;
 492         if (!un || un->magic != DGNC_UNIT_MAGIC)
 493                 return;
 494
 495         ch = un->un_ch;
 496         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 497                 return;
 498
 499         bd = ch->ch_bd;
 500         if (!bd || bd->magic != DGNC_BOARD_MAGIC)
 501                 return;
 502
 503         DPR_PARAM(("param start: tdev: %x cflags: %x oflags: %x iflags: %x\n",
 504                 ch->ch_tun.un_dev, ch->ch_c_cflag, ch->ch_c_oflag,
 505                                                          ch->ch_c_iflag));
 506
 507         /*
 508          * If baud rate is zero, flush queues, and set mval to drop DTR.
 509          */
 510         if ((ch->ch_c_cflag & (CBAUD)) == 0) {
 511                 ch->ch_r_head = ch->ch_r_tail = 0;
 512                 ch->ch_e_head = ch->ch_e_tail = 0;
 513                 ch->ch_w_head = ch->ch_w_tail = 0;
 514
 515                 cls_flush_uart_write(ch);
 516                 cls_flush_uart_read(ch);
 517
 518                 /* The baudrate is B0 so all modem lines are to be dropped. */
 519                 ch->ch_flags |= (CH_BAUD0);
 520                 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
 521                 cls_assert_modem_signals(ch);
 522                 ch->ch_old_baud = 0;
 523                 return;
 524         } else if (ch->ch_custom_speed) {
 525
 526                 baud = ch->ch_custom_speed;
 527                 /* Handle transition from B0 */
 528                 if (ch->ch_flags & CH_BAUD0) {
 529                         ch->ch_flags &= ~(CH_BAUD0);
 530
 531                         /*
 532                          * Bring back up RTS and DTR...
 533                          * Also handle RTS or DTR toggle if set.
 534                          */
 535                         if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
 536                                 ch->ch_mostat |= (UART_MCR_RTS);
 537                         if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
 538                                 ch->ch_mostat |= (UART_MCR_DTR);
 539                 }
 540
 541         } else {
 542                 int iindex = 0;
 543                 int jindex = 0;
 544
 545                 ulong bauds[4][16] = {
 546                         { /* slowbaud */
 547                                 0,      50,     75,     110,
 548                                 134,    150,    200,    300,
 549                                 600,    1200,   1800,   2400,
 550                                 4800,   9600,   19200,  38400 },
 551                         { /* slowbaud & CBAUDEX */
 552                                 0,      57600,  115200, 230400,
 553                                 460800, 150,    200,    921600,
 554                                 600,    1200,   1800,   2400,
 555                                 4800,   9600,   19200,  38400 },
 556                         { /* fastbaud */
 557                                 0,      57600,   76800, 115200,
 558                                 131657, 153600, 230400, 460800,
 559                                 921600, 1200,   1800,   2400,
 560                                 4800,   9600,   19200,  38400 },
 561                         { /* fastbaud & CBAUDEX */
 562                                 0,      57600,  115200, 230400,
 563                                 460800, 150,    200,    921600,
 564                                 600,    1200,   1800,   2400,
 565                                 4800,   9600,   19200,  38400 }
 566                 };
 567
 568                 /*
 569                  * Only use the TXPrint baud rate if the terminal
 570                  * unit is NOT open
 571                  */
 572                 if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
 573                                          (un->un_type == DGNC_PRINT))
 574                         baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
 575                 else
 576                         baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
 577
 578                 if (ch->ch_c_cflag & CBAUDEX)
 579                         iindex = 1;
 580
 581                 if (ch->ch_digi.digi_flags & DIGI_FAST)
 582                         iindex += 2;
 583
 584                 jindex = baud;
 585
 586                 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) &&
 587                                                                 (jindex < 16)) {
 588                         baud = bauds[iindex][jindex];
 589                 } else {
 590                         DPR_IOCTL(("baud indices were out of range (%d)(%d)",
 591                                 iindex, jindex));
 592                         baud = 0;
 593                 }
 594
 595                 if (baud == 0)
 596                         baud = 9600;
 597
 598                 /* Handle transition from B0 */
 599                 if (ch->ch_flags & CH_BAUD0) {
 600                         ch->ch_flags &= ~(CH_BAUD0);
 601
 602                         /*
 603                          * Bring back up RTS and DTR...
 604                          * Also handle RTS or DTR toggle if set.
 605                          */
 606                         if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
 607                                 ch->ch_mostat |= (UART_MCR_RTS);
 608                         if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
 609                                 ch->ch_mostat |= (UART_MCR_DTR);
 610                 }
 611         }
 612
 613         if (ch->ch_c_cflag & PARENB)
 614                 lcr |= UART_LCR_PARITY;
 615
 616         if (!(ch->ch_c_cflag & PARODD))
 617                 lcr |= UART_LCR_EPAR;
 618
 619         /*
 620          * Not all platforms support mark/space parity,
 621          * so this will hide behind an ifdef.
 622          */
 623 #ifdef CMSPAR
 624         if (ch->ch_c_cflag & CMSPAR)
 625                 lcr |= UART_LCR_SPAR;
 626 #endif
 627
 628         if (ch->ch_c_cflag & CSTOPB)
 629                 lcr |= UART_LCR_STOP;
 630
 631         switch (ch->ch_c_cflag & CSIZE) {
 632         case CS5:
 633                 lcr |= UART_LCR_WLEN5;
 634                 break;
 635         case CS6:
 636                 lcr |= UART_LCR_WLEN6;
 637                 break;
 638         case CS7:
 639                 lcr |= UART_LCR_WLEN7;
 640                 break;
 641         case CS8:
 642         default:
 643                 lcr |= UART_LCR_WLEN8;
 644                 break;
 645         }
 646
 647         ier = uart_ier = readb(&ch->ch_cls_uart->ier);
 648         uart_lcr = readb(&ch->ch_cls_uart->lcr);
 649
 650         if (baud == 0)
 651                 baud = 9600;
 652
 653         quot = ch->ch_bd->bd_dividend / baud;
 654
 655         if (quot != 0 && ch->ch_old_baud != baud) {
 656                 ch->ch_old_baud = baud;
 657                 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
 658                 writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
 659                 writeb((quot >> 8), &ch->ch_cls_uart->ier);
 660                 writeb(lcr, &ch->ch_cls_uart->lcr);
 661         }
 662
 663         if (uart_lcr != lcr)
 664                 writeb(lcr, &ch->ch_cls_uart->lcr);
 665
 666         if (ch->ch_c_cflag & CREAD)
 667                 ier |= (UART_IER_RDI | UART_IER_RLSI);
 668         else
 669                 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
 670
 671         /*
 672          * Have the UART interrupt on modem signal changes ONLY when
 673          * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
 674          */
 675         if ((ch->ch_digi.digi_flags & CTSPACE) ||
 676                 (ch->ch_digi.digi_flags & RTSPACE) ||
 677                 (ch->ch_c_cflag & CRTSCTS) ||
 678                 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
 679                 !(ch->ch_c_cflag & CLOCAL))
 680                         ier |= UART_IER_MSI;
 681         else
 682                         ier &= ~UART_IER_MSI;
 683
 684         ier |= UART_IER_THRI;
 685
 686         if (ier != uart_ier)
 687                 writeb(ier, &ch->ch_cls_uart->ier);
 688
 689         if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
 690                 cls_set_cts_flow_control(ch);
 691         } else if (ch->ch_c_iflag & IXON) {
 692                 /*
 693                  * If start/stop is set to disable, then we should
 694                  * disable flow control
 695                  */
 696                 if ((ch->ch_startc == _POSIX_VDISABLE) ||
 697                                          (ch->ch_stopc == _POSIX_VDISABLE))
 698                         cls_set_no_output_flow_control(ch);
 699                 else
 700                         cls_set_ixon_flow_control(ch);
 701         } else {
 702                 cls_set_no_output_flow_control(ch);
 703         }
 704
 705         if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
 706                 cls_set_rts_flow_control(ch);
 707         } else if (ch->ch_c_iflag & IXOFF) {
 708                 /*
 709                  * If start/stop is set to disable, then we should disable
 710                  * flow control
 711                  */
 712                 if ((ch->ch_startc == _POSIX_VDISABLE) ||
 713                                 (ch->ch_stopc == _POSIX_VDISABLE))
 714                         cls_set_no_input_flow_control(ch);
 715                 else
 716                         cls_set_ixoff_flow_control(ch);
 717         } else {
 718                 cls_set_no_input_flow_control(ch);
 719         }
 720
 721         cls_assert_modem_signals(ch);
 722
 723         /* Get current status of the modem signals now */
 724         cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
 725 }
 726
 727
 728 /*
 729  * Our board poller function.
 730  */
 731 static void cls_tasklet(unsigned long data)
 732 {
 733         struct dgnc_board *bd = (struct dgnc_board *) data;
 734         struct channel_t *ch;
 735         ulong  lock_flags;
 736         int i;
 737         int state = 0;
 738         int ports = 0;
 739
 740         if (!bd || bd->magic != DGNC_BOARD_MAGIC) {
 741                 APR(("poll_tasklet() - NULL or bad bd.\n"));
 742                 return;
 743         }
 744
 745         /* Cache a couple board values */
 746         DGNC_LOCK(bd->bd_lock, lock_flags);
 747         state = bd->state;
 748         ports = bd->nasync;
 749         DGNC_UNLOCK(bd->bd_lock, lock_flags);
 750
 751         /*
 752          * Do NOT allow the interrupt routine to read the intr registers
 753          * Until we release this lock.
 754          */
 755         DGNC_LOCK(bd->bd_intr_lock, lock_flags);
 756
 757         /*
 758          * If board is ready, parse deeper to see if there is anything to do.
 759          */
 760         if ((state == BOARD_READY) && (ports > 0)) {
 761
 762                 /* Loop on each port */
 763                 for (i = 0; i < ports; i++) {
 764                         ch = bd->channels[i];
 765                         if (!ch)
 766                                 continue;
 767
 768                         /*
 769                          * NOTE: Remember you CANNOT hold any channel
 770                          * locks when calling input.
 771                          * During input processing, its possible we
 772                          * will call ld, which might do callbacks back
 773                          * into us.
 774                          */
 775                         dgnc_input(ch);
 776
 777                         /*
 778                          * Channel lock is grabbed and then released
 779                          * inside this routine.
 780                          */
 781                         cls_copy_data_from_queue_to_uart(ch);
 782                         dgnc_wakeup_writes(ch);
 783
 784                         /*
 785                          * Check carrier function.
 786                          */
 787                         dgnc_carrier(ch);
 788
 789                         /*
 790                          * The timing check of turning off the break is done
 791                          * inside clear_break()
 792                          */
 793                         if (ch->ch_stop_sending_break)
 794                                 cls_clear_break(ch, 0);
 795                 }
 796         }
 797
 798         DGNC_UNLOCK(bd->bd_intr_lock, lock_flags);
 799
 800 }
 801
 802
 803 /*
 804  * cls_intr()
 805  *
 806  * Classic specific interrupt handler.
 807  */
 808 static irqreturn_t cls_intr(int irq, void *voidbrd)
 809 {
 810         struct dgnc_board *brd = (struct dgnc_board *) voidbrd;
 811         uint i = 0;
 812         uchar poll_reg;
 813         unsigned long lock_flags;
 814
 815         if (!brd) {
 816                 APR(("Received interrupt (%d) with null board associated\n",
 817                                                                          irq));
 818                 return IRQ_NONE;
 819         }
 820
 821         /*
 822          * Check to make sure its for us.
 823          */
 824         if (brd->magic != DGNC_BOARD_MAGIC) {
 825                 APR(("Received interrupt (%d) with a board pointer that wasn't ours!\n",
 826                           irq));
 827                 return IRQ_NONE;
 828         }
 829
 830         DGNC_LOCK(brd->bd_intr_lock, lock_flags);
 831
 832         brd->intr_count++;
 833
 834         /*
 835          * Check the board's global interrupt offset to see if we
 836          * we actually do have an interrupt pending for us.
 837          */
 838         poll_reg = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);
 839
 840         /* If 0, no interrupts pending */
 841         if (!poll_reg) {
 842                 DPR_INTR((
 843                          "Kernel interrupted to me, but no pending interrupts...\n"));
 844                 DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
 845                 return IRQ_NONE;
 846         }
 847
 848         DPR_INTR(("%s:%d poll_reg: %x\n", __FILE__, __LINE__, poll_reg));
 849
 850         /* Parse each port to find out what caused the interrupt */
 851         for (i = 0; i < brd->nasync; i++)
 852                 cls_parse_isr(brd, i);
 853
 854         /*
 855          * Schedule tasklet to more in-depth servicing at a better time.
 856          */
 857         tasklet_schedule(&brd->helper_tasklet);
 858
 859         DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
 860
 861         DPR_INTR(("dgnc_intr finish.\n"));
 862         return IRQ_HANDLED;
 863 }
 864
 865
 866 static void cls_disable_receiver(struct channel_t *ch)
 867 {
 868         uchar tmp = readb(&ch->ch_cls_uart->ier);
 869         tmp &= ~(UART_IER_RDI);
 870         writeb(tmp, &ch->ch_cls_uart->ier);
 871 }
 872
 873
 874 static void cls_enable_receiver(struct channel_t *ch)
 875 {
 876         uchar tmp = readb(&ch->ch_cls_uart->ier);
 877         tmp |= (UART_IER_RDI);
 878         writeb(tmp, &ch->ch_cls_uart->ier);
 879 }
 880
 881
 882 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch)
 883 {
 884         int qleft = 0;
 885         uchar linestatus = 0;
 886         uchar error_mask = 0;
 887         ushort head;
 888         ushort tail;
 889         ulong lock_flags;
 890
 891         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 892                 return;
 893
 894         DGNC_LOCK(ch->ch_lock, lock_flags);
 895
 896         /* cache head and tail of queue */
 897         head = ch->ch_r_head;
 898         tail = ch->ch_r_tail;
 899
 900         /* Store how much space we have left in the queue */
 901         qleft = (tail - head - 1);
 902         if (qleft < 0)
 903                 qleft += RQUEUEMASK + 1;
 904
 905         /*
 906          * Create a mask to determine whether we should
 907          * insert the character (if any) into our queue.
 908          */
 909         if (ch->ch_c_iflag & IGNBRK)
 910                 error_mask |= UART_LSR_BI;
 911
 912         while (1) {
 913                 linestatus = readb(&ch->ch_cls_uart->lsr);
 914
 915                 if (!(linestatus & (UART_LSR_DR)))
 916                         break;
 917
 918                 /*
 919                  * Discard character if we are ignoring the error mask.
 920                 */
 921                 if (linestatus & error_mask)  {
 922                         uchar discard;
 923                         linestatus = 0;
 924                         discard = readb(&ch->ch_cls_uart->txrx);
 925                         continue;
 926                 }
 927
 928                 /*
 929                  * If our queue is full, we have no choice but to drop some
 930                  * data. The assumption is that HWFLOW or SWFLOW should have
 931                  * stopped things way way before we got to this point.
 932                  *
 933                  * I decided that I wanted to ditch the oldest data first,
 934                  * I hope thats okay with everyone? Yes? Good.
 935                  */
 936                 while (qleft < 1) {
 937                         DPR_READ(("Queue full, dropping DATA:%x LSR:%x\n",
 938                                 ch->ch_rqueue[tail], ch->ch_equeue[tail]));
 939
 940                         ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
 941                         ch->ch_err_overrun++;
 942                         qleft++;
 943                 }
 944
 945                 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
 946                                                                  | UART_LSR_FE);
 947                 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
 948                 dgnc_sniff_nowait_nolock(ch, "UART READ",
 949                                                  ch->ch_rqueue + head, 1);
 950
 951                 qleft--;
 952
 953                 DPR_READ(("DATA/LSR pair: %x %x\n", ch->ch_rqueue[head],
 954                                                          ch->ch_equeue[head]));
 955
 956                 if (ch->ch_equeue[head] & UART_LSR_PE)
 957                         ch->ch_err_parity++;
 958                 if (ch->ch_equeue[head] & UART_LSR_BI)
 959                         ch->ch_err_break++;
 960                 if (ch->ch_equeue[head] & UART_LSR_FE)
 961                         ch->ch_err_frame++;
 962
 963                 /* Add to, and flip head if needed */
 964                 head = (head + 1) & RQUEUEMASK;
 965                 ch->ch_rxcount++;
 966         }
 967
 968         /*
 969          * Write new final heads to channel structure.
 970          */
 971         ch->ch_r_head = head & RQUEUEMASK;
 972         ch->ch_e_head = head & EQUEUEMASK;
 973
 974         DGNC_UNLOCK(ch->ch_lock, lock_flags);
 975 }
 976
 977
 978 /*
 979  * This function basically goes to sleep for secs, or until
 980  * it gets signalled that the port has fully drained.
 981  */
 982 static int cls_drain(struct tty_struct *tty, uint seconds)
 983 {
 984         ulong lock_flags;
 985         struct channel_t *ch;
 986         struct un_t *un;
 987         int rc = 0;
 988
 989         if (!tty || tty->magic != TTY_MAGIC)
 990                 return -ENXIO;
 991
 992         un = (struct un_t *) tty->driver_data;
 993         if (!un || un->magic != DGNC_UNIT_MAGIC)
 994                 return -ENXIO;
 995
 996         ch = un->un_ch;
 997         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 998                 return -ENXIO;
 999
1000         DGNC_LOCK(ch->ch_lock, lock_flags);
1001         un->un_flags |= UN_EMPTY;
1002         DGNC_UNLOCK(ch->ch_lock, lock_flags);
1003
1004         /*
1005          * NOTE: Do something with time passed in.
1006          */
1007         rc = wait_event_interruptible(un->un_flags_wait,
1008                                          ((un->un_flags & UN_EMPTY) == 0));
1009
1010         /* If ret is non-zero, user ctrl-c'ed us */
1011         if (rc)
1012                 DPR_IOCTL(("%d Drain - User ctrl c'ed\n", __LINE__));
1013
1014         return rc;
1015 }
1016
1017
1018 /* Channel lock MUST be held before calling this function! */
1019 static void cls_flush_uart_write(struct channel_t *ch)
1020 {
1021         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1022                 return;
1023
1024         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
1025                                                 &ch->ch_cls_uart->isr_fcr);
1026         udelay(10);
1027
1028         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1029 }
1030
1031
1032 /* Channel lock MUST be held before calling this function! */
1033 static void cls_flush_uart_read(struct channel_t *ch)
1034 {
1035         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1036                 return;
1037
1038         /*
1039          * For complete POSIX compatibility, we should be purging the
1040          * read FIFO in the UART here.
1041          *
1042          * However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also
1043          * incorrectly flushes write data as well as just basically trashing the
1044          * FIFO.
1045          *
1046          * Presumably, this is a bug in this UART.
1047          */
1048
1049         udelay(10);
1050 }
1051
1052
1053 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch)
1054 {
1055         ushort head;
1056         ushort tail;
1057         int n;
1058         int qlen;
1059         uint len_written = 0;
1060         ulong lock_flags;
1061
1062         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1063                 return;
1064
1065         DGNC_LOCK(ch->ch_lock, lock_flags);
1066
1067         /* No data to write to the UART */
1068         if (ch->ch_w_tail == ch->ch_w_head) {
1069                 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1070                 return;
1071         }
1072
1073         /* If port is "stopped", don't send any data to the UART */
1074         if ((ch->ch_flags & CH_FORCED_STOP) ||
1075                                  (ch->ch_flags & CH_BREAK_SENDING)) {
1076                 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1077                 return;
1078         }
1079
1080         if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) {
1081                 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1082                 return;
1083         }
1084
1085         n = 32;
1086
1087         /* cache head and tail of queue */
1088         head = ch->ch_w_head & WQUEUEMASK;
1089         tail = ch->ch_w_tail & WQUEUEMASK;
1090         qlen = (head - tail) & WQUEUEMASK;
1091
1092         /* Find minimum of the FIFO space, versus queue length */
1093         n = min(n, qlen);
1094
1095         while (n > 0) {
1096
1097                 /*
1098                  * If RTS Toggle mode is on, turn on RTS now if not already set,
1099                  * and make sure we get an event when the data transfer has
1100                  * completed.
1101                  */
1102                 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1103                         if (!(ch->ch_mostat & UART_MCR_RTS)) {
1104                                 ch->ch_mostat |= (UART_MCR_RTS);
1105                                 cls_assert_modem_signals(ch);
1106                         }
1107                         ch->ch_tun.un_flags |= (UN_EMPTY);
1108                 }
1109
1110                 /*
1111                  * If DTR Toggle mode is on, turn on DTR now if not already set,
1112                  * and make sure we get an event when the data transfer has
1113                  * completed.
1114                  */
1115                 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1116                         if (!(ch->ch_mostat & UART_MCR_DTR)) {
1117                                 ch->ch_mostat |= (UART_MCR_DTR);
1118                                 cls_assert_modem_signals(ch);
1119                         }
1120                         ch->ch_tun.un_flags |= (UN_EMPTY);
1121                 }
1122                 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_cls_uart->txrx);
1123                 dgnc_sniff_nowait_nolock(ch, "UART WRITE",
1124                                             ch->ch_wqueue + ch->ch_w_tail, 1);
1125                 DPR_WRITE(("Tx data: %x\n", ch->ch_wqueue[ch->ch_w_tail]));
1126                 ch->ch_w_tail++;
1127                 ch->ch_w_tail &= WQUEUEMASK;
1128                 ch->ch_txcount++;
1129                 len_written++;
1130                 n--;
1131         }
1132
1133         if (len_written > 0)
1134                 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1135
1136         DGNC_UNLOCK(ch->ch_lock, lock_flags);
1137
1138         return;
1139 }
1140
1141
1142 static void cls_parse_modem(struct channel_t *ch, uchar signals)
1143 {
1144         uchar msignals = signals;
1145         ulong lock_flags;
1146
1147         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1148                 return;
1149
1150         DPR_MSIGS(("cls_parse_modem: port: %d signals: %d\n",
1151                                          ch->ch_portnum, msignals));
1152
1153         /*
1154          * Do altpin switching. Altpin switches DCD and DSR.
1155          * This prolly breaks DSRPACE, so we should be more clever here.
1156          */
1157         DGNC_LOCK(ch->ch_lock, lock_flags);
1158         if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1159                 uchar mswap = signals;
1160                 if (mswap & UART_MSR_DDCD) {
1161                         msignals &= ~UART_MSR_DDCD;
1162                         msignals |= UART_MSR_DDSR;
1163                 }
1164                 if (mswap & UART_MSR_DDSR) {
1165                         msignals &= ~UART_MSR_DDSR;
1166                         msignals |= UART_MSR_DDCD;
1167                 }
1168                 if (mswap & UART_MSR_DCD) {
1169                         msignals &= ~UART_MSR_DCD;
1170                         msignals |= UART_MSR_DSR;
1171                 }
1172                 if (mswap & UART_MSR_DSR) {
1173                         msignals &= ~UART_MSR_DSR;
1174                         msignals |= UART_MSR_DCD;
1175                 }
1176         }
1177         DGNC_UNLOCK(ch->ch_lock, lock_flags);
1178
1179         /*
1180          * Scrub off lower bits. They signify delta's, which I don't
1181          * care about
1182          */
1183         signals &= 0xf0;
1184
1185         DGNC_LOCK(ch->ch_lock, lock_flags);
1186         if (msignals & UART_MSR_DCD)
1187                 ch->ch_mistat |= UART_MSR_DCD;
1188         else
1189                 ch->ch_mistat &= ~UART_MSR_DCD;
1190
1191         if (msignals & UART_MSR_DSR)
1192                 ch->ch_mistat |= UART_MSR_DSR;
1193         else
1194                 ch->ch_mistat &= ~UART_MSR_DSR;
1195
1196         if (msignals & UART_MSR_RI)
1197                 ch->ch_mistat |= UART_MSR_RI;
1198         else
1199                 ch->ch_mistat &= ~UART_MSR_RI;
1200
1201         if (msignals & UART_MSR_CTS)
1202                 ch->ch_mistat |= UART_MSR_CTS;
1203         else
1204                 ch->ch_mistat &= ~UART_MSR_CTS;
1205         DGNC_UNLOCK(ch->ch_lock, lock_flags);
1206
1207
1208         DPR_MSIGS((
1209                 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
1210                 ch->ch_portnum,
1211                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
1212                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
1213                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
1214                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
1215                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
1216                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)));
1217 }
1218
1219
1220 /* Make the UART raise any of the output signals we want up */
1221 static void cls_assert_modem_signals(struct channel_t *ch)
1222 {
1223         uchar out;
1224
1225         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1226                 return;
1227
1228         out = ch->ch_mostat;
1229
1230         if (ch->ch_flags & CH_LOOPBACK)
1231                 out |= UART_MCR_LOOP;
1232
1233         writeb(out, &ch->ch_cls_uart->mcr);
1234
1235         /* Give time for the UART to actually drop the signals */
1236         udelay(10);
1237 }
1238
1239
1240 static void cls_send_start_character(struct channel_t *ch)
1241 {
1242         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1243                 return;
1244
1245         if (ch->ch_startc != _POSIX_VDISABLE) {
1246                 ch->ch_xon_sends++;
1247                 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
1248         }
1249 }
1250
1251
1252 static void cls_send_stop_character(struct channel_t *ch)
1253 {
1254         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1255                 return;
1256
1257         if (ch->ch_stopc != _POSIX_VDISABLE) {
1258                 ch->ch_xoff_sends++;
1259                 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
1260         }
1261 }
1262
1263
1264 /* Inits UART */
1265 static void cls_uart_init(struct channel_t *ch)
1266 {
1267         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
1268         uchar isr_fcr = 0;
1269
1270         writeb(0, &ch->ch_cls_uart->ier);
1271
1272         /*
1273          * The Enhanced Register Set may only be accessed when
1274          * the Line Control Register is set to 0xBFh.
1275          */
1276         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
1277
1278         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
1279
1280         /* Turn on Enhanced/Extended controls */
1281         isr_fcr |= (UART_EXAR654_EFR_ECB);
1282
1283         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
1284
1285         /* Write old LCR value back out, which turns enhanced access off */
1286         writeb(lcrb, &ch->ch_cls_uart->lcr);
1287
1288         /* Clear out UART and FIFO */
1289         readb(&ch->ch_cls_uart->txrx);
1290
1291         writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT),
1292                                                  &ch->ch_cls_uart->isr_fcr);
1293         udelay(10);
1294
1295         ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1296
1297         readb(&ch->ch_cls_uart->lsr);
1298         readb(&ch->ch_cls_uart->msr);
1299 }
1300
1301
1302 /*
1303  * Turns off UART.
1304  */
1305 static void cls_uart_off(struct channel_t *ch)
1306 {
1307         writeb(0, &ch->ch_cls_uart->ier);
1308 }
1309
1310
1311 /*
1312  * cls_get_uarts_bytes_left.
1313  * Returns 0 is nothing left in the FIFO, returns 1 otherwise.
1314  *
1315  * The channel lock MUST be held by the calling function.
1316  */
1317 static uint cls_get_uart_bytes_left(struct channel_t *ch)
1318 {
1319         uchar left = 0;
1320         uchar lsr = 0;
1321
1322         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1323                 return 0;
1324
1325         lsr = readb(&ch->ch_cls_uart->lsr);
1326
1327         /* Determine whether the Transmitter is empty or not */
1328         if (!(lsr & UART_LSR_TEMT)) {
1329                 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1330                         tasklet_schedule(&ch->ch_bd->helper_tasklet);
1331                 left = 1;
1332         } else {
1333                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1334                 left = 0;
1335         }
1336
1337         return left;
1338 }
1339
1340
1341 /*
1342  * cls_send_break.
1343  * Starts sending a break thru the UART.
1344  *
1345  * The channel lock MUST be held by the calling function.
1346  */
1347 static void cls_send_break(struct channel_t *ch, int msecs)
1348 {
1349         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1350                 return;
1351
1352         /*
1353          * If we receive a time of 0, this means turn off the break.
1354          */
1355         if (msecs == 0) {
1356                 /* Turn break off, and unset some variables */
1357                 if (ch->ch_flags & CH_BREAK_SENDING) {
1358                         uchar temp = readb(&ch->ch_cls_uart->lcr);
1359                         writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1360                         ch->ch_flags &= ~(CH_BREAK_SENDING);
1361                         ch->ch_stop_sending_break = 0;
1362                         DPR_IOCTL(("Finishing UART_LCR_SBC! finished: %lx\n",
1363                                                                      jiffies));
1364                 }
1365                 return;
1366         }
1367
1368         /*
1369          * Set the time we should stop sending the break.
1370          * If we are already sending a break, toss away the existing
1371          * time to stop, and use this new value instead.
1372          */
1373         ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1374
1375         /* Tell the UART to start sending the break */
1376         if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1377                 uchar temp = readb(&ch->ch_cls_uart->lcr);
1378                 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1379                 ch->ch_flags |= (CH_BREAK_SENDING);
1380                 DPR_IOCTL((
1381                         "Port %d. Starting UART_LCR_SBC! start: %lx should end: %lx\n",
1382                         ch->ch_portnum, jiffies, ch->ch_stop_sending_break));
1383         }
1384 }
1385
1386
1387 /*
1388  * cls_send_immediate_char.
1389  * Sends a specific character as soon as possible to the UART,
1390  * jumping over any bytes that might be in the write queue.
1391  *
1392  * The channel lock MUST be held by the calling function.
1393  */
1394 static void cls_send_immediate_char(struct channel_t *ch, unsigned char c)
1395 {
1396         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1397                 return;
1398
1399         writeb(c, &ch->ch_cls_uart->txrx);
1400 }
1401
1402 static void cls_vpd(struct dgnc_board *brd)
1403 {
1404         ulong           vpdbase;        /* Start of io base of the card */
1405         u8 __iomem           *re_map_vpdbase;/* Remapped memory of the card */
1406         int i = 0;
1407
1408
1409         vpdbase = pci_resource_start(brd->pdev, 3);
1410
1411         /* No VPD */
1412         if (!vpdbase)
1413                 return;
1414
1415         re_map_vpdbase = ioremap(vpdbase, 0x400);
1416
1417         if (!re_map_vpdbase)
1418                 return;
1419
1420         /* Store the VPD into our buffer */
1421         for (i = 0; i < 0x40; i++) {
1422                 brd->vpd[i] = readb(re_map_vpdbase + i);
1423                 pr_info("%x ", brd->vpd[i]);
1424         }
1425         pr_info("\n");
1426
1427         if (re_map_vpdbase)
1428                 iounmap(re_map_vpdbase);
1429 }
1430