drivers/staging/dgnc/dgnc_cls.c

   1 /*
   2  * Copyright 2003 Digi International (www.digi.com)
   3  *      Scott H Kilau <Scott_Kilau at digi dot com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2, or (at your option)
   8  * any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
  12  * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
  13  * PURPOSE.  See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  *
  20  *      NOTE TO LINUX KERNEL HACKERS:  DO NOT REFORMAT THIS CODE!
  21  *
  22  *      This is shared code between Digi's CVS archive and the
  23  *      Linux Kernel sources.
  24  *      Changing the source just for reformatting needlessly breaks
  25  *      our CVS diff history.
  26  *
  27  *      Send any bug fixes/changes to:  Eng.Linux at digi dot com.
  28  *      Thank you.
  29  *
  30  */
  31
  32 #include <linux/kernel.h>
  33 #include <linux/sched.h>        /* For jiffies, task states */
  34 #include <linux/interrupt.h>    /* For tasklet and interrupt structs/defines */
  35 #include <linux/delay.h>        /* For udelay */
  36 #include <linux/io.h>           /* For read[bwl]/write[bwl] */
  37 #include <linux/serial.h>       /* For struct async_serial */
  38 #include <linux/serial_reg.h>   /* For the various UART offsets */
  39 #include <linux/pci.h>
  40
  41 #include "dgnc_driver.h"        /* Driver main header file */
  42 #include "dgnc_cls.h"
  43 #include "dgnc_tty.h"
  44 #include "dgnc_trace.h"
  45
  46 static inline void cls_parse_isr(struct dgnc_board *brd, uint port);
  47 static inline void cls_clear_break(struct channel_t *ch, int force);
  48 static inline void cls_set_cts_flow_control(struct channel_t *ch);
  49 static inline void cls_set_rts_flow_control(struct channel_t *ch);
  50 static inline void cls_set_ixon_flow_control(struct channel_t *ch);
  51 static inline void cls_set_ixoff_flow_control(struct channel_t *ch);
  52 static inline void cls_set_no_output_flow_control(struct channel_t *ch);
  53 static inline void cls_set_no_input_flow_control(struct channel_t *ch);
  54 static void cls_parse_modem(struct channel_t *ch, uchar signals);
  55 static void cls_tasklet(unsigned long data);
  56 static void cls_vpd(struct dgnc_board *brd);
  57 static void cls_uart_init(struct channel_t *ch);
  58 static void cls_uart_off(struct channel_t *ch);
  59 static int cls_drain(struct tty_struct *tty, uint seconds);
  60 static void cls_param(struct tty_struct *tty);
  61 static void cls_assert_modem_signals(struct channel_t *ch);
  62 static void cls_flush_uart_write(struct channel_t *ch);
  63 static void cls_flush_uart_read(struct channel_t *ch);
  64 static void cls_disable_receiver(struct channel_t *ch);
  65 static void cls_enable_receiver(struct channel_t *ch);
  66 static void cls_send_break(struct channel_t *ch, int msecs);
  67 static void cls_send_start_character(struct channel_t *ch);
  68 static void cls_send_stop_character(struct channel_t *ch);
  69 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch);
  70 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch);
  71 static uint cls_get_uart_bytes_left(struct channel_t *ch);
  72 static void cls_send_immediate_char(struct channel_t *ch, unsigned char);
  73 static irqreturn_t cls_intr(int irq, void *voidbrd);
  74
  75 struct board_ops dgnc_cls_ops = {
  76         .tasklet =                      cls_tasklet,
  77         .intr =                         cls_intr,
  78         .uart_init =                    cls_uart_init,
  79         .uart_off =                     cls_uart_off,
  80         .drain =                        cls_drain,
  81         .param =                        cls_param,
  82         .vpd =                          cls_vpd,
  83         .assert_modem_signals =         cls_assert_modem_signals,
  84         .flush_uart_write =             cls_flush_uart_write,
  85         .flush_uart_read =              cls_flush_uart_read,
  86         .disable_receiver =             cls_disable_receiver,
  87         .enable_receiver =              cls_enable_receiver,
  88         .send_break =                   cls_send_break,
  89         .send_start_character =         cls_send_start_character,
  90         .send_stop_character =          cls_send_stop_character,
  91         .copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
  92         .get_uart_bytes_left =          cls_get_uart_bytes_left,
  93         .send_immediate_char =          cls_send_immediate_char
  94 };
  95
  96
  97 static inline void cls_set_cts_flow_control(struct channel_t *ch)
  98 {
  99         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 100         uchar ier = readb(&ch->ch_cls_uart->ier);
 101         uchar isr_fcr = 0;
 102
 103         DPR_PARAM(("Setting CTSFLOW\n"));
 104
 105         /*
 106          * The Enhanced Register Set may only be accessed when
 107          * the Line Control Register is set to 0xBFh.
 108          */
 109         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 110
 111         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 112
 113         /* Turn on CTS flow control, turn off IXON flow control */
 114         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR);
 115         isr_fcr &= ~(UART_EXAR654_EFR_IXON);
 116
 117         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 118
 119         /* Write old LCR value back out, which turns enhanced access off */
 120         writeb(lcrb, &ch->ch_cls_uart->lcr);
 121
 122         /*
 123          * Enable interrupts for CTS flow, turn off interrupts for
 124          * received XOFF chars
 125          */
 126         ier |= (UART_EXAR654_IER_CTSDSR);
 127         ier &= ~(UART_EXAR654_IER_XOFF);
 128         writeb(ier, &ch->ch_cls_uart->ier);
 129
 130         /* Set the usual FIFO values */
 131         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 132
 133         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
 134                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 135                 &ch->ch_cls_uart->isr_fcr);
 136
 137         ch->ch_t_tlevel = 16;
 138
 139 }
 140
 141
 142 static inline void cls_set_ixon_flow_control(struct channel_t *ch)
 143 {
 144         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 145         uchar ier = readb(&ch->ch_cls_uart->ier);
 146         uchar isr_fcr = 0;
 147
 148         DPR_PARAM(("Setting IXON FLOW\n"));
 149
 150         /*
 151          * The Enhanced Register Set may only be accessed when
 152          * the Line Control Register is set to 0xBFh.
 153          */
 154         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 155
 156         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 157
 158         /* Turn on IXON flow control, turn off CTS flow control */
 159         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON);
 160         isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR);
 161
 162         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 163
 164         /* Now set our current start/stop chars while in enhanced mode */
 165         writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
 166         writeb(0, &ch->ch_cls_uart->lsr);
 167         writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
 168         writeb(0, &ch->ch_cls_uart->spr);
 169
 170         /* Write old LCR value back out, which turns enhanced access off */
 171         writeb(lcrb, &ch->ch_cls_uart->lcr);
 172
 173         /*
 174          * Disable interrupts for CTS flow, turn on interrupts for
 175          * received XOFF chars
 176          */
 177         ier &= ~(UART_EXAR654_IER_CTSDSR);
 178         ier |= (UART_EXAR654_IER_XOFF);
 179         writeb(ier, &ch->ch_cls_uart->ier);
 180
 181         /* Set the usual FIFO values */
 182         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 183
 184         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 185                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 186                 &ch->ch_cls_uart->isr_fcr);
 187
 188 }
 189
 190
 191 static inline void cls_set_no_output_flow_control(struct channel_t *ch)
 192 {
 193         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 194         uchar ier = readb(&ch->ch_cls_uart->ier);
 195         uchar isr_fcr = 0;
 196
 197         DPR_PARAM(("Unsetting Output FLOW\n"));
 198
 199         /*
 200          * The Enhanced Register Set may only be accessed when
 201          * the Line Control Register is set to 0xBFh.
 202          */
 203         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 204
 205         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 206
 207         /* Turn off IXON flow control, turn off CTS flow control */
 208         isr_fcr |= (UART_EXAR654_EFR_ECB);
 209         isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON);
 210
 211         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 212
 213         /* Write old LCR value back out, which turns enhanced access off */
 214         writeb(lcrb, &ch->ch_cls_uart->lcr);
 215
 216         /*
 217          * Disable interrupts for CTS flow, turn off interrupts for
 218          * received XOFF chars
 219          */
 220         ier &= ~(UART_EXAR654_IER_CTSDSR);
 221         ier &= ~(UART_EXAR654_IER_XOFF);
 222         writeb(ier, &ch->ch_cls_uart->ier);
 223
 224         /* Set the usual FIFO values */
 225         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 226
 227         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 228                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 229                 &ch->ch_cls_uart->isr_fcr);
 230
 231         ch->ch_r_watermark = 0;
 232         ch->ch_t_tlevel = 16;
 233         ch->ch_r_tlevel = 16;
 234
 235 }
 236
 237
 238 static inline void cls_set_rts_flow_control(struct channel_t *ch)
 239 {
 240         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 241         uchar ier = readb(&ch->ch_cls_uart->ier);
 242         uchar isr_fcr = 0;
 243
 244         DPR_PARAM(("Setting RTSFLOW\n"));
 245
 246         /*
 247          * The Enhanced Register Set may only be accessed when
 248          * the Line Control Register is set to 0xBFh.
 249          */
 250         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 251
 252         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 253
 254         /* Turn on RTS flow control, turn off IXOFF flow control */
 255         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR);
 256         isr_fcr &= ~(UART_EXAR654_EFR_IXOFF);
 257
 258         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 259
 260         /* Write old LCR value back out, which turns enhanced access off */
 261         writeb(lcrb, &ch->ch_cls_uart->lcr);
 262
 263         /* Enable interrupts for RTS flow */
 264         ier |= (UART_EXAR654_IER_RTSDTR);
 265         writeb(ier, &ch->ch_cls_uart->ier);
 266
 267         /* Set the usual FIFO values */
 268         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 269
 270         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
 271                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 272                 &ch->ch_cls_uart->isr_fcr);
 273
 274
 275         ch->ch_r_watermark = 4;
 276         ch->ch_r_tlevel = 8;
 277
 278 }
 279
 280
 281 static inline void cls_set_ixoff_flow_control(struct channel_t *ch)
 282 {
 283         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 284         uchar ier = readb(&ch->ch_cls_uart->ier);
 285         uchar isr_fcr = 0;
 286
 287         DPR_PARAM(("Setting IXOFF FLOW\n"));
 288
 289         /*
 290          * The Enhanced Register Set may only be accessed when
 291          * the Line Control Register is set to 0xBFh.
 292          */
 293         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 294
 295         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 296
 297         /* Turn on IXOFF flow control, turn off RTS flow control */
 298         isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF);
 299         isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR);
 300
 301         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 302
 303         /* Now set our current start/stop chars while in enhanced mode */
 304         writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
 305         writeb(0, &ch->ch_cls_uart->lsr);
 306         writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
 307         writeb(0, &ch->ch_cls_uart->spr);
 308
 309         /* Write old LCR value back out, which turns enhanced access off */
 310         writeb(lcrb, &ch->ch_cls_uart->lcr);
 311
 312         /* Disable interrupts for RTS flow */
 313         ier &= ~(UART_EXAR654_IER_RTSDTR);
 314         writeb(ier, &ch->ch_cls_uart->ier);
 315
 316         /* Set the usual FIFO values */
 317         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 318
 319         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 320                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 321                 &ch->ch_cls_uart->isr_fcr);
 322
 323 }
 324
 325
 326 static inline void cls_set_no_input_flow_control(struct channel_t *ch)
 327 {
 328         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
 329         uchar ier = readb(&ch->ch_cls_uart->ier);
 330         uchar isr_fcr = 0;
 331
 332         DPR_PARAM(("Unsetting Input FLOW\n"));
 333
 334         /*
 335          * The Enhanced Register Set may only be accessed when
 336          * the Line Control Register is set to 0xBFh.
 337          */
 338         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
 339
 340         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
 341
 342         /* Turn off IXOFF flow control, turn off RTS flow control */
 343         isr_fcr |= (UART_EXAR654_EFR_ECB);
 344         isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF);
 345
 346         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
 347
 348         /* Write old LCR value back out, which turns enhanced access off */
 349         writeb(lcrb, &ch->ch_cls_uart->lcr);
 350
 351         /* Disable interrupts for RTS flow */
 352         ier &= ~(UART_EXAR654_IER_RTSDTR);
 353         writeb(ier, &ch->ch_cls_uart->ier);
 354
 355         /* Set the usual FIFO values */
 356         writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
 357
 358         writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
 359                 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
 360                 &ch->ch_cls_uart->isr_fcr);
 361
 362         ch->ch_t_tlevel = 16;
 363         ch->ch_r_tlevel = 16;
 364
 365 }
 366
 367
 368 /*
 369  * cls_clear_break.
 370  * Determines whether its time to shut off break condition.
 371  *
 372  * No locks are assumed to be held when calling this function.
 373  * channel lock is held and released in this function.
 374  */
 375 static inline void cls_clear_break(struct channel_t *ch, int force)
 376 {
 377         ulong lock_flags;
 378
 379         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 380                 return;
 381
 382         DGNC_LOCK(ch->ch_lock, lock_flags);
 383
 384         /* Bail if we aren't currently sending a break. */
 385         if (!ch->ch_stop_sending_break) {
 386                 DGNC_UNLOCK(ch->ch_lock, lock_flags);
 387                 return;
 388         }
 389
 390         /* Turn break off, and unset some variables */
 391         if (ch->ch_flags & CH_BREAK_SENDING) {
 392                 if (time_after(jiffies, ch->ch_stop_sending_break) || force) {
 393                         uchar temp = readb(&ch->ch_cls_uart->lcr);
 394                         writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
 395                         ch->ch_flags &= ~(CH_BREAK_SENDING);
 396                         ch->ch_stop_sending_break = 0;
 397                         DPR_IOCTL(("Finishing UART_LCR_SBC! finished: %lx\n",
 398                                                                 jiffies));
 399                 }
 400         }
 401         DGNC_UNLOCK(ch->ch_lock, lock_flags);
 402 }
 403
 404
 405 /* Parse the ISR register for the specific port */
 406 static inline void cls_parse_isr(struct dgnc_board *brd, uint port)
 407 {
 408         struct channel_t *ch;
 409         uchar isr = 0;
 410         ulong lock_flags;
 411
 412         /*
 413          * No need to verify board pointer, it was already
 414          * verified in the interrupt routine.
 415          */
 416
 417         if (port > brd->nasync)
 418                 return;
 419
 420         ch = brd->channels[port];
 421         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 422                 return;
 423
 424         /* Here we try to figure out what caused the interrupt to happen */
 425         while (1) {
 426
 427                 isr = readb(&ch->ch_cls_uart->isr_fcr);
 428
 429                 /* Bail if no pending interrupt on port */
 430                 if (isr & UART_IIR_NO_INT)
 431                         break;
 432
 433                 DPR_INTR(("%s:%d port: %x isr: %x\n", __FILE__, __LINE__,
 434                                                                  port, isr));
 435
 436                 /* Receive Interrupt pending */
 437                 if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) {
 438                         /* Read data from uart -> queue */
 439                         brd->intr_rx++;
 440                         ch->ch_intr_rx++;
 441                         cls_copy_data_from_uart_to_queue(ch);
 442                         dgnc_check_queue_flow_control(ch);
 443                 }
 444
 445                 /* Transmit Hold register empty pending */
 446                 if (isr & UART_IIR_THRI) {
 447                         /* Transfer data (if any) from Write Queue -> UART. */
 448                         DGNC_LOCK(ch->ch_lock, lock_flags);
 449                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 450                         brd->intr_tx++;
 451                         ch->ch_intr_tx++;
 452                         DGNC_UNLOCK(ch->ch_lock, lock_flags);
 453                         cls_copy_data_from_queue_to_uart(ch);
 454                 }
 455
 456                 /* CTS/RTS change of state */
 457                 if (isr & UART_IIR_CTSRTS) {
 458                         brd->intr_modem++;
 459                         ch->ch_intr_modem++;
 460                         /*
 461                          * Don't need to do anything, the cls_parse_modem
 462                          * below will grab the updated modem signals.
 463                          */
 464                 }
 465
 466                 /* Parse any modem signal changes */
 467                 DPR_INTR(("MOD_STAT: sending to parse_modem_sigs\n"));
 468                 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
 469         }
 470 }
 471
 472
 473 /*
 474  * cls_param()
 475  * Send any/all changes to the line to the UART.
 476  */
 477 static void cls_param(struct tty_struct *tty)
 478 {
 479         uchar lcr = 0;
 480         uchar uart_lcr = 0;
 481         uchar ier = 0;
 482         uchar uart_ier = 0;
 483         uint baud = 9600;
 484         int quot = 0;
 485         struct dgnc_board *bd;
 486         struct channel_t *ch;
 487         struct un_t   *un;
 488
 489         if (!tty || tty->magic != TTY_MAGIC)
 490                 return;
 491
 492         un = (struct un_t *) tty->driver_data;
 493         if (!un || un->magic != DGNC_UNIT_MAGIC)
 494                 return;
 495
 496         ch = un->un_ch;
 497         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 498                 return;
 499
 500         bd = ch->ch_bd;
 501         if (!bd || bd->magic != DGNC_BOARD_MAGIC)
 502                 return;
 503
 504         DPR_PARAM(("param start: tdev: %x cflags: %x oflags: %x iflags: %x\n",
 505                 ch->ch_tun.un_dev, ch->ch_c_cflag, ch->ch_c_oflag,
 506                                                          ch->ch_c_iflag));
 507
 508         /*
 509          * If baud rate is zero, flush queues, and set mval to drop DTR.
 510          */
 511         if ((ch->ch_c_cflag & (CBAUD)) == 0) {
 512                 ch->ch_r_head = ch->ch_r_tail = 0;
 513                 ch->ch_e_head = ch->ch_e_tail = 0;
 514                 ch->ch_w_head = ch->ch_w_tail = 0;
 515
 516                 cls_flush_uart_write(ch);
 517                 cls_flush_uart_read(ch);
 518
 519                 /* The baudrate is B0 so all modem lines are to be dropped. */
 520                 ch->ch_flags |= (CH_BAUD0);
 521                 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
 522                 cls_assert_modem_signals(ch);
 523                 ch->ch_old_baud = 0;
 524                 return;
 525         } else if (ch->ch_custom_speed) {
 526
 527                 baud = ch->ch_custom_speed;
 528                 /* Handle transition from B0 */
 529                 if (ch->ch_flags & CH_BAUD0) {
 530                         ch->ch_flags &= ~(CH_BAUD0);
 531
 532                         /*
 533                          * Bring back up RTS and DTR...
 534                          * Also handle RTS or DTR toggle if set.
 535                          */
 536                         if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
 537                                 ch->ch_mostat |= (UART_MCR_RTS);
 538                         if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
 539                                 ch->ch_mostat |= (UART_MCR_DTR);
 540                 }
 541
 542         } else {
 543                 int iindex = 0;
 544                 int jindex = 0;
 545
 546                 ulong bauds[4][16] = {
 547                         { /* slowbaud */
 548                                 0,      50,     75,     110,
 549                                 134,    150,    200,    300,
 550                                 600,    1200,   1800,   2400,
 551                                 4800,   9600,   19200,  38400 },
 552                         { /* slowbaud & CBAUDEX */
 553                                 0,      57600,  115200, 230400,
 554                                 460800, 150,    200,    921600,
 555                                 600,    1200,   1800,   2400,
 556                                 4800,   9600,   19200,  38400 },
 557                         { /* fastbaud */
 558                                 0,      57600,   76800, 115200,
 559                                 131657, 153600, 230400, 460800,
 560                                 921600, 1200,   1800,   2400,
 561                                 4800,   9600,   19200,  38400 },
 562                         { /* fastbaud & CBAUDEX */
 563                                 0,      57600,  115200, 230400,
 564                                 460800, 150,    200,    921600,
 565                                 600,    1200,   1800,   2400,
 566                                 4800,   9600,   19200,  38400 }
 567                 };
 568
 569                 /*
 570                  * Only use the TXPrint baud rate if the terminal
 571                  * unit is NOT open
 572                  */
 573                 if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
 574                                          (un->un_type == DGNC_PRINT))
 575                         baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
 576                 else
 577                         baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
 578
 579                 if (ch->ch_c_cflag & CBAUDEX)
 580                         iindex = 1;
 581
 582                 if (ch->ch_digi.digi_flags & DIGI_FAST)
 583                         iindex += 2;
 584
 585                 jindex = baud;
 586
 587                 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) &&
 588                                                                 (jindex < 16)) {
 589                         baud = bauds[iindex][jindex];
 590                 } else {
 591                         DPR_IOCTL(("baud indices were out of range (%d)(%d)",
 592                                 iindex, jindex));
 593                         baud = 0;
 594                 }
 595
 596                 if (baud == 0)
 597                         baud = 9600;
 598
 599                 /* Handle transition from B0 */
 600                 if (ch->ch_flags & CH_BAUD0) {
 601                         ch->ch_flags &= ~(CH_BAUD0);
 602
 603                         /*
 604                          * Bring back up RTS and DTR...
 605                          * Also handle RTS or DTR toggle if set.
 606                          */
 607                         if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
 608                                 ch->ch_mostat |= (UART_MCR_RTS);
 609                         if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
 610                                 ch->ch_mostat |= (UART_MCR_DTR);
 611                 }
 612         }
 613
 614         if (ch->ch_c_cflag & PARENB)
 615                 lcr |= UART_LCR_PARITY;
 616
 617         if (!(ch->ch_c_cflag & PARODD))
 618                 lcr |= UART_LCR_EPAR;
 619
 620         /*
 621          * Not all platforms support mark/space parity,
 622          * so this will hide behind an ifdef.
 623          */
 624 #ifdef CMSPAR
 625         if (ch->ch_c_cflag & CMSPAR)
 626                 lcr |= UART_LCR_SPAR;
 627 #endif
 628
 629         if (ch->ch_c_cflag & CSTOPB)
 630                 lcr |= UART_LCR_STOP;
 631
 632         switch (ch->ch_c_cflag & CSIZE) {
 633         case CS5:
 634                 lcr |= UART_LCR_WLEN5;
 635                 break;
 636         case CS6:
 637                 lcr |= UART_LCR_WLEN6;
 638                 break;
 639         case CS7:
 640                 lcr |= UART_LCR_WLEN7;
 641                 break;
 642         case CS8:
 643         default:
 644                 lcr |= UART_LCR_WLEN8;
 645                 break;
 646         }
 647
 648         ier = uart_ier = readb(&ch->ch_cls_uart->ier);
 649         uart_lcr = readb(&ch->ch_cls_uart->lcr);
 650
 651         if (baud == 0)
 652                 baud = 9600;
 653
 654         quot = ch->ch_bd->bd_dividend / baud;
 655
 656         if (quot != 0 && ch->ch_old_baud != baud) {
 657                 ch->ch_old_baud = baud;
 658                 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
 659                 writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
 660                 writeb((quot >> 8), &ch->ch_cls_uart->ier);
 661                 writeb(lcr, &ch->ch_cls_uart->lcr);
 662         }
 663
 664         if (uart_lcr != lcr)
 665                 writeb(lcr, &ch->ch_cls_uart->lcr);
 666
 667         if (ch->ch_c_cflag & CREAD)
 668                 ier |= (UART_IER_RDI | UART_IER_RLSI);
 669         else
 670                 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
 671
 672         /*
 673          * Have the UART interrupt on modem signal changes ONLY when
 674          * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
 675          */
 676         if ((ch->ch_digi.digi_flags & CTSPACE) ||
 677                 (ch->ch_digi.digi_flags & RTSPACE) ||
 678                 (ch->ch_c_cflag & CRTSCTS) ||
 679                 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
 680                 !(ch->ch_c_cflag & CLOCAL))
 681                         ier |= UART_IER_MSI;
 682         else
 683                         ier &= ~UART_IER_MSI;
 684
 685         ier |= UART_IER_THRI;
 686
 687         if (ier != uart_ier)
 688                 writeb(ier, &ch->ch_cls_uart->ier);
 689
 690         if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
 691                 cls_set_cts_flow_control(ch);
 692         } else if (ch->ch_c_iflag & IXON) {
 693                 /*
 694                  * If start/stop is set to disable, then we should
 695                  * disable flow control
 696                  */
 697                 if ((ch->ch_startc == _POSIX_VDISABLE) ||
 698                                          (ch->ch_stopc == _POSIX_VDISABLE))
 699                         cls_set_no_output_flow_control(ch);
 700                 else
 701                         cls_set_ixon_flow_control(ch);
 702         } else {
 703                 cls_set_no_output_flow_control(ch);
 704         }
 705
 706         if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
 707                 cls_set_rts_flow_control(ch);
 708         } else if (ch->ch_c_iflag & IXOFF) {
 709                 /*
 710                  * If start/stop is set to disable, then we should disable
 711                  * flow control
 712                  */
 713                 if ((ch->ch_startc == _POSIX_VDISABLE) ||
 714                                 (ch->ch_stopc == _POSIX_VDISABLE))
 715                         cls_set_no_input_flow_control(ch);
 716                 else
 717                         cls_set_ixoff_flow_control(ch);
 718         } else {
 719                 cls_set_no_input_flow_control(ch);
 720         }
 721
 722         cls_assert_modem_signals(ch);
 723
 724         /* Get current status of the modem signals now */
 725         cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
 726 }
 727
 728
 729 /*
 730  * Our board poller function.
 731  */
 732 static void cls_tasklet(unsigned long data)
 733 {
 734         struct dgnc_board *bd = (struct dgnc_board *) data;
 735         struct channel_t *ch;
 736         ulong  lock_flags;
 737         int i;
 738         int state = 0;
 739         int ports = 0;
 740
 741         if (!bd || bd->magic != DGNC_BOARD_MAGIC) {
 742                 APR(("poll_tasklet() - NULL or bad bd.\n"));
 743                 return;
 744         }
 745
 746         /* Cache a couple board values */
 747         DGNC_LOCK(bd->bd_lock, lock_flags);
 748         state = bd->state;
 749         ports = bd->nasync;
 750         DGNC_UNLOCK(bd->bd_lock, lock_flags);
 751
 752         /*
 753          * Do NOT allow the interrupt routine to read the intr registers
 754          * Until we release this lock.
 755          */
 756         DGNC_LOCK(bd->bd_intr_lock, lock_flags);
 757
 758         /*
 759          * If board is ready, parse deeper to see if there is anything to do.
 760          */
 761         if ((state == BOARD_READY) && (ports > 0)) {
 762
 763                 /* Loop on each port */
 764                 for (i = 0; i < ports; i++) {
 765                         ch = bd->channels[i];
 766                         if (!ch)
 767                                 continue;
 768
 769                         /*
 770                          * NOTE: Remember you CANNOT hold any channel
 771                          * locks when calling input.
 772                          * During input processing, its possible we
 773                          * will call ld, which might do callbacks back
 774                          * into us.
 775                          */
 776                         dgnc_input(ch);
 777
 778                         /*
 779                          * Channel lock is grabbed and then released
 780                          * inside this routine.
 781                          */
 782                         cls_copy_data_from_queue_to_uart(ch);
 783                         dgnc_wakeup_writes(ch);
 784
 785                         /*
 786                          * Check carrier function.
 787                          */
 788                         dgnc_carrier(ch);
 789
 790                         /*
 791                          * The timing check of turning off the break is done
 792                          * inside clear_break()
 793                          */
 794                         if (ch->ch_stop_sending_break)
 795                                 cls_clear_break(ch, 0);
 796                 }
 797         }
 798
 799         DGNC_UNLOCK(bd->bd_intr_lock, lock_flags);
 800
 801 }
 802
 803
 804 /*
 805  * cls_intr()
 806  *
 807  * Classic specific interrupt handler.
 808  */
 809 static irqreturn_t cls_intr(int irq, void *voidbrd)
 810 {
 811         struct dgnc_board *brd = (struct dgnc_board *) voidbrd;
 812         uint i = 0;
 813         uchar poll_reg;
 814         unsigned long lock_flags;
 815
 816         if (!brd) {
 817                 APR(("Received interrupt (%d) with null board associated\n",
 818                                                                          irq));
 819                 return IRQ_NONE;
 820         }
 821
 822         /*
 823          * Check to make sure its for us.
 824          */
 825         if (brd->magic != DGNC_BOARD_MAGIC) {
 826                 APR(("Received interrupt (%d) with a board pointer that wasn't ours!\n",
 827                           irq));
 828                 return IRQ_NONE;
 829         }
 830
 831         DGNC_LOCK(brd->bd_intr_lock, lock_flags);
 832
 833         brd->intr_count++;
 834
 835         /*
 836          * Check the board's global interrupt offset to see if we
 837          * we actually do have an interrupt pending for us.
 838          */
 839         poll_reg = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);
 840
 841         /* If 0, no interrupts pending */
 842         if (!poll_reg) {
 843                 DPR_INTR((
 844                          "Kernel interrupted to me, but no pending interrupts...\n"));
 845                 DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
 846                 return IRQ_NONE;
 847         }
 848
 849         DPR_INTR(("%s:%d poll_reg: %x\n", __FILE__, __LINE__, poll_reg));
 850
 851         /* Parse each port to find out what caused the interrupt */
 852         for (i = 0; i < brd->nasync; i++)
 853                 cls_parse_isr(brd, i);
 854
 855         /*
 856          * Schedule tasklet to more in-depth servicing at a better time.
 857          */
 858         tasklet_schedule(&brd->helper_tasklet);
 859
 860         DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
 861
 862         DPR_INTR(("dgnc_intr finish.\n"));
 863         return IRQ_HANDLED;
 864 }
 865
 866
 867 static void cls_disable_receiver(struct channel_t *ch)
 868 {
 869         uchar tmp = readb(&ch->ch_cls_uart->ier);
 870         tmp &= ~(UART_IER_RDI);
 871         writeb(tmp, &ch->ch_cls_uart->ier);
 872 }
 873
 874
 875 static void cls_enable_receiver(struct channel_t *ch)
 876 {
 877         uchar tmp = readb(&ch->ch_cls_uart->ier);
 878         tmp |= (UART_IER_RDI);
 879         writeb(tmp, &ch->ch_cls_uart->ier);
 880 }
 881
 882
 883 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch)
 884 {
 885         int qleft = 0;
 886         uchar linestatus = 0;
 887         uchar error_mask = 0;
 888         ushort head;
 889         ushort tail;
 890         ulong lock_flags;
 891
 892         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 893                 return;
 894
 895         DGNC_LOCK(ch->ch_lock, lock_flags);
 896
 897         /* cache head and tail of queue */
 898         head = ch->ch_r_head;
 899         tail = ch->ch_r_tail;
 900
 901         /* Store how much space we have left in the queue */
 902         qleft = (tail - head - 1);
 903         if (qleft < 0)
 904                 qleft += RQUEUEMASK + 1;
 905
 906         /*
 907          * Create a mask to determine whether we should
 908          * insert the character (if any) into our queue.
 909          */
 910         if (ch->ch_c_iflag & IGNBRK)
 911                 error_mask |= UART_LSR_BI;
 912
 913         while (1) {
 914                 linestatus = readb(&ch->ch_cls_uart->lsr);
 915
 916                 if (!(linestatus & (UART_LSR_DR)))
 917                         break;
 918
 919                 /*
 920                  * Discard character if we are ignoring the error mask.
 921                 */
 922                 if (linestatus & error_mask)  {
 923                         uchar discard;
 924                         linestatus = 0;
 925                         discard = readb(&ch->ch_cls_uart->txrx);
 926                         continue;
 927                 }
 928
 929                 /*
 930                  * If our queue is full, we have no choice but to drop some
 931                  * data. The assumption is that HWFLOW or SWFLOW should have
 932                  * stopped things way way before we got to this point.
 933                  *
 934                  * I decided that I wanted to ditch the oldest data first,
 935                  * I hope thats okay with everyone? Yes? Good.
 936                  */
 937                 while (qleft < 1) {
 938                         DPR_READ(("Queue full, dropping DATA:%x LSR:%x\n",
 939                                 ch->ch_rqueue[tail], ch->ch_equeue[tail]));
 940
 941                         ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
 942                         ch->ch_err_overrun++;
 943                         qleft++;
 944                 }
 945
 946                 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
 947                                                                  | UART_LSR_FE);
 948                 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
 949                 dgnc_sniff_nowait_nolock(ch, "UART READ",
 950                                                  ch->ch_rqueue + head, 1);
 951
 952                 qleft--;
 953
 954                 DPR_READ(("DATA/LSR pair: %x %x\n", ch->ch_rqueue[head],
 955                                                          ch->ch_equeue[head]));
 956
 957                 if (ch->ch_equeue[head] & UART_LSR_PE)
 958                         ch->ch_err_parity++;
 959                 if (ch->ch_equeue[head] & UART_LSR_BI)
 960                         ch->ch_err_break++;
 961                 if (ch->ch_equeue[head] & UART_LSR_FE)
 962                         ch->ch_err_frame++;
 963
 964                 /* Add to, and flip head if needed */
 965                 head = (head + 1) & RQUEUEMASK;
 966                 ch->ch_rxcount++;
 967         }
 968
 969         /*
 970          * Write new final heads to channel structure.
 971          */
 972         ch->ch_r_head = head & RQUEUEMASK;
 973         ch->ch_e_head = head & EQUEUEMASK;
 974
 975         DGNC_UNLOCK(ch->ch_lock, lock_flags);
 976 }
 977
 978
 979 /*
 980  * This function basically goes to sleep for secs, or until
 981  * it gets signalled that the port has fully drained.
 982  */
 983 static int cls_drain(struct tty_struct *tty, uint seconds)
 984 {
 985         ulong lock_flags;
 986         struct channel_t *ch;
 987         struct un_t *un;
 988         int rc = 0;
 989
 990         if (!tty || tty->magic != TTY_MAGIC)
 991                 return -ENXIO;
 992
 993         un = (struct un_t *) tty->driver_data;
 994         if (!un || un->magic != DGNC_UNIT_MAGIC)
 995                 return -ENXIO;
 996
 997         ch = un->un_ch;
 998         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
 999                 return -ENXIO;
1000
1001         DGNC_LOCK(ch->ch_lock, lock_flags);
1002         un->un_flags |= UN_EMPTY;
1003         DGNC_UNLOCK(ch->ch_lock, lock_flags);
1004
1005         /*
1006          * NOTE: Do something with time passed in.
1007          */
1008         rc = wait_event_interruptible(un->un_flags_wait,
1009                                          ((un->un_flags & UN_EMPTY) == 0));
1010
1011         /* If ret is non-zero, user ctrl-c'ed us */
1012         if (rc)
1013                 DPR_IOCTL(("%d Drain - User ctrl c'ed\n", __LINE__));
1014
1015         return rc;
1016 }
1017
1018
1019 /* Channel lock MUST be held before calling this function! */
1020 static void cls_flush_uart_write(struct channel_t *ch)
1021 {
1022         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1023                 return;
1024
1025         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
1026                                                 &ch->ch_cls_uart->isr_fcr);
1027         udelay(10);
1028
1029         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1030 }
1031
1032
1033 /* Channel lock MUST be held before calling this function! */
1034 static void cls_flush_uart_read(struct channel_t *ch)
1035 {
1036         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1037                 return;
1038
1039         /*
1040          * For complete POSIX compatibility, we should be purging the
1041          * read FIFO in the UART here.
1042          *
1043          * However, doing the statement below also incorrectly flushes
1044          * write data as well as just basically trashing the FIFO.
1045          *
1046          * I believe this is a BUG in this UART.
1047          * So for now, we will leave the code #ifdef'ed out...
1048          */
1049 #if 0
1050         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR),
1051                                          &ch->ch_cls_uart->isr_fcr);
1052 #endif
1053         udelay(10);
1054 }
1055
1056
1057 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch)
1058 {
1059         ushort head;
1060         ushort tail;
1061         int n;
1062         int qlen;
1063         uint len_written = 0;
1064         ulong lock_flags;
1065
1066         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1067                 return;
1068
1069         DGNC_LOCK(ch->ch_lock, lock_flags);
1070
1071         /* No data to write to the UART */
1072         if (ch->ch_w_tail == ch->ch_w_head) {
1073                 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1074                 return;
1075         }
1076
1077         /* If port is "stopped", don't send any data to the UART */
1078         if ((ch->ch_flags & CH_FORCED_STOP) ||
1079                                  (ch->ch_flags & CH_BREAK_SENDING)) {
1080                 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1081                 return;
1082         }
1083
1084         if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) {
1085                 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1086                 return;
1087         }
1088
1089         n = 32;
1090
1091         /* cache head and tail of queue */
1092         head = ch->ch_w_head & WQUEUEMASK;
1093         tail = ch->ch_w_tail & WQUEUEMASK;
1094         qlen = (head - tail) & WQUEUEMASK;
1095
1096         /* Find minimum of the FIFO space, versus queue length */
1097         n = min(n, qlen);
1098
1099         while (n > 0) {
1100
1101                 /*
1102                  * If RTS Toggle mode is on, turn on RTS now if not already set,
1103                  * and make sure we get an event when the data transfer has
1104                  * completed.
1105                  */
1106                 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1107                         if (!(ch->ch_mostat & UART_MCR_RTS)) {
1108                                 ch->ch_mostat |= (UART_MCR_RTS);
1109                                 cls_assert_modem_signals(ch);
1110                         }
1111                         ch->ch_tun.un_flags |= (UN_EMPTY);
1112                 }
1113
1114                 /*
1115                  * If DTR Toggle mode is on, turn on DTR now if not already set,
1116                  * and make sure we get an event when the data transfer has
1117                  * completed.
1118                  */
1119                 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1120                         if (!(ch->ch_mostat & UART_MCR_DTR)) {
1121                                 ch->ch_mostat |= (UART_MCR_DTR);
1122                                 cls_assert_modem_signals(ch);
1123                         }
1124                         ch->ch_tun.un_flags |= (UN_EMPTY);
1125                 }
1126                 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_cls_uart->txrx);
1127                 dgnc_sniff_nowait_nolock(ch, "UART WRITE",
1128                                             ch->ch_wqueue + ch->ch_w_tail, 1);
1129                 DPR_WRITE(("Tx data: %x\n", ch->ch_wqueue[ch->ch_w_tail]));
1130                 ch->ch_w_tail++;
1131                 ch->ch_w_tail &= WQUEUEMASK;
1132                 ch->ch_txcount++;
1133                 len_written++;
1134                 n--;
1135         }
1136
1137         if (len_written > 0)
1138                 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1139
1140         DGNC_UNLOCK(ch->ch_lock, lock_flags);
1141
1142         return;
1143 }
1144
1145
1146 static void cls_parse_modem(struct channel_t *ch, uchar signals)
1147 {
1148         uchar msignals = signals;
1149         ulong lock_flags;
1150
1151         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1152                 return;
1153
1154         DPR_MSIGS(("cls_parse_modem: port: %d signals: %d\n",
1155                                          ch->ch_portnum, msignals));
1156
1157         /*
1158          * Do altpin switching. Altpin switches DCD and DSR.
1159          * This prolly breaks DSRPACE, so we should be more clever here.
1160          */
1161         DGNC_LOCK(ch->ch_lock, lock_flags);
1162         if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1163                 uchar mswap = signals;
1164                 if (mswap & UART_MSR_DDCD) {
1165                         msignals &= ~UART_MSR_DDCD;
1166                         msignals |= UART_MSR_DDSR;
1167                 }
1168                 if (mswap & UART_MSR_DDSR) {
1169                         msignals &= ~UART_MSR_DDSR;
1170                         msignals |= UART_MSR_DDCD;
1171                 }
1172                 if (mswap & UART_MSR_DCD) {
1173                         msignals &= ~UART_MSR_DCD;
1174                         msignals |= UART_MSR_DSR;
1175                 }
1176                 if (mswap & UART_MSR_DSR) {
1177                         msignals &= ~UART_MSR_DSR;
1178                         msignals |= UART_MSR_DCD;
1179                 }
1180         }
1181         DGNC_UNLOCK(ch->ch_lock, lock_flags);
1182
1183         /*
1184          * Scrub off lower bits. They signify delta's, which I don't
1185          * care about
1186          */
1187         signals &= 0xf0;
1188
1189         DGNC_LOCK(ch->ch_lock, lock_flags);
1190         if (msignals & UART_MSR_DCD)
1191                 ch->ch_mistat |= UART_MSR_DCD;
1192         else
1193                 ch->ch_mistat &= ~UART_MSR_DCD;
1194
1195         if (msignals & UART_MSR_DSR)
1196                 ch->ch_mistat |= UART_MSR_DSR;
1197         else
1198                 ch->ch_mistat &= ~UART_MSR_DSR;
1199
1200         if (msignals & UART_MSR_RI)
1201                 ch->ch_mistat |= UART_MSR_RI;
1202         else
1203                 ch->ch_mistat &= ~UART_MSR_RI;
1204
1205         if (msignals & UART_MSR_CTS)
1206                 ch->ch_mistat |= UART_MSR_CTS;
1207         else
1208                 ch->ch_mistat &= ~UART_MSR_CTS;
1209         DGNC_UNLOCK(ch->ch_lock, lock_flags);
1210
1211
1212         DPR_MSIGS((
1213                 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
1214                 ch->ch_portnum,
1215                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
1216                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
1217                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
1218                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
1219                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
1220                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)));
1221 }
1222
1223
1224 /* Make the UART raise any of the output signals we want up */
1225 static void cls_assert_modem_signals(struct channel_t *ch)
1226 {
1227         uchar out;
1228
1229         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1230                 return;
1231
1232         out = ch->ch_mostat;
1233
1234         if (ch->ch_flags & CH_LOOPBACK)
1235                 out |= UART_MCR_LOOP;
1236
1237         writeb(out, &ch->ch_cls_uart->mcr);
1238
1239         /* Give time for the UART to actually drop the signals */
1240         udelay(10);
1241 }
1242
1243
1244 static void cls_send_start_character(struct channel_t *ch)
1245 {
1246         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1247                 return;
1248
1249         if (ch->ch_startc != _POSIX_VDISABLE) {
1250                 ch->ch_xon_sends++;
1251                 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
1252         }
1253 }
1254
1255
1256 static void cls_send_stop_character(struct channel_t *ch)
1257 {
1258         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1259                 return;
1260
1261         if (ch->ch_stopc != _POSIX_VDISABLE) {
1262                 ch->ch_xoff_sends++;
1263                 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
1264         }
1265 }
1266
1267
1268 /* Inits UART */
1269 static void cls_uart_init(struct channel_t *ch)
1270 {
1271         uchar lcrb = readb(&ch->ch_cls_uart->lcr);
1272         uchar isr_fcr = 0;
1273
1274         writeb(0, &ch->ch_cls_uart->ier);
1275
1276         /*
1277          * The Enhanced Register Set may only be accessed when
1278          * the Line Control Register is set to 0xBFh.
1279          */
1280         writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
1281
1282         isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
1283
1284         /* Turn on Enhanced/Extended controls */
1285         isr_fcr |= (UART_EXAR654_EFR_ECB);
1286
1287         writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
1288
1289         /* Write old LCR value back out, which turns enhanced access off */
1290         writeb(lcrb, &ch->ch_cls_uart->lcr);
1291
1292         /* Clear out UART and FIFO */
1293         readb(&ch->ch_cls_uart->txrx);
1294
1295         writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT),
1296                                                  &ch->ch_cls_uart->isr_fcr);
1297         udelay(10);
1298
1299         ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1300
1301         readb(&ch->ch_cls_uart->lsr);
1302         readb(&ch->ch_cls_uart->msr);
1303 }
1304
1305
1306 /*
1307  * Turns off UART.
1308  */
1309 static void cls_uart_off(struct channel_t *ch)
1310 {
1311         writeb(0, &ch->ch_cls_uart->ier);
1312 }
1313
1314
1315 /*
1316  * cls_get_uarts_bytes_left.
1317  * Returns 0 is nothing left in the FIFO, returns 1 otherwise.
1318  *
1319  * The channel lock MUST be held by the calling function.
1320  */
1321 static uint cls_get_uart_bytes_left(struct channel_t *ch)
1322 {
1323         uchar left = 0;
1324         uchar lsr = 0;
1325
1326         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1327                 return 0;
1328
1329         lsr = readb(&ch->ch_cls_uart->lsr);
1330
1331         /* Determine whether the Transmitter is empty or not */
1332         if (!(lsr & UART_LSR_TEMT)) {
1333                 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1334                         tasklet_schedule(&ch->ch_bd->helper_tasklet);
1335                 left = 1;
1336         } else {
1337                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1338                 left = 0;
1339         }
1340
1341         return left;
1342 }
1343
1344
1345 /*
1346  * cls_send_break.
1347  * Starts sending a break thru the UART.
1348  *
1349  * The channel lock MUST be held by the calling function.
1350  */
1351 static void cls_send_break(struct channel_t *ch, int msecs)
1352 {
1353         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1354                 return;
1355
1356         /*
1357          * If we receive a time of 0, this means turn off the break.
1358          */
1359         if (msecs == 0) {
1360                 /* Turn break off, and unset some variables */
1361                 if (ch->ch_flags & CH_BREAK_SENDING) {
1362                         uchar temp = readb(&ch->ch_cls_uart->lcr);
1363                         writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1364                         ch->ch_flags &= ~(CH_BREAK_SENDING);
1365                         ch->ch_stop_sending_break = 0;
1366                         DPR_IOCTL(("Finishing UART_LCR_SBC! finished: %lx\n",
1367                                                                      jiffies));
1368                 }
1369                 return;
1370         }
1371
1372         /*
1373          * Set the time we should stop sending the break.
1374          * If we are already sending a break, toss away the existing
1375          * time to stop, and use this new value instead.
1376          */
1377         ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1378
1379         /* Tell the UART to start sending the break */
1380         if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1381                 uchar temp = readb(&ch->ch_cls_uart->lcr);
1382                 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1383                 ch->ch_flags |= (CH_BREAK_SENDING);
1384                 DPR_IOCTL((
1385                         "Port %d. Starting UART_LCR_SBC! start: %lx should end: %lx\n",
1386                         ch->ch_portnum, jiffies, ch->ch_stop_sending_break));
1387         }
1388 }
1389
1390
1391 /*
1392  * cls_send_immediate_char.
1393  * Sends a specific character as soon as possible to the UART,
1394  * jumping over any bytes that might be in the write queue.
1395  *
1396  * The channel lock MUST be held by the calling function.
1397  */
1398 static void cls_send_immediate_char(struct channel_t *ch, unsigned char c)
1399 {
1400         if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1401                 return;
1402
1403         writeb(c, &ch->ch_cls_uart->txrx);
1404 }
1405
1406 static void cls_vpd(struct dgnc_board *brd)
1407 {
1408         ulong           vpdbase;        /* Start of io base of the card */
1409         u8 __iomem           *re_map_vpdbase;/* Remapped memory of the card */
1410         int i = 0;
1411
1412
1413         vpdbase = pci_resource_start(brd->pdev, 3);
1414
1415         /* No VPD */
1416         if (!vpdbase)
1417                 return;
1418
1419         re_map_vpdbase = ioremap(vpdbase, 0x400);
1420
1421         if (!re_map_vpdbase)
1422                 return;
1423
1424         /* Store the VPD into our buffer */
1425         for (i = 0; i < 0x40; i++) {
1426                 brd->vpd[i] = readb(re_map_vpdbase + i);
1427                 pr_info("%x ", brd->vpd[i]);
1428         }
1429         pr_info("\n");
1430
1431         if (re_map_vpdbase)
1432                 iounmap(re_map_vpdbase);
1433 }
1434