2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 * NOTE TO LINUX KERNEL HACKERS: DO NOT REFORMAT THIS CODE!
22 * This is shared code between Digi's CVS archive and the
23 * Linux Kernel sources.
24 * Changing the source just for reformatting needlessly breaks
25 * our CVS diff history.
27 * Send any bug fixes/changes to: Eng.Linux at digi dot com.
33 #include <linux/kernel.h>
34 #include <linux/sched.h> /* For jiffies, task states */
35 #include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */
36 #include <linux/delay.h> /* For udelay */
37 #include <asm/io.h> /* For read[bwl]/write[bwl] */
38 #include <linux/serial.h> /* For struct async_serial */
39 #include <linux/serial_reg.h> /* For the various UART offsets */
41 #include "dgnc_driver.h" /* Driver main header file */
42 #include "dgnc_neo.h" /* Our header file */
44 #include "dgnc_trace.h"
46 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port);
47 static inline void neo_parse_isr(struct dgnc_board *brd, uint port);
48 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch);
49 static inline void neo_clear_break(struct channel_t *ch, int force);
50 static inline void neo_set_cts_flow_control(struct channel_t *ch);
51 static inline void neo_set_rts_flow_control(struct channel_t *ch);
52 static inline void neo_set_ixon_flow_control(struct channel_t *ch);
53 static inline void neo_set_ixoff_flow_control(struct channel_t *ch);
54 static inline void neo_set_no_output_flow_control(struct channel_t *ch);
55 static inline void neo_set_no_input_flow_control(struct channel_t *ch);
56 static inline void neo_set_new_start_stop_chars(struct channel_t *ch);
57 static void neo_parse_modem(struct channel_t *ch, uchar signals);
58 static void neo_tasklet(unsigned long data);
59 static void neo_vpd(struct dgnc_board *brd);
60 static void neo_uart_init(struct channel_t *ch);
61 static void neo_uart_off(struct channel_t *ch);
62 static int neo_drain(struct tty_struct *tty, uint seconds);
63 static void neo_param(struct tty_struct *tty);
64 static void neo_assert_modem_signals(struct channel_t *ch);
65 static void neo_flush_uart_write(struct channel_t *ch);
66 static void neo_flush_uart_read(struct channel_t *ch);
67 static void neo_disable_receiver(struct channel_t *ch);
68 static void neo_enable_receiver(struct channel_t *ch);
69 static void neo_send_break(struct channel_t *ch, int msecs);
70 static void neo_send_start_character(struct channel_t *ch);
71 static void neo_send_stop_character(struct channel_t *ch);
72 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch);
73 static uint neo_get_uart_bytes_left(struct channel_t *ch);
74 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c);
75 static irqreturn_t neo_intr(int irq, void *voidbrd);
78 struct board_ops dgnc_neo_ops = {
79 .tasklet = neo_tasklet,
81 .uart_init = neo_uart_init,
82 .uart_off = neo_uart_off,
86 .assert_modem_signals = neo_assert_modem_signals,
87 .flush_uart_write = neo_flush_uart_write,
88 .flush_uart_read = neo_flush_uart_read,
89 .disable_receiver = neo_disable_receiver,
90 .enable_receiver = neo_enable_receiver,
91 .send_break = neo_send_break,
92 .send_start_character = neo_send_start_character,
93 .send_stop_character = neo_send_stop_character,
94 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
95 .get_uart_bytes_left = neo_get_uart_bytes_left,
96 .send_immediate_char = neo_send_immediate_char
99 static uint dgnc_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
103 * This function allows calls to ensure that all outstanding
104 * PCI writes have been completed, by doing a PCI read against
105 * a non-destructive, read-only location on the Neo card.
107 * In this case, we are reading the DVID (Read-only Device Identification)
108 * value of the Neo card.
110 static inline void neo_pci_posting_flush(struct dgnc_board *bd)
112 readb(bd->re_map_membase + 0x8D);
115 static inline void neo_set_cts_flow_control(struct channel_t *ch)
117 uchar ier = readb(&ch->ch_neo_uart->ier);
118 uchar efr = readb(&ch->ch_neo_uart->efr);
121 DPR_PARAM(("Setting CTSFLOW\n"));
123 /* Turn on auto CTS flow control */
125 ier |= (UART_17158_IER_CTSDSR);
127 ier &= ~(UART_17158_IER_CTSDSR);
130 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
132 /* Turn off auto Xon flow control */
133 efr &= ~(UART_17158_EFR_IXON);
135 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
136 writeb(0, &ch->ch_neo_uart->efr);
138 /* Turn on UART enhanced bits */
139 writeb(efr, &ch->ch_neo_uart->efr);
141 /* Turn on table D, with 8 char hi/low watermarks */
142 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
144 /* Feed the UART our trigger levels */
145 writeb(8, &ch->ch_neo_uart->tfifo);
148 writeb(ier, &ch->ch_neo_uart->ier);
150 neo_pci_posting_flush(ch->ch_bd);
154 static inline void neo_set_rts_flow_control(struct channel_t *ch)
156 uchar ier = readb(&ch->ch_neo_uart->ier);
157 uchar efr = readb(&ch->ch_neo_uart->efr);
159 DPR_PARAM(("Setting RTSFLOW\n"));
161 /* Turn on auto RTS flow control */
163 ier |= (UART_17158_IER_RTSDTR);
165 ier &= ~(UART_17158_IER_RTSDTR);
167 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
169 /* Turn off auto Xoff flow control */
170 ier &= ~(UART_17158_IER_XOFF);
171 efr &= ~(UART_17158_EFR_IXOFF);
173 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
174 writeb(0, &ch->ch_neo_uart->efr);
176 /* Turn on UART enhanced bits */
177 writeb(efr, &ch->ch_neo_uart->efr);
179 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
180 ch->ch_r_watermark = 4;
182 writeb(32, &ch->ch_neo_uart->rfifo);
183 ch->ch_r_tlevel = 32;
185 writeb(ier, &ch->ch_neo_uart->ier);
188 * From the Neo UART spec sheet:
189 * The auto RTS/DTR function must be started by asserting
190 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
193 ch->ch_mostat |= (UART_MCR_RTS);
195 neo_pci_posting_flush(ch->ch_bd);
199 static inline void neo_set_ixon_flow_control(struct channel_t *ch)
201 uchar ier = readb(&ch->ch_neo_uart->ier);
202 uchar efr = readb(&ch->ch_neo_uart->efr);
204 DPR_PARAM(("Setting IXON FLOW\n"));
206 /* Turn off auto CTS flow control */
207 ier &= ~(UART_17158_IER_CTSDSR);
208 efr &= ~(UART_17158_EFR_CTSDSR);
210 /* Turn on auto Xon flow control */
211 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
213 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
214 writeb(0, &ch->ch_neo_uart->efr);
216 /* Turn on UART enhanced bits */
217 writeb(efr, &ch->ch_neo_uart->efr);
219 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
220 ch->ch_r_watermark = 4;
222 writeb(32, &ch->ch_neo_uart->rfifo);
223 ch->ch_r_tlevel = 32;
225 /* Tell UART what start/stop chars it should be looking for */
226 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
227 writeb(0, &ch->ch_neo_uart->xonchar2);
229 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
230 writeb(0, &ch->ch_neo_uart->xoffchar2);
232 writeb(ier, &ch->ch_neo_uart->ier);
234 neo_pci_posting_flush(ch->ch_bd);
238 static inline void neo_set_ixoff_flow_control(struct channel_t *ch)
240 uchar ier = readb(&ch->ch_neo_uart->ier);
241 uchar efr = readb(&ch->ch_neo_uart->efr);
243 DPR_PARAM(("Setting IXOFF FLOW\n"));
245 /* Turn off auto RTS flow control */
246 ier &= ~(UART_17158_IER_RTSDTR);
247 efr &= ~(UART_17158_EFR_RTSDTR);
249 /* Turn on auto Xoff flow control */
250 ier |= (UART_17158_IER_XOFF);
251 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
253 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
254 writeb(0, &ch->ch_neo_uart->efr);
256 /* Turn on UART enhanced bits */
257 writeb(efr, &ch->ch_neo_uart->efr);
259 /* Turn on table D, with 8 char hi/low watermarks */
260 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
262 writeb(8, &ch->ch_neo_uart->tfifo);
265 /* Tell UART what start/stop chars it should be looking for */
266 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
267 writeb(0, &ch->ch_neo_uart->xonchar2);
269 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
270 writeb(0, &ch->ch_neo_uart->xoffchar2);
272 writeb(ier, &ch->ch_neo_uart->ier);
274 neo_pci_posting_flush(ch->ch_bd);
278 static inline void neo_set_no_input_flow_control(struct channel_t *ch)
280 uchar ier = readb(&ch->ch_neo_uart->ier);
281 uchar efr = readb(&ch->ch_neo_uart->efr);
283 DPR_PARAM(("Unsetting Input FLOW\n"));
285 /* Turn off auto RTS flow control */
286 ier &= ~(UART_17158_IER_RTSDTR);
287 efr &= ~(UART_17158_EFR_RTSDTR);
289 /* Turn off auto Xoff flow control */
290 ier &= ~(UART_17158_IER_XOFF);
291 if (ch->ch_c_iflag & IXON)
292 efr &= ~(UART_17158_EFR_IXOFF);
294 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
297 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
298 writeb(0, &ch->ch_neo_uart->efr);
300 /* Turn on UART enhanced bits */
301 writeb(efr, &ch->ch_neo_uart->efr);
303 /* Turn on table D, with 8 char hi/low watermarks */
304 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
306 ch->ch_r_watermark = 0;
308 writeb(16, &ch->ch_neo_uart->tfifo);
309 ch->ch_t_tlevel = 16;
311 writeb(16, &ch->ch_neo_uart->rfifo);
312 ch->ch_r_tlevel = 16;
314 writeb(ier, &ch->ch_neo_uart->ier);
316 neo_pci_posting_flush(ch->ch_bd);
320 static inline void neo_set_no_output_flow_control(struct channel_t *ch)
322 uchar ier = readb(&ch->ch_neo_uart->ier);
323 uchar efr = readb(&ch->ch_neo_uart->efr);
325 DPR_PARAM(("Unsetting Output FLOW\n"));
327 /* Turn off auto CTS flow control */
328 ier &= ~(UART_17158_IER_CTSDSR);
329 efr &= ~(UART_17158_EFR_CTSDSR);
331 /* Turn off auto Xon flow control */
332 if (ch->ch_c_iflag & IXOFF)
333 efr &= ~(UART_17158_EFR_IXON);
335 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
337 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
338 writeb(0, &ch->ch_neo_uart->efr);
340 /* Turn on UART enhanced bits */
341 writeb(efr, &ch->ch_neo_uart->efr);
343 /* Turn on table D, with 8 char hi/low watermarks */
344 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
346 ch->ch_r_watermark = 0;
348 writeb(16, &ch->ch_neo_uart->tfifo);
349 ch->ch_t_tlevel = 16;
351 writeb(16, &ch->ch_neo_uart->rfifo);
352 ch->ch_r_tlevel = 16;
354 writeb(ier, &ch->ch_neo_uart->ier);
356 neo_pci_posting_flush(ch->ch_bd);
360 /* change UARTs start/stop chars */
361 static inline void neo_set_new_start_stop_chars(struct channel_t *ch)
364 /* if hardware flow control is set, then skip this whole thing */
365 if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) || ch->ch_c_cflag & CRTSCTS)
368 DPR_PARAM(("In new start stop chars\n"));
370 /* Tell UART what start/stop chars it should be looking for */
371 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
372 writeb(0, &ch->ch_neo_uart->xonchar2);
374 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
375 writeb(0, &ch->ch_neo_uart->xoffchar2);
377 neo_pci_posting_flush(ch->ch_bd);
382 * No locks are assumed to be held when calling this function.
384 static inline void neo_clear_break(struct channel_t *ch, int force)
388 DGNC_LOCK(ch->ch_lock, lock_flags);
390 /* Bail if we aren't currently sending a break. */
391 if (!ch->ch_stop_sending_break) {
392 DGNC_UNLOCK(ch->ch_lock, lock_flags);
396 /* Turn break off, and unset some variables */
397 if (ch->ch_flags & CH_BREAK_SENDING) {
398 if ((jiffies >= ch->ch_stop_sending_break) || force) {
399 uchar temp = readb(&ch->ch_neo_uart->lcr);
400 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
401 neo_pci_posting_flush(ch->ch_bd);
402 ch->ch_flags &= ~(CH_BREAK_SENDING);
403 ch->ch_stop_sending_break = 0;
404 DPR_IOCTL(("Finishing UART_LCR_SBC! finished: %lx\n", jiffies));
407 DGNC_UNLOCK(ch->ch_lock, lock_flags);
412 * Parse the ISR register.
414 static inline void neo_parse_isr(struct dgnc_board *brd, uint port)
416 struct channel_t *ch;
421 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
424 if (port > brd->maxports)
427 ch = brd->channels[port];
428 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
431 /* Here we try to figure out what caused the interrupt to happen */
434 isr = readb(&ch->ch_neo_uart->isr_fcr);
436 /* Bail if no pending interrupt */
437 if (isr & UART_IIR_NO_INT) {
442 * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
444 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
446 DPR_INTR(("%s:%d isr: %x\n", __FILE__, __LINE__, isr));
448 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
449 /* Read data from uart -> queue */
452 neo_copy_data_from_uart_to_queue(ch);
454 /* Call our tty layer to enforce queue flow control if needed. */
455 DGNC_LOCK(ch->ch_lock, lock_flags);
456 dgnc_check_queue_flow_control(ch);
457 DGNC_UNLOCK(ch->ch_lock, lock_flags);
460 if (isr & UART_IIR_THRI) {
463 /* Transfer data (if any) from Write Queue -> UART. */
464 DGNC_LOCK(ch->ch_lock, lock_flags);
465 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
466 DGNC_UNLOCK(ch->ch_lock, lock_flags);
467 neo_copy_data_from_queue_to_uart(ch);
470 if (isr & UART_17158_IIR_XONXOFF) {
471 cause = readb(&ch->ch_neo_uart->xoffchar1);
473 DPR_INTR(("Port %d. Got ISR_XONXOFF: cause:%x\n", port, cause));
476 * Since the UART detected either an XON or
477 * XOFF match, we need to figure out which
478 * one it was, so we can suspend or resume data flow.
480 if (cause == UART_17158_XON_DETECT) {
481 /* Is output stopped right now, if so, resume it */
482 if (brd->channels[port]->ch_flags & CH_STOP) {
483 DGNC_LOCK(ch->ch_lock, lock_flags);
484 ch->ch_flags &= ~(CH_STOP);
485 DGNC_UNLOCK(ch->ch_lock, lock_flags);
487 DPR_INTR(("Port %d. XON detected in incoming data\n", port));
489 else if (cause == UART_17158_XOFF_DETECT) {
490 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
491 DGNC_LOCK(ch->ch_lock, lock_flags);
492 ch->ch_flags |= CH_STOP;
493 DGNC_UNLOCK(ch->ch_lock, lock_flags);
494 DPR_INTR(("Setting CH_STOP\n"));
496 DPR_INTR(("Port: %d. XOFF detected in incoming data\n", port));
500 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
502 * If we get here, this means the hardware is doing auto flow control.
503 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
507 cause = readb(&ch->ch_neo_uart->mcr);
508 /* Which pin is doing auto flow? RTS or DTR? */
509 if ((cause & 0x4) == 0) {
510 if (cause & UART_MCR_RTS) {
511 DGNC_LOCK(ch->ch_lock, lock_flags);
512 ch->ch_mostat |= UART_MCR_RTS;
513 DGNC_UNLOCK(ch->ch_lock, lock_flags);
516 DGNC_LOCK(ch->ch_lock, lock_flags);
517 ch->ch_mostat &= ~(UART_MCR_RTS);
518 DGNC_UNLOCK(ch->ch_lock, lock_flags);
521 if (cause & UART_MCR_DTR) {
522 DGNC_LOCK(ch->ch_lock, lock_flags);
523 ch->ch_mostat |= UART_MCR_DTR;
524 DGNC_UNLOCK(ch->ch_lock, lock_flags);
527 DGNC_LOCK(ch->ch_lock, lock_flags);
528 ch->ch_mostat &= ~(UART_MCR_DTR);
529 DGNC_UNLOCK(ch->ch_lock, lock_flags);
534 /* Parse any modem signal changes */
535 DPR_INTR(("MOD_STAT: sending to parse_modem_sigs\n"));
536 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
541 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port)
543 struct channel_t *ch;
550 if (brd->magic != DGNC_BOARD_MAGIC)
553 if (port > brd->maxports)
556 ch = brd->channels[port];
557 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
560 linestatus = readb(&ch->ch_neo_uart->lsr);
562 DPR_INTR(("%s:%d port: %d linestatus: %x\n", __FILE__, __LINE__, port, linestatus));
564 ch->ch_cached_lsr |= linestatus;
566 if (ch->ch_cached_lsr & UART_LSR_DR) {
569 /* Read data from uart -> queue */
570 neo_copy_data_from_uart_to_queue(ch);
571 DGNC_LOCK(ch->ch_lock, lock_flags);
572 dgnc_check_queue_flow_control(ch);
573 DGNC_UNLOCK(ch->ch_lock, lock_flags);
577 * This is a special flag. It indicates that at least 1
578 * RX error (parity, framing, or break) has happened.
579 * Mark this in our struct, which will tell me that I have
580 *to do the special RX+LSR read for this FIFO load.
582 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) {
583 DPR_INTR(("%s:%d Port: %d Got an RX error, need to parse LSR\n",
584 __FILE__, __LINE__, port));
588 * The next 3 tests should *NOT* happen, as the above test
589 * should encapsulate all 3... At least, thats what Exar says.
592 if (linestatus & UART_LSR_PE) {
594 DPR_INTR(("%s:%d Port: %d. PAR ERR!\n", __FILE__, __LINE__, port));
597 if (linestatus & UART_LSR_FE) {
599 DPR_INTR(("%s:%d Port: %d. FRM ERR!\n", __FILE__, __LINE__, port));
602 if (linestatus & UART_LSR_BI) {
604 DPR_INTR(("%s:%d Port: %d. BRK INTR!\n", __FILE__, __LINE__, port));
607 if (linestatus & UART_LSR_OE) {
609 * Rx Oruns. Exar says that an orun will NOT corrupt
610 * the FIFO. It will just replace the holding register
611 * with this new data byte. So basically just ignore this.
612 * Probably we should eventually have an orun stat in our driver...
614 ch->ch_err_overrun++;
615 DPR_INTR(("%s:%d Port: %d. Rx Overrun!\n", __FILE__, __LINE__, port));
618 if (linestatus & UART_LSR_THRE) {
621 DGNC_LOCK(ch->ch_lock, lock_flags);
622 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
623 DGNC_UNLOCK(ch->ch_lock, lock_flags);
625 /* Transfer data (if any) from Write Queue -> UART. */
626 neo_copy_data_from_queue_to_uart(ch);
628 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
631 DGNC_LOCK(ch->ch_lock, lock_flags);
632 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
633 DGNC_UNLOCK(ch->ch_lock, lock_flags);
635 /* Transfer data (if any) from Write Queue -> UART. */
636 neo_copy_data_from_queue_to_uart(ch);
643 * Send any/all changes to the line to the UART.
645 static void neo_param(struct tty_struct *tty)
653 struct dgnc_board *bd;
654 struct channel_t *ch;
657 if (!tty || tty->magic != TTY_MAGIC) {
661 un = (struct un_t *) tty->driver_data;
662 if (!un || un->magic != DGNC_UNIT_MAGIC) {
667 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
672 if (!bd || bd->magic != DGNC_BOARD_MAGIC) {
676 DPR_PARAM(("param start: tdev: %x cflags: %x oflags: %x iflags: %x\n",
677 ch->ch_tun.un_dev, ch->ch_c_cflag, ch->ch_c_oflag, ch->ch_c_iflag));
680 * If baud rate is zero, flush queues, and set mval to drop DTR.
682 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
683 ch->ch_r_head = ch->ch_r_tail = 0;
684 ch->ch_e_head = ch->ch_e_tail = 0;
685 ch->ch_w_head = ch->ch_w_tail = 0;
687 neo_flush_uart_write(ch);
688 neo_flush_uart_read(ch);
690 /* The baudrate is B0 so all modem lines are to be dropped. */
691 ch->ch_flags |= (CH_BAUD0);
692 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
693 neo_assert_modem_signals(ch);
697 } else if (ch->ch_custom_speed) {
699 baud = ch->ch_custom_speed;
700 /* Handle transition from B0 */
701 if (ch->ch_flags & CH_BAUD0) {
702 ch->ch_flags &= ~(CH_BAUD0);
705 * Bring back up RTS and DTR...
706 * Also handle RTS or DTR toggle if set.
708 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
709 ch->ch_mostat |= (UART_MCR_RTS);
710 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
711 ch->ch_mostat |= (UART_MCR_DTR);
717 ulong bauds[4][16] = {
721 600, 1200, 1800, 2400,
722 4800, 9600, 19200, 38400 },
723 { /* slowbaud & CBAUDEX */
724 0, 57600, 115200, 230400,
725 460800, 150, 200, 921600,
726 600, 1200, 1800, 2400,
727 4800, 9600, 19200, 38400 },
729 0, 57600, 76800, 115200,
730 131657, 153600, 230400, 460800,
731 921600, 1200, 1800, 2400,
732 4800, 9600, 19200, 38400 },
733 { /* fastbaud & CBAUDEX */
734 0, 57600, 115200, 230400,
735 460800, 150, 200, 921600,
736 600, 1200, 1800, 2400,
737 4800, 9600, 19200, 38400 }
740 /* Only use the TXPrint baud rate if the terminal unit is NOT open */
741 if (!(ch->ch_tun.un_flags & UN_ISOPEN) && (un->un_type == DGNC_PRINT))
742 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
744 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
746 if (ch->ch_c_cflag & CBAUDEX)
749 if (ch->ch_digi.digi_flags & DIGI_FAST)
754 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && (jindex < 16)) {
755 baud = bauds[iindex][jindex];
757 DPR_IOCTL(("baud indices were out of range (%d)(%d)",
765 /* Handle transition from B0 */
766 if (ch->ch_flags & CH_BAUD0) {
767 ch->ch_flags &= ~(CH_BAUD0);
770 * Bring back up RTS and DTR...
771 * Also handle RTS or DTR toggle if set.
773 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
774 ch->ch_mostat |= (UART_MCR_RTS);
775 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
776 ch->ch_mostat |= (UART_MCR_DTR);
780 if (ch->ch_c_cflag & PARENB) {
781 lcr |= UART_LCR_PARITY;
784 if (!(ch->ch_c_cflag & PARODD)) {
785 lcr |= UART_LCR_EPAR;
789 * Not all platforms support mark/space parity,
790 * so this will hide behind an ifdef.
793 if (ch->ch_c_cflag & CMSPAR)
794 lcr |= UART_LCR_SPAR;
797 if (ch->ch_c_cflag & CSTOPB)
798 lcr |= UART_LCR_STOP;
800 switch (ch->ch_c_cflag & CSIZE) {
802 lcr |= UART_LCR_WLEN5;
805 lcr |= UART_LCR_WLEN6;
808 lcr |= UART_LCR_WLEN7;
812 lcr |= UART_LCR_WLEN8;
816 ier = uart_ier = readb(&ch->ch_neo_uart->ier);
817 uart_lcr = readb(&ch->ch_neo_uart->lcr);
822 quot = ch->ch_bd->bd_dividend / baud;
824 if (quot != 0 && ch->ch_old_baud != baud) {
825 ch->ch_old_baud = baud;
826 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
827 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
828 writeb((quot >> 8), &ch->ch_neo_uart->ier);
829 writeb(lcr, &ch->ch_neo_uart->lcr);
833 writeb(lcr, &ch->ch_neo_uart->lcr);
835 if (ch->ch_c_cflag & CREAD) {
836 ier |= (UART_IER_RDI | UART_IER_RLSI);
839 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
843 * Have the UART interrupt on modem signal changes ONLY when
844 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
846 if ((ch->ch_digi.digi_flags & CTSPACE) || (ch->ch_digi.digi_flags & RTSPACE) ||
847 (ch->ch_c_cflag & CRTSCTS) || !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
848 !(ch->ch_c_cflag & CLOCAL))
853 ier &= ~UART_IER_MSI;
856 ier |= UART_IER_THRI;
859 writeb(ier, &ch->ch_neo_uart->ier);
861 /* Set new start/stop chars */
862 neo_set_new_start_stop_chars(ch);
864 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
865 neo_set_cts_flow_control(ch);
867 else if (ch->ch_c_iflag & IXON) {
868 /* If start/stop is set to disable, then we should disable flow control */
869 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
870 neo_set_no_output_flow_control(ch);
872 neo_set_ixon_flow_control(ch);
875 neo_set_no_output_flow_control(ch);
878 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
879 neo_set_rts_flow_control(ch);
881 else if (ch->ch_c_iflag & IXOFF) {
882 /* If start/stop is set to disable, then we should disable flow control */
883 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
884 neo_set_no_input_flow_control(ch);
886 neo_set_ixoff_flow_control(ch);
889 neo_set_no_input_flow_control(ch);
893 * Adjust the RX FIFO Trigger level if baud is less than 9600.
894 * Not exactly elegant, but this is needed because of the Exar chip's
895 * delay on firing off the RX FIFO interrupt on slower baud rates.
898 writeb(1, &ch->ch_neo_uart->rfifo);
902 neo_assert_modem_signals(ch);
904 /* Get current status of the modem signals now */
905 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
910 * Our board poller function.
912 static void neo_tasklet(unsigned long data)
914 struct dgnc_board *bd = (struct dgnc_board *) data;
915 struct channel_t *ch;
921 if (!bd || bd->magic != DGNC_BOARD_MAGIC) {
922 APR(("poll_tasklet() - NULL or bad bd.\n"));
926 /* Cache a couple board values */
927 DGNC_LOCK(bd->bd_lock, lock_flags);
930 DGNC_UNLOCK(bd->bd_lock, lock_flags);
933 * Do NOT allow the interrupt routine to read the intr registers
934 * Until we release this lock.
936 DGNC_LOCK(bd->bd_intr_lock, lock_flags);
939 * If board is ready, parse deeper to see if there is anything to do.
941 if ((state == BOARD_READY) && (ports > 0)) {
942 /* Loop on each port */
943 for (i = 0; i < ports; i++) {
944 ch = bd->channels[i];
946 /* Just being careful... */
947 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
951 * NOTE: Remember you CANNOT hold any channel
952 * locks when calling the input routine.
954 * During input processing, its possible we
955 * will call the Linux ld, which might in turn,
956 * do a callback right back into us, resulting
957 * in us trying to grab the channel lock twice!
962 * Channel lock is grabbed and then released
963 * inside both of these routines, but neither
964 * call anything else that could call back into us.
966 neo_copy_data_from_queue_to_uart(ch);
967 dgnc_wakeup_writes(ch);
970 * Call carrier carrier function, in case something
976 * Check to see if we need to turn off a sending break.
977 * The timing check is done inside clear_break()
979 if (ch->ch_stop_sending_break)
980 neo_clear_break(ch, 0);
984 /* Allow interrupt routine to access the interrupt register again */
985 DGNC_UNLOCK(bd->bd_intr_lock, lock_flags);
993 * Neo specific interrupt handler.
995 static irqreturn_t neo_intr(int irq, void *voidbrd)
997 struct dgnc_board *brd = (struct dgnc_board *) voidbrd;
998 struct channel_t *ch;
1004 unsigned long lock_flags;
1005 unsigned long lock_flags2;
1008 APR(("Received interrupt (%d) with null board associated\n", irq));
1013 * Check to make sure its for us.
1015 if (brd->magic != DGNC_BOARD_MAGIC) {
1016 APR(("Received interrupt (%d) with a board pointer that wasn't ours!\n", irq));
1022 /* Lock out the slow poller from running on this board. */
1023 DGNC_LOCK(brd->bd_intr_lock, lock_flags);
1026 * Read in "extended" IRQ information from the 32bit Neo register.
1027 * Bits 0-7: What port triggered the interrupt.
1028 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
1030 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1032 DPR_INTR(("%s:%d uart_poll: %x\n", __FILE__, __LINE__, uart_poll));
1035 * If 0, no interrupts pending.
1036 * This can happen if the IRQ is shared among a couple Neo/Classic boards.
1039 DPR_INTR(("Kernel interrupted to me, but no pending interrupts...\n"));
1040 DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
1044 /* At this point, we have at least SOMETHING to service, dig further... */
1048 /* Loop on each port */
1049 while ((uart_poll & 0xff) != 0) {
1053 /* Check current port to see if it has interrupt pending */
1054 if ((tmp & dgnc_offset_table[current_port]) != 0) {
1055 port = current_port;
1056 type = tmp >> (8 + (port * 3));
1063 DPR_INTR(("%s:%d port: %x type: %x\n", __FILE__, __LINE__, port, type));
1065 /* Remove this port + type from uart_poll */
1066 uart_poll &= ~(dgnc_offset_table[port]);
1069 /* If no type, just ignore it, and move onto next port */
1070 DPR_INTR(("Interrupt with no type! port: %d\n", port));
1074 /* Switch on type of interrupt we have */
1077 case UART_17158_RXRDY_TIMEOUT:
1079 * RXRDY Time-out is cleared by reading data in the
1080 * RX FIFO until it falls below the trigger level.
1083 /* Verify the port is in range. */
1084 if (port > brd->nasync)
1087 ch = brd->channels[port];
1088 neo_copy_data_from_uart_to_queue(ch);
1090 /* Call our tty layer to enforce queue flow control if needed. */
1091 DGNC_LOCK(ch->ch_lock, lock_flags2);
1092 dgnc_check_queue_flow_control(ch);
1093 DGNC_UNLOCK(ch->ch_lock, lock_flags2);
1097 case UART_17158_RX_LINE_STATUS:
1099 * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1101 neo_parse_lsr(brd, port);
1104 case UART_17158_TXRDY:
1106 * TXRDY interrupt clears after reading ISR register for the UART channel.
1110 * Yes, this is odd...
1111 * Why would I check EVERY possibility of type of
1112 * interrupt, when we know its TXRDY???
1113 * Becuz for some reason, even tho we got triggered for TXRDY,
1114 * it seems to be occasionally wrong. Instead of TX, which
1115 * it should be, I was getting things like RXDY too. Weird.
1117 neo_parse_isr(brd, port);
1120 case UART_17158_MSR:
1122 * MSR or flow control was seen.
1124 neo_parse_isr(brd, port);
1129 * The UART triggered us with a bogus interrupt type.
1130 * It appears the Exar chip, when REALLY bogged down, will throw
1131 * these once and awhile.
1132 * Its harmless, just ignore it and move on.
1134 DPR_INTR(("%s:%d Unknown Interrupt type: %x\n", __FILE__, __LINE__, type));
1140 * Schedule tasklet to more in-depth servicing at a better time.
1142 tasklet_schedule(&brd->helper_tasklet);
1144 DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
1146 DPR_INTR(("dgnc_intr finish.\n"));
1152 * Neo specific way of turning off the receiver.
1153 * Used as a way to enforce queue flow control when in
1154 * hardware flow control mode.
1156 static void neo_disable_receiver(struct channel_t *ch)
1158 uchar tmp = readb(&ch->ch_neo_uart->ier);
1159 tmp &= ~(UART_IER_RDI);
1160 writeb(tmp, &ch->ch_neo_uart->ier);
1161 neo_pci_posting_flush(ch->ch_bd);
1166 * Neo specific way of turning on the receiver.
1167 * Used as a way to un-enforce queue flow control when in
1168 * hardware flow control mode.
1170 static void neo_enable_receiver(struct channel_t *ch)
1172 uchar tmp = readb(&ch->ch_neo_uart->ier);
1173 tmp |= (UART_IER_RDI);
1174 writeb(tmp, &ch->ch_neo_uart->ier);
1175 neo_pci_posting_flush(ch->ch_bd);
1179 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch)
1182 uchar linestatus = 0;
1183 uchar error_mask = 0;
1190 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1193 DGNC_LOCK(ch->ch_lock, lock_flags);
1195 /* cache head and tail of queue */
1196 head = ch->ch_r_head & RQUEUEMASK;
1197 tail = ch->ch_r_tail & RQUEUEMASK;
1199 /* Get our cached LSR */
1200 linestatus = ch->ch_cached_lsr;
1201 ch->ch_cached_lsr = 0;
1203 /* Store how much space we have left in the queue */
1204 qleft = tail - head - 1;
1206 qleft += RQUEUEMASK + 1;
1209 * If the UART is not in FIFO mode, force the FIFO copy to
1210 * NOT be run, by setting total to 0.
1212 * On the other hand, if the UART IS in FIFO mode, then ask
1213 * the UART to give us an approximation of data it has RX'ed.
1215 if (!(ch->ch_flags & CH_FIFO_ENABLED))
1218 total = readb(&ch->ch_neo_uart->rfifo);
1221 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
1223 * This resolves a problem/bug with the Exar chip that sometimes
1224 * returns a bogus value in the rfifo register.
1225 * The count can be any where from 0-3 bytes "off".
1226 * Bizarre, but true.
1228 if ((ch->ch_bd->dvid & 0xf0) >= UART_XR17E158_DVID) {
1238 * Finally, bound the copy to make sure we don't overflow
1240 * The byte by byte copy loop below this loop this will
1241 * deal with the queue overflow possibility.
1243 total = min(total, qleft);
1248 * Grab the linestatus register, we need to check
1249 * to see if there are any errors in the FIFO.
1251 linestatus = readb(&ch->ch_neo_uart->lsr);
1254 * Break out if there is a FIFO error somewhere.
1255 * This will allow us to go byte by byte down below,
1256 * finding the exact location of the error.
1258 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
1261 /* Make sure we don't go over the end of our queue */
1262 n = min(((uint) total), (RQUEUESIZE - (uint) head));
1265 * Cut down n even further if needed, this is to fix
1266 * a problem with memcpy_fromio() with the Neo on the
1267 * IBM pSeries platform.
1268 * 15 bytes max appears to be the magic number.
1270 n = min((uint) n, (uint) 12);
1273 * Since we are grabbing the linestatus register, which
1274 * will reset some bits after our read, we need to ensure
1275 * we don't miss our TX FIFO emptys.
1277 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
1278 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1283 /* Copy data from uart to the queue */
1284 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
1285 dgnc_sniff_nowait_nolock(ch, "UART READ", ch->ch_rqueue + head, n);
1288 * Since RX_FIFO_DATA_ERROR was 0, we are guarenteed
1289 * that all the data currently in the FIFO is free of
1290 * breaks and parity/frame/orun errors.
1292 memset(ch->ch_equeue + head, 0, n);
1294 /* Add to and flip head if needed */
1295 head = (head + n) & RQUEUEMASK;
1298 ch->ch_rxcount += n;
1302 * Create a mask to determine whether we should
1303 * insert the character (if any) into our queue.
1305 if (ch->ch_c_iflag & IGNBRK)
1306 error_mask |= UART_LSR_BI;
1309 * Now cleanup any leftover bytes still in the UART.
1310 * Also deal with any possible queue overflow here as well.
1315 * Its possible we have a linestatus from the loop above
1316 * this, so we "OR" on any extra bits.
1318 linestatus |= readb(&ch->ch_neo_uart->lsr);
1321 * If the chip tells us there is no more data pending to
1322 * be read, we can then leave.
1323 * But before we do, cache the linestatus, just in case.
1325 if (!(linestatus & UART_LSR_DR)) {
1326 ch->ch_cached_lsr = linestatus;
1330 /* No need to store this bit */
1331 linestatus &= ~UART_LSR_DR;
1334 * Since we are grabbing the linestatus register, which
1335 * will reset some bits after our read, we need to ensure
1336 * we don't miss our TX FIFO emptys.
1338 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
1339 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
1340 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1344 * Discard character if we are ignoring the error mask.
1346 if (linestatus & error_mask) {
1349 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
1354 * If our queue is full, we have no choice but to drop some data.
1355 * The assumption is that HWFLOW or SWFLOW should have stopped
1356 * things way way before we got to this point.
1358 * I decided that I wanted to ditch the oldest data first,
1359 * I hope thats okay with everyone? Yes? Good.
1362 DPR_READ(("Queue full, dropping DATA:%x LSR:%x\n",
1363 ch->ch_rqueue[tail], ch->ch_equeue[tail]));
1365 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
1366 ch->ch_err_overrun++;
1370 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
1371 ch->ch_equeue[head] = (uchar) linestatus;
1372 dgnc_sniff_nowait_nolock(ch, "UART READ", ch->ch_rqueue + head, 1);
1374 DPR_READ(("DATA/LSR pair: %x %x\n", ch->ch_rqueue[head], ch->ch_equeue[head]));
1376 /* Ditch any remaining linestatus value. */
1379 /* Add to and flip head if needed */
1380 head = (head + 1) & RQUEUEMASK;
1387 * Write new final heads to channel structure.
1389 ch->ch_r_head = head & RQUEUEMASK;
1390 ch->ch_e_head = head & EQUEUEMASK;
1392 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1397 * This function basically goes to sleep for secs, or until
1398 * it gets signalled that the port has fully drained.
1400 static int neo_drain(struct tty_struct *tty, uint seconds)
1403 struct channel_t *ch;
1407 if (!tty || tty->magic != TTY_MAGIC) {
1411 un = (struct un_t *) tty->driver_data;
1412 if (!un || un->magic != DGNC_UNIT_MAGIC) {
1417 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
1421 DPR_IOCTL(("%d Drain wait started.\n", __LINE__));
1423 DGNC_LOCK(ch->ch_lock, lock_flags);
1424 un->un_flags |= UN_EMPTY;
1425 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1428 * Go to sleep waiting for the tty layer to wake me back up when
1429 * the empty flag goes away.
1431 * NOTE: TODO: Do something with time passed in.
1433 rc = wait_event_interruptible(un->un_flags_wait, ((un->un_flags & UN_EMPTY) == 0));
1435 /* If ret is non-zero, user ctrl-c'ed us */
1437 DPR_IOCTL(("%d Drain - User ctrl c'ed\n", __LINE__));
1440 DPR_IOCTL(("%d Drain wait finished.\n", __LINE__));
1448 * Flush the WRITE FIFO on the Neo.
1450 * NOTE: Channel lock MUST be held before calling this function!
1452 static void neo_flush_uart_write(struct channel_t *ch)
1457 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
1461 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1462 neo_pci_posting_flush(ch->ch_bd);
1464 for (i = 0; i < 10; i++) {
1466 /* Check to see if the UART feels it completely flushed the FIFO. */
1467 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1469 DPR_IOCTL(("Still flushing TX UART... i: %d\n", i));
1476 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1481 * Flush the READ FIFO on the Neo.
1483 * NOTE: Channel lock MUST be held before calling this function!
1485 static void neo_flush_uart_read(struct channel_t *ch)
1490 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
1494 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
1495 neo_pci_posting_flush(ch->ch_bd);
1497 for (i = 0; i < 10; i++) {
1499 /* Check to see if the UART feels it completely flushed the FIFO. */
1500 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1502 DPR_IOCTL(("Still flushing RX UART... i: %d\n", i));
1511 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch)
1518 uint len_written = 0;
1521 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1524 DGNC_LOCK(ch->ch_lock, lock_flags);
1526 /* No data to write to the UART */
1527 if (ch->ch_w_tail == ch->ch_w_head) {
1528 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1532 /* If port is "stopped", don't send any data to the UART */
1533 if ((ch->ch_flags & CH_FORCED_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) {
1534 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1539 * If FIFOs are disabled. Send data directly to txrx register
1541 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1542 uchar lsrbits = readb(&ch->ch_neo_uart->lsr);
1544 /* Cache the LSR bits for later parsing */
1545 ch->ch_cached_lsr |= lsrbits;
1546 if (ch->ch_cached_lsr & UART_LSR_THRE) {
1547 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
1550 * If RTS Toggle mode is on, turn on RTS now if not already set,
1551 * and make sure we get an event when the data transfer has completed.
1553 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1554 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1555 ch->ch_mostat |= (UART_MCR_RTS);
1556 neo_assert_modem_signals(ch);
1558 ch->ch_tun.un_flags |= (UN_EMPTY);
1561 * If DTR Toggle mode is on, turn on DTR now if not already set,
1562 * and make sure we get an event when the data transfer has completed.
1564 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1565 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1566 ch->ch_mostat |= (UART_MCR_DTR);
1567 neo_assert_modem_signals(ch);
1569 ch->ch_tun.un_flags |= (UN_EMPTY);
1572 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx);
1573 DPR_WRITE(("Tx data: %x\n", ch->ch_wqueue[ch->ch_w_head]));
1575 ch->ch_w_tail &= WQUEUEMASK;
1578 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1583 * We have to do it this way, because of the EXAR TXFIFO count bug.
1585 if ((ch->ch_bd->dvid & 0xf0) < UART_XR17E158_DVID) {
1586 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) {
1587 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1593 n = readb(&ch->ch_neo_uart->tfifo);
1595 if ((unsigned int) n > ch->ch_t_tlevel) {
1596 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1600 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
1603 n = UART_17158_TX_FIFOSIZE - readb(&ch->ch_neo_uart->tfifo);
1606 /* cache head and tail of queue */
1607 head = ch->ch_w_head & WQUEUEMASK;
1608 tail = ch->ch_w_tail & WQUEUEMASK;
1609 qlen = (head - tail) & WQUEUEMASK;
1611 /* Find minimum of the FIFO space, versus queue length */
1616 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
1623 * If RTS Toggle mode is on, turn on RTS now if not already set,
1624 * and make sure we get an event when the data transfer has completed.
1626 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1627 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1628 ch->ch_mostat |= (UART_MCR_RTS);
1629 neo_assert_modem_signals(ch);
1631 ch->ch_tun.un_flags |= (UN_EMPTY);
1635 * If DTR Toggle mode is on, turn on DTR now if not already set,
1636 * and make sure we get an event when the data transfer has completed.
1638 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1639 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1640 ch->ch_mostat |= (UART_MCR_DTR);
1641 neo_assert_modem_signals(ch);
1643 ch->ch_tun.un_flags |= (UN_EMPTY);
1646 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s);
1647 dgnc_sniff_nowait_nolock(ch, "UART WRITE", ch->ch_wqueue + tail, s);
1649 /* Add and flip queue if needed */
1650 tail = (tail + s) & WQUEUEMASK;
1652 ch->ch_txcount += s;
1656 /* Update the final tail */
1657 ch->ch_w_tail = tail & WQUEUEMASK;
1659 if (len_written > 0) {
1660 neo_pci_posting_flush(ch->ch_bd);
1661 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1664 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1668 static void neo_parse_modem(struct channel_t *ch, uchar signals)
1670 volatile uchar msignals = signals;
1672 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1675 DPR_MSIGS(("neo_parse_modem: port: %d msignals: %x\n", ch->ch_portnum, msignals));
1678 * Do altpin switching. Altpin switches DCD and DSR.
1679 * This prolly breaks DSRPACE, so we should be more clever here.
1681 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1682 uchar mswap = msignals;
1684 if (mswap & UART_MSR_DDCD) {
1685 msignals &= ~UART_MSR_DDCD;
1686 msignals |= UART_MSR_DDSR;
1688 if (mswap & UART_MSR_DDSR) {
1689 msignals &= ~UART_MSR_DDSR;
1690 msignals |= UART_MSR_DDCD;
1692 if (mswap & UART_MSR_DCD) {
1693 msignals &= ~UART_MSR_DCD;
1694 msignals |= UART_MSR_DSR;
1696 if (mswap & UART_MSR_DSR) {
1697 msignals &= ~UART_MSR_DSR;
1698 msignals |= UART_MSR_DCD;
1702 /* Scrub off lower bits. They signify delta's, which I don't care about */
1705 if (msignals & UART_MSR_DCD)
1706 ch->ch_mistat |= UART_MSR_DCD;
1708 ch->ch_mistat &= ~UART_MSR_DCD;
1710 if (msignals & UART_MSR_DSR)
1711 ch->ch_mistat |= UART_MSR_DSR;
1713 ch->ch_mistat &= ~UART_MSR_DSR;
1715 if (msignals & UART_MSR_RI)
1716 ch->ch_mistat |= UART_MSR_RI;
1718 ch->ch_mistat &= ~UART_MSR_RI;
1720 if (msignals & UART_MSR_CTS)
1721 ch->ch_mistat |= UART_MSR_CTS;
1723 ch->ch_mistat &= ~UART_MSR_CTS;
1725 DPR_MSIGS(("Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
1727 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
1728 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
1729 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
1730 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
1731 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
1732 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)));
1736 /* Make the UART raise any of the output signals we want up */
1737 static void neo_assert_modem_signals(struct channel_t *ch)
1741 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1744 out = ch->ch_mostat;
1746 if (ch->ch_flags & CH_LOOPBACK)
1747 out |= UART_MCR_LOOP;
1749 writeb(out, &ch->ch_neo_uart->mcr);
1750 neo_pci_posting_flush(ch->ch_bd);
1752 /* Give time for the UART to actually raise/drop the signals */
1757 static void neo_send_start_character(struct channel_t *ch)
1759 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1762 if (ch->ch_startc != _POSIX_VDISABLE) {
1764 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1765 neo_pci_posting_flush(ch->ch_bd);
1771 static void neo_send_stop_character(struct channel_t *ch)
1773 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1776 if (ch->ch_stopc != _POSIX_VDISABLE) {
1777 ch->ch_xoff_sends++;
1778 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1779 neo_pci_posting_flush(ch->ch_bd);
1788 static void neo_uart_init(struct channel_t *ch)
1791 writeb(0, &ch->ch_neo_uart->ier);
1792 writeb(0, &ch->ch_neo_uart->efr);
1793 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1796 /* Clear out UART and FIFO */
1797 readb(&ch->ch_neo_uart->txrx);
1798 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1799 readb(&ch->ch_neo_uart->lsr);
1800 readb(&ch->ch_neo_uart->msr);
1802 ch->ch_flags |= CH_FIFO_ENABLED;
1804 /* Assert any signals we want up */
1805 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1806 neo_pci_posting_flush(ch->ch_bd);
1811 * Make the UART completely turn off.
1813 static void neo_uart_off(struct channel_t *ch)
1815 /* Turn off UART enhanced bits */
1816 writeb(0, &ch->ch_neo_uart->efr);
1818 /* Stop all interrupts from occurring. */
1819 writeb(0, &ch->ch_neo_uart->ier);
1820 neo_pci_posting_flush(ch->ch_bd);
1824 static uint neo_get_uart_bytes_left(struct channel_t *ch)
1827 uchar lsr = readb(&ch->ch_neo_uart->lsr);
1829 /* We must cache the LSR as some of the bits get reset once read... */
1830 ch->ch_cached_lsr |= lsr;
1832 /* Determine whether the Transmitter is empty or not */
1833 if (!(lsr & UART_LSR_TEMT)) {
1834 if (ch->ch_flags & CH_TX_FIFO_EMPTY) {
1835 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1839 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1847 /* Channel lock MUST be held by the calling function! */
1848 static void neo_send_break(struct channel_t *ch, int msecs)
1851 * If we receive a time of 0, this means turn off the break.
1854 if (ch->ch_flags & CH_BREAK_SENDING) {
1855 uchar temp = readb(&ch->ch_neo_uart->lcr);
1856 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1857 neo_pci_posting_flush(ch->ch_bd);
1858 ch->ch_flags &= ~(CH_BREAK_SENDING);
1859 ch->ch_stop_sending_break = 0;
1860 DPR_IOCTL(("Finishing UART_LCR_SBC! finished: %lx\n", jiffies));
1866 * Set the time we should stop sending the break.
1867 * If we are already sending a break, toss away the existing
1868 * time to stop, and use this new value instead.
1870 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1872 /* Tell the UART to start sending the break */
1873 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1874 uchar temp = readb(&ch->ch_neo_uart->lcr);
1875 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1876 neo_pci_posting_flush(ch->ch_bd);
1877 ch->ch_flags |= (CH_BREAK_SENDING);
1878 DPR_IOCTL(("Port %d. Starting UART_LCR_SBC! start: %lx should end: %lx\n",
1879 ch->ch_portnum, jiffies, ch->ch_stop_sending_break));
1885 * neo_send_immediate_char.
1887 * Sends a specific character as soon as possible to the UART,
1888 * jumping over any bytes that might be in the write queue.
1890 * The channel lock MUST be held by the calling function.
1892 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c)
1894 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1897 writeb(c, &ch->ch_neo_uart->txrx);
1898 neo_pci_posting_flush(ch->ch_bd);
1902 static unsigned int neo_read_eeprom(unsigned char __iomem *base, unsigned int address)
1904 unsigned int enable;
1906 unsigned int databit;
1909 /* enable chip select */
1910 writeb(NEO_EECS, base + NEO_EEREG);
1912 enable = (address | 0x180);
1914 for (bits = 9; bits--; ) {
1915 databit = (enable & (1 << bits)) ? NEO_EEDI : 0;
1916 /* Set read address */
1917 writeb(databit | NEO_EECS, base + NEO_EEREG);
1918 writeb(databit | NEO_EECS | NEO_EECK, base + NEO_EEREG);
1923 for (bits = 17; bits--; ) {
1924 /* clock to EEPROM */
1925 writeb(NEO_EECS, base + NEO_EEREG);
1926 writeb(NEO_EECS | NEO_EECK, base + NEO_EEREG);
1929 if (readb(base + NEO_EEREG) & NEO_EEDO)
1933 /* clock falling edge */
1934 writeb(NEO_EECS, base + NEO_EEREG);
1936 /* drop chip select */
1937 writeb(0x00, base + NEO_EEREG);
1943 static void neo_vpd(struct dgnc_board *brd)
1948 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
1951 if (!brd->re_map_membase)
1954 /* Store the VPD into our buffer */
1955 for (i = 0; i < NEO_VPD_IMAGESIZE; i++) {
1956 a = neo_read_eeprom(brd->re_map_membase, i);
1957 brd->vpd[i*2] = a & 0xff;
1958 brd->vpd[(i*2)+1] = (a >> 8) & 0xff;
1961 if (((brd->vpd[0x08] != 0x82) /* long resource name tag */
1962 && (brd->vpd[0x10] != 0x82)) /* long resource name tag (PCI-66 files)*/
1963 || (brd->vpd[0x7F] != 0x78)) /* small resource end tag */
1965 memset(brd->vpd, '\0', NEO_VPD_IMAGESIZE);
1968 /* Search for the serial number */
1969 for (i = 0; i < NEO_VPD_IMAGEBYTES - 3; i++) {
1970 if (brd->vpd[i] == 'S' && brd->vpd[i + 1] == 'N') {
1971 strncpy(brd->serial_num, &(brd->vpd[i + 3]), 9);