3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright * 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_phy.c - Routines for configuring and accessing the PHY
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright * 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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58 #include "et131x_version.h"
59 #include "et131x_defs.h"
61 #include <linux/pci.h>
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/slab.h>
70 #include <linux/ctype.h>
71 #include <linux/string.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
75 #include <linux/delay.h>
77 #include <linux/bitops.h>
78 #include <asm/system.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
85 #include <linux/random.h>
87 #include "et1310_phy.h"
88 #include "et1310_pm.h"
89 #include "et1310_jagcore.h"
91 #include "et131x_adapter.h"
92 #include "et131x_netdev.h"
93 #include "et131x_initpci.h"
95 #include "et1310_address_map.h"
96 #include "et1310_tx.h"
97 #include "et1310_rx.h"
98 #include "et1310_mac.h"
100 /* Prototypes for functions with local scope */
101 static int et131x_xcvr_init(struct et131x_adapter *adapter);
104 * PhyMiRead - Read from the PHY through the MII Interface on the MAC
105 * @adapter: pointer to our private adapter structure
106 * @xcvrAddr: the address of the transciever
107 * @xcvrReg: the register to read
108 * @value: pointer to a 16-bit value in which the value will be stored
110 * Returns 0 on success, errno on failure (as defined in errno.h)
112 int PhyMiRead(struct et131x_adapter *adapter, uint8_t xcvrAddr,
113 uint8_t xcvrReg, uint16_t *value)
115 struct _MAC_t __iomem *mac = &adapter->regs->mac;
118 MII_MGMT_ADDR_t miiAddr;
119 MII_MGMT_CMD_t miiCmd;
120 MII_MGMT_INDICATOR_t miiIndicator;
122 /* Save a local copy of the registers we are dealing with so we can
125 miiAddr.value = readl(&mac->mii_mgmt_addr.value);
126 miiCmd.value = readl(&mac->mii_mgmt_cmd.value);
128 /* Stop the current operation */
129 writel(0, &mac->mii_mgmt_cmd.value);
131 /* Set up the register we need to read from on the correct PHY */
133 MII_MGMT_ADDR_t mii_mgmt_addr = { 0 };
135 mii_mgmt_addr.bits.phy_addr = xcvrAddr;
136 mii_mgmt_addr.bits.reg_addr = xcvrReg;
137 writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value);
140 /* Kick the read cycle off */
143 writel(0x1, &mac->mii_mgmt_cmd.value);
148 miiIndicator.value = readl(&mac->mii_mgmt_indicator.value);
149 } while ((miiIndicator.bits.not_valid || miiIndicator.bits.busy) &&
152 /* If we hit the max delay, we could not read the register */
154 dev_warn(&adapter->pdev->dev,
155 "xcvrReg 0x%08x could not be read\n", xcvrReg);
156 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
162 /* If we hit here we were able to read the register and we need to
163 * return the value to the caller
165 /* TODO: make this stuff a simple readw()?! */
167 MII_MGMT_STAT_t mii_mgmt_stat;
169 mii_mgmt_stat.value = readl(&mac->mii_mgmt_stat.value);
170 *value = (uint16_t) mii_mgmt_stat.bits.phy_stat;
173 /* Stop the read operation */
174 writel(0, &mac->mii_mgmt_cmd.value);
176 /* set the registers we touched back to the state at which we entered
179 writel(miiAddr.value, &mac->mii_mgmt_addr.value);
180 writel(miiCmd.value, &mac->mii_mgmt_cmd.value);
186 * MiWrite - Write to a PHY register through the MII interface of the MAC
187 * @adapter: pointer to our private adapter structure
188 * @xcvrReg: the register to read
189 * @value: 16-bit value to write
191 * Return 0 on success, errno on failure (as defined in errno.h)
193 int MiWrite(struct et131x_adapter *adapter, uint8_t xcvrReg, uint16_t value)
195 struct _MAC_t __iomem *mac = &adapter->regs->mac;
197 uint8_t xcvrAddr = adapter->Stats.xcvr_addr;
199 MII_MGMT_ADDR_t miiAddr;
200 MII_MGMT_CMD_t miiCmd;
201 MII_MGMT_INDICATOR_t miiIndicator;
203 /* Save a local copy of the registers we are dealing with so we can
206 miiAddr.value = readl(&mac->mii_mgmt_addr.value);
207 miiCmd.value = readl(&mac->mii_mgmt_cmd.value);
209 /* Stop the current operation */
210 writel(0, &mac->mii_mgmt_cmd.value);
212 /* Set up the register we need to write to on the correct PHY */
214 MII_MGMT_ADDR_t mii_mgmt_addr;
216 mii_mgmt_addr.bits.phy_addr = xcvrAddr;
217 mii_mgmt_addr.bits.reg_addr = xcvrReg;
218 writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value);
221 /* Add the value to write to the registers to the mac */
222 writel(value, &mac->mii_mgmt_ctrl.value);
228 miiIndicator.value = readl(&mac->mii_mgmt_indicator.value);
229 } while (miiIndicator.bits.busy && delay < 100);
231 /* If we hit the max delay, we could not write the register */
235 dev_warn(&adapter->pdev->dev,
236 "xcvrReg 0x%08x could not be written", xcvrReg);
237 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
239 dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
240 readl(&mac->mii_mgmt_cmd.value));
242 MiRead(adapter, xcvrReg, &TempValue);
247 /* Stop the write operation */
248 writel(0, &mac->mii_mgmt_cmd.value);
250 /* set the registers we touched back to the state at which we entered
253 writel(miiAddr.value, &mac->mii_mgmt_addr.value);
254 writel(miiCmd.value, &mac->mii_mgmt_cmd.value);
260 * et131x_xcvr_find - Find the PHY ID
261 * @adapter: pointer to our private adapter structure
263 * Returns 0 on success, errno on failure (as defined in errno.h)
265 int et131x_xcvr_find(struct et131x_adapter *adapter)
267 int status = -ENODEV;
273 /* We need to get xcvr id and address we just get the first one */
274 for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
275 /* Read the ID from the PHY */
276 PhyMiRead(adapter, xcvr_addr,
277 (uint8_t) offsetof(MI_REGS_t, idr1),
279 PhyMiRead(adapter, xcvr_addr,
280 (uint8_t) offsetof(MI_REGS_t, idr2),
283 xcvr_id = (uint32_t) ((idr1.value << 16) | idr2.value);
285 if ((idr1.value != 0) && (idr1.value != 0xffff)) {
286 adapter->Stats.xcvr_id = xcvr_id;
287 adapter->Stats.xcvr_addr = xcvr_addr;
297 * et131x_setphy_normal - Set PHY for normal operation.
298 * @adapter: pointer to our private adapter structure
300 * Used by Power Management to force the PHY into 10 Base T half-duplex mode,
301 * when going to D3 in WOL mode. Also used during initialization to set the
302 * PHY for normal operation.
304 int et131x_setphy_normal(struct et131x_adapter *adapter)
308 /* Make sure the PHY is powered up */
309 ET1310_PhyPowerDown(adapter, 0);
310 status = et131x_xcvr_init(adapter);
315 * et131x_xcvr_init - Init the phy if we are setting it into force mode
316 * @adapter: pointer to our private adapter structure
318 * Returns 0 on success, errno on failure (as defined in errno.h)
320 static int et131x_xcvr_init(struct et131x_adapter *adapter)
327 /* Zero out the adapter structure variable representing BMSR */
328 adapter->Bmsr.value = 0;
330 MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, isr), &isr.value);
332 MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, imr), &imr.value);
334 /* Set the link status interrupt only. Bad behavior when link status
335 * and auto neg are set, we run into a nested interrupt problem
337 imr.bits.int_en = 0x1;
338 imr.bits.link_status = 0x1;
339 imr.bits.autoneg_status = 0x1;
341 MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, imr), imr.value);
343 /* Set the LED behavior such that LED 1 indicates speed (off =
344 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
345 * link and activity (on for link, blink off for activity).
347 * NOTE: Some customizations have been added here for specific
348 * vendors; The LED behavior is now determined by vendor data in the
349 * EEPROM. However, the above description is the default.
351 if ((adapter->eepromData[1] & 0x4) == 0) {
352 MiRead(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2),
354 if ((adapter->eepromData[1] & 0x8) == 0)
355 lcr2.bits.led_tx_rx = 0x3;
357 lcr2.bits.led_tx_rx = 0x4;
358 lcr2.bits.led_link = 0xa;
359 MiWrite(adapter, (uint8_t) offsetof(MI_REGS_t, lcr2),
363 /* Determine if we need to go into a force mode and set it */
364 if (adapter->AiForceSpeed == 0 && adapter->AiForceDpx == 0) {
365 if ((adapter->RegistryFlowControl == TxOnly) ||
366 (adapter->RegistryFlowControl == Both)) {
367 ET1310_PhyAccessMiBit(adapter,
368 TRUEPHY_BIT_SET, 4, 11, NULL);
370 ET1310_PhyAccessMiBit(adapter,
371 TRUEPHY_BIT_CLEAR, 4, 11, NULL);
374 if (adapter->RegistryFlowControl == Both) {
375 ET1310_PhyAccessMiBit(adapter,
376 TRUEPHY_BIT_SET, 4, 10, NULL);
378 ET1310_PhyAccessMiBit(adapter,
379 TRUEPHY_BIT_CLEAR, 4, 10, NULL);
382 /* Set the phy to autonegotiation */
383 ET1310_PhyAutoNeg(adapter, true);
385 /* NOTE - Do we need this? */
386 ET1310_PhyAccessMiBit(adapter, TRUEPHY_BIT_SET, 0, 9, NULL);
389 ET1310_PhyAutoNeg(adapter, false);
391 /* Set to the correct force mode. */
392 if (adapter->AiForceDpx != 1) {
393 if ((adapter->RegistryFlowControl == TxOnly) ||
394 (adapter->RegistryFlowControl == Both)) {
395 ET1310_PhyAccessMiBit(adapter,
396 TRUEPHY_BIT_SET, 4, 11,
399 ET1310_PhyAccessMiBit(adapter,
400 TRUEPHY_BIT_CLEAR, 4, 11,
404 if (adapter->RegistryFlowControl == Both) {
405 ET1310_PhyAccessMiBit(adapter,
406 TRUEPHY_BIT_SET, 4, 10,
409 ET1310_PhyAccessMiBit(adapter,
410 TRUEPHY_BIT_CLEAR, 4, 10,
414 ET1310_PhyAccessMiBit(adapter,
415 TRUEPHY_BIT_CLEAR, 4, 10, NULL);
416 ET1310_PhyAccessMiBit(adapter,
417 TRUEPHY_BIT_CLEAR, 4, 11, NULL);
420 switch (adapter->AiForceSpeed) {
422 if (adapter->AiForceDpx == 1)
423 TPAL_SetPhy10HalfDuplex(adapter);
424 else if (adapter->AiForceDpx == 2)
425 TPAL_SetPhy10FullDuplex(adapter);
427 TPAL_SetPhy10Force(adapter);
430 if (adapter->AiForceDpx == 1)
431 TPAL_SetPhy100HalfDuplex(adapter);
432 else if (adapter->AiForceDpx == 2)
433 TPAL_SetPhy100FullDuplex(adapter);
435 TPAL_SetPhy100Force(adapter);
438 TPAL_SetPhy1000FullDuplex(adapter);
446 void et131x_Mii_check(struct et131x_adapter *etdev,
447 MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints)
450 uint32_t autoneg_status;
454 uint32_t masterslave;
458 if (bmsr_ints.bits.link_status) {
459 if (bmsr.bits.link_status) {
460 etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
462 /* Update our state variables and indicate the
465 spin_lock_irqsave(&etdev->Lock, flags);
467 etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT;
468 etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION;
470 spin_unlock_irqrestore(&etdev->Lock, flags);
472 netif_carrier_on(etdev->netdev);
474 dev_warn(&etdev->pdev->dev,
475 "Link down - cable problem ?\n");
477 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
478 /* NOTE - Is there a way to query this without
480 * && TRU_QueryCoreType(etdev->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
484 MiRead(etdev, 0x12, &Register18);
485 MiWrite(etdev, 0x12, Register18 | 0x4);
486 MiWrite(etdev, 0x10, Register18 | 0x8402);
487 MiWrite(etdev, 0x11, Register18 | 511);
488 MiWrite(etdev, 0x12, Register18);
491 /* For the first N seconds of life, we are in "link
492 * detection" When we are in this state, we should
493 * only report "connected". When the LinkDetection
494 * Timer expires, we can report disconnected (handled
495 * in the LinkDetectionDPC).
497 if (!(etdev->Flags & fMP_ADAPTER_LINK_DETECTION) ||
498 (etdev->MediaState == NETIF_STATUS_MEDIA_DISCONNECT)) {
499 spin_lock_irqsave(&etdev->Lock, flags);
501 NETIF_STATUS_MEDIA_DISCONNECT;
502 spin_unlock_irqrestore(&etdev->Lock,
505 netif_carrier_off(etdev->netdev);
508 etdev->linkspeed = 0;
509 etdev->duplex_mode = 0;
511 /* Free the packets being actively sent & stopped */
512 et131x_free_busy_send_packets(etdev);
514 /* Re-initialize the send structures */
515 et131x_init_send(etdev);
517 /* Reset the RFD list and re-start RU */
518 et131x_reset_recv(etdev);
521 * Bring the device back to the state it was during
522 * init prior to autonegotiation being complete. This
523 * way, when we get the auto-neg complete interrupt,
524 * we can complete init by calling ConfigMacREGS2.
526 et131x_soft_reset(etdev);
528 /* Setup ET1310 as per the documentation */
529 et131x_adapter_setup(etdev);
531 /* Setup the PHY into coma mode until the cable is
534 if (etdev->RegistryPhyComa == 1)
535 EnablePhyComa(etdev);
539 if (bmsr_ints.bits.auto_neg_complete ||
540 (etdev->AiForceDpx == 3 && bmsr_ints.bits.link_status)) {
541 if (bmsr.bits.auto_neg_complete || etdev->AiForceDpx == 3) {
542 ET1310_PhyLinkStatus(etdev,
543 &link_status, &autoneg_status,
544 &speed, &duplex, &mdi_mdix,
545 &masterslave, &polarity);
547 etdev->linkspeed = speed;
548 etdev->duplex_mode = duplex;
550 etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
552 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
554 * NOTE - Is there a way to query this without
556 * && TRU_QueryCoreType(etdev->hTruePhy, 0)== EMI_TRUEPHY_A13O) {
560 MiRead(etdev, 0x12, &Register18);
561 MiWrite(etdev, 0x12, Register18 | 0x4);
562 MiWrite(etdev, 0x10, Register18 | 0x8402);
563 MiWrite(etdev, 0x11, Register18 | 511);
564 MiWrite(etdev, 0x12, Register18);
567 ConfigFlowControl(etdev);
569 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS &&
570 etdev->RegistryJumboPacket > 2048)
571 ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff,
574 SetRxDmaTimer(etdev);
575 ConfigMACRegs2(etdev);
581 * TPAL_SetPhy10HalfDuplex - Force the phy into 10 Base T Half Duplex mode.
582 * @etdev: pointer to the adapter structure
584 * Also sets the MAC so it is syncd up properly
586 void TPAL_SetPhy10HalfDuplex(struct et131x_adapter *etdev)
589 ET1310_PhyPowerDown(etdev, 1);
591 /* First we need to turn off all other advertisement */
592 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
594 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
596 /* Set our advertise values accordingly */
597 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_HALF);
600 ET1310_PhyPowerDown(etdev, 0);
604 * TPAL_SetPhy10FullDuplex - Force the phy into 10 Base T Full Duplex mode.
605 * @etdev: pointer to the adapter structure
607 * Also sets the MAC so it is syncd up properly
609 void TPAL_SetPhy10FullDuplex(struct et131x_adapter *etdev)
612 ET1310_PhyPowerDown(etdev, 1);
614 /* First we need to turn off all other advertisement */
615 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
617 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
619 /* Set our advertise values accordingly */
620 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
623 ET1310_PhyPowerDown(etdev, 0);
627 * TPAL_SetPhy10Force - Force Base-T FD mode WITHOUT using autonegotiation
628 * @etdev: pointer to the adapter structure
630 void TPAL_SetPhy10Force(struct et131x_adapter *etdev)
633 ET1310_PhyPowerDown(etdev, 1);
635 /* Disable autoneg */
636 ET1310_PhyAutoNeg(etdev, false);
638 /* Disable all advertisement */
639 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
640 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
641 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
644 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_10MBPS);
646 /* Force Full duplex */
647 ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
650 ET1310_PhyPowerDown(etdev, 0);
654 * TPAL_SetPhy100HalfDuplex - Force 100 Base T Half Duplex mode.
655 * @etdev: pointer to the adapter structure
657 * Also sets the MAC so it is syncd up properly.
659 void TPAL_SetPhy100HalfDuplex(struct et131x_adapter *etdev)
662 ET1310_PhyPowerDown(etdev, 1);
664 /* first we need to turn off all other advertisement */
665 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
667 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
669 /* Set our advertise values accordingly */
670 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_HALF);
673 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
676 ET1310_PhyPowerDown(etdev, 0);
680 * TPAL_SetPhy100FullDuplex - Force 100 Base T Full Duplex mode.
681 * @etdev: pointer to the adapter structure
683 * Also sets the MAC so it is syncd up properly
685 void TPAL_SetPhy100FullDuplex(struct et131x_adapter *etdev)
688 ET1310_PhyPowerDown(etdev, 1);
690 /* First we need to turn off all other advertisement */
691 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
693 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
695 /* Set our advertise values accordingly */
696 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
699 ET1310_PhyPowerDown(etdev, 0);
703 * TPAL_SetPhy100Force - Force 100 BaseT FD mode WITHOUT using autonegotiation
704 * @etdev: pointer to the adapter structure
706 void TPAL_SetPhy100Force(struct et131x_adapter *etdev)
709 ET1310_PhyPowerDown(etdev, 1);
711 /* Disable autoneg */
712 ET1310_PhyAutoNeg(etdev, false);
714 /* Disable all advertisement */
715 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
716 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
717 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
720 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
722 /* Force Full duplex */
723 ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
726 ET1310_PhyPowerDown(etdev, 0);
730 * TPAL_SetPhy1000FullDuplex - Force 1000 Base T Full Duplex mode
731 * @etdev: pointer to the adapter structure
733 * Also sets the MAC so it is syncd up properly.
735 void TPAL_SetPhy1000FullDuplex(struct et131x_adapter *etdev)
738 ET1310_PhyPowerDown(etdev, 1);
740 /* first we need to turn off all other advertisement */
741 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
743 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
745 /* set our advertise values accordingly */
746 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
749 ET1310_PhyPowerDown(etdev, 0);
753 * TPAL_SetPhyAutoNeg - Set phy to autonegotiation mode.
754 * @etdev: pointer to the adapter structure
756 void TPAL_SetPhyAutoNeg(struct et131x_adapter *etdev)
759 ET1310_PhyPowerDown(etdev, 1);
761 /* Turn on advertisement of all capabilities */
762 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_BOTH);
764 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_BOTH);
766 if (etdev->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
767 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
769 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
771 /* Make sure auto-neg is ON (it is disabled in FORCE modes) */
772 ET1310_PhyAutoNeg(etdev, true);
775 ET1310_PhyPowerDown(etdev, 0);
780 * The routines which follow provide low-level access to the PHY, and are used
781 * primarily by the routines above (although there are a few places elsewhere
782 * in the driver where this level of access is required).
785 static const uint16_t ConfigPhy[25][2] = {
786 /* Reg Value Register */
788 {0x880B, 0x0926}, /* AfeIfCreg4B1000Msbs */
789 {0x880C, 0x0926}, /* AfeIfCreg4B100Msbs */
790 {0x880D, 0x0926}, /* AfeIfCreg4B10Msbs */
792 {0x880E, 0xB4D3}, /* AfeIfCreg4B1000Lsbs */
793 {0x880F, 0xB4D3}, /* AfeIfCreg4B100Lsbs */
794 {0x8810, 0xB4D3}, /* AfeIfCreg4B10Lsbs */
796 {0x8805, 0xB03E}, /* AfeIfCreg3B1000Msbs */
797 {0x8806, 0xB03E}, /* AfeIfCreg3B100Msbs */
798 {0x8807, 0xFF00}, /* AfeIfCreg3B10Msbs */
800 {0x8808, 0xE090}, /* AfeIfCreg3B1000Lsbs */
801 {0x8809, 0xE110}, /* AfeIfCreg3B100Lsbs */
802 {0x880A, 0x0000}, /* AfeIfCreg3B10Lsbs */
804 {0x300D, 1}, /* DisableNorm */
806 {0x280C, 0x0180}, /* LinkHoldEnd */
808 {0x1C21, 0x0002}, /* AlphaM */
810 {0x3821, 6}, /* FfeLkgTx0 */
811 {0x381D, 1}, /* FfeLkg1g4 */
812 {0x381E, 1}, /* FfeLkg1g5 */
813 {0x381F, 1}, /* FfeLkg1g6 */
814 {0x3820, 1}, /* FfeLkg1g7 */
816 {0x8402, 0x01F0}, /* Btinact */
817 {0x800E, 20}, /* LftrainTime */
818 {0x800F, 24}, /* DvguardTime */
819 {0x8010, 46}, /* IdlguardTime */
825 /* condensed version of the phy initialization routine */
826 void ET1310_PhyInit(struct et131x_adapter *etdev)
828 uint16_t data, index;
833 /* get the identity (again ?) */
834 MiRead(etdev, PHY_ID_1, &data);
835 MiRead(etdev, PHY_ID_2, &data);
837 /* what does this do/achieve ? */
838 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
839 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
841 /* read modem register 0402, should I do something with the return
843 MiWrite(etdev, PHY_INDEX_REG, 0x0402);
844 MiRead(etdev, PHY_DATA_REG, &data);
846 /* what does this do/achieve ? */
847 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
849 /* get the identity (again ?) */
850 MiRead(etdev, PHY_ID_1, &data);
851 MiRead(etdev, PHY_ID_2, &data);
853 /* what does this achieve ? */
854 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
855 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
857 /* read modem register 0402, should I do something with
859 MiWrite(etdev, PHY_INDEX_REG, 0x0402);
860 MiRead(etdev, PHY_DATA_REG, &data);
862 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
864 /* what does this achieve (should return 0x1040) */
865 MiRead(etdev, PHY_CONTROL, &data);
866 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
867 MiWrite(etdev, PHY_CONTROL, 0x1840);
869 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0007);
871 /* here the writing of the array starts.... */
873 while (ConfigPhy[index][0] != 0x0000) {
875 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
876 MiWrite(etdev, PHY_DATA_REG, ConfigPhy[index][1]);
879 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
880 MiRead(etdev, PHY_DATA_REG, &data);
882 /* do a check on the value read back ? */
885 /* here the writing of the array ends... */
887 MiRead(etdev, PHY_CONTROL, &data); /* 0x1840 */
888 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data);/* should read 0007 */
889 MiWrite(etdev, PHY_CONTROL, 0x1040);
890 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
893 void ET1310_PhyReset(struct et131x_adapter *etdev)
895 MiWrite(etdev, PHY_CONTROL, 0x8000);
898 void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down)
902 MiRead(etdev, PHY_CONTROL, &data);
907 MiWrite(etdev, PHY_CONTROL, data);
911 MiWrite(etdev, PHY_CONTROL, data);
915 void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable)
919 MiRead(etdev, PHY_CONTROL, &data);
921 if (enable == true) {
922 /* Autonegotiation ON */
924 MiWrite(etdev, PHY_CONTROL, data);
926 /* Autonegotiation OFF */
928 MiWrite(etdev, PHY_CONTROL, data);
932 void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, uint16_t duplex)
936 MiRead(etdev, PHY_CONTROL, &data);
938 if (duplex == TRUEPHY_DUPLEX_FULL) {
939 /* Set Full Duplex */
941 MiWrite(etdev, PHY_CONTROL, data);
943 /* Set Half Duplex */
945 MiWrite(etdev, PHY_CONTROL, data);
949 void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, uint16_t speed)
953 /* Read the PHY control register */
954 MiRead(etdev, PHY_CONTROL, &data);
956 /* Clear all Speed settings (Bits 6, 13) */
959 /* Reset the speed bits based on user selection */
961 case TRUEPHY_SPEED_10MBPS:
962 /* Bits already cleared above, do nothing */
965 case TRUEPHY_SPEED_100MBPS:
966 /* 100M == Set bit 13 */
970 case TRUEPHY_SPEED_1000MBPS:
976 /* Write back the new speed */
977 MiWrite(etdev, PHY_CONTROL, data);
980 void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev,
985 /* Read the PHY 1000 Base-T Control Register */
986 MiRead(etdev, PHY_1000_CONTROL, &data);
992 case TRUEPHY_ADV_DUPLEX_NONE:
993 /* Duplex already cleared, do nothing */
996 case TRUEPHY_ADV_DUPLEX_FULL:
1001 case TRUEPHY_ADV_DUPLEX_HALF:
1006 case TRUEPHY_ADV_DUPLEX_BOTH:
1012 /* Write back advertisement */
1013 MiWrite(etdev, PHY_1000_CONTROL, data);
1016 void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev,
1021 /* Read the Autonegotiation Register (10/100) */
1022 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
1024 /* Clear bits 7,8 */
1028 case TRUEPHY_ADV_DUPLEX_NONE:
1029 /* Duplex already cleared, do nothing */
1032 case TRUEPHY_ADV_DUPLEX_FULL:
1037 case TRUEPHY_ADV_DUPLEX_HALF:
1042 case TRUEPHY_ADV_DUPLEX_BOTH:
1049 /* Write back advertisement */
1050 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
1053 void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev,
1058 /* Read the Autonegotiation Register (10/100) */
1059 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
1061 /* Clear bits 5,6 */
1065 case TRUEPHY_ADV_DUPLEX_NONE:
1066 /* Duplex already cleared, do nothing */
1069 case TRUEPHY_ADV_DUPLEX_FULL:
1074 case TRUEPHY_ADV_DUPLEX_HALF:
1079 case TRUEPHY_ADV_DUPLEX_BOTH:
1086 /* Write back advertisement */
1087 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
1090 void ET1310_PhyLinkStatus(struct et131x_adapter *etdev,
1091 uint8_t *link_status,
1093 uint32_t *linkspeed,
1094 uint32_t *duplex_mode,
1096 uint32_t *masterslave, uint32_t *polarity)
1098 uint16_t mistatus = 0;
1099 uint16_t is1000BaseT = 0;
1100 uint16_t vmi_phystatus = 0;
1101 uint16_t control = 0;
1103 MiRead(etdev, PHY_STATUS, &mistatus);
1104 MiRead(etdev, PHY_1000_STATUS, &is1000BaseT);
1105 MiRead(etdev, PHY_PHY_STATUS, &vmi_phystatus);
1106 MiRead(etdev, PHY_CONTROL, &control);
1110 (unsigned char)((vmi_phystatus & 0x0040) ? 1 : 0);
1115 (control & 0x1000) ? ((vmi_phystatus & 0x0020) ?
1116 TRUEPHY_ANEG_COMPLETE :
1117 TRUEPHY_ANEG_NOT_COMPLETE) :
1118 TRUEPHY_ANEG_DISABLED;
1122 *linkspeed = (vmi_phystatus & 0x0300) >> 8;
1125 *duplex_mode = (vmi_phystatus & 0x0080) >> 7;
1128 /* NOTE: Need to complete this */
1133 (is1000BaseT & 0x4000) ? TRUEPHY_CFG_MASTER :
1139 (vmi_phystatus & 0x0400) ? TRUEPHY_POLARITY_INVERTED :
1140 TRUEPHY_POLARITY_NORMAL;
1144 void ET1310_PhyAndOrReg(struct et131x_adapter *etdev,
1145 uint16_t regnum, uint16_t andMask, uint16_t orMask)
1149 /* Read the requested register */
1150 MiRead(etdev, regnum, ®);
1152 /* Apply the AND mask */
1155 /* Apply the OR mask */
1158 /* Write the value back to the register */
1159 MiWrite(etdev, regnum, reg);
1162 void ET1310_PhyAccessMiBit(struct et131x_adapter *etdev, uint16_t action,
1163 uint16_t regnum, uint16_t bitnum, uint8_t *value)
1168 /* Create a mask to isolate the requested bit */
1169 mask = 0x0001 << bitnum;
1171 /* Read the requested register */
1172 MiRead(etdev, regnum, ®);
1175 case TRUEPHY_BIT_READ:
1177 *value = (reg & mask) >> bitnum;
1180 case TRUEPHY_BIT_SET:
1182 MiWrite(etdev, regnum, reg);
1185 case TRUEPHY_BIT_CLEAR:
1187 MiWrite(etdev, regnum, reg);