2 * AD7190 AD7192 AD7195 SPI ADC driver
4 * Copyright 2011-2012 Analog Devices Inc.
6 * Licensed under the GPL-2.
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/kfifo_buf.h>
24 #include <linux/iio/trigger.h>
25 #include <linux/iio/trigger_consumer.h>
30 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
31 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
32 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
33 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
34 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
35 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
36 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
37 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit
38 * (AD7792)/24-bit (AD7192)) */
39 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register
40 * (RW, 16-bit (AD7792)/24-bit (AD7192)) */
42 /* Communications Register Bit Designations (AD7192_REG_COMM) */
43 #define AD7192_COMM_WEN (1 << 7) /* Write Enable */
44 #define AD7192_COMM_WRITE (0 << 6) /* Write Operation */
45 #define AD7192_COMM_READ (1 << 6) /* Read Operation */
46 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
47 #define AD7192_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */
49 /* Status Register Bit Designations (AD7192_REG_STAT) */
50 #define AD7192_STAT_RDY (1 << 7) /* Ready */
51 #define AD7192_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */
52 #define AD7192_STAT_NOREF (1 << 5) /* Error no external reference */
53 #define AD7192_STAT_PARITY (1 << 4) /* Parity */
54 #define AD7192_STAT_CH3 (1 << 2) /* Channel 3 */
55 #define AD7192_STAT_CH2 (1 << 1) /* Channel 2 */
56 #define AD7192_STAT_CH1 (1 << 0) /* Channel 1 */
58 /* Mode Register Bit Designations (AD7192_REG_MODE) */
59 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
60 #define AD7192_MODE_DAT_STA (1 << 20) /* Status Register transmission */
61 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
62 #define AD7192_MODE_SINC3 (1 << 15) /* SINC3 Filter Select */
63 #define AD7192_MODE_ACX (1 << 14) /* AC excitation enable(AD7195 only)*/
64 #define AD7192_MODE_ENPAR (1 << 13) /* Parity Enable */
65 #define AD7192_MODE_CLKDIV (1 << 12) /* Clock divide by 2 (AD7190/2 only)*/
66 #define AD7192_MODE_SCYCLE (1 << 11) /* Single cycle conversion */
67 #define AD7192_MODE_REJ60 (1 << 10) /* 50/60Hz notch filter */
68 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
70 /* Mode Register: AD7192_MODE_SEL options */
71 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
72 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
73 #define AD7192_MODE_IDLE 2 /* Idle Mode */
74 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
75 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
76 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
77 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
78 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
80 /* Mode Register: AD7192_MODE_CLKSRC options */
81 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected
82 * from MCLK1 to MCLK2 */
83 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
84 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not
85 * available at the MCLK2 pin */
86 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available
90 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
92 #define AD7192_CONF_CHOP (1 << 23) /* CHOP enable */
93 #define AD7192_CONF_REFSEL (1 << 20) /* REFIN1/REFIN2 Reference Select */
94 #define AD7192_CONF_CHAN(x) (((x) & 0xFF) << 8) /* Channel select */
95 #define AD7192_CONF_BURN (1 << 7) /* Burnout current enable */
96 #define AD7192_CONF_REFDET (1 << 6) /* Reference detect enable */
97 #define AD7192_CONF_BUF (1 << 4) /* Buffered Mode Enable */
98 #define AD7192_CONF_UNIPOLAR (1 << 3) /* Unipolar/Bipolar Enable */
99 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
101 #define AD7192_CH_AIN1P_AIN2M 0 /* AIN1(+) - AIN2(-) */
102 #define AD7192_CH_AIN3P_AIN4M 1 /* AIN3(+) - AIN4(-) */
103 #define AD7192_CH_TEMP 2 /* Temp Sensor */
104 #define AD7192_CH_AIN2P_AIN2M 3 /* AIN2(+) - AIN2(-) */
105 #define AD7192_CH_AIN1 4 /* AIN1 - AINCOM */
106 #define AD7192_CH_AIN2 5 /* AIN2 - AINCOM */
107 #define AD7192_CH_AIN3 6 /* AIN3 - AINCOM */
108 #define AD7192_CH_AIN4 7 /* AIN4 - AINCOM */
110 /* ID Register Bit Designations (AD7192_REG_ID) */
111 #define ID_AD7190 0x4
112 #define ID_AD7192 0x0
113 #define ID_AD7195 0x6
114 #define AD7192_ID_MASK 0x0F
116 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
117 #define AD7192_GPOCON_BPDSW (1 << 6) /* Bridge power-down switch enable */
118 #define AD7192_GPOCON_GP32EN (1 << 5) /* Digital Output P3 and P2 enable */
119 #define AD7192_GPOCON_GP10EN (1 << 4) /* Digital Output P1 and P0 enable */
120 #define AD7192_GPOCON_P3DAT (1 << 3) /* P3 state */
121 #define AD7192_GPOCON_P2DAT (1 << 2) /* P2 state */
122 #define AD7192_GPOCON_P1DAT (1 << 1) /* P1 state */
123 #define AD7192_GPOCON_P0DAT (1 << 0) /* P0 state */
125 #define AD7192_INT_FREQ_MHz 4915200
128 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
129 * In order to avoid contentions on the SPI bus, it's therefore necessary
130 * to use spi bus locking.
132 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
135 struct ad7192_state {
136 struct spi_device *spi;
137 struct iio_trigger *trig;
138 struct regulator *reg;
139 struct ad7192_platform_data *pdata;
140 wait_queue_head_t wq_data_avail;
148 u32 scale_avail[8][2];
149 long available_scan_masks[9];
153 * DMA (thus cache coherency maintenance) requires the
154 * transfer buffers to live in their own cache lines.
156 u8 data[4] ____cacheline_aligned;
159 static int __ad7192_write_reg(struct ad7192_state *st, bool locked,
160 bool cs_change, unsigned char reg,
161 unsigned size, unsigned val)
164 struct spi_transfer t = {
167 .cs_change = cs_change,
169 struct spi_message m;
171 data[0] = AD7192_COMM_WRITE | AD7192_COMM_ADDR(reg);
190 spi_message_init(&m);
191 spi_message_add_tail(&t, &m);
194 return spi_sync_locked(st->spi, &m);
196 return spi_sync(st->spi, &m);
199 static int ad7192_write_reg(struct ad7192_state *st,
200 unsigned reg, unsigned size, unsigned val)
202 return __ad7192_write_reg(st, false, false, reg, size, val);
205 static int __ad7192_read_reg(struct ad7192_state *st, bool locked,
206 bool cs_change, unsigned char reg,
207 int *val, unsigned size)
211 struct spi_transfer t[] = {
218 .cs_change = cs_change,
221 struct spi_message m;
223 data[0] = AD7192_COMM_READ | AD7192_COMM_ADDR(reg);
225 spi_message_init(&m);
226 spi_message_add_tail(&t[0], &m);
227 spi_message_add_tail(&t[1], &m);
230 ret = spi_sync_locked(st->spi, &m);
232 ret = spi_sync(st->spi, &m);
239 *val = data[0] << 16 | data[1] << 8 | data[2];
242 *val = data[0] << 8 | data[1];
254 static int ad7192_read_reg(struct ad7192_state *st,
255 unsigned reg, int *val, unsigned size)
257 return __ad7192_read_reg(st, 0, 0, reg, val, size);
260 static int ad7192_read(struct ad7192_state *st, unsigned ch,
261 unsigned len, int *val)
264 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
265 AD7192_CONF_CHAN(1 << ch);
266 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
267 AD7192_MODE_SEL(AD7192_MODE_SINGLE);
269 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
271 spi_bus_lock(st->spi->master);
274 ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode);
279 enable_irq(st->spi->irq);
280 wait_event_interruptible(st->wq_data_avail, st->done);
282 ret = __ad7192_read_reg(st, 1, 0, AD7192_REG_DATA, val, len);
284 spi_bus_unlock(st->spi->master);
289 static int ad7192_calibrate(struct ad7192_state *st, unsigned mode, unsigned ch)
293 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
294 AD7192_CONF_CHAN(1 << ch);
295 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | AD7192_MODE_SEL(mode);
297 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
299 spi_bus_lock(st->spi->master);
302 ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3,
303 (st->devid != ID_AD7195) ?
304 st->mode | AD7192_MODE_CLKDIV :
310 enable_irq(st->spi->irq);
311 wait_event_interruptible(st->wq_data_avail, st->done);
313 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
314 AD7192_MODE_SEL(AD7192_MODE_IDLE);
316 ret = __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode);
318 spi_bus_unlock(st->spi->master);
323 static const u8 ad7192_calib_arr[8][2] = {
324 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
325 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
326 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
327 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
328 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
329 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
330 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
331 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
334 static int ad7192_calibrate_all(struct ad7192_state *st)
338 for (i = 0; i < ARRAY_SIZE(ad7192_calib_arr); i++) {
339 ret = ad7192_calibrate(st, ad7192_calib_arr[i][0],
340 ad7192_calib_arr[i][1]);
347 dev_err(&st->spi->dev, "Calibration failed\n");
351 static int ad7192_setup(struct ad7192_state *st)
353 struct iio_dev *indio_dev = spi_get_drvdata(st->spi);
354 struct ad7192_platform_data *pdata = st->pdata;
355 unsigned long long scale_uv;
359 /* reset the serial interface */
360 memset(&ones, 0xFF, 6);
361 ret = spi_write(st->spi, &ones, 6);
364 msleep(1); /* Wait for at least 500us */
366 /* write/read test for device presence */
367 ret = ad7192_read_reg(st, AD7192_REG_ID, &id, 1);
371 id &= AD7192_ID_MASK;
374 dev_warn(&st->spi->dev, "device ID query failed (0x%X)\n", id);
376 switch (pdata->clock_source_sel) {
377 case AD7192_CLK_EXT_MCLK1_2:
378 case AD7192_CLK_EXT_MCLK2:
379 st->mclk = AD7192_INT_FREQ_MHz;
382 case AD7192_CLK_INT_CO:
383 if (pdata->ext_clk_Hz)
384 st->mclk = pdata->ext_clk_Hz;
386 st->mclk = AD7192_INT_FREQ_MHz;
393 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
394 AD7192_MODE_CLKSRC(pdata->clock_source_sel) |
395 AD7192_MODE_RATE(480);
397 st->conf = AD7192_CONF_GAIN(0);
400 st->mode |= AD7192_MODE_REJ60;
403 st->mode |= AD7192_MODE_SINC3;
405 if (pdata->refin2_en && (st->devid != ID_AD7195))
406 st->conf |= AD7192_CONF_REFSEL;
408 if (pdata->chop_en) {
409 st->conf |= AD7192_CONF_CHOP;
411 st->f_order = 3; /* SINC 3rd order */
413 st->f_order = 4; /* SINC 4th order */
419 st->conf |= AD7192_CONF_BUF;
421 if (pdata->unipolar_en)
422 st->conf |= AD7192_CONF_UNIPOLAR;
424 if (pdata->burnout_curr_en)
425 st->conf |= AD7192_CONF_BURN;
427 ret = ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode);
431 ret = ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
435 ret = ad7192_calibrate_all(st);
439 /* Populate available ADC input ranges */
440 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
441 scale_uv = ((u64)st->int_vref_mv * 100000000)
442 >> (indio_dev->channels[0].scan_type.realbits -
443 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
446 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
447 st->scale_avail[i][0] = scale_uv;
452 dev_err(&st->spi->dev, "setup failed\n");
456 static int ad7192_ring_preenable(struct iio_dev *indio_dev)
458 struct ad7192_state *st = iio_priv(indio_dev);
462 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
465 ret = iio_sw_buffer_preenable(indio_dev);
469 channel = find_first_bit(indio_dev->active_scan_mask,
470 indio_dev->masklength);
472 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
473 AD7192_MODE_SEL(AD7192_MODE_CONT);
474 st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) |
475 AD7192_CONF_CHAN(1 << indio_dev->channels[channel].address);
477 ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf);
479 spi_bus_lock(st->spi->master);
480 __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode);
483 enable_irq(st->spi->irq);
488 static int ad7192_ring_postdisable(struct iio_dev *indio_dev)
490 struct ad7192_state *st = iio_priv(indio_dev);
492 st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) |
493 AD7192_MODE_SEL(AD7192_MODE_IDLE);
496 wait_event_interruptible(st->wq_data_avail, st->done);
499 disable_irq_nosync(st->spi->irq);
501 __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode);
503 return spi_bus_unlock(st->spi->master);
507 * ad7192_trigger_handler() bh of trigger launched polling to ring buffer
509 static irqreturn_t ad7192_trigger_handler(int irq, void *p)
511 struct iio_poll_func *pf = p;
512 struct iio_dev *indio_dev = pf->indio_dev;
513 struct iio_buffer *ring = indio_dev->buffer;
514 struct ad7192_state *st = iio_priv(indio_dev);
516 s32 *dat32 = (s32 *)dat64;
518 if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
519 __ad7192_read_reg(st, 1, 1, AD7192_REG_DATA,
521 indio_dev->channels[0].scan_type.realbits/8);
523 /* Guaranteed to be aligned with 8 byte boundary */
524 if (indio_dev->scan_timestamp)
525 dat64[1] = pf->timestamp;
527 ring->access->store_to(ring, (u8 *)dat64, pf->timestamp);
529 iio_trigger_notify_done(indio_dev->trig);
531 enable_irq(st->spi->irq);
536 static const struct iio_buffer_setup_ops ad7192_ring_setup_ops = {
537 .preenable = &ad7192_ring_preenable,
538 .postenable = &iio_triggered_buffer_postenable,
539 .predisable = &iio_triggered_buffer_predisable,
540 .postdisable = &ad7192_ring_postdisable,
543 static int ad7192_register_ring_funcs_and_init(struct iio_dev *indio_dev)
547 indio_dev->buffer = iio_kfifo_allocate(indio_dev);
548 if (!indio_dev->buffer) {
552 indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
553 &ad7192_trigger_handler,
558 if (indio_dev->pollfunc == NULL) {
560 goto error_deallocate_kfifo;
563 /* Ring buffer functions - here trigger setup related */
564 indio_dev->setup_ops = &ad7192_ring_setup_ops;
566 /* Flag that polled ring buffering is possible */
567 indio_dev->modes |= INDIO_BUFFER_TRIGGERED;
570 error_deallocate_kfifo:
571 iio_kfifo_free(indio_dev->buffer);
576 static void ad7192_ring_cleanup(struct iio_dev *indio_dev)
578 iio_dealloc_pollfunc(indio_dev->pollfunc);
579 iio_kfifo_free(indio_dev->buffer);
583 * ad7192_data_rdy_trig_poll() the event handler for the data rdy trig
585 static irqreturn_t ad7192_data_rdy_trig_poll(int irq, void *private)
587 struct ad7192_state *st = iio_priv(private);
590 wake_up_interruptible(&st->wq_data_avail);
591 disable_irq_nosync(irq);
593 iio_trigger_poll(st->trig, iio_get_time_ns());
598 static struct iio_trigger_ops ad7192_trigger_ops = {
599 .owner = THIS_MODULE,
602 static int ad7192_probe_trigger(struct iio_dev *indio_dev)
604 struct ad7192_state *st = iio_priv(indio_dev);
607 st->trig = iio_trigger_alloc("%s-dev%d",
608 spi_get_device_id(st->spi)->name,
610 if (st->trig == NULL) {
614 st->trig->ops = &ad7192_trigger_ops;
615 ret = request_irq(st->spi->irq,
616 ad7192_data_rdy_trig_poll,
618 spi_get_device_id(st->spi)->name,
621 goto error_free_trig;
623 disable_irq_nosync(st->spi->irq);
625 st->trig->dev.parent = &st->spi->dev;
626 st->trig->private_data = indio_dev;
628 ret = iio_trigger_register(st->trig);
630 /* select default trigger */
631 indio_dev->trig = st->trig;
638 free_irq(st->spi->irq, indio_dev);
640 iio_trigger_free(st->trig);
645 static void ad7192_remove_trigger(struct iio_dev *indio_dev)
647 struct ad7192_state *st = iio_priv(indio_dev);
649 iio_trigger_unregister(st->trig);
650 free_irq(st->spi->irq, indio_dev);
651 iio_trigger_free(st->trig);
654 static ssize_t ad7192_read_frequency(struct device *dev,
655 struct device_attribute *attr,
658 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
659 struct ad7192_state *st = iio_priv(indio_dev);
661 return sprintf(buf, "%d\n", st->mclk /
662 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)));
665 static ssize_t ad7192_write_frequency(struct device *dev,
666 struct device_attribute *attr,
670 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
671 struct ad7192_state *st = iio_priv(indio_dev);
675 ret = strict_strtoul(buf, 10, &lval);
679 mutex_lock(&indio_dev->mlock);
680 if (iio_buffer_enabled(indio_dev)) {
681 mutex_unlock(&indio_dev->mlock);
685 div = st->mclk / (lval * st->f_order * 1024);
686 if (div < 1 || div > 1023) {
691 st->mode &= ~AD7192_MODE_RATE(-1);
692 st->mode |= AD7192_MODE_RATE(div);
693 ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode);
696 mutex_unlock(&indio_dev->mlock);
698 return ret ? ret : len;
701 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
702 ad7192_read_frequency,
703 ad7192_write_frequency);
706 static ssize_t ad7192_show_scale_available(struct device *dev,
707 struct device_attribute *attr, char *buf)
709 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
710 struct ad7192_state *st = iio_priv(indio_dev);
713 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
714 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
715 st->scale_avail[i][1]);
717 len += sprintf(buf + len, "\n");
722 static IIO_DEVICE_ATTR_NAMED(in_v_m_v_scale_available,
723 in_voltage-voltage_scale_available,
724 S_IRUGO, ad7192_show_scale_available, NULL, 0);
726 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
727 ad7192_show_scale_available, NULL, 0);
729 static ssize_t ad7192_show_ac_excitation(struct device *dev,
730 struct device_attribute *attr,
733 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
734 struct ad7192_state *st = iio_priv(indio_dev);
736 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
739 static ssize_t ad7192_show_bridge_switch(struct device *dev,
740 struct device_attribute *attr,
743 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
744 struct ad7192_state *st = iio_priv(indio_dev);
746 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
749 static ssize_t ad7192_set(struct device *dev,
750 struct device_attribute *attr,
754 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
755 struct ad7192_state *st = iio_priv(indio_dev);
756 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
760 ret = strtobool(buf, &val);
764 mutex_lock(&indio_dev->mlock);
765 if (iio_buffer_enabled(indio_dev)) {
766 mutex_unlock(&indio_dev->mlock);
770 switch ((u32) this_attr->address) {
771 case AD7192_REG_GPOCON:
773 st->gpocon |= AD7192_GPOCON_BPDSW;
775 st->gpocon &= ~AD7192_GPOCON_BPDSW;
777 ad7192_write_reg(st, AD7192_REG_GPOCON, 1, st->gpocon);
779 case AD7192_REG_MODE:
781 st->mode |= AD7192_MODE_ACX;
783 st->mode &= ~AD7192_MODE_ACX;
785 ad7192_write_reg(st, AD7192_REG_GPOCON, 3, st->mode);
791 mutex_unlock(&indio_dev->mlock);
793 return ret ? ret : len;
796 static IIO_DEVICE_ATTR(bridge_switch_en, S_IRUGO | S_IWUSR,
797 ad7192_show_bridge_switch, ad7192_set,
800 static IIO_DEVICE_ATTR(ac_excitation_en, S_IRUGO | S_IWUSR,
801 ad7192_show_ac_excitation, ad7192_set,
804 static struct attribute *ad7192_attributes[] = {
805 &iio_dev_attr_sampling_frequency.dev_attr.attr,
806 &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
807 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
808 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
809 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
813 static const struct attribute_group ad7192_attribute_group = {
814 .attrs = ad7192_attributes,
817 static struct attribute *ad7195_attributes[] = {
818 &iio_dev_attr_sampling_frequency.dev_attr.attr,
819 &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
820 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
821 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
825 static const struct attribute_group ad7195_attribute_group = {
826 .attrs = ad7195_attributes,
829 static int ad7192_read_raw(struct iio_dev *indio_dev,
830 struct iio_chan_spec const *chan,
835 struct ad7192_state *st = iio_priv(indio_dev);
837 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
840 case IIO_CHAN_INFO_RAW:
841 mutex_lock(&indio_dev->mlock);
842 if (iio_buffer_enabled(indio_dev))
845 ret = ad7192_read(st, chan->address,
846 chan->scan_type.realbits / 8, &smpl);
847 mutex_unlock(&indio_dev->mlock);
852 *val = (smpl >> chan->scan_type.shift) &
853 ((1 << (chan->scan_type.realbits)) - 1);
855 switch (chan->type) {
858 *val -= (1 << (chan->scan_type.realbits - 1));
862 *val /= 2815; /* temp Kelvin */
863 *val -= 273; /* temp Celsius */
870 case IIO_CHAN_INFO_SCALE:
871 switch (chan->type) {
873 mutex_lock(&indio_dev->mlock);
874 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
875 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
876 mutex_unlock(&indio_dev->mlock);
877 return IIO_VAL_INT_PLUS_NANO;
889 static int ad7192_write_raw(struct iio_dev *indio_dev,
890 struct iio_chan_spec const *chan,
895 struct ad7192_state *st = iio_priv(indio_dev);
899 mutex_lock(&indio_dev->mlock);
900 if (iio_buffer_enabled(indio_dev)) {
901 mutex_unlock(&indio_dev->mlock);
906 case IIO_CHAN_INFO_SCALE:
908 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
909 if (val2 == st->scale_avail[i][1]) {
911 st->conf &= ~AD7192_CONF_GAIN(-1);
912 st->conf |= AD7192_CONF_GAIN(i);
914 if (tmp != st->conf) {
915 ad7192_write_reg(st, AD7192_REG_CONF,
917 ad7192_calibrate_all(st);
926 mutex_unlock(&indio_dev->mlock);
931 static int ad7192_validate_trigger(struct iio_dev *indio_dev,
932 struct iio_trigger *trig)
934 if (indio_dev->trig != trig)
940 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
941 struct iio_chan_spec const *chan,
944 return IIO_VAL_INT_PLUS_NANO;
947 static const struct iio_info ad7192_info = {
948 .read_raw = &ad7192_read_raw,
949 .write_raw = &ad7192_write_raw,
950 .write_raw_get_fmt = &ad7192_write_raw_get_fmt,
951 .attrs = &ad7192_attribute_group,
952 .validate_trigger = ad7192_validate_trigger,
953 .driver_module = THIS_MODULE,
956 static const struct iio_info ad7195_info = {
957 .read_raw = &ad7192_read_raw,
958 .write_raw = &ad7192_write_raw,
959 .write_raw_get_fmt = &ad7192_write_raw_get_fmt,
960 .attrs = &ad7195_attribute_group,
961 .validate_trigger = ad7192_validate_trigger,
962 .driver_module = THIS_MODULE,
965 #define AD7192_CHAN_DIFF(_chan, _chan2, _name, _address, _si) \
966 { .type = IIO_VOLTAGE, \
969 .extend_name = _name, \
971 .channel2 = _chan2, \
972 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | \
973 IIO_CHAN_INFO_SCALE_SHARED_BIT, \
974 .address = _address, \
976 .scan_type = IIO_ST('s', 24, 32, 0)}
978 #define AD7192_CHAN(_chan, _address, _si) \
979 { .type = IIO_VOLTAGE, \
982 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | \
983 IIO_CHAN_INFO_SCALE_SHARED_BIT, \
984 .address = _address, \
986 .scan_type = IIO_ST('s', 24, 32, 0)}
988 #define AD7192_CHAN_TEMP(_chan, _address, _si) \
989 { .type = IIO_TEMP, \
992 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | \
993 IIO_CHAN_INFO_SCALE_SEPARATE_BIT, \
994 .address = _address, \
996 .scan_type = IIO_ST('s', 24, 32, 0)}
998 static struct iio_chan_spec ad7192_channels[] = {
999 AD7192_CHAN_DIFF(1, 2, NULL, AD7192_CH_AIN1P_AIN2M, 0),
1000 AD7192_CHAN_DIFF(3, 4, NULL, AD7192_CH_AIN3P_AIN4M, 1),
1001 AD7192_CHAN_TEMP(0, AD7192_CH_TEMP, 2),
1002 AD7192_CHAN_DIFF(2, 2, "shorted", AD7192_CH_AIN2P_AIN2M, 3),
1003 AD7192_CHAN(1, AD7192_CH_AIN1, 4),
1004 AD7192_CHAN(2, AD7192_CH_AIN2, 5),
1005 AD7192_CHAN(3, AD7192_CH_AIN3, 6),
1006 AD7192_CHAN(4, AD7192_CH_AIN4, 7),
1007 IIO_CHAN_SOFT_TIMESTAMP(8),
1010 static int __devinit ad7192_probe(struct spi_device *spi)
1012 struct ad7192_platform_data *pdata = spi->dev.platform_data;
1013 struct ad7192_state *st;
1014 struct iio_dev *indio_dev;
1015 int ret, i , voltage_uv = 0;
1018 dev_err(&spi->dev, "no platform data?\n");
1023 dev_err(&spi->dev, "no IRQ?\n");
1027 indio_dev = iio_device_alloc(sizeof(*st));
1028 if (indio_dev == NULL)
1031 st = iio_priv(indio_dev);
1033 st->reg = regulator_get(&spi->dev, "vcc");
1034 if (!IS_ERR(st->reg)) {
1035 ret = regulator_enable(st->reg);
1039 voltage_uv = regulator_get_voltage(st->reg);
1044 if (pdata && pdata->vref_mv)
1045 st->int_vref_mv = pdata->vref_mv;
1046 else if (voltage_uv)
1047 st->int_vref_mv = voltage_uv / 1000;
1049 dev_warn(&spi->dev, "reference voltage undefined\n");
1051 spi_set_drvdata(spi, indio_dev);
1053 st->devid = spi_get_device_id(spi)->driver_data;
1054 indio_dev->dev.parent = &spi->dev;
1055 indio_dev->name = spi_get_device_id(spi)->name;
1056 indio_dev->modes = INDIO_DIRECT_MODE;
1057 indio_dev->channels = ad7192_channels;
1058 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
1059 indio_dev->available_scan_masks = st->available_scan_masks;
1060 if (st->devid == ID_AD7195)
1061 indio_dev->info = &ad7195_info;
1063 indio_dev->info = &ad7192_info;
1065 for (i = 0; i < indio_dev->num_channels; i++)
1066 st->available_scan_masks[i] = (1 << i) | (1 <<
1067 indio_dev->channels[indio_dev->num_channels - 1].
1070 init_waitqueue_head(&st->wq_data_avail);
1072 ret = ad7192_register_ring_funcs_and_init(indio_dev);
1074 goto error_disable_reg;
1076 ret = ad7192_probe_trigger(indio_dev);
1078 goto error_ring_cleanup;
1080 ret = iio_buffer_register(indio_dev,
1081 indio_dev->channels,
1082 indio_dev->num_channels);
1084 goto error_remove_trigger;
1086 ret = ad7192_setup(st);
1088 goto error_unreg_ring;
1090 ret = iio_device_register(indio_dev);
1092 goto error_unreg_ring;
1096 iio_buffer_unregister(indio_dev);
1097 error_remove_trigger:
1098 ad7192_remove_trigger(indio_dev);
1100 ad7192_ring_cleanup(indio_dev);
1102 if (!IS_ERR(st->reg))
1103 regulator_disable(st->reg);
1105 if (!IS_ERR(st->reg))
1106 regulator_put(st->reg);
1108 iio_device_free(indio_dev);
1113 static int ad7192_remove(struct spi_device *spi)
1115 struct iio_dev *indio_dev = spi_get_drvdata(spi);
1116 struct ad7192_state *st = iio_priv(indio_dev);
1118 iio_device_unregister(indio_dev);
1119 iio_buffer_unregister(indio_dev);
1120 ad7192_remove_trigger(indio_dev);
1121 ad7192_ring_cleanup(indio_dev);
1123 if (!IS_ERR(st->reg)) {
1124 regulator_disable(st->reg);
1125 regulator_put(st->reg);
1131 static const struct spi_device_id ad7192_id[] = {
1132 {"ad7190", ID_AD7190},
1133 {"ad7192", ID_AD7192},
1134 {"ad7195", ID_AD7195},
1137 MODULE_DEVICE_TABLE(spi, ad7192_id);
1139 static struct spi_driver ad7192_driver = {
1142 .owner = THIS_MODULE,
1144 .probe = ad7192_probe,
1145 .remove = __devexit_p(ad7192_remove),
1146 .id_table = ad7192_id,
1148 module_spi_driver(ad7192_driver);
1150 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
1151 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7195 ADC");
1152 MODULE_LICENSE("GPL v2");