drivers/staging/otus/hal/hpmain.c

   1 /*
   2  * Copyright (c) 2007-2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16 #include "../80211core/cprecomp.h"
  17 #include "hpani.h"
  18 #include "hpusb.h"
  19 #include "otus.ini"
  20
  21 extern const u32_t zcFwImage[];
  22 extern const u32_t zcFwImageSize;
  23 extern const u32_t zcDKFwImage[];
  24 extern const u32_t zcDKFwImageSize;
  25 extern const u32_t zcFwImageSPI[];
  26 extern const u32_t zcFwImageSPISize;
  27
  28 #ifdef ZM_OTUS_LINUX_PHASE_2
  29 extern const u32_t zcFwBufImage[];
  30 extern const u32_t zcFwBufImageSize;
  31 extern const u32_t zcP2FwImage[];
  32 extern const u32_t zcP2FwImageSize;
  33 #endif
  34 extern void zfInitCmdQueue(zdev_t* dev);
  35 extern u16_t zfIssueCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen,
  36         u16_t src, u8_t* buf);
  37 extern void zfIdlRsp(zdev_t* dev, u32_t* rsp, u16_t rspLen);
  38 extern u16_t zfDelayWriteInternalReg(zdev_t* dev, u32_t addr, u32_t val);
  39 extern u16_t zfFlushDelayWrite(zdev_t* dev);
  40 extern void zfUsbInit(zdev_t* dev);
  41 extern u16_t zfFirmwareDownload(zdev_t* dev, u32_t* fw, u32_t len, u32_t offset);
  42 extern u16_t zfFirmwareDownloadNotJump(zdev_t* dev, u32_t* fw, u32_t len, u32_t offset);
  43 extern void zfUsbFree(zdev_t* dev);
  44 extern u16_t zfCwmIsExtChanBusy(u32_t ctlBusy, u32_t extBusy);
  45 extern void zfCoreCwmBusy(zdev_t* dev, u16_t busy);
  46
  47 /* Prototypes */
  48 void zfInitRf(zdev_t* dev, u32_t frequency);
  49 void zfInitPhy(zdev_t* dev, u32_t frequency, u8_t bw40);
  50 void zfInitMac(zdev_t* dev);
  51
  52 void zfSetPowerCalTable(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset);
  53 void zfInitPowerCal(zdev_t* dev);
  54
  55 #ifdef ZM_DRV_INIT_USB_MODE
  56 void zfInitUsbMode(zdev_t* dev);
  57 u16_t zfHpUsbReset(zdev_t* dev);
  58 #endif
  59
  60 /* Bank 0 1 2 3 5 6 7 */
  61 void zfSetRfRegs(zdev_t* dev, u32_t frequency);
  62 /* Bank 4 */
  63 void zfSetBank4AndPowerTable(zdev_t* dev, u32_t frequency, u8_t bw40,
  64         u8_t extOffset);
  65 /* Get param for turnoffdyn */
  66 void zfGetHwTurnOffdynParam(zdev_t* dev,
  67                             u32_t frequency, u8_t bw40, u8_t extOffset,
  68                             int* delta_slope_coeff_exp,
  69                             int* delta_slope_coeff_man,
  70                             int* delta_slope_coeff_exp_shgi,
  71                             int* delta_slope_coeff_man_shgi);
  72
  73 void zfSelAdcClk(zdev_t* dev, u8_t bw40, u32_t frequency);
  74 u32_t zfHpEchoCommand(zdev_t* dev, u32_t value);
  75
  76
  77
  78 #define zm_hp_priv(x) (((struct zsHpPriv*)wd->hpPrivate)->x)
  79 static struct zsHpPriv zgHpPriv;
  80
  81 #define ZM_FIRMWARE_WLAN_ADDR           0x200000
  82 #define ZM_FIRMWARE_SPI_ADDR      0x114000
  83 /* 0: real chip     1: FPGA test */
  84 #define ZM_FPGA_PHY  0
  85
  86 #define reg_write(addr, val) zfDelayWriteInternalReg(dev, addr+0x1bc000, val)
  87 #define zm_min(A, B) ((A>B)? B:A)
  88
  89
  90 /******************** Intialization ********************/
  91 u16_t zfHpInit(zdev_t* dev, u32_t frequency)
  92 {
  93     u16_t ret;
  94     zmw_get_wlan_dev(dev);
  95
  96     /* Initializa HAL Plus private variables */
  97     wd->hpPrivate = &zgHpPriv;
  98
  99     ((struct zsHpPriv*)wd->hpPrivate)->halCapability = ZM_HP_CAP_11N;
 100
 101     ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = 0;
 102     ((struct zsHpPriv*)wd->hpPrivate)->hwBw40 = 0;
 103     ((struct zsHpPriv*)wd->hpPrivate)->hwExtOffset = 0;
 104
 105     ((struct zsHpPriv*)wd->hpPrivate)->disableDfsCh = 0;
 106
 107     ((struct zsHpPriv*)wd->hpPrivate)->ledMode[0] = 1;
 108     ((struct zsHpPriv*)wd->hpPrivate)->ledMode[1] = 1;
 109     ((struct zsHpPriv*)wd->hpPrivate)->strongRSSI = 0;
 110     ((struct zsHpPriv*)wd->hpPrivate)->rxStrongRSSI = 0;
 111
 112     ((struct zsHpPriv*)wd->hpPrivate)->slotType = 1;
 113     ((struct zsHpPriv*)wd->hpPrivate)->aggPktNum = 0x10000a;
 114
 115     ((struct zsHpPriv*)wd->hpPrivate)->eepromImageIndex = 0;
 116
 117
 118     ((struct zsHpPriv*)wd->hpPrivate)->eepromImageRdReq     = 0;
 119 #ifdef ZM_OTUS_RX_STREAM_MODE
 120     ((struct zsHpPriv*)wd->hpPrivate)->remainBuf = NULL;
 121     ((struct zsHpPriv*)wd->hpPrivate)->usbRxRemainLen = 0;
 122     ((struct zsHpPriv*)wd->hpPrivate)->usbRxPktLen = 0;
 123     ((struct zsHpPriv*)wd->hpPrivate)->usbRxPadLen = 0;
 124     ((struct zsHpPriv*)wd->hpPrivate)->usbRxTransferLen = 0;
 125 #endif
 126
 127     ((struct zsHpPriv*)wd->hpPrivate)->enableBBHeavyClip = 1;
 128     ((struct zsHpPriv*)wd->hpPrivate)->hwBBHeavyClip     = 1; // force enable 8107
 129     ((struct zsHpPriv*)wd->hpPrivate)->doBBHeavyClip     = 0;
 130     ((struct zsHpPriv*)wd->hpPrivate)->setValueHeavyClip = 0;
 131
 132
 133     /* Initialize driver core */
 134     zfInitCmdQueue(dev);
 135
 136     /* Initialize USB */
 137     zfUsbInit(dev);
 138
 139 #if ZM_SW_LOOP_BACK != 1
 140
 141     /* TODO : [Download FW] */
 142     if (wd->modeMDKEnable)
 143     {
 144         /* download the MDK firmware */
 145         ret = zfFirmwareDownload(dev, (u32_t*)zcDKFwImage,
 146                 (u32_t)zcDKFwImageSize, ZM_FIRMWARE_WLAN_ADDR);
 147         if (ret != ZM_SUCCESS)
 148         {
 149             /* TODO : exception handling */
 150             //return 1;
 151         }
 152     }
 153     else
 154     {
 155     #ifndef ZM_OTUS_LINUX_PHASE_2
 156         /* download the normal firmware */
 157         ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
 158                 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR);
 159         if (ret != ZM_SUCCESS)
 160         {
 161             /* TODO : exception handling */
 162             //return 1;
 163         }
 164     #else
 165
 166         // 1-PH fw: ReadMac() store some global variable
 167         ret = zfFirmwareDownloadNotJump(dev, (u32_t*)zcFwBufImage,
 168                 (u32_t)zcFwBufImageSize, 0x102800);
 169         if (ret != ZM_SUCCESS)
 170         {
 171             DbgPrint("Dl zcFwBufImage failed!");
 172         }
 173
 174         zfwSleep(dev, 1000);
 175
 176         ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
 177                 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR);
 178         if (ret != ZM_SUCCESS)
 179         {
 180             DbgPrint("Dl zcFwBufImage failed!");
 181         }
 182     #endif
 183     }
 184 #endif
 185
 186 #ifdef ZM_DRV_INIT_USB_MODE
 187     /* Init USB Mode */
 188     zfInitUsbMode(dev);
 189
 190     /* Do the USB Reset */
 191     zfHpUsbReset(dev);
 192 #endif
 193
 194 /* Register setting */
 195 /* ZM_DRIVER_MODEL_TYPE_MDK
 196  *  1=>for MDK, disable init RF, PHY, and MAC,
 197  *  0=>normal init
 198  */
 199 //#if ((ZM_SW_LOOP_BACK != 1) && (ZM_DRIVER_MODEL_TYPE_MDK !=1))
 200 #if ZM_SW_LOOP_BACK != 1
 201     if(!wd->modeMDKEnable)
 202     {
 203         /* Init MAC */
 204         zfInitMac(dev);
 205
 206     #if ZM_FW_LOOP_BACK != 1
 207         /* Init PHY */
 208         zfInitPhy(dev, frequency, 0);
 209
 210         /* Init RF */
 211         zfInitRf(dev, frequency);
 212
 213         #if ZM_FPGA_PHY == 0
 214         /* BringUp issue */
 215         //zfDelayWriteInternalReg(dev, 0x9800+0x1bc000, 0x10000007);
 216         //zfFlushDelayWrite(dev);
 217         #endif
 218
 219     #endif /* end of ZM_FW_LOOP_BACK != 1 */
 220     }
 221 #endif /* end of ((ZM_SW_LOOP_BACK != 1) && (ZM_DRIVER_MODEL_TYPE_MDK !=1)) */
 222
 223     zfHpEchoCommand(dev, 0xAABBCCDD);
 224
 225     return 0;
 226 }
 227
 228
 229 u16_t zfHpReinit(zdev_t* dev, u32_t frequency)
 230 {
 231     u16_t ret;
 232     zmw_get_wlan_dev(dev);
 233
 234     ((struct zsHpPriv*)wd->hpPrivate)->halReInit = 1;
 235
 236     ((struct zsHpPriv*)wd->hpPrivate)->strongRSSI = 0;
 237     ((struct zsHpPriv*)wd->hpPrivate)->rxStrongRSSI = 0;
 238
 239 #ifdef ZM_OTUS_RX_STREAM_MODE
 240     if (((struct zsHpPriv*)wd->hpPrivate)->remainBuf != NULL)
 241     {
 242         zfwBufFree(dev, ((struct zsHpPriv*)wd->hpPrivate)->remainBuf, 0);
 243     }
 244     ((struct zsHpPriv*)wd->hpPrivate)->remainBuf = NULL;
 245     ((struct zsHpPriv*)wd->hpPrivate)->usbRxRemainLen = 0;
 246     ((struct zsHpPriv*)wd->hpPrivate)->usbRxPktLen = 0;
 247     ((struct zsHpPriv*)wd->hpPrivate)->usbRxPadLen = 0;
 248     ((struct zsHpPriv*)wd->hpPrivate)->usbRxTransferLen = 0;
 249 #endif
 250
 251     zfInitCmdQueue(dev);
 252     zfCoreReinit(dev);
 253
 254     #ifndef ZM_OTUS_LINUX_PHASE_2
 255     /* Download firmware */
 256     ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
 257             (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR);
 258     if (ret != ZM_SUCCESS)
 259     {
 260         /* TODO : exception handling */
 261         //return 1;
 262     }
 263     #else
 264     ret = zfFirmwareDownload(dev, (u32_t*)zcP2FwImage,
 265             (u32_t)zcP2FwImageSize, ZM_FIRMWARE_WLAN_ADDR);
 266     if (ret != ZM_SUCCESS)
 267     {
 268         /* TODO : exception handling */
 269         //return 1;
 270     }
 271     #endif
 272
 273 #ifdef ZM_DRV_INIT_USB_MODE
 274     /* Init USB Mode */
 275     zfInitUsbMode(dev);
 276
 277     /* Do the USB Reset */
 278     zfHpUsbReset(dev);
 279 #endif
 280
 281     /* Init MAC */
 282     zfInitMac(dev);
 283
 284     /* Init PHY */
 285     zfInitPhy(dev, frequency, 0);
 286     /* Init RF */
 287     zfInitRf(dev, frequency);
 288
 289     #if ZM_FPGA_PHY == 0
 290     /* BringUp issue */
 291     //zfDelayWriteInternalReg(dev, 0x9800+0x1bc000, 0x10000007);
 292     //zfFlushDelayWrite(dev);
 293     #endif
 294
 295     zfHpEchoCommand(dev, 0xAABBCCDD);
 296
 297     return 0;
 298 }
 299
 300
 301 u16_t zfHpRelease(zdev_t* dev)
 302 {
 303     /* Free USB resource */
 304     zfUsbFree(dev);
 305
 306     return 0;
 307 }
 308
 309 /* MDK mode setting for dontRetransmit */
 310 void zfHpConfigFM(zdev_t* dev, u32_t RxMaxSize, u32_t DontRetransmit)
 311 {
 312     u32_t cmd[3];
 313     u16_t ret;
 314
 315     cmd[0] = 8 | (ZM_CMD_CONFIG << 8);
 316     cmd[1] = RxMaxSize;          /* zgRxMaxSize */
 317     cmd[2] = DontRetransmit;     /* zgDontRetransmit */
 318
 319     ret = zfIssueCmd(dev, cmd, 12, ZM_OID_INTERNAL_WRITE, 0);
 320 }
 321
 322 const u8_t zcXpdToPd[16] =
 323 {
 324  /* 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF */
 325     0x2, 0x2, 0x2, 0x1, 0x2, 0x2, 0x6, 0x2, 0x2, 0x3, 0x7, 0x2, 0xB, 0x2, 0x2, 0x2
 326 };
 327
 328 /******************** RF and PHY ********************/
 329
 330 void zfInitPhy(zdev_t* dev,  u32_t frequency, u8_t bw40)
 331 {
 332     u16_t i, j, k;
 333     u16_t entries;
 334     u16_t modesIndex = 0;
 335     u16_t freqIndex = 0;
 336     u32_t tmp, tmp1;
 337     struct zsHpPriv* hpPriv;
 338
 339     u32_t eepromBoardData[15][6] = {
 340     /* Register   A-20        A-20/40     G-20/40     G-20        G-Turbo    */
 341         {0x9964,    0,      0,      0,      0,      0},
 342         {0x9960,    0,      0,      0,      0,      0},
 343         {0xb960,    0,      0,      0,      0,      0},
 344         {0x9844,    0,      0,      0,      0,      0},
 345         {0x9850,    0,      0,      0,      0,      0},
 346         {0x9834,    0,      0,      0,      0,      0},
 347         {0x9828,    0,      0,      0,      0,      0},
 348         {0xc864,    0,      0,      0,      0,      0},
 349         {0x9848,    0,      0,      0,      0,      0},
 350         {0xb848,    0,      0,      0,      0,      0},
 351         {0xa20c,    0,      0,      0,      0,      0},
 352         {0xc20c,    0,      0,      0,      0,      0},
 353         {0x9920,    0,      0,      0,      0,      0},
 354         {0xb920,    0,      0,      0,      0,      0},
 355         {0xa258,    0,      0,      0,      0,      0},
 356     };
 357
 358     zmw_get_wlan_dev(dev);
 359     hpPriv=wd->hpPrivate;
 360
 361     /* #1 Save the initial value of the related RIFS register settings */
 362     //((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy++;
 363
 364     /*
 365      * Setup the indices for the next set of register array writes
 366      * PHY mode is static20 / 2040
 367      * Frequency is 2.4GHz (B) / 5GHz (A)
 368      */
 369     if ( frequency > ZM_CH_G_14 )
 370     {
 371         /* 5GHz */
 372         freqIndex  = 1;
 373         if (bw40)
 374         {
 375             modesIndex = 2;
 376             zm_debug_msg0("init ar5416Modes in 2: A-20/40");
 377         }
 378         else
 379         {
 380             modesIndex = 1;
 381             zm_debug_msg0("init ar5416Modes in 1: A-20");
 382         }
 383     }
 384     else
 385     {
 386         /* 2.4GHz */
 387         freqIndex  = 2;
 388         if (bw40)
 389         {
 390             modesIndex = 3;
 391             zm_debug_msg0("init ar5416Modes in 3: G-20/40");
 392         }
 393         else
 394         {
 395             modesIndex = 4;
 396             zm_debug_msg0("init ar5416Modes in 4: G-20");
 397         }
 398     }
 399
 400
 401 #if ZM_FPGA_PHY == 1
 402     /* Starting External Hainan Register Initialization */
 403     /* TODO: */
 404
 405     zfwSleep(dev, 10);
 406 #endif
 407
 408     /*
 409      *Set correct Baseband to analog shift setting to access analog chips.
 410      */
 411     //reg_write(PHY_BASE, 0x00000007);
 412 //    reg_write(0x9800, 0x00000007);
 413
 414     /*
 415      * Write addac shifts
 416      */
 417      // do this in firmware
 418
 419
 420
 421     /* Zeroize board data */
 422     for (j=0; j<15; j++)
 423     {
 424         for (k=1; k<=4; k++)
 425         {
 426             eepromBoardData[j][k] = 0;
 427         }
 428     }
 429      /*
 430      * Register setting by mode
 431      */
 432
 433     entries = sizeof(ar5416Modes) / sizeof(*ar5416Modes);
 434     zm_msg1_scan(ZM_LV_2, "Modes register setting entries=", entries);
 435     for (i=0; i<entries; i++)
 436     {
 437 #if 0
 438         if ( ((struct zsHpPriv*)wd->hpPrivate)->hwNotFirstInit && (ar5416Modes[i][0] == 0xa27c) )
 439         {
 440             /* Force disable CR671 bit20 / 7823                                            */
 441             /* The bug has to do with the polarity of the pdadc offset calibration.  There */
 442             /* is an initial calibration that is OK, and there is a continuous             */
 443             /* calibration that updates the pddac with the wrong polarity.  Fortunately    */
 444             /* the second loop can be disabled with a bit called en_pd_dc_offset_thr.      */
 445
 446             reg_write(ar5416Modes[i][0], (ar5416Modes[i][modesIndex]& 0xffefffff) );
 447             ((struct zsHpPriv*)wd->hpPrivate)->hwNotFirstInit = 1;
 448         }
 449         else
 450         {
 451 #endif
 452             /* FirstTime Init or not 0xa27c(CR671) */
 453             reg_write(ar5416Modes[i][0], ar5416Modes[i][modesIndex]);
 454 //        }
 455         /* Initialize board data */
 456         for (j=0; j<15; j++)
 457         {
 458             if (ar5416Modes[i][0] == eepromBoardData[j][0])
 459             {
 460                 for (k=1; k<=4; k++)
 461                 {
 462                     eepromBoardData[j][k] = ar5416Modes[i][k];
 463                 }
 464             }
 465         }
 466         /* #1 Save the initial value of the related RIFS register settings */
 467         //if( ((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy == 1 )
 468         {
 469             switch(ar5416Modes[i][0])
 470             {
 471                 case 0x9850 :
 472                     ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize           = ar5416Modes[i][modesIndex];
 473                     break;
 474                 case 0x985c :
 475                     ((struct zsHpPriv*)wd->hpPrivate)->initAGC                      = ar5416Modes[i][modesIndex];
 476                     break;
 477                 case 0x9860 :
 478                     ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl               = ar5416Modes[i][modesIndex];
 479                     break;
 480                 case 0x9918 :
 481                     ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay         = ar5416Modes[i][modesIndex];
 482                     break;
 483                 case 0x99ec :
 484                     ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams         = ar5416Modes[i][modesIndex];
 485                     break;
 486                 case 0xa388 :
 487                     ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl = ar5416Modes[i][modesIndex];
 488                 default :
 489                     break;
 490             }
 491         }
 492     }
 493 #if 0
 494     zfFlushDelayWrite(dev);
 495
 496     /*
 497      * Common Register setting
 498      */
 499     entries = sizeof(ar5416Common) / sizeof(*ar5416Common);
 500     for (i=0; i<entries; i++)
 501     {
 502         reg_write(ar5416Common[i][0], ar5416Common[i][1]);
 503     }
 504     zfFlushDelayWrite(dev);
 505
 506     /*
 507      * RF Gain setting by freqIndex
 508      */
 509     entries = sizeof(ar5416BB_RfGain) / sizeof(*ar5416BB_RfGain);
 510     for (i=0; i<entries; i++)
 511     {
 512         reg_write(ar5416BB_RfGain[i][0], ar5416BB_RfGain[i][freqIndex]);
 513     }
 514     zfFlushDelayWrite(dev);
 515
 516     /*
 517      * Moved ar5416InitChainMask() here to ensure the swap bit is set before
 518      * the pdadc table is written.  Swap must occur before any radio dependent
 519      * replicated register access.  The pdadc curve addressing in particular
 520      * depends on the consistent setting of the swap bit.
 521      */
 522     //ar5416InitChainMask(pDev);
 523
 524     /* Setup the transmit power values. */
 525     // TODO
 526 #endif
 527
 528     /* Update 5G board data */
 529     //Ant control common
 530     tmp = hpPriv->eepromImage[0x100+0x144*2/4];
 531     eepromBoardData[0][1] = tmp;
 532     eepromBoardData[0][2] = tmp;
 533     //Ant control chain 0
 534     tmp = hpPriv->eepromImage[0x100+0x140*2/4];
 535     eepromBoardData[1][1] = tmp;
 536     eepromBoardData[1][2] = tmp;
 537     //Ant control chain 2
 538     tmp = hpPriv->eepromImage[0x100+0x142*2/4];
 539     eepromBoardData[2][1] = tmp;
 540     eepromBoardData[2][2] = tmp;
 541     //SwSettle
 542     tmp = hpPriv->eepromImage[0x100+0x146*2/4];
 543     tmp = (tmp >> 16) & 0x7f;
 544     eepromBoardData[3][1] &= (~((u32_t)0x3f80));
 545     eepromBoardData[3][1] |= (tmp << 7);
 546 #if 0
 547     //swSettleHt40
 548     tmp = hpPriv->eepromImage[0x100+0x158*2/4];
 549     tmp = (tmp) & 0x7f;
 550     eepromBoardData[3][2] &= (~((u32_t)0x3f80));
 551     eepromBoardData[3][2] |= (tmp << 7);
 552 #endif
 553     //adcDesired, pdaDesired
 554     tmp = hpPriv->eepromImage[0x100+0x148*2/4];
 555     tmp = (tmp >> 24);
 556     tmp1 = hpPriv->eepromImage[0x100+0x14a*2/4];
 557     tmp1 = tmp1 & 0xff;
 558     tmp = tmp + (tmp1<<8);
 559     eepromBoardData[4][1] &= (~((u32_t)0xffff));
 560     eepromBoardData[4][1] |= tmp;
 561     eepromBoardData[4][2] &= (~((u32_t)0xffff));
 562     eepromBoardData[4][2] |= tmp;
 563     //TxEndToXpaOff, TxFrameToXpaOn
 564     tmp = hpPriv->eepromImage[0x100+0x14a*2/4];
 565     tmp = (tmp >> 24) & 0xff;
 566     tmp1 = hpPriv->eepromImage[0x100+0x14c*2/4];
 567     tmp1 = (tmp1 >> 8) & 0xff;
 568     tmp = (tmp<<24) + (tmp<<16) + (tmp1<<8) + tmp1;
 569     eepromBoardData[5][1] = tmp;
 570     eepromBoardData[5][2] = tmp;
 571     //TxEnaToRxOm
 572     tmp = hpPriv->eepromImage[0x100+0x14c*2/4] & 0xff;
 573     eepromBoardData[6][1] &= (~((u32_t)0xff0000));
 574     eepromBoardData[6][1] |= (tmp<<16);
 575     eepromBoardData[6][2] &= (~((u32_t)0xff0000));
 576     eepromBoardData[6][2] |= (tmp<<16);
 577     //Thresh62
 578     tmp = hpPriv->eepromImage[0x100+0x14c*2/4];
 579     tmp = (tmp >> 16) & 0x7f;
 580     eepromBoardData[7][1] &= (~((u32_t)0x7f000));
 581     eepromBoardData[7][1] |= (tmp<<12);
 582     eepromBoardData[7][2] &= (~((u32_t)0x7f000));
 583     eepromBoardData[7][2] |= (tmp<<12);
 584     //TxRxAtten chain_0
 585     tmp = hpPriv->eepromImage[0x100+0x146*2/4];
 586     tmp = (tmp >> 24) & 0x3f;
 587     eepromBoardData[8][1] &= (~((u32_t)0x3f000));
 588     eepromBoardData[8][1] |= (tmp<<12);
 589     eepromBoardData[8][2] &= (~((u32_t)0x3f000));
 590     eepromBoardData[8][2] |= (tmp<<12);
 591     //TxRxAtten chain_2
 592     tmp = hpPriv->eepromImage[0x100+0x148*2/4] & 0x3f;
 593     eepromBoardData[9][1] &= (~((u32_t)0x3f000));
 594     eepromBoardData[9][1] |= (tmp<<12);
 595     eepromBoardData[9][2] &= (~((u32_t)0x3f000));
 596     eepromBoardData[9][2] |= (tmp<<12);
 597     //TxRxMargin chain_0
 598     tmp = hpPriv->eepromImage[0x100+0x148*2/4];
 599     tmp = (tmp >> 8) & 0x3f;
 600     eepromBoardData[10][1] &= (~((u32_t)0xfc0000));
 601     eepromBoardData[10][1] |= (tmp<<18);
 602     eepromBoardData[10][2] &= (~((u32_t)0xfc0000));
 603     eepromBoardData[10][2] |= (tmp<<18);
 604     //TxRxMargin chain_2
 605     tmp = hpPriv->eepromImage[0x100+0x148*2/4];
 606     tmp = (tmp >> 16) & 0x3f;
 607     eepromBoardData[11][1] &= (~((u32_t)0xfc0000));
 608     eepromBoardData[11][1] |= (tmp<<18);
 609     eepromBoardData[11][2] &= (~((u32_t)0xfc0000));
 610     eepromBoardData[11][2] |= (tmp<<18);
 611     //iqCall chain_0, iqCallQ chain_0
 612     tmp = hpPriv->eepromImage[0x100+0x14e*2/4];
 613     tmp = (tmp >> 24) & 0x3f;
 614     tmp1 = hpPriv->eepromImage[0x100+0x150*2/4];
 615     tmp1 = (tmp1 >> 8) & 0x1f;
 616     tmp  = (tmp<<5) + tmp1;
 617     eepromBoardData[12][1] &= (~((u32_t)0x7ff));
 618     eepromBoardData[12][1] |= (tmp);
 619     eepromBoardData[12][2] &= (~((u32_t)0x7ff));
 620     eepromBoardData[12][2] |= (tmp);
 621     //iqCall chain_2, iqCallQ chain_2
 622     tmp = hpPriv->eepromImage[0x100+0x150*2/4];
 623     tmp = tmp & 0x3f;
 624     tmp1 = hpPriv->eepromImage[0x100+0x150*2/4];
 625     tmp1 = (tmp1 >> 16) & 0x1f;
 626     tmp  = (tmp<<5) + tmp1;
 627     eepromBoardData[13][1] &= (~((u32_t)0x7ff));
 628     eepromBoardData[13][1] |= (tmp);
 629     eepromBoardData[13][2] &= (~((u32_t)0x7ff));
 630     eepromBoardData[13][2] |= (tmp);
 631     //bsw_Margin chain_0
 632     tmp = hpPriv->eepromImage[0x100+0x156*2/4];
 633     tmp = (tmp >> 16) & 0xf;
 634     eepromBoardData[10][1] &= (~((u32_t)0x3c00));
 635     eepromBoardData[10][1] |= (tmp << 10);
 636     eepromBoardData[10][2] &= (~((u32_t)0x3c00));
 637     eepromBoardData[10][2] |= (tmp << 10);
 638     //xpd gain mask
 639     tmp = hpPriv->eepromImage[0x100+0x14e*2/4];
 640     tmp = (tmp >> 8) & 0xf;
 641     eepromBoardData[14][1] &= (~((u32_t)0xf0000));
 642     eepromBoardData[14][1] |= (zcXpdToPd[tmp] << 16);
 643     eepromBoardData[14][2] &= (~((u32_t)0xf0000));
 644     eepromBoardData[14][2] |= (zcXpdToPd[tmp] << 16);
 645 #if 0
 646     //bsw_Atten chain_0
 647     tmp = hpPriv->eepromImage[0x100+0x156*2/4];
 648     tmp = (tmp) & 0x1f;
 649     eepromBoardData[10][1] &= (~((u32_t)0x1f));
 650     eepromBoardData[10][1] |= (tmp);
 651     eepromBoardData[10][2] &= (~((u32_t)0x1f));
 652     eepromBoardData[10][2] |= (tmp);
 653     //bsw_Margin chain_2
 654     tmp = hpPriv->eepromImage[0x100+0x156*2/4];
 655     tmp = (tmp >> 24) & 0xf;
 656     eepromBoardData[11][1] &= (~((u32_t)0x3c00));
 657     eepromBoardData[11][1] |= (tmp << 10);
 658     eepromBoardData[11][2] &= (~((u32_t)0x3c00));
 659     eepromBoardData[11][2] |= (tmp << 10);
 660     //bsw_Atten chain_2
 661     tmp = hpPriv->eepromImage[0x100+0x156*2/4];
 662     tmp = (tmp >> 8) & 0x1f;
 663     eepromBoardData[11][1] &= (~((u32_t)0x1f));
 664     eepromBoardData[11][1] |= (tmp);
 665     eepromBoardData[11][2] &= (~((u32_t)0x1f));
 666     eepromBoardData[11][2] |= (tmp);
 667 #endif
 668
 669     /* Update 2.4G board data */
 670     //Ant control common
 671     tmp = hpPriv->eepromImage[0x100+0x170*2/4];
 672     tmp = tmp >> 24;
 673     tmp1 = hpPriv->eepromImage[0x100+0x172*2/4];
 674     tmp = tmp + (tmp1 << 8);
 675     eepromBoardData[0][3] = tmp;
 676     eepromBoardData[0][4] = tmp;
 677     //Ant control chain 0
 678     tmp = hpPriv->eepromImage[0x100+0x16c*2/4];
 679     tmp = tmp >> 24;
 680     tmp1 = hpPriv->eepromImage[0x100+0x16e*2/4];
 681     tmp = tmp + (tmp1 << 8);
 682     eepromBoardData[1][3] = tmp;
 683     eepromBoardData[1][4] = tmp;
 684     //Ant control chain 2
 685     tmp = hpPriv->eepromImage[0x100+0x16e*2/4];
 686     tmp = tmp >> 24;
 687     tmp1 = hpPriv->eepromImage[0x100+0x170*2/4];
 688     tmp = tmp + (tmp1 << 8);
 689     eepromBoardData[2][3] = tmp;
 690     eepromBoardData[2][4] = tmp;
 691     //SwSettle
 692     tmp = hpPriv->eepromImage[0x100+0x174*2/4];
 693     tmp = (tmp >> 8) & 0x7f;
 694     eepromBoardData[3][4] &= (~((u32_t)0x3f80));
 695     eepromBoardData[3][4] |= (tmp << 7);
 696 #if 0
 697     //swSettleHt40
 698     tmp = hpPriv->eepromImage[0x100+0x184*2/4];
 699     tmp = (tmp >> 24) & 0x7f;
 700     eepromBoardData[3][3] &= (~((u32_t)0x3f80));
 701     eepromBoardData[3][3] |= (tmp << 7);
 702 #endif
 703     //adcDesired, pdaDesired
 704     tmp = hpPriv->eepromImage[0x100+0x176*2/4];
 705     tmp = (tmp >> 16) & 0xff;
 706     tmp1 = hpPriv->eepromImage[0x100+0x176*2/4];
 707     tmp1 = tmp1 >> 24;
 708     tmp = tmp + (tmp1<<8);
 709     eepromBoardData[4][3] &= (~((u32_t)0xffff));
 710     eepromBoardData[4][3] |= tmp;
 711     eepromBoardData[4][4] &= (~((u32_t)0xffff));
 712     eepromBoardData[4][4] |= tmp;
 713     //TxEndToXpaOff, TxFrameToXpaOn
 714     tmp = hpPriv->eepromImage[0x100+0x178*2/4];
 715     tmp = (tmp >> 16) & 0xff;
 716     tmp1 = hpPriv->eepromImage[0x100+0x17a*2/4];
 717     tmp1 = tmp1 & 0xff;
 718     tmp = (tmp << 24) + (tmp << 16) + (tmp1 << 8) + tmp1;
 719     eepromBoardData[5][3] = tmp;
 720     eepromBoardData[5][4] = tmp;
 721     //TxEnaToRxOm
 722     tmp = hpPriv->eepromImage[0x100+0x178*2/4];
 723     tmp = (tmp >> 24);
 724     eepromBoardData[6][3] &= (~((u32_t)0xff0000));
 725     eepromBoardData[6][3] |= (tmp<<16);
 726     eepromBoardData[6][4] &= (~((u32_t)0xff0000));
 727     eepromBoardData[6][4] |= (tmp<<16);
 728     //Thresh62
 729     tmp = hpPriv->eepromImage[0x100+0x17a*2/4];
 730     tmp = (tmp >> 8) & 0x7f;
 731     eepromBoardData[7][3] &= (~((u32_t)0x7f000));
 732     eepromBoardData[7][3] |= (tmp<<12);
 733     eepromBoardData[7][4] &= (~((u32_t)0x7f000));
 734     eepromBoardData[7][4] |= (tmp<<12);
 735     //TxRxAtten chain_0
 736     tmp = hpPriv->eepromImage[0x100+0x174*2/4];
 737     tmp = (tmp >> 16) & 0x3f;
 738     eepromBoardData[8][3] &= (~((u32_t)0x3f000));
 739     eepromBoardData[8][3] |= (tmp<<12);
 740     eepromBoardData[8][4] &= (~((u32_t)0x3f000));
 741     eepromBoardData[8][4] |= (tmp<<12);
 742     //TxRxAtten chain_2
 743     tmp = hpPriv->eepromImage[0x100+0x174*2/4];
 744     tmp = (tmp >> 24) & 0x3f;
 745     eepromBoardData[9][3] &= (~((u32_t)0x3f000));
 746     eepromBoardData[9][3] |= (tmp<<12);
 747     eepromBoardData[9][4] &= (~((u32_t)0x3f000));
 748     eepromBoardData[9][4] |= (tmp<<12);
 749     //TxRxMargin chain_0
 750     tmp = hpPriv->eepromImage[0x100+0x176*2/4];
 751     tmp = (tmp) & 0x3f;
 752     eepromBoardData[10][3] &= (~((u32_t)0xfc0000));
 753     eepromBoardData[10][3] |= (tmp<<18);
 754     eepromBoardData[10][4] &= (~((u32_t)0xfc0000));
 755     eepromBoardData[10][4] |= (tmp<<18);
 756     //TxRxMargin chain_2
 757     tmp = hpPriv->eepromImage[0x100+0x176*2/4];
 758     tmp = (tmp >> 8) & 0x3f;
 759     eepromBoardData[11][3] &= (~((u32_t)0xfc0000));
 760     eepromBoardData[11][3] |= (tmp<<18);
 761     eepromBoardData[11][4] &= (~((u32_t)0xfc0000));
 762     eepromBoardData[11][4] |= (tmp<<18);
 763     //iqCall chain_0, iqCallQ chain_0
 764     tmp = hpPriv->eepromImage[0x100+0x17c*2/4];
 765     tmp = (tmp >> 16) & 0x3f;
 766     tmp1 = hpPriv->eepromImage[0x100+0x17e*2/4];
 767     tmp1 = (tmp1) & 0x1f;
 768     tmp  = (tmp<<5) + tmp1;
 769     eepromBoardData[12][3] &= (~((u32_t)0x7ff));
 770     eepromBoardData[12][3] |= (tmp);
 771     eepromBoardData[12][4] &= (~((u32_t)0x7ff));
 772     eepromBoardData[12][4] |= (tmp);
 773     //iqCall chain_2, iqCallQ chain_2
 774     tmp = hpPriv->eepromImage[0x100+0x17c*2/4];
 775     tmp = (tmp>>24) & 0x3f;
 776     tmp1 = hpPriv->eepromImage[0x100+0x17e*2/4];
 777     tmp1 = (tmp1 >> 8) & 0x1f;
 778     tmp  = (tmp<<5) + tmp1;
 779     eepromBoardData[13][3] &= (~((u32_t)0x7ff));
 780     eepromBoardData[13][3] |= (tmp);
 781     eepromBoardData[13][4] &= (~((u32_t)0x7ff));
 782     eepromBoardData[13][4] |= (tmp);
 783     //xpd gain mask
 784     tmp = hpPriv->eepromImage[0x100+0x17c*2/4];
 785     tmp = tmp & 0xf;
 786     DbgPrint("xpd=0x%x, pd=0x%x\n", tmp, zcXpdToPd[tmp]);
 787     eepromBoardData[14][3] &= (~((u32_t)0xf0000));
 788     eepromBoardData[14][3] |= (zcXpdToPd[tmp] << 16);
 789     eepromBoardData[14][4] &= (~((u32_t)0xf0000));
 790     eepromBoardData[14][4] |= (zcXpdToPd[tmp] << 16);
 791 #if 0
 792     //bsw_Margin chain_0
 793     tmp = hpPriv->eepromImage[0x100+0x184*2/4];
 794     tmp = (tmp >> 8) & 0xf;
 795     eepromBoardData[10][3] &= (~((u32_t)0x3c00));
 796     eepromBoardData[10][3] |= (tmp << 10);
 797     eepromBoardData[10][4] &= (~((u32_t)0x3c00));
 798     eepromBoardData[10][4] |= (tmp << 10);
 799     //bsw_Atten chain_0
 800     tmp = hpPriv->eepromImage[0x100+0x182*2/4];
 801     tmp = (tmp>>24) & 0x1f;
 802     eepromBoardData[10][3] &= (~((u32_t)0x1f));
 803     eepromBoardData[10][3] |= (tmp);
 804     eepromBoardData[10][4] &= (~((u32_t)0x1f));
 805     eepromBoardData[10][4] |= (tmp);
 806     //bsw_Margin chain_2
 807     tmp = hpPriv->eepromImage[0x100+0x184*2/4];
 808     tmp = (tmp >> 16) & 0xf;
 809     eepromBoardData[11][3] &= (~((u32_t)0x3c00));
 810     eepromBoardData[11][3] |= (tmp << 10);
 811     eepromBoardData[11][4] &= (~((u32_t)0x3c00));
 812     eepromBoardData[11][4] |= (tmp << 10);
 813     //bsw_Atten chain_2
 814     tmp = hpPriv->eepromImage[0x100+0x184*2/4];
 815     tmp = (tmp) & 0x1f;
 816     eepromBoardData[11][3] &= (~((u32_t)0x1f));
 817     eepromBoardData[11][3] |= (tmp);
 818     eepromBoardData[11][4] &= (~((u32_t)0x1f));
 819     eepromBoardData[11][4] |= (tmp);
 820 #endif
 821
 822 #if 0
 823     for (j=0; j<14; j++)
 824     {
 825         DbgPrint("%04x, %08x, %08x, %08x, %08x\n", eepromBoardData[j][0], eepromBoardData[j][1], eepromBoardData[j][2], eepromBoardData[j][3], eepromBoardData[j][4]);
 826     }
 827 #endif
 828
 829     if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
 830     {
 831         /* Update board data to registers */
 832         for (j=0; j<15; j++)
 833         {
 834             reg_write(eepromBoardData[j][0], eepromBoardData[j][modesIndex]);
 835
 836             /* #1 Save the initial value of the related RIFS register settings */
 837             //if( ((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy == 1 )
 838             {
 839                 switch(eepromBoardData[j][0])
 840                 {
 841                     case 0x9850 :
 842                         ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize           = eepromBoardData[j][modesIndex];
 843                         break;
 844                     case 0x985c :
 845                         ((struct zsHpPriv*)wd->hpPrivate)->initAGC                      = eepromBoardData[j][modesIndex];
 846                         break;
 847                     case 0x9860 :
 848                         ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl               = eepromBoardData[j][modesIndex];
 849                         break;
 850                     case 0x9918 :
 851                         ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay         = eepromBoardData[j][modesIndex];
 852                         break;
 853                     case 0x99ec :
 854                         ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams         = eepromBoardData[j][modesIndex];
 855                         break;
 856                     case 0xa388 :
 857                         ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl = eepromBoardData[j][modesIndex];
 858                     default :
 859                         break;
 860                 }
 861             }
 862         }
 863     } /* if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE */
 864
 865
 866     /* Bringup issue : force tx gain */
 867     //reg_write(0xa258, 0x0cc65381);
 868     //reg_write(0xa274, 0x0a1a7c15);
 869     zfInitPowerCal(dev);
 870
 871     if(frequency > ZM_CH_G_14)
 872     {
 873         zfDelayWriteInternalReg(dev, 0x1d4014, 0x5143);
 874     }
 875     else
 876     {
 877         zfDelayWriteInternalReg(dev, 0x1d4014, 0x5163);
 878     }
 879
 880     zfFlushDelayWrite(dev);
 881 }
 882
 883
 884 void zfInitRf(zdev_t* dev, u32_t frequency)
 885 {
 886     u32_t cmd[8];
 887     u16_t ret;
 888     int delta_slope_coeff_exp;
 889     int delta_slope_coeff_man;
 890     int delta_slope_coeff_exp_shgi;
 891     int delta_slope_coeff_man_shgi;
 892
 893     zmw_get_wlan_dev(dev);
 894
 895     zm_debug_msg1(" initRf frequency = ", frequency);
 896
 897     if (frequency == 0)
 898     {
 899         frequency = 2412;
 900     }
 901
 902     /* Bank 0 1 2 3 5 6 7 */
 903     zfSetRfRegs(dev, frequency);
 904     /* Bank 4 */
 905     zfSetBank4AndPowerTable(dev, frequency, 0, 0);
 906
 907     /* stroe frequency */
 908     ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = (u16_t)frequency;
 909
 910     zfGetHwTurnOffdynParam(dev,
 911                            frequency, 0, 0,
 912                            &delta_slope_coeff_exp,
 913                            &delta_slope_coeff_man,
 914                            &delta_slope_coeff_exp_shgi,
 915                            &delta_slope_coeff_man_shgi);
 916
 917     /* related functions */
 918     frequency = frequency*1000;
 919     cmd[0] = 28 | (ZM_CMD_RF_INIT << 8);
 920     cmd[1] = frequency;
 921     cmd[2] = 0;//((struct zsHpPriv*)wd->hpPrivate)->hw_DYNAMIC_HT2040_EN;
 922     cmd[3] = 1;//((wd->ExtOffset << 2) | ((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE);
 923     cmd[4] = delta_slope_coeff_exp;
 924     cmd[5] = delta_slope_coeff_man;
 925     cmd[6] = delta_slope_coeff_exp_shgi;
 926     cmd[7] = delta_slope_coeff_man_shgi;
 927
 928     ret = zfIssueCmd(dev, cmd, 32, ZM_OID_INTERNAL_WRITE, 0);
 929
 930     // delay temporarily, wait for new PHY and RF
 931     zfwSleep(dev, 1000);
 932 }
 933
 934 int tn(int exp)
 935 {
 936     int i;
 937         int tmp = 1;
 938     for(i=0; i<exp; i++)
 939         tmp = tmp*2;
 940
 941     return tmp;
 942 }
 943
 944 /*int zfFloor(double indata)
 945 {
 946    if(indata<0)
 947            return (int)indata-1;
 948    else
 949            return (int)indata;
 950 }
 951 */
 952 u32_t reverse_bits(u32_t chan_sel)
 953 {
 954         /* reverse_bits */
 955     u32_t chansel = 0;
 956         u8_t i;
 957
 958         for (i=0; i<8; i++)
 959         chansel |= ((chan_sel>>(7-i) & 0x1) << i);
 960         return chansel;
 961 }
 962
 963 /* Bank 0 1 2 3 5 6 7 */
 964 void zfSetRfRegs(zdev_t* dev, u32_t frequency)
 965 {
 966     u16_t entries;
 967     u16_t freqIndex = 0;
 968     u16_t i;
 969
 970     //zmw_get_wlan_dev(dev);
 971
 972     if ( frequency > ZM_CH_G_14 )
 973     {
 974         /* 5G */
 975         freqIndex = 1;
 976         zm_msg0_scan(ZM_LV_2, "Set to 5GHz");
 977
 978     }
 979     else
 980     {
 981         /* 2.4G */
 982         freqIndex = 2;
 983         zm_msg0_scan(ZM_LV_2, "Set to 2.4GHz");
 984     }
 985
 986 #if 1
 987     entries = sizeof(otusBank) / sizeof(*otusBank);
 988     for (i=0; i<entries; i++)
 989     {
 990         reg_write(otusBank[i][0], otusBank[i][freqIndex]);
 991     }
 992 #else
 993     /* Bank0 */
 994     entries = sizeof(ar5416Bank0) / sizeof(*ar5416Bank0);
 995     for (i=0; i<entries; i++)
 996     {
 997         reg_write(ar5416Bank0[i][0], ar5416Bank0[i][1]);
 998     }
 999     /* Bank1 */
1000     entries = sizeof(ar5416Bank1) / sizeof(*ar5416Bank1);
1001     for (i=0; i<entries; i++)
1002     {
1003         reg_write(ar5416Bank1[i][0], ar5416Bank1[i][1]);
1004     }
1005     /* Bank2 */
1006     entries = sizeof(ar5416Bank2) / sizeof(*ar5416Bank2);
1007     for (i=0; i<entries; i++)
1008     {
1009         reg_write(ar5416Bank2[i][0], ar5416Bank2[i][1]);
1010     }
1011     /* Bank3 */
1012     entries = sizeof(ar5416Bank3) / sizeof(*ar5416Bank3);
1013     for (i=0; i<entries; i++)
1014     {
1015         reg_write(ar5416Bank3[i][0], ar5416Bank3[i][freqIndex]);
1016     }
1017     /* Bank5 */
1018     reg_write (0x98b0,  0x00000013);
1019     reg_write (0x98e4,  0x00000002);
1020     /* Bank6 */
1021     entries = sizeof(ar5416Bank6) / sizeof(*ar5416Bank6);
1022     for (i=0; i<entries; i++)
1023     {
1024         reg_write(ar5416Bank6[i][0], ar5416Bank6[i][freqIndex]);
1025     }
1026     /* Bank7 */
1027     entries = sizeof(ar5416Bank7) / sizeof(*ar5416Bank7);
1028     for (i=0; i<entries; i++)
1029     {
1030         reg_write(ar5416Bank7[i][0], ar5416Bank7[i][1]);
1031     }
1032 #endif
1033
1034     zfFlushDelayWrite(dev);
1035 }
1036
1037 /* Bank 4 */
1038 void zfSetBank4AndPowerTable(zdev_t* dev, u32_t frequency, u8_t bw40,
1039         u8_t extOffset)
1040 {
1041     u32_t chup = 1;
1042         u32_t bmode_LF_synth_freq = 0;
1043         u32_t amode_refsel_1 = 0;
1044         u32_t amode_refsel_0 = 1;
1045         u32_t addr2 = 1;
1046         u32_t addr1 = 0;
1047         u32_t addr0 = 0;
1048
1049         u32_t d1;
1050         u32_t d0;
1051         u32_t tmp_0;
1052         u32_t tmp_1;
1053         u32_t data0;
1054         u32_t data1;
1055
1056         u8_t chansel;
1057         u8_t chan_sel;
1058         u32_t temp_chan_sel;
1059
1060     u16_t i;
1061
1062     zmw_get_wlan_dev(dev);
1063
1064
1065     /* if enable 802.11h, need to record curent channel index in channel array */
1066     if (wd->sta.DFSEnable)
1067     {
1068         for (i = 0; i < wd->regulationTable.allowChannelCnt; i++)
1069         {
1070             if (wd->regulationTable.allowChannel[i].channel == frequency)
1071                 break;
1072         }
1073         wd->regulationTable.CurChIndex = i;
1074     }
1075
1076         if (bw40 == 1)
1077         {
1078         if (extOffset == 1)
1079         {
1080             frequency += 10;
1081         }
1082         else
1083         {
1084             frequency -= 10;
1085         }
1086
1087         }
1088
1089
1090         if ( frequency > 3000 )
1091         {
1092             if ( frequency % 10 )
1093             {
1094                 /* 5M */
1095             chan_sel = (u8_t)((frequency - 4800)/5);
1096             chan_sel = (u8_t)(chan_sel & 0xff);
1097             chansel  = (u8_t)reverse_bits(chan_sel);
1098         }
1099         else
1100         {
1101             /* 10M : improve Tx EVM */
1102             chan_sel = (u8_t)((frequency - 4800)/10);
1103             chan_sel = (u8_t)(chan_sel & 0xff)<<1;
1104             chansel  = (u8_t)reverse_bits(chan_sel);
1105
1106                 amode_refsel_1 = 1;
1107                 amode_refsel_0 = 0;
1108         }
1109         }
1110         else
1111         {
1112         //temp_chan_sel = (((frequency - 672)*2) - 3040)/10;
1113         if (frequency == 2484)
1114         {
1115                 temp_chan_sel = 10 + (frequency - 2274)/5 ;
1116                 bmode_LF_synth_freq = 1;
1117         }
1118         else
1119         {
1120             temp_chan_sel = 16 + (frequency - 2272)/5 ;
1121             bmode_LF_synth_freq = 0;
1122         }
1123         chan_sel = (u8_t)(temp_chan_sel << 2) & 0xff;
1124         chansel  = (u8_t)reverse_bits(chan_sel);
1125         }
1126
1127         d1   = chansel;   //# 8 bits of chan
1128         d0   = addr0<<7 | addr1<<6 | addr2<<5
1129                         | amode_refsel_0<<3 | amode_refsel_1<<2
1130                         | bmode_LF_synth_freq<<1 | chup;
1131
1132     tmp_0 = d0 & 0x1f;  //# 5-1
1133     tmp_1 = d1 & 0x1f;  //# 5-1
1134     data0 = tmp_1<<5 | tmp_0;
1135
1136     tmp_0 = d0>>5 & 0x7;  //# 8-6
1137     tmp_1 = d1>>5 & 0x7;  //# 8-6
1138     data1 = tmp_1<<5 | tmp_0;
1139
1140     /* Bank4 */
1141         reg_write (0x9800+(0x2c<<2), data0);
1142         reg_write (0x9800+(0x3a<<2), data1);
1143         //zm_debug_msg1("0x9800+(0x2c<<2 =  ", data0);
1144         //zm_debug_msg1("0x9800+(0x3a<<2 =  ", data1);
1145
1146
1147     zfFlushDelayWrite(dev);
1148
1149     zfwSleep(dev, 10);
1150
1151     return;
1152 }
1153
1154
1155 struct zsPhyFreqPara
1156 {
1157     u32_t coeff_exp;
1158     u32_t coeff_man;
1159     u32_t coeff_exp_shgi;
1160     u32_t coeff_man_shgi;
1161 };
1162
1163 struct zsPhyFreqTable
1164 {
1165     u32_t frequency;
1166     struct zsPhyFreqPara FpgaDynamicHT;
1167     struct zsPhyFreqPara FpgaStaticHT;
1168     struct zsPhyFreqPara ChipST20Mhz;
1169     struct zsPhyFreqPara Chip2040Mhz;
1170     struct zsPhyFreqPara Chip2040ExtAbove;
1171 };
1172
1173 const struct zsPhyFreqTable zgPhyFreqCoeff[] =
1174 {
1175 /*Index   freq  FPGA DYNAMIC_HT2040_EN  FPGA STATIC_HT20    Real Chip static20MHz     Real Chip 2040MHz   Real Chip 2040Mhz  */
1176        /* fclk =         10.8                21.6                  40                  ext below 40       ext above 40       */
1177 /*  0 */ {2412, {5, 23476, 5, 21128}, {4, 23476, 4, 21128}, {3, 21737, 3, 19563}, {3, 21827, 3, 19644}, {3, 21647, 3, 19482}},
1178 /*  1 */ {2417, {5, 23427, 5, 21084}, {4, 23427, 4, 21084}, {3, 21692, 3, 19523}, {3, 21782, 3, 19604}, {3, 21602, 3, 19442}},
1179 /*  2 */ {2422, {5, 23379, 5, 21041}, {4, 23379, 4, 21041}, {3, 21647, 3, 19482}, {3, 21737, 3, 19563}, {3, 21558, 3, 19402}},
1180 /*  3 */ {2427, {5, 23330, 5, 20997}, {4, 23330, 4, 20997}, {3, 21602, 3, 19442}, {3, 21692, 3, 19523}, {3, 21514, 3, 19362}},
1181 /*  4 */ {2432, {5, 23283, 5, 20954}, {4, 23283, 4, 20954}, {3, 21558, 3, 19402}, {3, 21647, 3, 19482}, {3, 21470, 3, 19323}},
1182 /*  5 */ {2437, {5, 23235, 5, 20911}, {4, 23235, 4, 20911}, {3, 21514, 3, 19362}, {3, 21602, 3, 19442}, {3, 21426, 3, 19283}},
1183 /*  6 */ {2442, {5, 23187, 5, 20868}, {4, 23187, 4, 20868}, {3, 21470, 3, 19323}, {3, 21558, 3, 19402}, {3, 21382, 3, 19244}},
1184 /*  7 */ {2447, {5, 23140, 5, 20826}, {4, 23140, 4, 20826}, {3, 21426, 3, 19283}, {3, 21514, 3, 19362}, {3, 21339, 3, 19205}},
1185 /*  8 */ {2452, {5, 23093, 5, 20783}, {4, 23093, 4, 20783}, {3, 21382, 3, 19244}, {3, 21470, 3, 19323}, {3, 21295, 3, 19166}},
1186 /*  9 */ {2457, {5, 23046, 5, 20741}, {4, 23046, 4, 20741}, {3, 21339, 3, 19205}, {3, 21426, 3, 19283}, {3, 21252, 3, 19127}},
1187 /* 10 */ {2462, {5, 22999, 5, 20699}, {4, 22999, 4, 20699}, {3, 21295, 3, 19166}, {3, 21382, 3, 19244}, {3, 21209, 3, 19088}},
1188 /* 11 */ {2467, {5, 22952, 5, 20657}, {4, 22952, 4, 20657}, {3, 21252, 3, 19127}, {3, 21339, 3, 19205}, {3, 21166, 3, 19050}},
1189 /* 12 */ {2472, {5, 22906, 5, 20615}, {4, 22906, 4, 20615}, {3, 21209, 3, 19088}, {3, 21295, 3, 19166}, {3, 21124, 3, 19011}},
1190 /* 13 */ {2484, {5, 22795, 5, 20516}, {4, 22795, 4, 20516}, {3, 21107, 3, 18996}, {3, 21192, 3, 19073}, {3, 21022, 3, 18920}},
1191 /* 14 */ {4920, {6, 23018, 6, 20716}, {5, 23018, 5, 20716}, {4, 21313, 4, 19181}, {4, 21356, 4, 19220}, {4, 21269, 4, 19142}},
1192 /* 15 */ {4940, {6, 22924, 6, 20632}, {5, 22924, 5, 20632}, {4, 21226, 4, 19104}, {4, 21269, 4, 19142}, {4, 21183, 4, 19065}},
1193 /* 16 */ {4960, {6, 22832, 6, 20549}, {5, 22832, 5, 20549}, {4, 21141, 4, 19027}, {4, 21183, 4, 19065}, {4, 21098, 4, 18988}},
1194 /* 17 */ {4980, {6, 22740, 6, 20466}, {5, 22740, 5, 20466}, {4, 21056, 4, 18950}, {4, 21098, 4, 18988}, {4, 21014, 4, 18912}},
1195 /* 18 */ {5040, {6, 22469, 6, 20223}, {5, 22469, 5, 20223}, {4, 20805, 4, 18725}, {4, 20846, 4, 18762}, {4, 20764, 4, 18687}},
1196 /* 19 */ {5060, {6, 22381, 6, 20143}, {5, 22381, 5, 20143}, {4, 20723, 4, 18651}, {4, 20764, 4, 18687}, {4, 20682, 4, 18614}},
1197 /* 20 */ {5080, {6, 22293, 6, 20063}, {5, 22293, 5, 20063}, {4, 20641, 4, 18577}, {4, 20682, 4, 18614}, {4, 20601, 4, 18541}},
1198 /* 21 */ {5180, {6, 21862, 6, 19676}, {5, 21862, 5, 19676}, {4, 20243, 4, 18219}, {4, 20282, 4, 18254}, {4, 20204, 4, 18183}},
1199 /* 22 */ {5200, {6, 21778, 6, 19600}, {5, 21778, 5, 19600}, {4, 20165, 4, 18148}, {4, 20204, 4, 18183}, {4, 20126, 4, 18114}},
1200 /* 23 */ {5220, {6, 21695, 6, 19525}, {5, 21695, 5, 19525}, {4, 20088, 4, 18079}, {4, 20126, 4, 18114}, {4, 20049, 4, 18044}},
1201 /* 24 */ {5240, {6, 21612, 6, 19451}, {5, 21612, 5, 19451}, {4, 20011, 4, 18010}, {4, 20049, 4, 18044}, {4, 19973, 4, 17976}},
1202 /* 25 */ {5260, {6, 21530, 6, 19377}, {5, 21530, 5, 19377}, {4, 19935, 4, 17941}, {4, 19973, 4, 17976}, {4, 19897, 4, 17907}},
1203 /* 26 */ {5280, {6, 21448, 6, 19303}, {5, 21448, 5, 19303}, {4, 19859, 4, 17873}, {4, 19897, 4, 17907}, {4, 19822, 4, 17840}},
1204 /* 27 */ {5300, {6, 21367, 6, 19230}, {5, 21367, 5, 19230}, {4, 19784, 4, 17806}, {4, 19822, 4, 17840}, {4, 19747, 4, 17772}},
1205 /* 28 */ {5320, {6, 21287, 6, 19158}, {5, 21287, 5, 19158}, {4, 19710, 4, 17739}, {4, 19747, 4, 17772}, {4, 19673, 4, 17706}},
1206 /* 29 */ {5500, {6, 20590, 6, 18531}, {5, 20590, 5, 18531}, {4, 19065, 4, 17159}, {4, 19100, 4, 17190}, {4, 19030, 4, 17127}},
1207 /* 30 */ {5520, {6, 20516, 6, 18464}, {5, 20516, 5, 18464}, {4, 18996, 4, 17096}, {4, 19030, 4, 17127}, {4, 18962, 4, 17065}},
1208 /* 31 */ {5540, {6, 20442, 6, 18397}, {5, 20442, 5, 18397}, {4, 18927, 4, 17035}, {4, 18962, 4, 17065}, {4, 18893, 4, 17004}},
1209 /* 32 */ {5560, {6, 20368, 6, 18331}, {5, 20368, 5, 18331}, {4, 18859, 4, 16973}, {4, 18893, 4, 17004}, {4, 18825, 4, 16943}},
1210 /* 33 */ {5580, {6, 20295, 6, 18266}, {5, 20295, 5, 18266}, {4, 18792, 4, 16913}, {4, 18825, 4, 16943}, {4, 18758, 4, 16882}},
1211 /* 34 */ {5600, {6, 20223, 6, 18200}, {5, 20223, 5, 18200}, {4, 18725, 4, 16852}, {4, 18758, 4, 16882}, {4, 18691, 4, 16822}},
1212 /* 35 */ {5620, {6, 20151, 6, 18136}, {5, 20151, 5, 18136}, {4, 18658, 4, 16792}, {4, 18691, 4, 16822}, {4, 18625, 4, 16762}},
1213 /* 36 */ {5640, {6, 20079, 6, 18071}, {5, 20079, 5, 18071}, {4, 18592, 4, 16733}, {4, 18625, 4, 16762}, {4, 18559, 4, 16703}},
1214 /* 37 */ {5660, {6, 20008, 6, 18007}, {5, 20008, 5, 18007}, {4, 18526, 4, 16673}, {4, 18559, 4, 16703}, {4, 18493, 4, 16644}},
1215 /* 38 */ {5680, {6, 19938, 6, 17944}, {5, 19938, 5, 17944}, {4, 18461, 4, 16615}, {4, 18493, 4, 16644}, {4, 18428, 4, 16586}},
1216 /* 39 */ {5700, {6, 19868, 6, 17881}, {5, 19868, 5, 17881}, {4, 18396, 4, 16556}, {4, 18428, 4, 16586}, {4, 18364, 4, 16527}},
1217 /* 40 */ {5745, {6, 19712, 6, 17741}, {5, 19712, 5, 17741}, {4, 18252, 4, 16427}, {4, 18284, 4, 16455}, {4, 18220, 4, 16398}},
1218 /* 41 */ {5765, {6, 19644, 6, 17679}, {5, 19644, 5, 17679}, {4, 18189, 5, 32740}, {4, 18220, 4, 16398}, {4, 18157, 5, 32683}},
1219 /* 42 */ {5785, {6, 19576, 6, 17618}, {5, 19576, 5, 17618}, {4, 18126, 5, 32626}, {4, 18157, 5, 32683}, {4, 18094, 5, 32570}},
1220 /* 43 */ {5805, {6, 19508, 6, 17558}, {5, 19508, 5, 17558}, {4, 18063, 5, 32514}, {4, 18094, 5, 32570}, {4, 18032, 5, 32458}},
1221 /* 44 */ {5825, {6, 19441, 6, 17497}, {5, 19441, 5, 17497}, {4, 18001, 5, 32402}, {4, 18032, 5, 32458}, {4, 17970, 5, 32347}},
1222 /* 45 */ {5170, {6, 21904, 6, 19714}, {5, 21904, 5, 19714}, {4, 20282, 4, 18254}, {4, 20321, 4, 18289}, {4, 20243, 4, 18219}},
1223 /* 46 */ {5190, {6, 21820, 6, 19638}, {5, 21820, 5, 19638}, {4, 20204, 4, 18183}, {4, 20243, 4, 18219}, {4, 20165, 4, 18148}},
1224 /* 47 */ {5210, {6, 21736, 6, 19563}, {5, 21736, 5, 19563}, {4, 20126, 4, 18114}, {4, 20165, 4, 18148}, {4, 20088, 4, 18079}},
1225 /* 48 */ {5230, {6, 21653, 6, 19488}, {5, 21653, 5, 19488}, {4, 20049, 4, 18044}, {4, 20088, 4, 18079}, {4, 20011, 4, 18010}}
1226 };
1227 /* to reduce search time, please modify this define if you add or delete channel in table */
1228 #define First5GChannelIndex 14
1229
1230 void zfGetHwTurnOffdynParam(zdev_t* dev,
1231                             u32_t frequency, u8_t bw40, u8_t extOffset,
1232                             int* delta_slope_coeff_exp,
1233                             int* delta_slope_coeff_man,
1234                             int* delta_slope_coeff_exp_shgi,
1235                             int* delta_slope_coeff_man_shgi)
1236 {
1237     /* Get param for turnoffdyn */
1238     u16_t i, arraySize;
1239
1240     //zmw_get_wlan_dev(dev);
1241
1242     arraySize = sizeof(zgPhyFreqCoeff)/sizeof(struct zsPhyFreqTable);
1243     if (frequency < 3000)
1244     {
1245         /* 2.4GHz Channel */
1246         for (i = 0; i < First5GChannelIndex; i++)
1247         {
1248             if (frequency == zgPhyFreqCoeff[i].frequency)
1249                 break;
1250         }
1251
1252         if (i < First5GChannelIndex)
1253         {
1254         }
1255         else
1256         {
1257             zm_msg1_scan(ZM_LV_0, "Unsupported 2.4G frequency = ", frequency);
1258             return;
1259         }
1260     }
1261     else
1262     {
1263         /* 5GHz Channel */
1264         for (i = First5GChannelIndex; i < arraySize; i++)
1265         {
1266             if (frequency == zgPhyFreqCoeff[i].frequency)
1267                 break;
1268         }
1269
1270         if (i < arraySize)
1271         {
1272         }
1273         else
1274         {
1275             zm_msg1_scan(ZM_LV_0, "Unsupported 5G frequency = ", frequency);
1276             return;
1277         }
1278     }
1279
1280     /* FPGA DYNAMIC_HT2040_EN        fclk = 10.8  */
1281     /* FPGA STATIC_HT20_             fclk = 21.6  */
1282     /* Real Chip                     fclk = 40    */
1283     #if ZM_FPGA_PHY == 1
1284     //fclk = 10.8;
1285     *delta_slope_coeff_exp = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_exp;
1286     *delta_slope_coeff_man = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_man;
1287     *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_exp_shgi;
1288     *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_man_shgi;
1289     #else
1290     //fclk = 40;
1291     if (bw40)
1292     {
1293         /* ht2040 */
1294         if (extOffset == 1) {
1295             *delta_slope_coeff_exp = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_exp;
1296             *delta_slope_coeff_man = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_man;
1297             *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_exp_shgi;
1298             *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_man_shgi;
1299         }
1300         else {
1301             *delta_slope_coeff_exp = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_exp;
1302             *delta_slope_coeff_man = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_man;
1303             *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_exp_shgi;
1304             *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_man_shgi;
1305         }
1306     }
1307     else
1308     {
1309         /* static 20 */
1310         *delta_slope_coeff_exp = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_exp;
1311         *delta_slope_coeff_man = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_man;
1312         *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_exp_shgi;
1313         *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_man_shgi;
1314     }
1315     #endif
1316 }
1317
1318 /* Main routin frequency setting function */
1319 /* If 2.4G/5G switch, PHY need resetting BB and RF for band switch */
1320 /* Do the setting switch in zfSendFrequencyCmd() */
1321 void zfHpSetFrequencyEx(zdev_t* dev, u32_t frequency, u8_t bw40,
1322         u8_t extOffset, u8_t initRF)
1323 {
1324     u32_t cmd[9];
1325     u16_t ret;
1326     u8_t old_band;
1327     u8_t new_band;
1328     u32_t checkLoopCount;
1329     u32_t tmpValue;
1330
1331     int delta_slope_coeff_exp;
1332     int delta_slope_coeff_man;
1333     int delta_slope_coeff_exp_shgi;
1334     int delta_slope_coeff_man_shgi;
1335     struct zsHpPriv* hpPriv;
1336
1337     zmw_get_wlan_dev(dev);
1338     hpPriv = wd->hpPrivate;
1339
1340     zm_msg1_scan(ZM_LV_1, "Frequency = ", frequency);
1341     zm_msg1_scan(ZM_LV_1, "bw40 = ", bw40);
1342     zm_msg1_scan(ZM_LV_1, "extOffset = ", extOffset);
1343
1344     if ( hpPriv->coldResetNeedFreq )
1345     {
1346         hpPriv->coldResetNeedFreq = 0;
1347         initRF = 2;
1348         zm_debug_msg0("zfHpSetFrequencyEx: Do ColdReset ");
1349     }
1350     if ( hpPriv->isSiteSurvey == 2 )
1351     {
1352         /* wait time for AGC and noise calibration : not in sitesurvey and connected */
1353         checkLoopCount = 2000; /* 2000*100 = 200ms */
1354     }
1355     else
1356     {
1357         /* wait time for AGC and noise calibration : in sitesurvey */
1358         checkLoopCount = 1000; /* 1000*100 = 100ms */
1359     }
1360
1361     hpPriv->latestFrequency = frequency;
1362     hpPriv->latestBw40 = bw40;
1363     hpPriv->latestExtOffset = extOffset;
1364
1365     if ((hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_GENERAL) ||
1366         (hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK))
1367     {
1368         if ( frequency <= ZM_CH_G_14 )
1369         {
1370             /* workaround for 11g Ad Hoc beacon distribution */
1371             zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, 0x7f0007);
1372             //zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_AIFS, 0x1c04901c);
1373         }
1374     }
1375
1376     /* AHB, DAC, ADC clock selection by static20/ht2040 */
1377     zfSelAdcClk(dev, bw40, frequency);
1378
1379     /* clear bb_heavy_clip_enable */
1380     reg_write(0x99e0, 0x200);
1381     zfFlushDelayWrite(dev);
1382
1383     /* Set CTS/RTS rate */
1384     if ( frequency > ZM_CH_G_14 )
1385     {
1386         //zfHpSetRTSCTSRate(dev, 0x10b010b);  /* OFDM 6M */
1387             new_band = 1;
1388         }
1389     else
1390     {
1391         //zfHpSetRTSCTSRate(dev, 0x30003);  /* CCK 11M */
1392         new_band = 0;
1393     }
1394
1395     if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency > ZM_CH_G_14)
1396         old_band = 1;
1397     else
1398         old_band = 0;
1399
1400     //Workaround for 2.4GHz only device
1401     if ((hpPriv->OpFlags & 0x1) == 0)
1402     {
1403         if ((((struct zsHpPriv*)wd->hpPrivate)->hwFrequency == ZM_CH_G_1) && (frequency == ZM_CH_G_2))
1404         {
1405             /* Force to do band switching */
1406             old_band = 1;
1407         }
1408     }
1409
1410     /* Notify channel switch to firmware */
1411     /* TX/RX must be stopped by now */
1412     cmd[0] = 0 | (ZM_CMD_FREQ_STRAT << 8);
1413     ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, 0);
1414
1415     if ((initRF != 0) || (new_band != old_band)
1416             || (((struct zsHpPriv*)wd->hpPrivate)->hwBw40 != bw40))
1417     {
1418         /* band switch */
1419         zm_msg0_scan(ZM_LV_1, "=====band switch=====");
1420
1421         if (initRF == 2 )
1422         {
1423             //Cold reset BB/ADDA
1424             zfDelayWriteInternalReg(dev, 0x1d4004, 0x800);
1425             zfFlushDelayWrite(dev);
1426             zm_msg0_scan(ZM_LV_1, "Do cold reset BB/ADDA");
1427         }
1428         else
1429         {
1430             //Warm reset BB/ADDA
1431             zfDelayWriteInternalReg(dev, 0x1d4004, 0x400);
1432             zfFlushDelayWrite(dev);
1433         }
1434
1435         /* reset workaround state to default */
1436         hpPriv->rxStrongRSSI = 0;
1437         hpPriv->strongRSSI = 0;
1438
1439         zfDelayWriteInternalReg(dev, 0x1d4004, 0x0);
1440         zfFlushDelayWrite(dev);
1441
1442         zfInitPhy(dev, frequency, bw40);
1443
1444 //        zfiCheckRifs(dev);
1445
1446         /* Bank 0 1 2 3 5 6 7 */
1447         zfSetRfRegs(dev, frequency);
1448         /* Bank 4 */
1449         zfSetBank4AndPowerTable(dev, frequency, bw40, extOffset);
1450
1451         cmd[0] = 32 | (ZM_CMD_RF_INIT << 8);
1452     }
1453     else //((new_band == old_band) && !initRF)
1454     {
1455        /* same band */
1456
1457        /* Force disable CR671 bit20 / 7823                                            */
1458        /* The bug has to do with the polarity of the pdadc offset calibration.  There */
1459        /* is an initial calibration that is OK, and there is a continuous             */
1460        /* calibration that updates the pddac with the wrong polarity.  Fortunately    */
1461        /* the second loop can be disabled with a bit called en_pd_dc_offset_thr.      */
1462 #if 0
1463         cmdB[0] = 8 | (ZM_CMD_BITAND << 8);;
1464         cmdB[1] = (0xa27c + 0x1bc000);
1465         cmdB[2] = 0xffefffff;
1466         ret = zfIssueCmd(dev, cmdB, 12, ZM_OID_INTERNAL_WRITE, 0);
1467 #endif
1468
1469        /* Bank 4 */
1470        zfSetBank4AndPowerTable(dev, frequency, bw40, extOffset);
1471
1472
1473         cmd[0] = 32 | (ZM_CMD_FREQUENCY << 8);
1474     }
1475
1476     /* Compatibility for new layout UB83 */
1477     /* Setting code at CR1 here move from the func:zfHwHTEnable() in firmware */
1478     if (((struct zsHpPriv*)wd->hpPrivate)->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
1479     {
1480         /* UB83 : one stream */
1481         tmpValue = 0;
1482     }
1483     else
1484     {
1485         /* UB81, UB82 : two stream */
1486         tmpValue = 0x100;
1487     }
1488
1489     if (1) //if (((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE == 1)
1490         {
1491         if (bw40 == 1)
1492                 {
1493                         if (extOffset == 1) {
1494                 reg_write(0x9804, tmpValue | 0x2d4); //3d4 for real
1495                         }
1496                         else {
1497                                 reg_write(0x9804, tmpValue | 0x2c4);   //3c4 for real
1498                         }
1499                         //# Dyn HT2040.Refer to Reg 1.
1500             //#[3]:single length (4us) 1st HT long training symbol; use Walsh spatial spreading for 2 chains 2 streams TX
1501             //#[c]:allow short GI for HT40 packets; enable HT detection.
1502             //#[4]:enable 20/40 MHz channel detection.
1503         }
1504         else
1505             {
1506             reg_write(0x9804, tmpValue | 0x240);
1507                     //# Static HT20
1508             //#[3]:single length (4us) 1st HT long training symbol; use Walsh spatial spreading for 2 chains 2 streams TX
1509             //#[4]:Otus don't allow short GI for HT20 packets yet; enable HT detection.
1510             //#[0]:disable 20/40 MHz channel detection.
1511         }
1512     }
1513     else
1514         {
1515         reg_write(0x9804, 0x0);
1516                 //# Legacy;# Direct Mapping for each chain.
1517         //#Be modified by Oligo to add dynanic for legacy.
1518         if (bw40 == 1)
1519                 {
1520             reg_write(0x9804, 0x4);     //# Dyn Legacy .Refer to reg 1.
1521         }
1522         else
1523                 {
1524             reg_write(0x9804, 0x0);    //# Static Legacy
1525         }
1526         }
1527         zfFlushDelayWrite(dev);
1528         /* end of ub83 compatibility */
1529
1530     /* Set Power, TPC, Gain table... */
1531         zfSetPowerCalTable(dev, frequency, bw40, extOffset);
1532
1533
1534     /* store frequency */
1535     ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = (u16_t)frequency;
1536     ((struct zsHpPriv*)wd->hpPrivate)->hwBw40 = bw40;
1537     ((struct zsHpPriv*)wd->hpPrivate)->hwExtOffset = extOffset;
1538
1539     zfGetHwTurnOffdynParam(dev,
1540                            frequency, bw40, extOffset,
1541                            &delta_slope_coeff_exp,
1542                            &delta_slope_coeff_man,
1543                            &delta_slope_coeff_exp_shgi,
1544                            &delta_slope_coeff_man_shgi);
1545
1546     /* related functions */
1547     frequency = frequency*1000;
1548     /* len[36] : type[0x30] : seq[?] */
1549 //    cmd[0] = 28 | (ZM_CMD_FREQUENCY << 8);
1550     cmd[1] = frequency;
1551     cmd[2] = bw40;//((struct zsHpPriv*)wd->hpPrivate)->hw_DYNAMIC_HT2040_EN;
1552     cmd[3] = (extOffset<<2)|0x1;//((wd->ExtOffset << 2) | ((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE);
1553     cmd[4] = delta_slope_coeff_exp;
1554     cmd[5] = delta_slope_coeff_man;
1555     cmd[6] = delta_slope_coeff_exp_shgi;
1556     cmd[7] = delta_slope_coeff_man_shgi;
1557     cmd[8] = checkLoopCount;
1558
1559     ret = zfIssueCmd(dev, cmd, 36, ZM_CMD_SET_FREQUENCY, 0);
1560
1561     // delay temporarily, wait for new PHY and RF
1562     //zfwSleep(dev, 1000);
1563 }
1564
1565
1566 /******************** Key ********************/
1567
1568 u16_t zfHpResetKeyCache(zdev_t* dev)
1569 {
1570     u8_t i;
1571     u32_t key[4] = {0, 0, 0, 0};
1572     struct zsHpPriv* hpPriv;
1573
1574     zmw_get_wlan_dev(dev);
1575     hpPriv=wd->hpPrivate;
1576
1577     for(i=0;i<4;i++)
1578     {
1579         zfHpSetDefaultKey(dev, i, ZM_WEP64, key, NULL);
1580     }
1581     zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_L, 0x00);
1582     zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_H, 0x00);
1583     zfFlushDelayWrite(dev);
1584
1585     hpPriv->camRollCallTable = (u64_t) 0;
1586
1587     return 0;
1588 }
1589
1590
1591 /************************************************************************/
1592 /*                                                                      */
1593 /*    FUNCTION DESCRIPTION                  zfSetKey                    */
1594 /*      Set key.                                                        */
1595 /*                                                                      */
1596 /*    INPUTS                                                            */
1597 /*      dev : device pointer                                            */
1598 /*                                                                      */
1599 /*    OUTPUTS                                                           */
1600 /*      0 : success                                                     */
1601 /*      other : fail                                                    */
1602 /*                                                                      */
1603 /*    AUTHOR                                                            */
1604 /*      Stephen Chen        ZyDAS Technology Corporation    2006.1      */
1605 /*                                                                      */
1606 /************************************************************************/
1607 /* ! please use zfCoreSetKey() in 80211Core for SetKey */
1608 u32_t zfHpSetKey(zdev_t* dev, u8_t user, u8_t keyId, u8_t type,
1609         u16_t* mac, u32_t* key)
1610 {
1611     u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1612     u16_t ret;
1613     u16_t i;
1614     struct zsHpPriv* hpPriv;
1615
1616     zmw_get_wlan_dev(dev);
1617     hpPriv=wd->hpPrivate;
1618
1619 #if 0   /* remove to zfCoreSetKey() */
1620     zmw_declare_for_critical_section();
1621
1622     zmw_enter_critical_section(dev);
1623     wd->sta.flagKeyChanging++;
1624     zm_debug_msg1("   zfHpSetKey++++ ", wd->sta.flagKeyChanging);
1625     zmw_leave_critical_section(dev);
1626 #endif
1627
1628     cmd[0] = 0x0000281C;
1629     cmd[1] = ((u32_t)keyId<<16) + (u32_t)user;
1630     cmd[2] = ((u32_t)mac[0]<<16) + (u32_t)type;
1631     cmd[3] = ((u32_t)mac[2]<<16) + ((u32_t)mac[1]);
1632
1633     for (i=0; i<4; i++)
1634     {
1635         cmd[4+i] = key[i];
1636     }
1637
1638     if (user < 64)
1639     {
1640         hpPriv->camRollCallTable |= ((u64_t) 1) << user;
1641     }
1642
1643     //ret = zfIssueCmd(dev, cmd, 32, ZM_OID_INTERNAL_WRITE, NULL);
1644     ret = zfIssueCmd(dev, cmd, 32, ZM_CMD_SET_KEY, NULL);
1645     return ret;
1646 }
1647
1648
1649 u32_t zfHpSetApPairwiseKey(zdev_t* dev, u16_t* staMacAddr, u8_t type,
1650         u32_t* key, u32_t* micKey, u16_t staAid)
1651 {
1652     if ((staAid!=0) && (staAid<64))
1653     {
1654         zfHpSetKey(dev, (staAid-1), 0, type, staMacAddr, key);
1655                 if ((type == ZM_TKIP)
1656 #ifdef ZM_ENABLE_CENC
1657          || (type == ZM_CENC)
1658 #endif //ZM_ENABLE_CENC
1659            )
1660             zfHpSetKey(dev, (staAid-1), 1, type, staMacAddr, micKey);
1661         return 0;
1662     }
1663     return 1;
1664 }
1665
1666 u32_t zfHpSetApGroupKey(zdev_t* dev, u16_t* apMacAddr, u8_t type,
1667         u32_t* key, u32_t* micKey, u16_t vapId)
1668 {
1669     zfHpSetKey(dev, ZM_USER_KEY_DEFAULT - 1 - vapId, 0, type, apMacAddr, key);  // 6D18 modify from 0 to 1 ??
1670             if ((type == ZM_TKIP)
1671 #ifdef ZM_ENABLE_CENC
1672          || (type == ZM_CENC)
1673 #endif //ZM_ENABLE_CENC
1674            )
1675         zfHpSetKey(dev, ZM_USER_KEY_DEFAULT - 1 - vapId, 1, type, apMacAddr, micKey);
1676     return 0;
1677 }
1678
1679 u32_t zfHpSetDefaultKey(zdev_t* dev, u8_t keyId, u8_t type, u32_t* key, u32_t* micKey)
1680 {
1681     u16_t macAddr[3] = {0, 0, 0};
1682
1683     #ifdef ZM_ENABLE_IBSS_WPA2PSK
1684     struct zsHpPriv* hpPriv;
1685
1686     zmw_get_wlan_dev(dev);
1687     hpPriv = wd->hpPrivate;
1688
1689     if ( hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK )
1690     { /* If not wpa2psk , use traditional */
1691       /* Because the bug of chip , defaultkey should follow the key map rule in register 700 */
1692         if ( keyId == 0 )
1693             zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key);
1694         else
1695             zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 1, type, macAddr, key);
1696     }
1697     else
1698         zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key);
1699     #else
1700         zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key);
1701     #endif
1702             if ((type == ZM_TKIP)
1703
1704 #ifdef ZM_ENABLE_CENC
1705          || (type == ZM_CENC)
1706 #endif //ZM_ENABLE_CENC
1707            )
1708     {
1709         zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 1, type, macAddr, micKey);
1710     }
1711
1712     return 0;
1713 }
1714
1715 u32_t zfHpSetPerUserKey(zdev_t* dev, u8_t user, u8_t keyId, u8_t* mac, u8_t type, u32_t* key, u32_t* micKey)
1716 {
1717 #ifdef ZM_ENABLE_IBSS_WPA2PSK
1718     struct zsHpPriv* hpPriv;
1719
1720     zmw_get_wlan_dev(dev);
1721     hpPriv = wd->hpPrivate;
1722
1723     if ( hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK )
1724     { /* If not wpa2psk , use traditional */
1725         if(keyId)
1726         {  /* Set Group Key */
1727             zfHpSetKey(dev, user, 1, type, (u16_t *)mac, key);
1728         }
1729         else if(keyId == 0)
1730         {  /* Set Pairwise Key */
1731             zfHpSetKey(dev, user, 0, type, (u16_t *)mac, key);
1732         }
1733     }
1734     else
1735     {
1736         zfHpSetKey(dev, user, keyId, type, (u16_t *)mac, key);
1737     }
1738 #else
1739     zfHpSetKey(dev, user, keyId, type, (u16_t *)mac, key);
1740 #endif
1741
1742             if ((type == ZM_TKIP)
1743 #ifdef ZM_ENABLE_CENC
1744          || (type == ZM_CENC)
1745 #endif //ZM_ENABLE_CENC
1746            )
1747     {
1748         zfHpSetKey(dev, user, keyId + 1, type, (u16_t *)mac, micKey);
1749     }
1750     return 0;
1751 }
1752
1753 /************************************************************************/
1754 /*                                                                      */
1755 /*    FUNCTION DESCRIPTION                  zfHpRemoveKey               */
1756 /*      Remove key.                                                     */
1757 /*                                                                      */
1758 /*    INPUTS                                                            */
1759 /*      dev : device pointer                                            */
1760 /*                                                                      */
1761 /*    OUTPUTS                                                           */
1762 /*      0 : success                                                     */
1763 /*      other : fail                                                    */
1764 /*                                                                      */
1765 /*    AUTHOR                                                            */
1766 /*      Yuan-Gu Wei         ZyDAS Technology Corporation    2006.6      */
1767 /*                                                                      */
1768 /************************************************************************/
1769 u16_t zfHpRemoveKey(zdev_t* dev, u16_t user)
1770 {
1771     u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1772     u16_t ret = 0;
1773
1774     cmd[0] = 0x00002904;
1775     cmd[1] = (u32_t)user;
1776
1777     ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
1778     return ret;
1779 }
1780
1781
1782
1783 /******************** DMA ********************/
1784 u16_t zfHpStartRecv(zdev_t* dev)
1785 {
1786     zfDelayWriteInternalReg(dev, 0x1c3d30, 0x100);
1787     zfFlushDelayWrite(dev);
1788
1789     return 0;
1790 }
1791
1792 u16_t zfHpStopRecv(zdev_t* dev)
1793 {
1794     return 0;
1795 }
1796
1797
1798 /******************** MAC ********************/
1799 void zfInitMac(zdev_t* dev)
1800 {
1801     /* ACK extension register */
1802     // jhlee temp : change value 0x2c -> 0x40
1803     // honda resolve short preamble problem : 0x40 -> 0x75
1804     zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_EXTENSION, 0x40); // 0x28 -> 0x2c 6522:yflee
1805
1806     /* TxQ0/1/2/3 Retry MAX=2 => transmit 3 times and degrade rate for retry */
1807     /* PB42 AP crash issue:                                                  */
1808     /* Workaround the crash issue by CTS/RTS, set retry max to zero for      */
1809     /*   workaround tx underrun which enable CTS/RTS */
1810     zfDelayWriteInternalReg(dev, ZM_MAC_REG_RETRY_MAX, 0); // 0x11111 => 0
1811
1812     /* use hardware MIC check */
1813     zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000000);
1814
1815     /* Set Rx threshold to 1600 */
1816 #if ZM_LARGEPAYLOAD_TEST == 1
1817     zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc4000);
1818 #else
1819     #ifndef ZM_DISABLE_AMSDU8K_SUPPORT
1820     /* The maximum A-MSDU length is 3839/7935 */
1821     zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc1f80);
1822     #else
1823     zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc0f80);
1824     #endif
1825 #endif
1826
1827     //zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x10A);
1828     zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_PE_DELAY, 0x70);
1829     zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
1830     zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 9<<10);
1831
1832     /* CF-END mode */
1833     zfDelayWriteInternalReg(dev, 0x1c3b2c, 0x19000000);
1834
1835     //NAV protects ACK only (in TXOP)
1836     zfDelayWriteInternalReg(dev, 0x1c3b38, 0x201);
1837
1838
1839     /* Set Beacon PHY CTRL's TPC to 0x7, TA1=1 */
1840     /* OTUS set AM to 0x1 */
1841     zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_HT1, 0x8000170);
1842
1843     /* TODO : wep backoff protection 0x63c */
1844     zfDelayWriteInternalReg(dev, ZM_MAC_REG_BACKOFF_PROTECT, 0x105);
1845
1846     /* AGG test code*/
1847     /* Aggregation MAX number and timeout */
1848     zfDelayWriteInternalReg(dev, 0x1c3b9c, 0x10000a);
1849     /* Filter any control frames, BAR is bit 24 */
1850     zfDelayWriteInternalReg(dev, 0x1c368c, 0x0500ffff);
1851     /* Enable deaggregator */
1852     zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1853
1854     /* Basic rate */
1855     zfDelayWriteInternalReg(dev, ZM_MAC_REG_BASIC_RATE, 0x150f);
1856     zfDelayWriteInternalReg(dev, ZM_MAC_REG_MANDATORY_RATE, 0x150f);
1857     zfDelayWriteInternalReg(dev, ZM_MAC_REG_RTS_CTS_RATE, 0x10b01bb);
1858
1859     /* MIMO resposne control */
1860     zfDelayWriteInternalReg(dev, 0x1c3694, 0x4003C1E);/* bit 26~28  otus-AM */
1861
1862     /* Enable LED0 and LED1 */
1863     zfDelayWriteInternalReg(dev, 0x1d0100, 0x3);
1864     zfDelayWriteInternalReg(dev, 0x1d0104, 0x3);
1865
1866     /* switch MAC to OTUS interface */
1867     zfDelayWriteInternalReg(dev, 0x1c3600, 0x3);
1868
1869     /* RXMAC A-MPDU length threshold */
1870     zfDelayWriteInternalReg(dev, 0x1c3c50, 0xffff);
1871
1872         /* Phy register read timeout */
1873         zfDelayWriteInternalReg(dev, 0x1c3680, 0xf00008);
1874
1875         /* Disable Rx TimeOut : workaround for BB.
1876          *  OTUS would interrupt the rx frame that sent by OWL TxUnderRun
1877          *  because OTUS rx timeout behavior, then OTUS would not ack the BA for
1878          *  this AMPDU from OWL.
1879          *  Fix by Perry Hwang.  2007/05/10.
1880          *  0x1c362c : Rx timeout value : bit 27~16
1881          */
1882         zfDelayWriteInternalReg(dev, 0x1c362c, 0x0);
1883
1884     //Set USB Rx stream mode MAX packet number to 2
1885     //    Max packet number = *0x1e1110 + 1
1886     zfDelayWriteInternalReg(dev, 0x1e1110, 0x4);
1887     //Set USB Rx stream mode timeout to 10us
1888     zfDelayWriteInternalReg(dev, 0x1e1114, 0x80);
1889
1890     //Set CPU clock frequency to 88/80MHz
1891     zfDelayWriteInternalReg(dev, 0x1D4008, 0x73);
1892
1893     //Set WLAN DMA interrupt mode : generate int per packet
1894     zfDelayWriteInternalReg(dev, 0x1c3d7c, 0x110011);
1895
1896     /* 7807 */
1897     /* enable func : Reset FIFO1 and FIFO2 when queue-gnt is low */
1898     /* 0x1c3bb0 Bit2 */
1899     /* Disable SwReset in firmware for TxHang, enable reset FIFO func. */
1900     zfDelayWriteInternalReg(dev, 0x1c3bb0, 0x4);
1901
1902     /* Disables the CF_END frame */
1903     zfDelayWriteInternalReg(dev, ZM_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141E0F48);
1904
1905         /* Disable the SW Decrypt*/
1906         zfDelayWriteInternalReg(dev, 0x1c3678, 0x70);
1907     zfFlushDelayWrite(dev);
1908     //---------------------
1909
1910     /* Set TxQs CWMIN, CWMAX, AIFS and TXO to WME STA default. */
1911     zfUpdateDefaultQosParameter(dev, 0);
1912
1913     //zfSelAdcClk(dev, 0);
1914
1915     return;
1916 }
1917
1918
1919 u16_t zfHpSetSnifferMode(zdev_t* dev, u16_t on)
1920 {
1921     if (on != 0)
1922     {
1923         zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000001);
1924     }
1925     else
1926     {
1927         zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000000);
1928     }
1929     zfFlushDelayWrite(dev);
1930     return 0;
1931 }
1932
1933
1934 u16_t zfHpSetApStaMode(zdev_t* dev, u8_t mode)
1935 {
1936     struct zsHpPriv* hpPriv;
1937
1938     zmw_get_wlan_dev(dev);
1939     hpPriv = wd->hpPrivate;
1940     hpPriv->dot11Mode = mode;
1941
1942     switch(mode)
1943     {
1944         case ZM_HAL_80211_MODE_AP:
1945             zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f0000a1);
1946             zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1947             break;
1948
1949         case ZM_HAL_80211_MODE_STA:
1950             zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f000002);
1951             zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1952             break;
1953
1954         case ZM_HAL_80211_MODE_IBSS_GENERAL:
1955             zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f000000);
1956             zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1957             break;
1958
1959         case ZM_HAL_80211_MODE_IBSS_WPA2PSK:
1960             zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f0000e0);
1961             zfDelayWriteInternalReg(dev, 0x1c3c40, 0x41);       // for multiple ( > 2 ) stations IBSS network
1962             break;
1963
1964         default:
1965             goto skip;
1966     }
1967
1968     zfFlushDelayWrite(dev);
1969
1970 skip:
1971     return 0;
1972 }
1973
1974
1975 u16_t zfHpSetBssid(zdev_t* dev, u8_t* bssidSrc)
1976 {
1977     u32_t  address;
1978     u16_t *bssid = (u16_t *)bssidSrc;
1979
1980     address = bssid[0] + (((u32_t)bssid[1]) << 16);
1981     zfDelayWriteInternalReg(dev, 0x1c3618, address);
1982
1983     address = (u32_t)bssid[2];
1984     zfDelayWriteInternalReg(dev, 0x1c361C, address);
1985     zfFlushDelayWrite(dev);
1986     return 0;
1987 }
1988
1989
1990 /************************************************************************/
1991 /*                                                                      */
1992 /*    FUNCTION DESCRIPTION                  zfHpUpdateQosParameter      */
1993 /*      Update TxQs CWMIN, CWMAX, AIFS and TXOP.                        */
1994 /*                                                                      */
1995 /*    INPUTS                                                            */
1996 /*      dev : device pointer                                            */
1997 /*      cwminTbl : CWMIN parameter for TxQs                             */
1998 /*      cwmaxTbl : CWMAX parameter for TxQs                             */
1999 /*      aifsTbl: AIFS parameter for TxQs                                */
2000 /*      txopTbl : TXOP parameter for TxQs                               */
2001 /*                                                                      */
2002 /*    OUTPUTS                                                           */
2003 /*      none                                                            */
2004 /*                                                                      */
2005 /*    AUTHOR                                                            */
2006 /*      Stephen             ZyDAS Technology Corporation    2006.6      */
2007 /*                                                                      */
2008 /************************************************************************/
2009 u8_t zfHpUpdateQosParameter(zdev_t* dev, u16_t* cwminTbl, u16_t* cwmaxTbl,
2010         u16_t* aifsTbl, u16_t* txopTbl)
2011 {
2012     struct zsHpPriv* hpPriv;
2013
2014     zmw_get_wlan_dev(dev);
2015     hpPriv = wd->hpPrivate;
2016
2017     zm_msg0_mm(ZM_LV_0, "zfHalUpdateQosParameter()");
2018
2019     /* Note : Do not change cwmin for Q0 in Ad Hoc mode              */
2020     /*        otherwise driver will fail in Wifi beacon distribution */
2021     if (hpPriv->dot11Mode == ZM_HAL_80211_MODE_STA)
2022     {
2023 #if 0 //Restore CWmin to improve down link throughput
2024         //cheating in BE traffic
2025         if (wd->sta.EnableHT == 1)
2026         {
2027             //cheating in BE traffic
2028             cwminTbl[0] = 7;//15;
2029         }
2030 #endif
2031         cwmaxTbl[0] = 127;//1023;
2032         aifsTbl[0] = 2*9+10;//3 * 9 + 10;
2033     }
2034
2035     /* CWMIN and CWMAX */
2036     zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, cwminTbl[0]
2037             + ((u32_t)cwmaxTbl[0]<<16));
2038     zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_CW, cwminTbl[1]
2039             + ((u32_t)cwmaxTbl[1]<<16));
2040     zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC2_CW, cwminTbl[2]
2041             + ((u32_t)cwmaxTbl[2]<<16));
2042     zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_CW, cwminTbl[3]
2043             + ((u32_t)cwmaxTbl[3]<<16));
2044     zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC4_CW, cwminTbl[4]
2045             + ((u32_t)cwmaxTbl[4]<<16));
2046
2047     /* AIFS */
2048     zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_AIFS, aifsTbl[0]
2049             +((u32_t)aifsTbl[0]<<12)+((u32_t)aifsTbl[0]<<24));
2050     zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_AC2_AIFS, (aifsTbl[0]>>8)
2051             +((u32_t)aifsTbl[0]<<4)+((u32_t)aifsTbl[0]<<16));
2052
2053     /* TXOP */
2054     zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, txopTbl[0]
2055             + ((u32_t)txopTbl[1]<<16));
2056     zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_AC2_TXOP, txopTbl[2]
2057             + ((u32_t)txopTbl[3]<<16));
2058
2059     zfFlushDelayWrite(dev);
2060
2061     hpPriv->txop[0] = txopTbl[0];
2062     hpPriv->txop[1] = txopTbl[1];
2063     hpPriv->txop[2] = txopTbl[2];
2064     hpPriv->txop[3] = txopTbl[3];
2065     hpPriv->cwmin[0] = cwminTbl[0];
2066     hpPriv->cwmax[0] = cwmaxTbl[0];
2067     hpPriv->cwmin[1] = cwminTbl[1];
2068     hpPriv->cwmax[1] = cwmaxTbl[1];
2069
2070     return 0;
2071 }
2072
2073
2074 void zfHpSetAtimWindow(zdev_t* dev, u16_t atimWin)
2075 {
2076     zm_msg1_mm(ZM_LV_0, "Set ATIM window to ", atimWin);
2077     zfDelayWriteInternalReg(dev, ZM_MAC_REG_ATIM_WINDOW, atimWin);
2078     zfFlushDelayWrite(dev);
2079 }
2080
2081
2082 void zfHpSetBasicRateSet(zdev_t* dev, u16_t bRateBasic, u16_t gRateBasic)
2083 {
2084     zfDelayWriteInternalReg(dev, ZM_MAC_REG_BASIC_RATE, bRateBasic
2085                             | ((u16_t)gRateBasic<<8));
2086     zfFlushDelayWrite(dev);
2087 }
2088
2089
2090 /* HT40 send by OFDM 6M    */
2091 /* otherwise use reg 0x638 */
2092 void zfHpSetRTSCTSRate(zdev_t* dev, u32_t rate)
2093 {
2094     zfDelayWriteInternalReg(dev, ZM_MAC_REG_RTS_CTS_RATE, rate);
2095     zfFlushDelayWrite(dev);
2096 }
2097
2098 void zfHpSetMacAddress(zdev_t* dev, u16_t* macAddr, u16_t macAddrId)
2099 {
2100     if (macAddrId == 0)
2101     {
2102         zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_L,
2103                 (((u32_t)macAddr[1])<<16) | macAddr[0]);
2104         zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_H, macAddr[2]);
2105     }
2106     else if (macAddrId <= 7)
2107     {
2108         zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_TABLE+((macAddrId-1)*8),
2109                 macAddr[0] + ((u32_t)macAddr[1]<<16));
2110         zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_TABLE+((macAddrId-1)*8)+4,
2111                 macAddr[2]);
2112     }
2113     zfFlushDelayWrite(dev);
2114 }
2115
2116 void zfHpSetMulticastList(zdev_t* dev, u8_t size, u8_t* pList, u8_t bAllMulticast)
2117 {
2118     struct zsMulticastAddr* pMacList = (struct zsMulticastAddr*) pList;
2119     u8_t   i;
2120     u32_t  value;
2121     u32_t  swRegMulHashValueH, swRegMulHashValueL;
2122
2123     swRegMulHashValueH = 0x80000000;
2124     swRegMulHashValueL = 0;
2125
2126     if ( bAllMulticast )
2127     {
2128         swRegMulHashValueH = swRegMulHashValueL = ~0;
2129     }
2130     else
2131     {
2132         for(i=0; i<size; i++)
2133         {
2134             value = pMacList[i].addr[5] >> 2;
2135
2136             if ( value < 32 )
2137             {
2138                 swRegMulHashValueL |= (1 << value);
2139             }
2140             else
2141             {
2142                 swRegMulHashValueH |= (1 << (value-32));
2143             }
2144         }
2145     }
2146
2147     zfDelayWriteInternalReg(dev, ZM_MAC_REG_GROUP_HASH_TBL_L,
2148                             swRegMulHashValueL);
2149     zfDelayWriteInternalReg(dev, ZM_MAC_REG_GROUP_HASH_TBL_H,
2150                             swRegMulHashValueH);
2151     zfFlushDelayWrite(dev);
2152     return;
2153 }
2154
2155 /******************** Beacon ********************/
2156 void zfHpEnableBeacon(zdev_t* dev, u16_t mode, u16_t bcnInterval, u16_t dtim, u8_t enableAtim)
2157 {
2158     u32_t  value;
2159
2160     zmw_get_wlan_dev(dev);
2161
2162     /* Beacon Ready */
2163     zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_CTRL, 0);
2164     /* Beacon DMA buffer address */
2165     zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_ADDR, ZM_BEACON_BUFFER_ADDRESS);
2166
2167     value = bcnInterval;
2168
2169     value |= (((u32_t) dtim) << 16);
2170
2171     if (mode == ZM_MODE_AP)
2172     {
2173
2174         value |= 0x1000000;
2175     }
2176     else if (mode == ZM_MODE_IBSS)
2177     {
2178         value |= 0x2000000;
2179
2180                 if ( enableAtim )
2181                 {
2182                         value |= 0x4000000;
2183                 }
2184                 ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnEnabled = 1;
2185         ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnInterval = value;
2186     }
2187     zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, (bcnInterval-6)<<16);
2188
2189     /* Beacon period and beacon enable */
2190     zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, value);
2191     zfFlushDelayWrite(dev);
2192 }
2193
2194 void zfHpDisableBeacon(zdev_t* dev)
2195 {
2196     zmw_get_wlan_dev(dev);
2197
2198     ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnEnabled = 0;
2199
2200     zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, 0);
2201     zfFlushDelayWrite(dev);
2202 }
2203
2204 void zfHpLedCtrl(zdev_t* dev, u16_t ledId, u8_t mode)
2205 {
2206     u16_t state;
2207     zmw_get_wlan_dev(dev);
2208
2209     //zm_debug_msg1("LED ID=", ledId);
2210     //zm_debug_msg1("LED mode=", mode);
2211     if (ledId < 2)
2212     {
2213         if (((struct zsHpPriv*)wd->hpPrivate)->ledMode[ledId] != mode)
2214         {
2215             ((struct zsHpPriv*)wd->hpPrivate)->ledMode[ledId] = mode;
2216
2217             state = ((struct zsHpPriv*)wd->hpPrivate)->ledMode[0]
2218                     | (((struct zsHpPriv*)wd->hpPrivate)->ledMode[1]<<1);
2219             zfDelayWriteInternalReg(dev, 0x1d0104, state);
2220             zfFlushDelayWrite(dev);
2221             //zm_debug_msg0("Update LED");
2222         }
2223     }
2224 }
2225
2226 /************************************************************************/
2227 /*                                                                      */
2228 /*    FUNCTION DESCRIPTION                  zfHpResetTxRx               */
2229 /*      Reset Tx and Rx Desc.                                           */
2230 /*                                                                      */
2231 /*    INPUTS                                                            */
2232 /*      dev : device pointer                                            */
2233 /*                                                                      */
2234 /*    OUTPUTS                                                           */
2235 /*      0 : success                                                     */
2236 /*      other : fail                                                    */
2237 /*                                                                      */
2238 /*    AUTHOR                                                            */
2239 /*      Chao-Wen Yang         ZyDAS Technology Corporation    2007.3    */
2240 /*                                                                      */
2241 /************************************************************************/
2242 u16_t zfHpUsbReset(zdev_t* dev)
2243 {
2244     u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
2245     u16_t ret = 0;
2246
2247     //zm_debug_msg0("CWY - Reset Tx and Rx");
2248
2249     cmd[0] =  0 | (ZM_CMD_RESET << 8);
2250
2251     ret = zfIssueCmd(dev, cmd, 4, ZM_OID_INTERNAL_WRITE, NULL);
2252     return ret;
2253 }
2254
2255 u16_t zfHpDKReset(zdev_t* dev, u8_t flag)
2256 {
2257     u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
2258     u16_t ret = 0;
2259
2260     //zm_debug_msg0("CWY - Reset Tx and Rx");
2261
2262     cmd[0] =  4 | (ZM_CMD_DKRESET << 8);
2263     cmd[1] = flag;
2264
2265     ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
2266     return ret;
2267 }
2268
2269 u32_t zfHpCwmUpdate(zdev_t* dev)
2270 {
2271     //u32_t cmd[3];
2272     //u16_t ret;
2273     //
2274     //cmd[0] = 0x00000008;
2275     //cmd[1] = 0x1c36e8;
2276     //cmd[2] = 0x1c36ec;
2277     //
2278     //ret = zfIssueCmd(dev, cmd, 12, ZM_CWM_READ, 0);
2279     //return ret;
2280
2281     struct zsHpPriv* hpPriv;
2282
2283     zmw_get_wlan_dev(dev);
2284     hpPriv=wd->hpPrivate;
2285
2286     zfCoreCwmBusy(dev, zfCwmIsExtChanBusy(hpPriv->ctlBusy, hpPriv->extBusy));
2287
2288     hpPriv->ctlBusy = 0;
2289     hpPriv->extBusy = 0;
2290
2291     return 0;
2292 }
2293
2294 u32_t zfHpAniUpdate(zdev_t* dev)
2295 {
2296     u32_t cmd[5];
2297     u16_t ret;
2298
2299     cmd[0] = 0x00000010;
2300     cmd[1] = 0x1c36e8;
2301     cmd[2] = 0x1c36ec;
2302     cmd[3] = 0x1c3cb4;
2303     cmd[4] = 0x1c3cb8;
2304
2305     ret = zfIssueCmd(dev, cmd, 20, ZM_ANI_READ, 0);
2306     return ret;
2307 }
2308
2309 /*
2310  * Update Beacon RSSI in ANI
2311  */
2312 u32_t zfHpAniUpdateRssi(zdev_t* dev, u8_t rssi)
2313 {
2314     struct zsHpPriv* hpPriv;
2315
2316     zmw_get_wlan_dev(dev);
2317     hpPriv=wd->hpPrivate;
2318
2319     hpPriv->stats.ast_nodestats.ns_avgbrssi = rssi;
2320
2321     return 0;
2322 }
2323
2324 #define ZM_SEEPROM_MAC_ADDRESS_OFFSET   (0x1400 + (0x106<<1))
2325 #define ZM_SEEPROM_REGDOMAIN_OFFSET   (0x1400 + (0x104<<1))
2326 #define ZM_SEEPROM_VERISON_OFFSET   (0x1400 + (0x102<<1))
2327 #define ZM_SEEPROM_HARDWARE_TYPE_OFFSET   (0x1374)
2328 #define ZM_SEEPROM_HW_HEAVY_CLIP          (0x161c)
2329
2330 u32_t zfHpGetMacAddress(zdev_t* dev)
2331 {
2332     u32_t cmd[7];
2333     u16_t ret;
2334
2335     cmd[0] = 0x00000000 | 24;
2336     cmd[1] = ZM_SEEPROM_MAC_ADDRESS_OFFSET;
2337     cmd[2] = ZM_SEEPROM_MAC_ADDRESS_OFFSET+4;
2338     cmd[3] = ZM_SEEPROM_REGDOMAIN_OFFSET;
2339     cmd[4] = ZM_SEEPROM_VERISON_OFFSET;
2340     cmd[5] = ZM_SEEPROM_HARDWARE_TYPE_OFFSET;
2341     cmd[6] = ZM_SEEPROM_HW_HEAVY_CLIP;
2342
2343     ret = zfIssueCmd(dev, cmd, 28, ZM_MAC_READ, 0);
2344     return ret;
2345 }
2346
2347 u32_t zfHpGetTransmitPower(zdev_t* dev)
2348 {
2349     struct zsHpPriv*    hpPriv;
2350     u16_t               tpc     = 0;
2351
2352     zmw_get_wlan_dev(dev);
2353     hpPriv  = wd->hpPrivate;
2354
2355     if (hpPriv->hwFrequency < 3000) {
2356         tpc = hpPriv->tPow2x2g[0] & 0x3f;
2357         wd->maxTxPower2 &= 0x3f;
2358         tpc = (tpc > wd->maxTxPower2)? wd->maxTxPower2 : tpc;
2359     } else {
2360         tpc = hpPriv->tPow2x5g[0] & 0x3f;
2361         wd->maxTxPower5 &= 0x3f;
2362         tpc = (tpc > wd->maxTxPower5)? wd->maxTxPower5 : tpc;
2363     }
2364
2365     return tpc;
2366 }
2367
2368 u8_t zfHpGetMinTxPower(zdev_t* dev)
2369 {
2370     struct zsHpPriv*    hpPriv;
2371     u8_t               tpc     = 0;
2372
2373     zmw_get_wlan_dev(dev);
2374     hpPriv  = wd->hpPrivate;
2375
2376     if (hpPriv->hwFrequency < 3000)
2377     {
2378         if(wd->BandWidth40)
2379         {
2380             //40M
2381             tpc = (hpPriv->tPow2x2gHt40[7]&0x3f);
2382         }
2383         else
2384         {
2385             //20M
2386             tpc = (hpPriv->tPow2x2gHt20[7]&0x3f);
2387         }
2388     }
2389     else
2390     {
2391         if(wd->BandWidth40)
2392         {
2393             //40M
2394             tpc = (hpPriv->tPow2x5gHt40[7]&0x3f);
2395         }
2396         else
2397         {
2398             //20M
2399             tpc = (hpPriv->tPow2x5gHt20[7]&0x3f);
2400         }
2401     }
2402
2403     return tpc;
2404 }
2405
2406 u8_t zfHpGetMaxTxPower(zdev_t* dev)
2407 {
2408     struct zsHpPriv*    hpPriv;
2409     u8_t               tpc     = 0;
2410
2411     zmw_get_wlan_dev(dev);
2412     hpPriv  = wd->hpPrivate;
2413
2414     if (hpPriv->hwFrequency < 3000)
2415     {
2416         tpc = (hpPriv->tPow2xCck[0]&0x3f);
2417     }
2418     else
2419     {
2420         tpc =(hpPriv->tPow2x5g[0]&0x3f);
2421     }
2422
2423     return tpc;
2424 }
2425
2426 u32_t zfHpLoadEEPROMFromFW(zdev_t* dev)
2427 {
2428     u32_t cmd[16];
2429     u32_t ret=0, i, j;
2430     zmw_get_wlan_dev(dev);
2431
2432     i = ((struct zsHpPriv*)wd->hpPrivate)->eepromImageRdReq;
2433
2434     cmd[0] = ZM_HAL_MAX_EEPROM_PRQ*4;
2435
2436     for (j=0; j<ZM_HAL_MAX_EEPROM_PRQ; j++)
2437     {
2438         cmd[j+1] = 0x1000 + (((i*ZM_HAL_MAX_EEPROM_PRQ) + j)*4);
2439     }
2440
2441     ret = zfIssueCmd(dev, cmd, (ZM_HAL_MAX_EEPROM_PRQ+1)*4, ZM_EEPROM_READ, 0);
2442
2443     return ret;
2444 }
2445
2446 void zfHpHeartBeat(zdev_t* dev)
2447 {
2448     struct zsHpPriv* hpPriv;
2449     u8_t polluted = 0;
2450     u8_t ackTpc;
2451
2452     zmw_get_wlan_dev(dev);
2453     hpPriv=wd->hpPrivate;
2454
2455     /* Workaround : Make OTUS fire more beacon in ad hoc mode in 2.4GHz */
2456     if (hpPriv->ibssBcnEnabled != 0)
2457     {
2458         if (hpPriv->hwFrequency <= ZM_CH_G_14)
2459         {
2460             if ((wd->tick % 10) == 0)
2461             {
2462                 if ((wd->tick % 40) == 0)
2463                 {
2464                     zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, hpPriv->ibssBcnInterval-1);
2465                     polluted = 1;
2466                 }
2467                 else
2468                 {
2469                     zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, hpPriv->ibssBcnInterval);
2470                     polluted = 1;
2471                 }
2472             }
2473         }
2474     }
2475
2476     if ((wd->tick & 0x3f) == 0x25)
2477     {
2478         /* Workaround for beacon stuck after SW reset */
2479         if (hpPriv->ibssBcnEnabled != 0)
2480         {
2481             zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_ADDR, ZM_BEACON_BUFFER_ADDRESS);
2482             polluted = 1;
2483         }
2484
2485         //DbgPrint("hpPriv->aggMaxDurationBE=%d", hpPriv->aggMaxDurationBE);
2486         //DbgPrint("wd->sta.avgSizeOfReceivePackets=%d", wd->sta.avgSizeOfReceivePackets);
2487         if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2488             && (zfStaIsConnected(dev))
2489             && (wd->sta.EnableHT == 1) //11n mode
2490             && (wd->BandWidth40 == 1) //40MHz mode
2491             && (wd->sta.enableDrvBA ==0) //Marvel AP
2492             && (hpPriv->aggMaxDurationBE > 2000) //BE TXOP > 2ms
2493             && (wd->sta.avgSizeOfReceivePackets > 1420))
2494         {
2495             zfDelayWriteInternalReg(dev, 0x1c3b9c, 0x8000a);
2496             polluted = 1;
2497         }
2498         else
2499         {
2500             zfDelayWriteInternalReg(dev, 0x1c3b9c, hpPriv->aggPktNum);
2501             polluted = 1;
2502         }
2503
2504         if (wd->dynamicSIFSEnable == 0)
2505         {
2506             if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2507                 && (zfStaIsConnected(dev))
2508                 && (wd->sta.EnableHT == 1) //11n mode
2509                 && (wd->BandWidth40 == 0) //20MHz mode
2510                 && (wd->sta.enableDrvBA ==0)) //Marvel AP
2511             {
2512                 zfDelayWriteInternalReg(dev, 0x1c3698, 0x5144000);
2513                 polluted = 1;
2514             }
2515             else
2516             {
2517                 zfDelayWriteInternalReg(dev, 0x1c3698, 0xA144000);
2518                 polluted = 1;
2519             }
2520         }
2521         else
2522         {
2523             if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2524                 && (zfStaIsConnected(dev))
2525                 && (wd->sta.EnableHT == 1) //11n mode
2526                 && (wd->sta.athOwlAp == 1)) //Atheros AP
2527             {
2528                 if (hpPriv->retransmissionEvent)
2529                 {
2530                     switch(hpPriv->latestSIFS)
2531                     {
2532                     case 0:
2533                         hpPriv->latestSIFS = 1;
2534                         zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0x8144000);
2535                         break;
2536                     case 1:
2537                         hpPriv->latestSIFS = 2;
2538                         zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2539                         break;
2540                     case 2:
2541                         hpPriv->latestSIFS = 3;
2542                         zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xc144000);
2543                         break;
2544                     case 3:
2545                         hpPriv->latestSIFS = 0;
2546                         zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2547                         break;
2548                     default:
2549                         hpPriv->latestSIFS = 0;
2550                         zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2551                         break;
2552                     }
2553                     polluted = 1;
2554                     zm_debug_msg1("##### Correct Tx retransmission issue #####, ", hpPriv->latestSIFS);
2555                     hpPriv->retransmissionEvent = 0;
2556                 }
2557             }
2558             else
2559             {
2560                 hpPriv->latestSIFS = 0;
2561                 hpPriv->retransmissionEvent = 0;
2562                 zfDelayWriteInternalReg(dev, 0x1c3698, 0xA144000);
2563                 polluted = 1;
2564             }
2565         }
2566
2567         if ((wd->sta.bScheduleScan == FALSE) && (wd->sta.bChannelScan == FALSE))
2568         {
2569 #define ZM_SIGNAL_THRESHOLD  66
2570         if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2571             && (zfStaIsConnected(dev))
2572             && (wd->SignalStrength > ZM_SIGNAL_THRESHOLD))
2573         {
2574                 /* remove state handle, always rewrite register setting */
2575                 //if (hpPriv->strongRSSI == 0)
2576             {
2577                 hpPriv->strongRSSI = 1;
2578                 /* Strong RSSI, set ACK to one Tx stream and lower Tx power 7dbm */
2579                 if (hpPriv->currentAckRtsTpc > (14+10))
2580                 {
2581                     ackTpc = hpPriv->currentAckRtsTpc - 14;
2582                 }
2583                 else
2584                 {
2585                     ackTpc = 10;
2586                 }
2587                 zfDelayWriteInternalReg(dev, 0x1c3694, ((ackTpc) << 20) | (0x1<<26));
2588                 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((ackTpc) << 5 ) | (0x1<<11) |
2589                                                        ((ackTpc) << 21) | (0x1<<27)  );
2590                 polluted = 1;
2591             }
2592         }
2593         else
2594         {
2595                 /* remove state handle, always rewrite register setting */
2596                 //if (hpPriv->strongRSSI == 1)
2597             {
2598                 hpPriv->strongRSSI = 0;
2599                 if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
2600                 {
2601                     zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x1<<26));
2602                     zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x1<<11) |
2603                                                        ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x1<<27)  );
2604                 }
2605                 else
2606                 {
2607                     zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x5<<26));
2608                     zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x5<<11) |
2609                                                        ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x5<<27)  );
2610                 }
2611                 polluted = 1;
2612             }
2613         }
2614 #undef ZM_SIGNAL_THRESHOLD
2615         }
2616
2617         if ((hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM) == 0)
2618         {
2619             if ((wd->sta.bScheduleScan == FALSE) && (wd->sta.bChannelScan == FALSE))
2620             {
2621     #define ZM_RX_SIGNAL_THRESHOLD_H  71
2622     #define ZM_RX_SIGNAL_THRESHOLD_L  66
2623                 u8_t rxSignalThresholdH = ZM_RX_SIGNAL_THRESHOLD_H;
2624                 u8_t rxSignalThresholdL = ZM_RX_SIGNAL_THRESHOLD_L;
2625     #undef ZM_RX_SIGNAL_THRESHOLD_H
2626     #undef ZM_RX_SIGNAL_THRESHOLD_L
2627
2628                 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2629                     && (zfStaIsConnected(dev))
2630                     && (wd->SignalStrength > rxSignalThresholdH)
2631                     )//&& (hpPriv->rxStrongRSSI == 0))
2632                 {
2633                     hpPriv->rxStrongRSSI = 1;
2634                     //zfDelayWriteInternalReg(dev, 0x1c5964, 0x1220);
2635                     //zfDelayWriteInternalReg(dev, 0x1c5960, 0x900);
2636                     //zfDelayWriteInternalReg(dev, 0x1c6960, 0x900);
2637                     //zfDelayWriteInternalReg(dev, 0x1c7960, 0x900);
2638                     if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
2639                     {
2640                         if (hpPriv->hwFrequency <= ZM_CH_G_14)
2641                         {
2642                             zfDelayWriteInternalReg(dev, 0x1c8960, 0x900);
2643                         }
2644                         else
2645                         {
2646                             zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49);
2647                         }
2648                     }
2649                     else
2650                     {
2651                         zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900);
2652                     }
2653                     polluted = 1;
2654                 }
2655                 else if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2656                     && (zfStaIsConnected(dev))
2657                     && (wd->SignalStrength > rxSignalThresholdL)
2658                     )//&& (hpPriv->rxStrongRSSI == 1))
2659                 {
2660                     //Do nothing to prevent frequently Rx switching
2661                 }
2662                 else
2663                 {
2664                     /* remove state handle, always rewrite register setting */
2665                     //if (hpPriv->rxStrongRSSI == 1)
2666                     {
2667                         hpPriv->rxStrongRSSI = 0;
2668                         //zfDelayWriteInternalReg(dev, 0x1c5964, 0x1120);
2669                         //zfDelayWriteInternalReg(dev, 0x1c5960, 0x9b40);
2670                         //zfDelayWriteInternalReg(dev, 0x1c6960, 0x9b40);
2671                         //zfDelayWriteInternalReg(dev, 0x1c7960, 0x9b40);
2672                         if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
2673                         {
2674                             if (hpPriv->hwFrequency <= ZM_CH_G_14)
2675                             {
2676                                 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49);
2677                             }
2678                             else
2679                             {
2680                                 zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900);
2681                             }
2682                         }
2683                         else
2684                         {
2685                             zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b40);
2686                         }
2687                         polluted = 1;
2688                     }
2689                 }
2690
2691             }
2692         }
2693
2694         if (hpPriv->usbAcSendBytes[3] > (hpPriv->usbAcSendBytes[0]*2))
2695         {
2696             zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[3]);
2697             polluted = 1;
2698         }
2699         else if (hpPriv->usbAcSendBytes[2] > (hpPriv->usbAcSendBytes[0]*2))
2700         {
2701             zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[2]);
2702             polluted = 1;
2703         }
2704         else if (hpPriv->usbAcSendBytes[1] > (hpPriv->usbAcSendBytes[0]*2))
2705         {
2706             zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[1]+((u32_t)hpPriv->cwmax[1]<<16));
2707             polluted = 1;
2708         }
2709         else
2710         {
2711             if (hpPriv->slotType == 1)
2712             {
2713                 if ((wd->sta.enableDrvBA ==0) //Marvel AP
2714                    && (hpPriv->aggMaxDurationBE > 2000)) //BE TXOP > 2ms
2715                 {
2716                     zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, (hpPriv->cwmin[0]/2)+((u32_t)hpPriv->cwmax[0]<<16));
2717                 }
2718                 else
2719                 {
2720                     zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[0]+((u32_t)hpPriv->cwmax[0]<<16));
2721                 }
2722                 polluted = 1;
2723             }
2724             else
2725             {
2726                 /* Compensation for 20us slot time */
2727                 //zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, 58+((u32_t)hpPriv->cwmax[0]<<16));
2728                 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[0]+((u32_t)hpPriv->cwmax[0]<<16));
2729                 polluted = 1;
2730             }
2731
2732             if ((wd->sta.SWEncryptEnable & (ZM_SW_TKIP_ENCRY_EN|ZM_SW_WEP_ENCRY_EN)) == 0)
2733             {
2734                 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[0]);
2735                 polluted = 1;
2736             }
2737             else
2738             {
2739                 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, 0x30);
2740                 polluted = 1;
2741             }
2742
2743         }
2744         hpPriv->usbAcSendBytes[3] = 0;
2745         hpPriv->usbAcSendBytes[2] = 0;
2746         hpPriv->usbAcSendBytes[1] = 0;
2747         hpPriv->usbAcSendBytes[0] = 0;
2748     }
2749
2750     if (polluted == 1)
2751     {
2752         zfFlushDelayWrite(dev);
2753     }
2754
2755     return;
2756 }
2757
2758 /*
2759  *  0x1d4008 : AHB, DAC, ADC clock selection
2760  *             bit1~0  AHB_CLK : AHB clock selection,
2761  *                               00 : OSC 40MHz;
2762  *                               01 : 20MHz in A mode, 22MHz in G mode;
2763  *                               10 : 40MHz in A mode, 44MHz in G mode;
2764  *                               11 : 80MHz in A mode, 88MHz in G mode.
2765  *             bit3~2  CLK_SEL : Select the clock source of clk160 in ADDAC.
2766  *                               00 : PLL divider's output;
2767  *                               01 : PLL divider's output divided by 2;
2768  *                               10 : PLL divider's output divided by 4;
2769  *                               11 : REFCLK from XTALOSCPAD.
2770  */
2771 void zfSelAdcClk(zdev_t* dev, u8_t bw40, u32_t frequency)
2772 {
2773     if(bw40 == 1)
2774     {
2775         //zfDelayWriteInternalReg(dev, 0x1D4008, 0x73);
2776         zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x10A);
2777         zfFlushDelayWrite(dev);
2778     }
2779     else
2780     {
2781         //zfDelayWriteInternalReg(dev, 0x1D4008, 0x70);
2782         if ( frequency <= ZM_CH_G_14 )
2783         {
2784             zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x105);
2785         }
2786         else
2787         {
2788             zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x104);
2789         }
2790         zfFlushDelayWrite(dev);
2791     }
2792 }
2793
2794 u32_t zfHpEchoCommand(zdev_t* dev, u32_t value)
2795 {
2796     u32_t cmd[2];
2797     u16_t ret;
2798
2799     cmd[0] = 0x00008004;
2800     cmd[1] = value;
2801
2802     ret = zfIssueCmd(dev, cmd, 8, ZM_CMD_ECHO, NULL);
2803     return ret;
2804 }
2805
2806 #ifdef ZM_DRV_INIT_USB_MODE
2807
2808 #define ZM_USB_US_STREAM_MODE               0x00000000
2809 #define ZM_USB_US_PACKET_MODE               0x00000008
2810 #define ZM_USB_DS_ENABLE                    0x00000001
2811 #define ZM_USB_US_ENABLE                    0x00000002
2812
2813 #define ZM_USB_RX_STREAM_4K                 0x00000000
2814 #define ZM_USB_RX_STREAM_8K                 0x00000010
2815 #define ZM_USB_RX_STREAM_16K                0x00000020
2816 #define ZM_USB_RX_STREAM_32K                0x00000030
2817
2818 #define ZM_USB_TX_STREAM_MODE               0x00000040
2819
2820 #define ZM_USB_MODE_CTRL_REG                0x001E1108
2821
2822 void zfInitUsbMode(zdev_t* dev)
2823 {
2824     u32_t mode;
2825     zmw_get_wlan_dev(dev);
2826
2827     /* TODO: Set USB mode by reading registery */
2828     mode = ZM_USB_DS_ENABLE | ZM_USB_US_ENABLE | ZM_USB_US_PACKET_MODE;
2829
2830     zfDelayWriteInternalReg(dev, ZM_USB_MODE_CTRL_REG, mode);
2831     zfFlushDelayWrite(dev);
2832 }
2833 #endif
2834
2835 void zfDumpEepBandEdges(struct ar5416Eeprom* eepromImage);
2836 void zfPrintTargetPower2G(u8_t* tPow2xCck, u8_t* tPow2x2g, u8_t* tPow2x2gHt20, u8_t* tPow2x2gHt40);
2837 void zfPrintTargetPower5G(u8_t* tPow2x5g, u8_t* tPow2x5gHt20, u8_t* tPow2x5gHt40);
2838
2839
2840 s32_t zfInterpolateFunc(s32_t x, s32_t x1, s32_t y1, s32_t x2, s32_t y2)
2841 {
2842     s32_t y;
2843
2844     if (y2 == y1)
2845     {
2846         y = y1;
2847     }
2848     else if (x == x1)
2849     {
2850         y = y1;
2851     }
2852     else if (x == x2)
2853     {
2854         y = y2;
2855     }
2856     else if (x2 != x1)
2857     {
2858         y = y1 + (((y2-y1) * (x-x1))/(x2-x1));
2859     }
2860     else
2861     {
2862         y = y1;
2863     }
2864
2865     return y;
2866 }
2867
2868 //#define ZM_ENABLE_TPC_WINDOWS_DEBUG
2869 //#define ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
2870
2871 /* the tx power offset workaround for ART vs NDIS/MDK */
2872 #define HALTX_POWER_OFFSET      0
2873
2874 u8_t zfInterpolateFuncX(u8_t x, u8_t x1, u8_t y1, u8_t x2, u8_t y2)
2875 {
2876     s32_t y;
2877     s32_t inc;
2878
2879     #define ZM_MULTIPLIER   8
2880     y = zfInterpolateFunc((s32_t)x<<ZM_MULTIPLIER,
2881                           (s32_t)x1<<ZM_MULTIPLIER,
2882                           (s32_t)y1<<ZM_MULTIPLIER,
2883                           (s32_t)x2<<ZM_MULTIPLIER,
2884                           (s32_t)y2<<ZM_MULTIPLIER);
2885
2886     inc = (y & (1<<(ZM_MULTIPLIER-1))) >> (ZM_MULTIPLIER-1);
2887     y = (y >> ZM_MULTIPLIER) + inc;
2888     #undef ZM_MULTIPLIER
2889
2890     return (u8_t)y;
2891 }
2892
2893 u8_t zfGetInterpolatedValue(u8_t x, u8_t* x_array, u8_t* y_array)
2894 {
2895     s32_t y;
2896     u16_t xIndex;
2897
2898     if (x <= x_array[1])
2899     {
2900         xIndex = 0;
2901     }
2902     else if (x <= x_array[2])
2903     {
2904         xIndex = 1;
2905     }
2906     else if (x <= x_array[3])
2907     {
2908         xIndex = 2;
2909     }
2910     else //(x > x_array[3])
2911     {
2912         xIndex = 3;
2913     }
2914
2915     y = zfInterpolateFuncX(x,
2916             x_array[xIndex],
2917             y_array[xIndex],
2918             x_array[xIndex+1],
2919             y_array[xIndex+1]);
2920
2921     return (u8_t)y;
2922 }
2923
2924 u8_t zfFindFreqIndex(u8_t f, u8_t* fArray, u8_t fArraySize)
2925 {
2926     u8_t i;
2927 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
2928     DbgPrint("f=%d ", f);
2929     for (i=0; i<fArraySize; i++)
2930     {
2931         DbgPrint("%d ", fArray[i]);
2932     }
2933     DbgPrint("\n");
2934 #endif
2935     i=fArraySize-2;
2936     while(1)
2937     {
2938         if (f >= fArray[i])
2939         {
2940             return i;
2941         }
2942         if (i!=0)
2943         {
2944             i--;
2945         }
2946         else
2947         {
2948             return 0;
2949         }
2950     }
2951 }
2952
2953
2954
2955
2956 void zfInitPowerCal(zdev_t* dev)
2957 {
2958     //Program PHY Tx power relatives registers
2959 #define zm_write_phy_reg(cr, val) reg_write((cr*4)+0x9800, val)
2960
2961     zm_write_phy_reg(79, 0x7f);
2962     zm_write_phy_reg(77, 0x3f3f3f3f);
2963     zm_write_phy_reg(78, 0x3f3f3f3f);
2964     zm_write_phy_reg(653, 0x3f3f3f3f);
2965     zm_write_phy_reg(654, 0x3f3f3f3f);
2966     zm_write_phy_reg(739, 0x3f3f3f3f);
2967     zm_write_phy_reg(740, 0x3f3f3f3f);
2968     zm_write_phy_reg(755, 0x3f3f3f3f);
2969     zm_write_phy_reg(756, 0x3f3f3f3f);
2970     zm_write_phy_reg(757, 0x3f3f3f3f);
2971
2972 #undef zm_write_phy_reg
2973 }
2974
2975
2976
2977 void zfPrintTp(u8_t* pwr0, u8_t* vpd0, u8_t* pwr1, u8_t* vpd1)
2978 {
2979     #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
2980     DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]);
2981     DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]);
2982     DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]);
2983     DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]);
2984     #endif
2985 }
2986
2987
2988 /*
2989  * To find CTL index(0~23)
2990  * return 24(AR5416_NUM_CTLS)=>no desired index found
2991  */
2992 u8_t zfFindCtlEdgesIndex(zdev_t* dev, u8_t desired_CtlIndex)
2993 {
2994     u8_t i;
2995     struct zsHpPriv* hpPriv;
2996     struct ar5416Eeprom* eepromImage;
2997
2998     zmw_get_wlan_dev(dev);
2999
3000     hpPriv = wd->hpPrivate;
3001
3002     eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]);
3003
3004     //for (i = 0; (i < AR5416_NUM_CTLS) && eepromImage->ctlIndex[i]; i++)
3005     for (i = 0; i < AR5416_NUM_CTLS; i++)
3006     {
3007         if(desired_CtlIndex == eepromImage->ctlIndex[i])
3008             break;
3009     }
3010     return i;
3011 }
3012
3013 /**************************************************************************
3014  * fbin2freq
3015  *
3016  * Get channel value from binary representation held in eeprom
3017  * RETURNS: the frequency in MHz
3018  */
3019 u32_t
3020 fbin2freq(u8_t fbin, u8_t is2GHz)
3021 {
3022     /*
3023      * Reserved value 0xFF provides an empty definition both as
3024      * an fbin and as a frequency - do not convert
3025      */
3026     if (fbin == AR5416_BCHAN_UNUSED) {
3027         return fbin;
3028     }
3029
3030     return (u32_t)((is2GHz==1) ? (2300 + fbin) : (4800 + 5 * fbin));
3031 }
3032
3033
3034 u8_t zfGetMaxEdgePower(zdev_t* dev, CAL_CTL_EDGES *pCtlEdges, u32_t freq)
3035 {
3036     u8_t i;
3037     u8_t maxEdgePower;
3038     u8_t is2GHz;
3039     struct zsHpPriv* hpPriv;
3040     struct ar5416Eeprom* eepromImage;
3041
3042     zmw_get_wlan_dev(dev);
3043
3044     hpPriv = wd->hpPrivate;
3045
3046     eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]);
3047
3048     if(freq > ZM_CH_G_14)
3049         is2GHz = 0;
3050     else
3051         is2GHz = 1;
3052
3053     maxEdgePower = AR5416_MAX_RATE_POWER;
3054
3055     /* Get the edge power */
3056     for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pCtlEdges[i].bChannel != AR5416_BCHAN_UNUSED) ; i++)
3057     {
3058         /*
3059          * If there's an exact channel match or an inband flag set
3060          * on the lower channel use the given rdEdgePower
3061          */
3062         if (freq == fbin2freq(pCtlEdges[i].bChannel, is2GHz))
3063         {
3064             maxEdgePower = pCtlEdges[i].tPower;
3065             #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3066             zm_dbg(("zfGetMaxEdgePower index i = %d \n", i));
3067             #endif
3068             break;
3069         }
3070         else if ((i > 0) && (freq < fbin2freq(pCtlEdges[i].bChannel, is2GHz)))
3071         {
3072             if (fbin2freq(pCtlEdges[i - 1].bChannel, is2GHz) < freq && pCtlEdges[i - 1].flag)
3073             {
3074                 maxEdgePower = pCtlEdges[i - 1].tPower;
3075                 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3076                 zm_dbg(("zfGetMaxEdgePower index i-1 = %d \n", i-1));
3077                 #endif
3078             }
3079             /* Leave loop - no more affecting edges possible in this monotonic increasing list */
3080             break;
3081         }
3082
3083     }
3084
3085     if( i == AR5416_NUM_BAND_EDGES )
3086     {
3087         if (freq > fbin2freq(pCtlEdges[i - 1].bChannel, is2GHz) && pCtlEdges[i - 1].flag)
3088         {
3089             maxEdgePower = pCtlEdges[i - 1].tPower;
3090             #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3091             zm_dbg(("zfGetMaxEdgePower index=>i-1 = %d \n", i-1));
3092             #endif
3093         }
3094     }
3095
3096     zm_assert(maxEdgePower > 0);
3097
3098   #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3099     if ( maxEdgePower == AR5416_MAX_RATE_POWER )
3100     {
3101         zm_dbg(("zfGetMaxEdgePower = %d !!!\n", AR5416_MAX_RATE_POWER));
3102     }
3103   #endif
3104     return maxEdgePower;
3105 }
3106
3107 u32_t zfAdjustHT40FreqOffset(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset)
3108 {
3109     u32_t newFreq = frequency;
3110
3111         if (bw40 == 1)
3112         {
3113         if (extOffset == 1)
3114         {
3115             newFreq += 10;
3116         }
3117         else
3118         {
3119             newFreq -= 10;
3120         }
3121         }
3122         return newFreq;
3123 }
3124
3125 u32_t zfHpCheckDoHeavyClip(zdev_t* dev, u32_t freq, CAL_CTL_EDGES *pCtlEdges, u8_t bw40)
3126 {
3127     u32_t ret = 0;
3128     u8_t i;
3129     u8_t is2GHz;
3130     struct zsHpPriv* hpPriv;
3131
3132     zmw_get_wlan_dev(dev);
3133
3134     hpPriv = wd->hpPrivate;
3135
3136     if(freq > ZM_CH_G_14)
3137         is2GHz = 0;
3138     else
3139         is2GHz = 1;
3140
3141     /* HT40 force enable heavy clip */
3142     if (bw40)
3143     {
3144         ret |= 0xf0;
3145     }
3146 #if 1
3147     /* HT20 : frequency bandedge */
3148     for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pCtlEdges[i].bChannel != AR5416_BCHAN_UNUSED) ; i++)
3149     {
3150         if (freq == fbin2freq(pCtlEdges[i].bChannel, is2GHz))
3151         {
3152             if (pCtlEdges[i].flag == 0)
3153             {
3154                 ret |= 0xf;
3155             }
3156             break;
3157         }
3158     }
3159 #endif
3160
3161     return ret;
3162 }
3163
3164
3165 void zfSetPowerCalTable(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset)
3166 {
3167     struct ar5416Eeprom* eepromImage;
3168     u8_t pwr0[5];
3169     u8_t pwr1[5];
3170     u8_t vpd0[5];
3171     u8_t vpd1[5];
3172     u8_t vpd_chain1[128];
3173     u8_t vpd_chain3[128];
3174     u16_t boundary1 = 18; //CR 667
3175     u16_t powerTxMax = 63; //CR 79
3176     u8_t i;
3177     struct zsHpPriv* hpPriv;
3178     u8_t fbin;
3179     u8_t index, max2gIndex, max5gIndex;
3180     u8_t chain0pwrPdg0[5];
3181     u8_t chain0vpdPdg0[5];
3182     u8_t chain0pwrPdg1[5];
3183     u8_t chain0vpdPdg1[5];
3184     u8_t chain2pwrPdg0[5];
3185     u8_t chain2vpdPdg0[5];
3186     u8_t chain2pwrPdg1[5];
3187     u8_t chain2vpdPdg1[5];
3188     u8_t fbinArray[8];
3189
3190     /* 4 CTL */
3191     u8_t ctl_i;
3192     u8_t desired_CtlIndex;
3193
3194     u8_t ctlEdgesMaxPowerCCK = AR5416_MAX_RATE_POWER;
3195     u8_t ctlEdgesMaxPower2G = AR5416_MAX_RATE_POWER;
3196     u8_t ctlEdgesMaxPower2GHT20 = AR5416_MAX_RATE_POWER;
3197     u8_t ctlEdgesMaxPower2GHT40 = AR5416_MAX_RATE_POWER;
3198     u8_t ctlEdgesMaxPower5G = AR5416_MAX_RATE_POWER;
3199     u8_t ctlEdgesMaxPower5GHT20 = AR5416_MAX_RATE_POWER;
3200     u8_t ctlEdgesMaxPower5GHT40 = AR5416_MAX_RATE_POWER;
3201
3202     u8_t ctlOffset;
3203
3204     zmw_get_wlan_dev(dev);
3205
3206     hpPriv = wd->hpPrivate;
3207
3208     eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]);
3209
3210     // Check the total bytes of the EEPROM structure to see the dongle have been calibrated or not.
3211     if (eepromImage->baseEepHeader.length == 0xffff)
3212     {
3213         #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3214         zm_dbg(("Warning! This dongle not been calibrated\n"));
3215         #endif
3216         return;
3217     }
3218
3219     #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3220     DbgPrint("-----zfSetPowerCalTable : frequency=%d-----\n", frequency);
3221     #endif
3222     /* TODO : 1. boundary1 and powerTxMax should be refered to CR667 and CR79 */
3223     /*           in otus.ini file                                          */
3224
3225     #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3226     /* 2. Interpolate pwr and vpd test points from frequency */
3227     DbgPrint("calFreqPier5G : %d, %d, %d, %d ,%d, %d, %d, %d\n",
3228                                             eepromImage->calFreqPier5G[0]*5+4800,
3229                                             eepromImage->calFreqPier5G[1]*5+4800,
3230                                             eepromImage->calFreqPier5G[2]*5+4800,
3231                                             eepromImage->calFreqPier5G[3]*5+4800,
3232                                             eepromImage->calFreqPier5G[4]*5+4800,
3233                                             eepromImage->calFreqPier5G[5]*5+4800,
3234                                             eepromImage->calFreqPier5G[6]*5+4800,
3235                                             eepromImage->calFreqPier5G[7]*5+4800
3236                                             );
3237     DbgPrint("calFreqPier2G : %d, %d, %d, %d\n",
3238                                             eepromImage->calFreqPier2G[0]+2300,
3239                                             eepromImage->calFreqPier2G[1]+2300,
3240                                             eepromImage->calFreqPier2G[2]+2300,
3241                                             eepromImage->calFreqPier2G[3]+2300
3242                                             );
3243     #endif
3244     if (frequency < 3000)
3245     {
3246         for (i=0; i<4; i++)
3247         {
3248             if (eepromImage->calFreqPier2G[i] == 0xff)
3249             {
3250                 break;
3251             }
3252         }
3253         max2gIndex = i;
3254         #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3255         DbgPrint("max2gIndex : %d\n", max2gIndex);
3256         #endif
3257         fbin = (u8_t)(frequency - 2300);
3258         index = zfFindFreqIndex(fbin, eepromImage->calFreqPier2G, max2gIndex);
3259         #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3260         DbgPrint("2G index : %d\n", index);
3261         DbgPrint("chain 0 index\n");
3262         #endif
3263         zfPrintTp(&eepromImage->calPierData2G[0][index].pwrPdg[0][0],
3264                   &eepromImage->calPierData2G[0][index].vpdPdg[0][0],
3265                   &eepromImage->calPierData2G[0][index].pwrPdg[1][0],
3266                   &eepromImage->calPierData2G[0][index].vpdPdg[1][0]
3267                   );
3268         #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3269         DbgPrint("chain 0 index+1\n");
3270         #endif
3271         zfPrintTp(&eepromImage->calPierData2G[0][index+1].pwrPdg[0][0],
3272                   &eepromImage->calPierData2G[0][index+1].vpdPdg[0][0],
3273                   &eepromImage->calPierData2G[0][index+1].pwrPdg[1][0],
3274                   &eepromImage->calPierData2G[0][index+1].vpdPdg[1][0]
3275                   );
3276
3277         for (i=0; i<5; i++)
3278         {
3279             chain0pwrPdg0[i] = zfInterpolateFuncX(fbin,
3280                     eepromImage->calFreqPier2G[index],
3281                     eepromImage->calPierData2G[0][index].pwrPdg[0][i],
3282                     eepromImage->calFreqPier2G[index+1],
3283                     eepromImage->calPierData2G[0][index+1].pwrPdg[0][i]
3284                     );
3285             chain0vpdPdg0[i] = zfInterpolateFuncX(fbin,
3286                     eepromImage->calFreqPier2G[index],
3287                     eepromImage->calPierData2G[0][index].vpdPdg[0][i],
3288                     eepromImage->calFreqPier2G[index+1],
3289                     eepromImage->calPierData2G[0][index+1].vpdPdg[0][i]
3290                     );
3291             chain0pwrPdg1[i] = zfInterpolateFuncX(fbin,
3292                     eepromImage->calFreqPier2G[index],
3293                     eepromImage->calPierData2G[0][index].pwrPdg[1][i],
3294                     eepromImage->calFreqPier2G[index+1],
3295                     eepromImage->calPierData2G[0][index+1].pwrPdg[1][i]
3296                     );
3297             chain0vpdPdg1[i] = zfInterpolateFuncX(fbin,
3298                     eepromImage->calFreqPier2G[index],
3299                     eepromImage->calPierData2G[0][index].vpdPdg[1][i],
3300                     eepromImage->calFreqPier2G[index+1],
3301                     eepromImage->calPierData2G[0][index+1].vpdPdg[1][i]
3302                     );
3303
3304             chain2pwrPdg0[i] = zfInterpolateFuncX(fbin,
3305                     eepromImage->calFreqPier2G[index],
3306                     eepromImage->calPierData2G[1][index].pwrPdg[0][i],
3307                     eepromImage->calFreqPier2G[index+1],
3308                     eepromImage->calPierData2G[1][index+1].pwrPdg[0][i]
3309                     );
3310             chain2vpdPdg0[i] = zfInterpolateFuncX(fbin,
3311                     eepromImage->calFreqPier2G[index],
3312                     eepromImage->calPierData2G[1][index].vpdPdg[0][i],
3313                     eepromImage->calFreqPier2G[index+1],
3314                     eepromImage->calPierData2G[1][index+1].vpdPdg[0][i]
3315                     );
3316             chain2pwrPdg1[i] = zfInterpolateFuncX(fbin,
3317                     eepromImage->calFreqPier2G[index],
3318                     eepromImage->calPierData2G[1][index].pwrPdg[1][i],
3319                     eepromImage->calFreqPier2G[index+1],
3320                     eepromImage->calPierData2G[1][index+1].pwrPdg[1][i]
3321                     );
3322             chain2vpdPdg1[i] = zfInterpolateFuncX(fbin,
3323                     eepromImage->calFreqPier2G[index],
3324                     eepromImage->calPierData2G[1][index].vpdPdg[1][i],
3325                     eepromImage->calFreqPier2G[index+1],
3326                     eepromImage->calPierData2G[1][index+1].vpdPdg[1][i]
3327                     );
3328         }
3329     }
3330     else
3331     {
3332         for (i=0; i<8; i++)
3333         {
3334             if (eepromImage->calFreqPier5G[i] == 0xff)
3335             {
3336                 break;
3337             }
3338         }
3339         max5gIndex = i;
3340         #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3341         DbgPrint("max5gIndex : %d\n", max5gIndex);
3342         #endif
3343         fbin = (u8_t)((frequency - 4800)/5);
3344         index = zfFindFreqIndex(fbin, eepromImage->calFreqPier5G, max5gIndex);
3345         #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3346         DbgPrint("5G index : %d\n", index);
3347         #endif
3348
3349         for (i=0; i<5; i++)
3350         {
3351             chain0pwrPdg0[i] = zfInterpolateFuncX(fbin,
3352                     eepromImage->calFreqPier5G[index],
3353                     eepromImage->calPierData5G[0][index].pwrPdg[0][i],
3354                     eepromImage->calFreqPier5G[index+1],
3355                     eepromImage->calPierData5G[0][index+1].pwrPdg[0][i]
3356                     );
3357             chain0vpdPdg0[i] = zfInterpolateFuncX(fbin,
3358                     eepromImage->calFreqPier5G[index],
3359                     eepromImage->calPierData5G[0][index].vpdPdg[0][i],
3360                     eepromImage->calFreqPier5G[index+1],
3361                     eepromImage->calPierData5G[0][index+1].vpdPdg[0][i]
3362                     );
3363             chain0pwrPdg1[i] = zfInterpolateFuncX(fbin,
3364                     eepromImage->calFreqPier5G[index],
3365                     eepromImage->calPierData5G[0][index].pwrPdg[1][i],
3366                     eepromImage->calFreqPier5G[index+1],
3367                     eepromImage->calPierData5G[0][index+1].pwrPdg[1][i]
3368                     );
3369             chain0vpdPdg1[i] = zfInterpolateFuncX(fbin,
3370                     eepromImage->calFreqPier5G[index],
3371                     eepromImage->calPierData5G[0][index].vpdPdg[1][i],
3372                     eepromImage->calFreqPier5G[index+1],
3373                     eepromImage->calPierData5G[0][index+1].vpdPdg[1][i]
3374                     );
3375
3376             chain2pwrPdg0[i] = zfInterpolateFuncX(fbin,
3377                     eepromImage->calFreqPier5G[index],
3378                     eepromImage->calPierData5G[1][index].pwrPdg[0][i],
3379                     eepromImage->calFreqPier5G[index+1],
3380                     eepromImage->calPierData5G[1][index+1].pwrPdg[0][i]
3381                     );
3382             chain2vpdPdg0[i] = zfInterpolateFuncX(fbin,
3383                     eepromImage->calFreqPier5G[index],
3384                     eepromImage->calPierData5G[1][index].vpdPdg[0][i],
3385                     eepromImage->calFreqPier5G[index+1],
3386                     eepromImage->calPierData5G[1][index+1].vpdPdg[0][i]
3387                     );
3388             chain2pwrPdg1[i] = zfInterpolateFuncX(fbin,
3389                     eepromImage->calFreqPier5G[index],
3390                     eepromImage->calPierData5G[1][index].pwrPdg[1][i],
3391                     eepromImage->calFreqPier5G[index+1],
3392                     eepromImage->calPierData5G[1][index+1].pwrPdg[1][i]
3393                     );
3394             chain2vpdPdg1[i] = zfInterpolateFuncX(fbin,
3395                     eepromImage->calFreqPier5G[index],
3396                     eepromImage->calPierData5G[1][index].vpdPdg[1][i],
3397                     eepromImage->calFreqPier5G[index+1],
3398                     eepromImage->calPierData5G[1][index+1].vpdPdg[1][i]
3399                     );
3400         }
3401
3402     }
3403
3404
3405     /* Chain 1 */
3406     /* Get pwr and vpd test points from frequency */
3407     for (i=0; i<5; i++)
3408     {
3409         pwr0[i] = chain0pwrPdg0[i]>>1;
3410         vpd0[i] = chain0vpdPdg0[i];
3411         pwr1[i] = chain0pwrPdg1[i]>>1;
3412         vpd1[i] = chain0vpdPdg1[i];
3413     }
3414     #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3415     DbgPrint("Test Points\n");
3416     DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]);
3417     DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]);
3418     DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]);
3419     DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]);
3420     #endif
3421     /* Generate the vpd arrays */
3422     for (i=0; i<boundary1+1+6; i++)
3423     {
3424         vpd_chain1[i] = zfGetInterpolatedValue(i, &pwr0[0], &vpd0[0]);
3425     }
3426     for (; i<powerTxMax+1+6+6; i++)
3427     {
3428         vpd_chain1[i] = zfGetInterpolatedValue(i-6-6, &pwr1[0], &vpd1[0]);
3429     }
3430     #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3431     DbgPrint("vpd_chain1\n");
3432     for (i=0; i<powerTxMax+1+6+6; i+=10)
3433     {
3434         DbgPrint("%d, %d, %d, %d ,%d, %d, %d, %d, %d, %d\n",
3435                 vpd_chain1[i+0], vpd_chain1[i+1], vpd_chain1[i+2], vpd_chain1[i+3], vpd_chain1[i+4],
3436                 vpd_chain1[i+5], vpd_chain1[i+6], vpd_chain1[i+7], vpd_chain1[i+8], vpd_chain1[i+9]);
3437     }
3438     #endif
3439     /* Write PHY regs 672-703 */
3440     for (i=0; i<128; i+=4)
3441     {
3442         u32_t val;
3443
3444         val = ((u32_t)vpd_chain1[i+3]<<24) |
3445                 ((u32_t)vpd_chain1[i+2]<<16) |
3446                 ((u32_t)vpd_chain1[i+1]<<8) |
3447                 ((u32_t)vpd_chain1[i]);
3448
3449         #ifndef ZM_OTUS_LINUX_PHASE_2
3450         reg_write(regAddr + i, val);  /* CR672 */
3451         #endif
3452     }
3453
3454     /* Chain 2 */
3455     /* Get pwr and vpd test points from frequency */
3456     for (i=0; i<5; i++)
3457     {
3458         pwr0[i] = chain2pwrPdg0[i]>>1;
3459         vpd0[i] = chain2vpdPdg0[i];
3460         pwr1[i] = chain2pwrPdg1[i]>>1;
3461         vpd1[i] = chain2vpdPdg1[i];
3462     }
3463     #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3464     DbgPrint("Test Points\n");
3465     DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]);
3466     DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]);
3467     DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]);
3468     DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]);
3469     #endif
3470     /* Generate the vpd arrays */
3471     for (i=0; i<boundary1+1+6; i++)
3472     {
3473         vpd_chain3[i] = zfGetInterpolatedValue(i, &pwr0[0], &vpd0[0]);
3474     }
3475     for (; i<powerTxMax+1+6+6; i++)
3476     {
3477         vpd_chain3[i] = zfGetInterpolatedValue(i-6-6, &pwr1[0], &vpd1[0]);
3478     }
3479     #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3480     DbgPrint("vpd_chain3\n");
3481     for (i=0; i<powerTxMax+1+6+6; i+=10)
3482     {
3483         DbgPrint("%d, %d, %d, %d ,%d, %d, %d, %d, %d, %d\n",
3484                 vpd_chain3[i+0], vpd_chain3[i+1], vpd_chain3[i+2], vpd_chain3[i+3], vpd_chain3[i+4],
3485                 vpd_chain3[i+5], vpd_chain3[i+6], vpd_chain3[i+7], vpd_chain3[i+8], vpd_chain3[i+9]);
3486     }
3487     #endif
3488
3489     /* Write PHY regs 672-703 + 0x1000 */
3490     for (i=0; i<128; i+=4)
3491     {
3492         u32_t val;
3493
3494         val = ((u32_t)vpd_chain3[i+3]<<24) |
3495                 ((u32_t)vpd_chain3[i+2]<<16) |
3496                 ((u32_t)vpd_chain3[i+1]<<8) |
3497                 ((u32_t)vpd_chain3[i]);
3498
3499         #ifndef ZM_OTUS_LINUX_PHASE_2
3500         reg_write(regAddr + i, val);  /* CR672 */
3501         #endif
3502     }
3503
3504     zfFlushDelayWrite(dev);
3505
3506     /* 3. Generate target power table */
3507     if (frequency < 3000)
3508     {
3509         for (i=0; i<3; i++)
3510         {
3511             if (eepromImage->calTargetPowerCck[i].bChannel != 0xff)
3512             {
3513                 fbinArray[i] = eepromImage->calTargetPowerCck[i].bChannel;
3514             }
3515             else
3516             {
3517                 break;
3518             }
3519
3520         }
3521         index = zfFindFreqIndex(fbin, fbinArray, i);
3522         #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3523         DbgPrint("CCK index=%d\n", index);
3524         #endif
3525         for (i=0; i<4; i++)
3526         {
3527             hpPriv->tPow2xCck[i] = zfInterpolateFuncX(fbin,
3528                     eepromImage->calTargetPowerCck[index].bChannel,
3529                     eepromImage->calTargetPowerCck[index].tPow2x[i],
3530                     eepromImage->calTargetPowerCck[index+1].bChannel,
3531                     eepromImage->calTargetPowerCck[index+1].tPow2x[i]
3532                     );
3533         }
3534
3535         for (i=0; i<4; i++)
3536         {
3537             if (eepromImage->calTargetPower2G[i].bChannel != 0xff)
3538             {
3539                 fbinArray[i] = eepromImage->calTargetPower2G[i].bChannel;
3540             }
3541             else
3542             {
3543                 break;
3544             }
3545
3546         }
3547         index = zfFindFreqIndex(fbin, fbinArray, i);
3548         #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3549         DbgPrint("2G index=%d\n", index);
3550         #endif
3551         for (i=0; i<4; i++)
3552         {
3553             hpPriv->tPow2x2g[i] = zfInterpolateFuncX(fbin,
3554                     eepromImage->calTargetPower2G[index].bChannel,
3555                     eepromImage->calTargetPower2G[index].tPow2x[i],
3556                     eepromImage->calTargetPower2G[index+1].bChannel,
3557                     eepromImage->calTargetPower2G[index+1].tPow2x[i]
3558                     );
3559         }
3560
3561         for (i=0; i<4; i++)
3562         {
3563             if (eepromImage->calTargetPower2GHT20[i].bChannel != 0xff)
3564             {
3565                 fbinArray[i] = eepromImage->calTargetPower2GHT20[i].bChannel;
3566             }
3567             else
3568             {
3569                 break;
3570             }
3571
3572         }
3573         index = zfFindFreqIndex(fbin, fbinArray, i);
3574         #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3575         DbgPrint("2G HT20 index=%d\n", index);
3576         #endif
3577         for (i=0; i<8; i++)
3578         {
3579             hpPriv->tPow2x2gHt20[i] = zfInterpolateFuncX(fbin,
3580                     eepromImage->calTargetPower2GHT20[index].bChannel,
3581                     eepromImage->calTargetPower2GHT20[index].tPow2x[i],
3582                     eepromImage->calTargetPower2GHT20[index+1].bChannel,
3583                     eepromImage->calTargetPower2GHT20[index+1].tPow2x[i]
3584                     );
3585         }
3586
3587         for (i=0; i<4; i++)
3588         {
3589             if (eepromImage->calTargetPower2GHT40[i].bChannel != 0xff)
3590             {
3591                 fbinArray[i] = eepromImage->calTargetPower2GHT40[i].bChannel;
3592             }
3593             else
3594             {
3595                 break;
3596             }
3597
3598         }
3599         index = zfFindFreqIndex( (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset), fbinArray, i);
3600         #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3601         DbgPrint("2G HT40 index=%d\n", index);
3602         #endif
3603         for (i=0; i<8; i++)
3604         {
3605             hpPriv->tPow2x2gHt40[i] = zfInterpolateFuncX(
3606                     (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset),
3607                     eepromImage->calTargetPower2GHT40[index].bChannel,
3608                     eepromImage->calTargetPower2GHT40[index].tPow2x[i],
3609                     eepromImage->calTargetPower2GHT40[index+1].bChannel,
3610                     eepromImage->calTargetPower2GHT40[index+1].tPow2x[i]
3611                     );
3612         }
3613
3614         zfPrintTargetPower2G(hpPriv->tPow2xCck,
3615                 hpPriv->tPow2x2g,
3616                 hpPriv->tPow2x2gHt20,
3617                 hpPriv->tPow2x2gHt40);
3618     }
3619     else
3620     {
3621         /* 5G */
3622         for (i=0; i<8; i++)
3623         {
3624             if (eepromImage->calTargetPower5G[i].bChannel != 0xff)
3625             {
3626                 fbinArray[i] = eepromImage->calTargetPower5G[i].bChannel;
3627             }
3628             else
3629             {
3630                 break;
3631             }
3632
3633         }
3634         index = zfFindFreqIndex(fbin, fbinArray, i);
3635         #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3636         DbgPrint("5G index=%d\n", index);
3637         #endif
3638         for (i=0; i<4; i++)
3639         {
3640             hpPriv->tPow2x5g[i] = zfInterpolateFuncX(fbin,
3641                     eepromImage->calTargetPower5G[index].bChannel,
3642                     eepromImage->calTargetPower5G[index].tPow2x[i],
3643                     eepromImage->calTargetPower5G[index+1].bChannel,
3644                     eepromImage->calTargetPower5G[index+1].tPow2x[i]
3645                     );
3646         }
3647
3648         for (i=0; i<8; i++)
3649         {
3650             if (eepromImage->calTargetPower5GHT20[i].bChannel != 0xff)
3651             {
3652                 fbinArray[i] = eepromImage->calTargetPower5GHT20[i].bChannel;
3653             }
3654             else
3655             {
3656                 break;
3657             }
3658
3659         }
3660         index = zfFindFreqIndex(fbin, fbinArray, i);
3661         #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3662         DbgPrint("5G HT20 index=%d\n", index);
3663         #endif
3664         for (i=0; i<8; i++)
3665         {
3666             hpPriv->tPow2x5gHt20[i] = zfInterpolateFuncX(fbin,
3667                     eepromImage->calTargetPower5GHT20[index].bChannel,
3668                     eepromImage->calTargetPower5GHT20[index].tPow2x[i],
3669                     eepromImage->calTargetPower5GHT20[index+1].bChannel,
3670                     eepromImage->calTargetPower5GHT20[index+1].tPow2x[i]
3671                     );
3672         }
3673
3674         for (i=0; i<8; i++)
3675         {
3676             if (eepromImage->calTargetPower5GHT40[i].bChannel != 0xff)
3677             {
3678                 fbinArray[i] = eepromImage->calTargetPower5GHT40[i].bChannel;
3679             }
3680             else
3681             {
3682                 break;
3683             }
3684
3685         }
3686         index = zfFindFreqIndex((u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset), fbinArray, i);
3687         #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3688         DbgPrint("5G HT40 index=%d\n", index);
3689         #endif
3690         for (i=0; i<8; i++)
3691         {
3692             hpPriv->tPow2x5gHt40[i] = zfInterpolateFuncX(
3693                     (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset),
3694                     eepromImage->calTargetPower5GHT40[index].bChannel,
3695                     eepromImage->calTargetPower5GHT40[index].tPow2x[i],
3696                     eepromImage->calTargetPower5GHT40[index+1].bChannel,
3697                     eepromImage->calTargetPower5GHT40[index+1].tPow2x[i]
3698                     );
3699         }
3700
3701         zfPrintTargetPower5G(
3702                 hpPriv->tPow2x5g,
3703                 hpPriv->tPow2x5gHt20,
3704                 hpPriv->tPow2x5gHt40);
3705     }
3706
3707
3708
3709     /* 4. CTL */
3710     /*
3711      * 4.1 Get the bandedges tx power by frequency
3712      *      2.4G we get ctlEdgesMaxPowerCCK
3713      *                  ctlEdgesMaxPower2G
3714      *                  ctlEdgesMaxPower2GHT20
3715      *                  ctlEdgesMaxPower2GHT40
3716      *      5G we get   ctlEdgesMaxPower5G
3717      *                  ctlEdgesMaxPower5GHT20
3718      *                  ctlEdgesMaxPower5GHT40
3719      * 4.2 Update (3.) target power table by 4.1
3720      * 4.3 Tx power offset for ART - NDIS/MDK
3721      * 4.4 Write MAC reg 0x694 for ACK's TPC
3722      *
3723      */
3724
3725     //zfDumpEepBandEdges(eepromImage);
3726
3727     /* get the cfg from Eeprom: regionCode => RegulatoryDomain : 0x10-FFC  0x30-eu 0x40-jap */
3728     desired_CtlIndex = zfHpGetRegulatoryDomain(dev);
3729     if ((desired_CtlIndex == 0x30) || (desired_CtlIndex == 0x40) || (desired_CtlIndex == 0x0))
3730     {
3731         /* skip CTL and heavy clip */
3732         hpPriv->enableBBHeavyClip = 0;
3733         #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3734         zm_dbg(("RegulatoryDomain = 0, skip CTL and heavy clip\n"));
3735         #endif
3736     }
3737     else
3738     {
3739         hpPriv->enableBBHeavyClip = 1;
3740
3741         if (desired_CtlIndex == 0xff)
3742         {
3743             /* desired index not found */
3744             desired_CtlIndex = 0x10;
3745         }
3746
3747         /* first part : 2.4G */
3748         if (frequency <= ZM_CH_G_14)
3749         {
3750             /* 2.4G - CTL_11B */
3751             ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11B);
3752             if(ctl_i<AR5416_NUM_CTLS)
3753             {
3754                 ctlEdgesMaxPowerCCK = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3755             }
3756             #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3757             zm_dbg(("CTL_11B ctl_i = %d\n", ctl_i));
3758             #endif
3759
3760             /* 2.4G - CTL_11G */
3761             ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11G);
3762             if(ctl_i<AR5416_NUM_CTLS)
3763             {
3764                 ctlEdgesMaxPower2G = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3765             }
3766             #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3767             zm_dbg(("CTL_11G ctl_i = %d\n", ctl_i));
3768             #endif
3769
3770             /* 2.4G - CTL_2GHT20 */
3771             ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_2GHT20);
3772             if(ctl_i<AR5416_NUM_CTLS)
3773             {
3774                 ctlEdgesMaxPower2GHT20 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3775             }
3776             else
3777             {
3778                 /* workaround for no data in Eeprom, replace by normal 2G */
3779                 ctlEdgesMaxPower2GHT20 = ctlEdgesMaxPower2G;
3780             }
3781             #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3782             zm_dbg(("CTL_2GHT20 ctl_i = %d\n", ctl_i));
3783             #endif
3784
3785             /* 2.4G - CTL_2GHT40 */
3786             ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_2GHT40);
3787             if(ctl_i<AR5416_NUM_CTLS)
3788             {
3789                 ctlEdgesMaxPower2GHT40 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1],
3790                                                                 zfAdjustHT40FreqOffset(dev, frequency, bw40, extOffset));
3791             }
3792             else
3793             {
3794                 /* workaround for no data in Eeprom, replace by normal 2G */
3795                 ctlEdgesMaxPower2GHT40 = ctlEdgesMaxPower2G;
3796             }
3797             #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3798             zm_dbg(("CTL_2GHT40 ctl_i = %d\n", ctl_i));
3799             #endif
3800
3801
3802             /* 7a17 :  */
3803             /* Max power (dBm) for channel range when using DFS define by madwifi*/
3804             for (i=0; i<wd->regulationTable.allowChannelCnt; i++)
3805             {
3806                 if (wd->regulationTable.allowChannel[i].channel == frequency)
3807                 {
3808                     if (zfHpIsDfsChannel(dev, (u16_t)frequency))
3809                     {
3810                         zm_debug_msg1("frequency use DFS  -- ", frequency);
3811                         ctlEdgesMaxPowerCCK     = zm_min(ctlEdgesMaxPowerCCK, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3812                         ctlEdgesMaxPower2G      = zm_min(ctlEdgesMaxPower2G, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3813                         ctlEdgesMaxPower2GHT20  = zm_min(ctlEdgesMaxPower2GHT20, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3814                         ctlEdgesMaxPower2GHT40  = zm_min(ctlEdgesMaxPower2GHT40, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3815                     }
3816                     break;
3817                 }
3818             }
3819
3820             /* Apply ctl mode to correct target power set */
3821             #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3822             zm_debug_msg1("ctlEdgesMaxPowerCCK    = ", ctlEdgesMaxPowerCCK);
3823             zm_debug_msg1("ctlEdgesMaxPower2G     = ", ctlEdgesMaxPower2G);
3824             zm_debug_msg1("ctlEdgesMaxPower2GHT20 = ", ctlEdgesMaxPower2GHT20);
3825             zm_debug_msg1("ctlEdgesMaxPower2GHT40 = ", ctlEdgesMaxPower2GHT40);
3826             #endif
3827             for (i=0; i<4; i++)
3828             {
3829                 hpPriv->tPow2xCck[i] = zm_min(hpPriv->tPow2xCck[i], ctlEdgesMaxPowerCCK) + HALTX_POWER_OFFSET;
3830             }
3831             hpPriv->tPow2x2g24HeavyClipOffset = 0;
3832             if (hpPriv->enableBBHeavyClip)
3833             {
3834                 ctlOffset = 2;
3835             }
3836             else
3837             {
3838                 ctlOffset = 0;
3839             }
3840             for (i=0; i<4; i++)
3841             {
3842                 if (((frequency == 2412) || (frequency == 2462)))
3843                 {
3844                     if (i != 0)
3845                     {
3846                         hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G-ctlOffset) + HALTX_POWER_OFFSET;
3847                     }
3848                     else
3849                     {
3850                         hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G) + HALTX_POWER_OFFSET;
3851                         if (hpPriv->tPow2x2g[i] > (ctlEdgesMaxPower2G-ctlOffset))
3852                         {
3853                             hpPriv->tPow2x2g24HeavyClipOffset = hpPriv->tPow2x2g[i] - (ctlEdgesMaxPower2G-ctlOffset);
3854                         }
3855                     }
3856                 }
3857                 else
3858                 {
3859                     hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G) + HALTX_POWER_OFFSET;
3860                 }
3861             }
3862             for (i=0; i<8; i++)
3863             {
3864                 if (((frequency == 2412) || (frequency == 2462)) && (i>=3))
3865                 {
3866                     hpPriv->tPow2x2gHt20[i] = zm_min(hpPriv->tPow2x2gHt20[i], ctlEdgesMaxPower2GHT20-ctlOffset) + HALTX_POWER_OFFSET;
3867                 }
3868                 else
3869                 {
3870                     hpPriv->tPow2x2gHt20[i] = zm_min(hpPriv->tPow2x2gHt20[i], ctlEdgesMaxPower2GHT20) + HALTX_POWER_OFFSET;
3871                 }
3872             }
3873             for (i=0; i<8; i++)
3874             {
3875                 if ((frequency == 2412) && (i>=3))
3876                 {
3877                     hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40-ctlOffset) + HALTX_POWER_OFFSET;
3878                 }
3879                 else if ((frequency == 2462) && (i>=3))
3880                 {
3881                     hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40-(ctlOffset*2)) + HALTX_POWER_OFFSET;
3882                 }
3883                 else
3884                 {
3885                     hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40) + HALTX_POWER_OFFSET;
3886                 }
3887             }
3888         }
3889         else
3890         {
3891             /* 5G - CTL_11A */
3892             ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11A);
3893             if(ctl_i<AR5416_NUM_CTLS)
3894             {
3895                 ctlEdgesMaxPower5G = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3896             }
3897             #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3898             zm_dbg(("CTL_11A ctl_i = %d\n", ctl_i));
3899             #endif
3900
3901             /* 5G - CTL_5GHT20 */
3902             ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_5GHT20);
3903             if(ctl_i<AR5416_NUM_CTLS)
3904             {
3905                 ctlEdgesMaxPower5GHT20 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3906             }
3907             else
3908             {
3909                 /* workaround for no data in Eeprom, replace by normal 5G */
3910                 ctlEdgesMaxPower5GHT20 = ctlEdgesMaxPower5G;
3911             }
3912             #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3913             zm_dbg(("CTL_5GHT20 ctl_i = %d\n", ctl_i));
3914             #endif
3915
3916             /* 5G - CTL_5GHT40 */
3917             ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_5GHT40);
3918             if(ctl_i<AR5416_NUM_CTLS)
3919             {
3920                 ctlEdgesMaxPower5GHT40 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1],
3921                                                                 zfAdjustHT40FreqOffset(dev, frequency, bw40, extOffset));
3922             }
3923             else
3924             {
3925                 /* workaround for no data in Eeprom, replace by normal 5G */
3926                 ctlEdgesMaxPower5GHT40 = ctlEdgesMaxPower5G;
3927             }
3928             #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3929             zm_dbg(("CTL_5GHT40 ctl_i = %d\n", ctl_i));
3930             #endif
3931
3932             /* 7a17 :  */
3933             /* Max power (dBm) for channel range when using DFS define by madwifi*/
3934             for (i=0; i<wd->regulationTable.allowChannelCnt; i++)
3935             {
3936                 if (wd->regulationTable.allowChannel[i].channel == frequency)
3937                 {
3938                     if (zfHpIsDfsChannel(dev, (u16_t)frequency))
3939                     {
3940                         zm_debug_msg1("frequency use DFS  -- ", frequency);
3941                         ctlEdgesMaxPower5G      = zm_min(ctlEdgesMaxPower5G, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3942                         ctlEdgesMaxPower5GHT20  = zm_min(ctlEdgesMaxPower5GHT20, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3943                         ctlEdgesMaxPower5GHT40  = zm_min(ctlEdgesMaxPower5GHT40, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3944                     }
3945                     break;
3946                 }
3947             }
3948
3949
3950             /* Apply ctl mode to correct target power set */
3951             #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3952             zm_debug_msg1("ctlEdgesMaxPower5G     = ", ctlEdgesMaxPower5G);
3953             zm_debug_msg1("ctlEdgesMaxPower5GHT20 = ", ctlEdgesMaxPower5GHT20);
3954             zm_debug_msg1("ctlEdgesMaxPower5GHT40 = ", ctlEdgesMaxPower5GHT40);
3955             #endif
3956             for (i=0; i<4; i++)
3957             {
3958                 hpPriv->tPow2x5g[i] = zm_min(hpPriv->tPow2x5g[i], ctlEdgesMaxPower5G) + HALTX_POWER_OFFSET;
3959             }
3960             for (i=0; i<8; i++)
3961             {
3962                 hpPriv->tPow2x5gHt20[i] = zm_min(hpPriv->tPow2x5gHt20[i], ctlEdgesMaxPower5GHT20) + HALTX_POWER_OFFSET;
3963             }
3964             for (i=0; i<8; i++)
3965             {
3966                 hpPriv->tPow2x5gHt40[i] = zm_min(hpPriv->tPow2x5gHt40[i], ctlEdgesMaxPower5GHT40) + HALTX_POWER_OFFSET;
3967             }
3968
3969         }/* end of bandedges of 5G */
3970     }/* end of  if ((desired_CtlIndex = zfHpGetRegulatoryDomain(dev)) == 0) */
3971
3972     /* workaround */
3973     /* 5. BB heavy clip */
3974     /*    only 2.4G do heavy clip */
3975     if (hpPriv->enableBBHeavyClip && hpPriv->hwBBHeavyClip && (frequency <= ZM_CH_G_14))
3976     {
3977         if (frequency <= ZM_CH_G_14)
3978         {
3979             ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11G);
3980         }
3981         else
3982         {
3983             ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11A);
3984         }
3985
3986         hpPriv->setValueHeavyClip = zfHpCheckDoHeavyClip(dev, frequency, eepromImage->ctlData[ctl_i].ctlEdges[1], bw40);
3987
3988         if (hpPriv->setValueHeavyClip)
3989         {
3990             hpPriv->doBBHeavyClip = 1;
3991         }
3992         else
3993         {
3994             hpPriv->doBBHeavyClip = 0;
3995         }
3996         #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3997         zm_dbg(("zfHpCheckDoHeavyClip ret = %02x, doBBHeavyClip = %d\n",
3998                  hpPriv->setValueHeavyClip, hpPriv->doBBHeavyClip));
3999         #endif
4000
4001         if (hpPriv->doBBHeavyClip)
4002         {
4003             if (hpPriv->setValueHeavyClip & 0xf0)
4004             {
4005                 hpPriv->tPow2x2gHt40[0] -= 1;
4006                 hpPriv->tPow2x2gHt40[1] -= 1;
4007                 hpPriv->tPow2x2gHt40[2] -= 1;
4008             }
4009
4010             if (hpPriv->setValueHeavyClip & 0xf)
4011             {
4012                 hpPriv->tPow2x2gHt20[0] += 1;
4013                 hpPriv->tPow2x2gHt20[1] += 1;
4014                 hpPriv->tPow2x2gHt20[2] += 1;
4015             }
4016         }
4017     }
4018     else
4019     {
4020         hpPriv->doBBHeavyClip = 0;
4021         hpPriv->setValueHeavyClip = 0;
4022     }
4023
4024     /* Final : write MAC register for some ctrl frame Tx power */
4025     /* first part : 2.4G */
4026     if (frequency <= ZM_CH_G_14)
4027     {
4028         /* Write MAC reg 0x694 for ACK's TPC */
4029         /* Write MAC reg 0xbb4 RTS and SF-CTS frame power control */
4030         /* Always use two stream for low legacy rate */
4031         #if 0
4032         //if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
4033         //{
4034             zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x2g[0]&0x3f) << 20) | (0x1<<26));
4035             zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x2g[0]&0x3f) << 5 ) | (0x1<<11) |
4036                                                    ((hpPriv->tPow2x2g[0]&0x3f) << 21) | (0x1<<27)  );
4037         //}
4038         #endif
4039         #if 1
4040         //else
4041         {
4042             #ifndef ZM_OTUS_LINUX_PHASE_2
4043             zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x2g[0]&0x3f) << 20) | (0x5<<26));
4044             zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x2g[0]&0x3f) << 5 ) | (0x5<<11) |
4045                                                    ((hpPriv->tPow2x2g[0]&0x3f) << 21) | (0x5<<27)  );
4046             #endif
4047             hpPriv->currentAckRtsTpc = hpPriv->tPow2x2g[0];
4048         }
4049         #endif
4050         zfFlushDelayWrite(dev);
4051
4052         zfPrintTargetPower2G(hpPriv->tPow2xCck,
4053                 hpPriv->tPow2x2g,
4054                 hpPriv->tPow2x2gHt20,
4055                 hpPriv->tPow2x2gHt40);
4056     }
4057     else
4058     {
4059         /* Write MAC reg 0x694 for ACK's TPC */
4060         /* Write MAC reg 0xbb4 RTS and SF-CTS frame power control */
4061         /* Always use two stream for low legacy rate */
4062         if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
4063         {
4064             #ifndef ZM_OTUS_LINUX_PHASE_2
4065             zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x5g[0]&0x3f) << 20) | (0x1<<26));
4066             zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x5g[0]&0x3f) << 5 ) | (0x1<<11) |
4067                                                    ((hpPriv->tPow2x5g[0]&0x3f) << 21) | (0x1<<27)  );
4068             #endif
4069         }
4070         else
4071         {
4072             #ifndef ZM_OTUS_LINUX_PHASE_2
4073             zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x5g[0]&0x3f) << 20) | (0x5<<26));
4074             zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x5g[0]&0x3f) << 5 ) | (0x5<<11) |
4075                                                    ((hpPriv->tPow2x5g[0]&0x3f) << 21) | (0x5<<27)  );
4076             #endif
4077             hpPriv->currentAckRtsTpc = hpPriv->tPow2x2g[0];
4078         }
4079
4080
4081         zfFlushDelayWrite(dev);
4082
4083         zfPrintTargetPower5G(
4084                 hpPriv->tPow2x5g,
4085                 hpPriv->tPow2x5gHt20,
4086                 hpPriv->tPow2x5gHt40);
4087     }/* end of bandedges of 5G */
4088
4089 }
4090
4091 void zfDumpEepBandEdges(struct ar5416Eeprom* eepromImage)
4092 {
4093     #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
4094     u8_t i, j, k;
4095
4096 #if 0
4097     zm_dbg(("\n === BandEdges index dump ==== \n"));
4098
4099     for (i = 0; i < AR5416_NUM_CTLS; i++)
4100     {
4101         zm_dbg(("%02x ", eepromImage->ctlIndex[i]));
4102     }
4103
4104     zm_dbg(("\n === BandEdges data dump ==== \n"));
4105
4106     for (i = 0; i < AR5416_NUM_CTLS; i++)
4107     {
4108         for (j = 0; j < 2; j++)
4109         {
4110             for(k = 0; k < AR5416_NUM_BAND_EDGES; k++)
4111             {
4112                 u8_t *pdata = (u8_t*)&(eepromImage->ctlData[i].ctlEdges[j][k]);
4113                 zm_dbg(("(%02x %02x)", pdata[0], pdata[1]));
4114             }
4115             zm_dbg(("\n"));
4116         }
4117     }
4118 #else
4119     zm_dbg(("\n === BandEdges index dump ==== \n"));
4120     for (i = 0; i < 24; i+=8)
4121     {
4122         zm_dbg(("%02x %02x %02x %02x %02x %02x %02x %02x",
4123                eepromImage->ctlIndex[i+0], eepromImage->ctlIndex[i+1], eepromImage->ctlIndex[i+2], eepromImage->ctlIndex[i+3],
4124                eepromImage->ctlIndex[i+4], eepromImage->ctlIndex[i+5], eepromImage->ctlIndex[i+6], eepromImage->ctlIndex[i+7]
4125                ));
4126     }
4127
4128     zm_dbg(("\n === BandEdges data dump ==== \n"));
4129
4130     for (i = 0; i < AR5416_NUM_CTLS; i++)
4131     {
4132         for (j = 0; j < 2; j++)
4133         {
4134             u8_t *pdata = (u8_t*)&(eepromImage->ctlData[i].ctlEdges[j]);
4135             zm_dbg(("(%03d %02x) (%03d %02x) (%03d %02x) (%03d %02x) \n",
4136                    pdata[0], pdata[1], pdata[2], pdata[3],
4137                    pdata[4], pdata[5], pdata[6], pdata[7]
4138                    ));
4139             zm_dbg(("(%03d %02x) (%03d %02x) (%03d %02x) (%03d %02x) \n",
4140                    pdata[8], pdata[9], pdata[10], pdata[11],
4141                    pdata[12], pdata[13], pdata[14], pdata[15]
4142                    ));
4143         }
4144     }
4145 #endif
4146     #endif
4147 }
4148
4149 void zfPrintTargetPower2G(u8_t* tPow2xCck, u8_t* tPow2x2g, u8_t* tPow2x2gHt20, u8_t* tPow2x2gHt40)
4150 {
4151     //#ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
4152     #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
4153     DbgPrint("targetPwr CCK : %d, %d, %d, %d\n",
4154             tPow2xCck[0],
4155             tPow2xCck[1],
4156             tPow2xCck[2],
4157             tPow2xCck[3]
4158             );
4159     DbgPrint("targetPwr 2G : %d, %d, %d, %d\n",
4160             tPow2x2g[0],
4161             tPow2x2g[1],
4162             tPow2x2g[2],
4163             tPow2x2g[3]
4164             );
4165     DbgPrint("targetPwr 2GHT20 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4166             tPow2x2gHt20[0],
4167             tPow2x2gHt20[1],
4168             tPow2x2gHt20[2],
4169             tPow2x2gHt20[3],
4170             tPow2x2gHt20[4],
4171             tPow2x2gHt20[5],
4172             tPow2x2gHt20[6],
4173             tPow2x2gHt20[7]
4174             );
4175     DbgPrint("targetPwr 2GHT40 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4176             tPow2x2gHt40[0],
4177             tPow2x2gHt40[1],
4178             tPow2x2gHt40[2],
4179             tPow2x2gHt40[3],
4180             tPow2x2gHt40[4],
4181             tPow2x2gHt40[5],
4182             tPow2x2gHt40[6],
4183             tPow2x2gHt40[7]
4184             );
4185     #endif
4186     return;
4187 }
4188
4189 void zfPrintTargetPower5G(u8_t* tPow2x5g, u8_t* tPow2x5gHt20, u8_t* tPow2x5gHt40)
4190 {
4191     //#ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
4192     #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
4193     DbgPrint("targetPwr 5G : %d, %d, %d, %d\n",
4194             tPow2x5g[0],
4195             tPow2x5g[1],
4196             tPow2x5g[2],
4197             tPow2x5g[3]
4198             );
4199     DbgPrint("targetPwr 5GHT20 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4200             tPow2x5gHt20[0],
4201             tPow2x5gHt20[1],
4202             tPow2x5gHt20[2],
4203             tPow2x5gHt20[3],
4204             tPow2x5gHt20[4],
4205             tPow2x5gHt20[5],
4206             tPow2x5gHt20[6],
4207             tPow2x5gHt20[7]
4208             );
4209     DbgPrint("targetPwr 5GHT40 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4210             tPow2x5gHt40[0],
4211             tPow2x5gHt40[1],
4212             tPow2x5gHt40[2],
4213             tPow2x5gHt40[3],
4214             tPow2x5gHt40[4],
4215             tPow2x5gHt40[5],
4216             tPow2x5gHt40[6],
4217             tPow2x5gHt40[7]
4218             );
4219     #endif
4220     return;
4221 }
4222
4223 void zfHpPowerSaveSetMode(zdev_t* dev, u8_t staMode, u8_t psMode, u16_t bcnInterval)
4224 {
4225     if ( staMode == 0 )
4226     {
4227         if ( psMode == 0 )
4228         {
4229             // Turn off pre-TBTT interrupt
4230             zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, 0);
4231             zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, 0);
4232             zfFlushDelayWrite(dev);
4233         }
4234         else
4235         {
4236             // Turn on pre-TBTT interrupt
4237             zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, (bcnInterval-6)<<16);
4238             zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, bcnInterval);
4239             zfFlushDelayWrite(dev);
4240         }
4241     }
4242 }
4243
4244 void zfHpPowerSaveSetState(zdev_t* dev, u8_t psState)
4245 {
4246     struct zsHpPriv* hpPriv;
4247
4248     zmw_get_wlan_dev(dev);
4249     hpPriv = wd->hpPrivate;
4250
4251         //DbgPrint("INTO zfHpPowerSaveSetState");
4252
4253     if ( psState == 0 ) //power up
4254     {
4255         //DbgPrint("zfHpPowerSaveSetState Wake up from PS\n");
4256         reg_write(0x982C, 0x0000a000); //wake up ADDAC
4257         reg_write(0x9808, 0x0);        //enable all agc gain and offset updates to a2
4258         //# bank 3
4259         if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency <= ZM_CH_G_14)
4260         {
4261             /* 11g */
4262             //reg_write (0x98f0,  0x01c00018);
4263             reg_write (0x98f0,  0x01c20098);//syn_on+RX_ON
4264         }
4265         else
4266         {
4267             /* 11a */
4268             //reg_write (0x98f0,  0x01400018);
4269             reg_write (0x98f0,  0x01420098);//syn_on+RX_ON
4270         }
4271
4272         ////#bank 5
4273         //reg_write(0x98b0,  0x00000013);
4274         //reg_write(0x98e4,  0x00000002);
4275
4276
4277         zfFlushDelayWrite(dev);
4278     }
4279     else //power down
4280     {
4281         //DbgPrint("zfHpPowerSaveSetState Go to PS\n");
4282         //reg_write(0x982C, 0xa000a000);
4283         reg_write(0x9808, 0x8000000);    //disable all agc gain and offset updates to a2
4284         reg_write(0x982C, 0xa000a000);   //power down ADDAC
4285         //# bank 3
4286         if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency <= ZM_CH_G_14)
4287         {
4288             /* 11g */
4289             reg_write (0x98f0,  0x00c00018);//syn_off+RX_off
4290         }
4291         else
4292         {
4293             /* 11a */
4294             reg_write (0x98f0,  0x00400018);//syn_off+RX_off
4295         }
4296
4297         ////#bank 5
4298         //reg_write(0x98b0,  0x000e0013);
4299         //reg_write(0x98e4,  0x00018002);
4300
4301
4302         zfFlushDelayWrite(dev);
4303     }
4304 }
4305
4306 void zfHpSetAggPktNum(zdev_t* dev, u32_t num)
4307 {
4308     struct zsHpPriv* hpPriv;
4309
4310     zmw_get_wlan_dev(dev);
4311     hpPriv = wd->hpPrivate;
4312
4313     num = (num << 16) | (0xa);
4314
4315     hpPriv->aggPktNum = num;
4316
4317     //aggregation number will be update in HAL heart beat
4318     //zfDelayWriteInternalReg(dev, 0x1c3b9c, num);
4319     //zfFlushDelayWrite(dev);
4320 }
4321
4322 void zfHpSetMPDUDensity(zdev_t* dev, u8_t density)
4323 {
4324     u32_t value;
4325
4326     if (density > ZM_MPDU_DENSITY_8US)
4327     {
4328         return;
4329     }
4330
4331     /* Default value in this register */
4332     value = 0x140A00 | density;
4333
4334     zfDelayWriteInternalReg(dev, 0x1c3ba0, value);
4335     zfFlushDelayWrite(dev);
4336     return;
4337 }
4338
4339 void zfHpSetSlotTime(zdev_t* dev, u8_t type)
4340 {
4341     struct zsHpPriv* hpPriv;
4342
4343     zmw_get_wlan_dev(dev);
4344     hpPriv = wd->hpPrivate;
4345
4346     if (type == 0)
4347     {
4348         //normal slot = 20us
4349         hpPriv->slotType = 0;
4350     }
4351     else //if (type == 1)
4352     {
4353         //short slot = 9us
4354         hpPriv->slotType = 1;
4355     }
4356
4357     return;
4358 }
4359
4360 void zfHpSetSlotTimeRegister(zdev_t* dev, u8_t type)
4361 {
4362     if(type == 0)
4363     {
4364         //normal slot = 20us
4365         zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 20<<10);
4366     }
4367     else
4368     {
4369         //short slot = 9us
4370         zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 9<<10);
4371     }
4372 }
4373
4374 void zfHpSetRifs(zdev_t* dev, u8_t ht_enable, u8_t ht2040, u8_t g_mode)
4375 {
4376     zfDelayWriteInternalReg(dev, 0x1c6388, 0x0c000000);
4377
4378     zfDelayWriteInternalReg(dev, 0x1c59ec, 0x0cc80caa);
4379
4380     if (ht_enable)
4381     {
4382         if (ht2040)
4383         {
4384             zfDelayWriteInternalReg(dev, 0x1c5918, 40);
4385         }
4386         else
4387         {
4388             zfDelayWriteInternalReg(dev, 0x1c5918, 20);
4389         }
4390     }
4391
4392     if (g_mode)
4393     {
4394         zfDelayWriteInternalReg(dev, 0x1c5850, 0xec08b4e2);
4395         zfDelayWriteInternalReg(dev, 0x1c585c, 0x313a5d5e);
4396     }
4397     else
4398     {
4399         zfDelayWriteInternalReg(dev, 0x1c5850, 0xede8b4e0);
4400         zfDelayWriteInternalReg(dev, 0x1c585c, 0x3139605e);
4401     }
4402
4403     zfFlushDelayWrite(dev);
4404     return;
4405 }
4406
4407 void zfHpBeginSiteSurvey(zdev_t* dev, u8_t status)
4408 {
4409     struct zsHpPriv* hpPriv;
4410
4411     zmw_get_wlan_dev(dev);
4412     hpPriv=wd->hpPrivate;
4413
4414     if ( status == 1 )
4415     { // Connected
4416         hpPriv->isSiteSurvey = 1;
4417     }
4418     else
4419     { // Not connected
4420         hpPriv->isSiteSurvey = 0;
4421     }
4422
4423     /* reset workaround state to default */
4424 //    if (hpPriv->rxStrongRSSI == 1)
4425     {
4426         hpPriv->rxStrongRSSI = 0;
4427         if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
4428         {
4429             if (hpPriv->hwFrequency <= ZM_CH_G_14)
4430             {
4431                 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49);
4432             }
4433             else
4434             {
4435                 zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900);
4436             }
4437         }
4438         else
4439         {
4440             zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b40);
4441         }
4442         zfFlushDelayWrite(dev);
4443     }
4444 //    if (hpPriv->strongRSSI == 1)
4445     {
4446         hpPriv->strongRSSI = 0;
4447         zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x5<<26));
4448         zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x5<<11) |
4449                                                ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x5<<27)  );
4450         zfFlushDelayWrite(dev);
4451     }
4452 }
4453
4454 void zfHpFinishSiteSurvey(zdev_t* dev, u8_t status)
4455 {
4456     struct zsHpPriv* hpPriv;
4457
4458     zmw_get_wlan_dev(dev);
4459     hpPriv=wd->hpPrivate;
4460
4461     zmw_declare_for_critical_section();
4462
4463     zmw_enter_critical_section(dev);
4464     if ( status == 1 )
4465     {
4466         hpPriv->isSiteSurvey = 2;
4467     }
4468     else
4469     {
4470         hpPriv->isSiteSurvey = 0;
4471     }
4472     zmw_leave_critical_section(dev);
4473 }
4474
4475 u16_t zfFwRetry(zdev_t* dev, u8_t enable)
4476 {
4477     u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
4478     u16_t ret = 0;
4479
4480     cmd[0] = 4 | (0x92 << 8);
4481     cmd[1] = (enable == 1) ? 0x01 : 0x00;
4482
4483     ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
4484     return ret;
4485 }
4486
4487 u16_t zfHpEnableHwRetry(zdev_t* dev)
4488 {
4489     u16_t ret;
4490
4491     ret = zfFwRetry(dev, 0);
4492
4493     zfDelayWriteInternalReg(dev, 0x1c3b28, 0x33333);
4494     zfFlushDelayWrite(dev);
4495
4496     return ret;
4497 }
4498
4499 u16_t zfHpDisableHwRetry(zdev_t* dev)
4500 {
4501     u16_t ret;
4502
4503     ret = zfFwRetry(dev, 1);
4504
4505     zfDelayWriteInternalReg(dev, 0x1c3b28, 0x00000);
4506     zfFlushDelayWrite(dev);
4507
4508     return ret;
4509 }
4510
4511 /* Download SPI Fw */
4512 #define ZM_FIRMWARE_WLAN                0
4513 #define ZM_FIRMWARE_SPI_FLASH           1
4514
4515
4516 u16_t zfHpFirmwareDownload(zdev_t* dev, u8_t fwType)
4517 {
4518     u16_t ret = ZM_SUCCESS;
4519
4520     if (fwType == ZM_FIRMWARE_WLAN)
4521     {
4522         ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
4523                 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR);
4524     }
4525     else if (fwType == ZM_FIRMWARE_SPI_FLASH)
4526     {
4527         ret = zfFirmwareDownload(dev, (u32_t*)zcFwImageSPI,
4528                 (u32_t)zcFwImageSPISize, ZM_FIRMWARE_SPI_ADDR);
4529     }
4530     else
4531     {
4532         zm_debug_msg1("Unknown firmware type = ", fwType);
4533         ret = ZM_ERR_FIRMWARE_WRONG_TYPE;
4534     }
4535
4536     return ret;
4537 }
4538
4539 /* Enable software decryption */
4540 void zfHpSWDecrypt(zdev_t* dev, u8_t enable)
4541 {
4542     u32_t value = 0x70;
4543
4544     /* Bit 4 for enable software decryption */
4545     if (enable == 1)
4546     {
4547         value = 0x78;
4548     }
4549
4550     zfDelayWriteInternalReg(dev, 0x1c3678, value);
4551     zfFlushDelayWrite(dev);
4552 }
4553
4554 /* Enable software encryption */
4555 void zfHpSWEncrypt(zdev_t* dev, u8_t enable)
4556 {
4557     /* Because encryption by software or hardware is judged by driver in Otus,
4558        we don't need to do anything in the HAL layer.
4559      */
4560 }
4561
4562 u32_t zfHpCapability(zdev_t* dev)
4563 {
4564     struct zsHpPriv* hpPriv;
4565
4566     zmw_get_wlan_dev(dev);
4567     hpPriv=wd->hpPrivate;
4568
4569     return hpPriv->halCapability;
4570 }
4571
4572 void zfHpSetRollCallTable(zdev_t* dev)
4573 {
4574     struct zsHpPriv* hpPriv;
4575
4576     zmw_get_wlan_dev(dev);
4577     hpPriv=wd->hpPrivate;
4578
4579     if (hpPriv->camRollCallTable != (u64_t) 0)
4580     {
4581         zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_L, (u32_t)(hpPriv->camRollCallTable & 0xffffffff));
4582         zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_H, (u32_t)((hpPriv->camRollCallTable >> 32) & 0xffffffff));
4583         zfFlushDelayWrite(dev);
4584     }
4585 }
4586
4587 void zfHpSetTTSIFSTime(zdev_t* dev, u8_t sifs_time)
4588 {
4589     u32_t reg_value = 0;
4590
4591     sifs_time &= 0x3f;
4592     reg_value = 0x14400b | (((u32_t)sifs_time)<<24);
4593
4594     zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, reg_value);
4595     zfFlushDelayWrite(dev);
4596 }
4597
4598 /* #3 Enable RIFS function if the RIFS pattern matched ! */
4599 void zfHpEnableRifs(zdev_t* dev, u8_t mode24g, u8_t modeHt, u8_t modeHt2040)
4600 {
4601
4602     /* # Enable Reset TDOMAIN
4603      * $rddata = &$phyreg_read(0x9800+(738<<2));
4604      * $wrdata = $rddata | (0x1 << 26) | (0x1 << 27);
4605      * &$phyreg_write(0x9800+(738<<2), $wrdata);
4606      */
4607     reg_write (0x9800+(738<<2), 0x08000000 | (0x1 << 26) | (0x1 << 27));
4608     //reg_write (0x9800+(738<<2), 0x08000000 | (0x1 << 26));
4609
4610     /* # reg 123: heavy clip factor, xr / RIFS search parameters */
4611     reg_write (0x99ec, 0x0cc80caa);
4612
4613     /* # Reduce Search Start Delay for RIFS    */
4614     if (modeHt == 1) /* ($HT_ENABLE == 1) */
4615     {
4616         if (modeHt2040 == 0x1) /* ($DYNAMIC_HT2040_EN == 0x1) */
4617         {
4618             reg_write(0x9800+(70<<2), 40);/*40*/
4619         }
4620         else
4621         {
4622             reg_write(0x9800+(70<<2), 20);
4623             if(mode24g == 0x0)
4624             {
4625                 /* $rddata = &$phyreg_read(0x9800+(24<<2));#0x9860;0x1c5860
4626                  *$wrdata = ($rddata & 0xffffffc7) | (0x4 << 3);
4627                  * &$phyreg_write(0x9800+(24<<2), $wrdata);
4628                  */
4629                 reg_write(0x9800+(24<<2), (0x0004dd10 & 0xffffffc7) | (0x4 << 3));
4630             }
4631         }
4632     }
4633
4634     if (mode24g == 0x1)
4635     {
4636         reg_write(0x9850, 0xece8b4e4);/*org*/
4637         //reg_write(0x9850, 0xece8b4e2);
4638         reg_write(0x985c, 0x313a5d5e);
4639     }
4640     else
4641     {
4642         reg_write(0x9850, 0xede8b4e4);
4643         reg_write(0x985c, 0x3139605e);
4644     }
4645
4646     zfFlushDelayWrite(dev);
4647
4648     return;
4649 }
4650
4651 /* #4 Disable RIFS function if the RIFS timer is timeout ! */
4652 void zfHpDisableRifs(zdev_t* dev)
4653 {
4654     zmw_get_wlan_dev(dev);
4655
4656     /* Disable RIFS function is to store these HW register initial value while the device plug-in and
4657        re-write to these register if the RIFS function is disabled  */
4658
4659     // reg : 9850
4660     reg_write(0x9850, ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize);
4661
4662     // reg : 985c
4663     reg_write(0x985c, ((struct zsHpPriv*)wd->hpPrivate)->initAGC);
4664
4665     // reg : 9860
4666     reg_write(0x9800+(24<<2), ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl);
4667
4668     // reg : 9918
4669     reg_write(0x9800+(70<<2), ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay);
4670
4671     // reg : 991c
4672     reg_write (0x99ec, ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams);
4673
4674     // reg : a388
4675     reg_write (0x9800+(738<<2), ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl);
4676
4677     zfFlushDelayWrite(dev);
4678
4679     return;
4680 }