5 * This file is provided under a dual BSD/GPLv2 license. When using or
6 * redistributing this file, you may do so under either license.
10 * Copyright(c) 2015 Intel Corporation.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
23 * Copyright(c) 2015 Intel Corporation.
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions
29 * - Redistributions of source code must retain the above copyright
30 * notice, this list of conditions and the following disclaimer.
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32 * notice, this list of conditions and the following disclaimer in
33 * the documentation and/or other materials provided with the
35 * - Neither the name of Intel Corporation nor the names of its
36 * contributors may be used to endorse or promote products derived
37 * from this software without specific prior written permission.
39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
40 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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49 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53 #include <linux/interrupt.h>
54 #include <linux/pci.h>
55 #include <linux/dma-mapping.h>
56 #include <linux/mutex.h>
57 #include <linux/list.h>
58 #include <linux/scatterlist.h>
59 #include <linux/slab.h>
62 #include <linux/completion.h>
63 #include <linux/kref.h>
64 #include <linux/sched.h>
65 #include <linux/cdev.h>
66 #include <linux/delay.h>
67 #include <linux/kthread.h>
69 #include "chip_registers.h"
76 #include "platform_config.h"
78 /* bumped 1 from s/w major version of TrueScale */
79 #define HFI1_CHIP_VERS_MAJ 3U
81 /* don't care about this except printing */
82 #define HFI1_CHIP_VERS_MIN 0U
84 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
85 #define HFI1_OUI 0x001175
86 #define HFI1_OUI_LSB 40
88 #define DROP_PACKET_OFF 0
89 #define DROP_PACKET_ON 1
91 extern unsigned long hfi1_cap_mask;
92 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
93 #define HFI1_CAP_UGET_MASK(mask, cap) \
94 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap)
95 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap))
96 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap))
97 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap))
98 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap))
99 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \
103 * Control context is always 0 and handles the error packets.
104 * It also handles the VL15 and multicast packets.
106 #define HFI1_CTRL_CTXT 0
109 * Driver context will store software counters for each of the events
110 * associated with these status registers
112 #define NUM_CCE_ERR_STATUS_COUNTERS 41
113 #define NUM_RCV_ERR_STATUS_COUNTERS 64
114 #define NUM_MISC_ERR_STATUS_COUNTERS 13
115 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36
116 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4
117 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64
118 #define NUM_SEND_ERR_STATUS_COUNTERS 3
119 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5
120 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24
123 * per driver stats, either not device nor port-specific, or
124 * summed over all of the devices and ports.
125 * They are described by name via ipathfs filesystem, so layout
126 * and number of elements can change without breaking compatibility.
127 * If members are added or deleted hfi1_statnames[] in debugfs.c must
130 struct hfi1_ib_stats {
131 __u64 sps_ints; /* number of interrupts handled */
132 __u64 sps_errints; /* number of error interrupts */
133 __u64 sps_txerrs; /* tx-related packet errors */
134 __u64 sps_rcverrs; /* non-crc rcv packet errors */
135 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
136 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
137 __u64 sps_ctxts; /* number of contexts currently open */
138 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
143 extern struct hfi1_ib_stats hfi1_stats;
144 extern const struct pci_error_handlers hfi1_pci_err_handler;
147 * First-cut criterion for "device is active" is
148 * two thousand dwords combined Tx, Rx traffic per
149 * 5-second interval. SMA packets are 64 dwords,
150 * and occur "a few per second", presumably each way.
152 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000)
155 * Below contains all data related to a single context (formerly called port).
158 #ifdef CONFIG_DEBUG_FS
159 struct hfi1_opcode_stats_perctx;
162 struct ctxt_eager_bufs {
163 ssize_t size; /* total size of eager buffers */
164 u32 count; /* size of buffers array */
165 u32 numbufs; /* number of buffers allocated */
166 u32 alloced; /* number of rcvarray entries used */
167 u32 rcvtid_size; /* size of each eager rcv tid */
168 u32 threshold; /* head update threshold */
169 struct eager_buffer {
180 struct hfi1_ctxtdata {
181 /* shadow the ctxt's RcvCtrl register */
183 /* rcvhdrq base, needs mmap before useful */
185 /* kernel virtual address where hdrqtail is updated */
186 volatile __le64 *rcvhdrtail_kvaddr;
188 * Shared page for kernel to signal user processes that send buffers
189 * need disarming. The process should call HFI1_CMD_DISARM_BUFS
190 * or HFI1_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set.
192 unsigned long *user_event_mask;
193 /* when waiting for rcv or pioavail */
194 wait_queue_head_t wait;
195 /* rcvhdrq size (for freeing) */
197 /* number of rcvhdrq entries */
199 /* size of each of the rcvhdrq entries */
201 /* mmap of hdrq, must fit in 44 bits */
202 dma_addr_t rcvhdrq_phys;
203 dma_addr_t rcvhdrqtailaddr_phys;
204 struct ctxt_eager_bufs egrbufs;
205 /* this receive context's assigned PIO ACK send context */
206 struct send_context *sc;
208 /* dynamic receive available interrupt timeout */
209 u32 rcvavail_timeout;
211 * number of opens (including slave sub-contexts) on this instance
212 * (ignoring forks, dup, etc. for now)
216 * how much space to leave at start of eager TID entries for
217 * protocol use, on each TID
219 /* instead of calculating it */
221 /* non-zero if ctxt is being shared. */
223 /* non-zero if ctxt is being shared. */
228 /* number of RcvArray groups for this context. */
229 u32 rcv_array_groups;
230 /* index of first eager TID entry. */
232 /* number of expected TID entries */
234 /* index of first expected TID entry. */
236 /* cursor into the exp group sets */
238 /* number of exp TID groups assigned to the ctxt */
240 /* size of exp TID group fields in tidusemap */
242 /* exp TID group usage bitfield array */
243 unsigned long *tidusemap;
244 /* pinned pages for exp sends, allocated at open */
245 struct page **tid_pg_list;
246 /* dma handles for exp tid pages */
247 dma_addr_t *physshadow;
248 /* lock protecting all Expected TID data */
250 /* number of pio bufs for this ctxt (all procs, if shared) */
252 /* first pio buffer for this ctxt */
254 /* chip offset of PIO buffers for this ctxt */
256 /* per-context configuration flags */
258 /* per-context event flags for fileops/intr communication */
259 unsigned long event_flags;
260 /* WAIT_RCV that timed out, no interrupt */
262 /* WAIT_PIO that timed out, no interrupt */
264 /* WAIT_RCV already happened, no wait */
266 /* WAIT_PIO already happened, no wait */
268 /* total number of polled urgent packets */
270 /* saved total number of polled urgent packets for poll edge trigger */
272 /* pid of process using this ctxt */
274 pid_t subpid[HFI1_MAX_SHARED_CTXTS];
275 /* same size as task_struct .comm[], command that opened context */
276 char comm[TASK_COMM_LEN];
277 /* so file ops can get at unit */
278 struct hfi1_devdata *dd;
279 /* so functions that need physical port can get it easily */
280 struct hfi1_pportdata *ppd;
281 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
282 void *subctxt_uregbase;
283 /* An array of pages for the eager receive buffers * N */
284 void *subctxt_rcvegrbuf;
285 /* An array of pages for the eager header queue entries * N */
286 void *subctxt_rcvhdr_base;
287 /* The version of the library which opened this ctxt */
289 /* Bitmask of active slaves */
291 /* Type of packets or conditions we want to poll for */
293 /* receive packet sequence counter */
296 /* ctxt rcvhdrq head offset */
299 /* QPs waiting for context processing */
300 struct list_head qp_wait_list;
301 /* interrupt handling */
302 u64 imask; /* clear interrupt mask */
303 int ireg; /* clear interrupt register */
304 unsigned numa_id; /* numa node of this context */
305 /* verbs stats per CTX */
306 struct hfi1_opcode_stats_perctx *opstats;
308 * This is the kernel thread that will keep making
309 * progress on the user sdma requests behind the scenes.
310 * There is one per context (shared contexts use the master's).
312 struct task_struct *progress;
313 struct list_head sdma_queues;
314 spinlock_t sdma_qlock;
317 * The interrupt handler for a particular receive context can vary
318 * throughout it's lifetime. This is not a lock protected data member so
319 * it must be updated atomically and the prev and new value must always
320 * be valid. Worst case is we process an extra interrupt and up to 64
321 * packets with the wrong interrupt handler.
323 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded);
327 * Represents a single packet at a high level. Put commonly computed things in
328 * here so we do not have to keep doing them over and over. The rule of thumb is
329 * if something is used one time to derive some value, store that something in
330 * here. If it is used multiple times, then store the result of that derivation
336 struct hfi1_ctxtdata *rcd;
339 struct hfi1_other_headers *ohdr;
354 static inline bool has_sc4_bit(struct hfi1_packet *p)
356 return !!rhf_dc_info(p->rhf);
360 * Private data for snoop/capture support.
362 struct hfi1_snoop_data {
365 struct device *class_dev;
366 spinlock_t snoop_lock;
367 struct list_head queue;
368 wait_queue_head_t waitq;
370 int (*filter_callback)(void *hdr, void *data, void *value);
371 u64 dcc_cfg; /* saved value of DCC Cfg register */
374 /* snoop mode_flag values */
375 #define HFI1_PORT_SNOOP_MODE 1U
376 #define HFI1_PORT_CAPTURE_MODE 2U
378 struct hfi1_sge_state;
381 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
382 * Mostly for MADs that set or query link parameters, also ipath
385 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
386 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */
387 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */
388 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */
389 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
390 #define HFI1_IB_CFG_SPD 5 /* current Link spd */
391 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
392 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
393 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
394 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
395 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */
396 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
397 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
398 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
399 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
400 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
401 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */
402 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */
403 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19
404 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
405 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */
408 * HFI or Host Link States
410 * These describe the states the driver thinks the logical and physical
411 * states are in. Used as an argument to set_link_state(). Implemented
412 * as bits for easy multi-state checking. The actual state can only be
415 #define __HLS_UP_INIT_BP 0
416 #define __HLS_UP_ARMED_BP 1
417 #define __HLS_UP_ACTIVE_BP 2
418 #define __HLS_DN_DOWNDEF_BP 3 /* link down default */
419 #define __HLS_DN_POLL_BP 4
420 #define __HLS_DN_DISABLE_BP 5
421 #define __HLS_DN_OFFLINE_BP 6
422 #define __HLS_VERIFY_CAP_BP 7
423 #define __HLS_GOING_UP_BP 8
424 #define __HLS_GOING_OFFLINE_BP 9
425 #define __HLS_LINK_COOLDOWN_BP 10
427 #define HLS_UP_INIT (1 << __HLS_UP_INIT_BP)
428 #define HLS_UP_ARMED (1 << __HLS_UP_ARMED_BP)
429 #define HLS_UP_ACTIVE (1 << __HLS_UP_ACTIVE_BP)
430 #define HLS_DN_DOWNDEF (1 << __HLS_DN_DOWNDEF_BP) /* link down default */
431 #define HLS_DN_POLL (1 << __HLS_DN_POLL_BP)
432 #define HLS_DN_DISABLE (1 << __HLS_DN_DISABLE_BP)
433 #define HLS_DN_OFFLINE (1 << __HLS_DN_OFFLINE_BP)
434 #define HLS_VERIFY_CAP (1 << __HLS_VERIFY_CAP_BP)
435 #define HLS_GOING_UP (1 << __HLS_GOING_UP_BP)
436 #define HLS_GOING_OFFLINE (1 << __HLS_GOING_OFFLINE_BP)
437 #define HLS_LINK_COOLDOWN (1 << __HLS_LINK_COOLDOWN_BP)
439 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
441 /* use this MTU size if none other is given */
442 #define HFI1_DEFAULT_ACTIVE_MTU 8192
443 /* use this MTU size as the default maximum */
444 #define HFI1_DEFAULT_MAX_MTU 8192
445 /* default partition key */
446 #define DEFAULT_PKEY 0xffff
449 * Possible fabric manager config parameters for fm_{get,set}_table()
451 #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */
452 #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */
453 #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */
454 #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */
455 #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */
456 #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */
459 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
460 * these are bits so they can be combined, e.g.
461 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB
463 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01
464 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02
465 #define HFI1_RCVCTRL_CTXT_ENB 0x04
466 #define HFI1_RCVCTRL_CTXT_DIS 0x08
467 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10
468 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20
469 #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
470 #define HFI1_RCVCTRL_PKEY_DIS 0x80
471 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400
472 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800
473 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000
474 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000
475 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000
476 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000
477 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000
478 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000
480 /* partition enforcement flags */
481 #define HFI1_PART_ENFORCE_IN 0x1
482 #define HFI1_PART_ENFORCE_OUT 0x2
484 /* how often we check for synthetic counter wrap around */
485 #define SYNTH_CNT_TIME 2
488 #define CNTR_NORMAL 0x0 /* Normal counters, just read register */
489 #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */
490 #define CNTR_DISABLED 0x2 /* Disable this counter */
491 #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */
492 #define CNTR_VL 0x8 /* Per VL counter */
493 #define CNTR_INVALID_VL -1 /* Specifies invalid VL */
494 #define CNTR_MODE_W 0x0
495 #define CNTR_MODE_R 0x1
497 /* VLs Supported/Operational */
498 #define HFI1_MIN_VLS_SUPPORTED 1
499 #define HFI1_MAX_VLS_SUPPORTED 8
501 static inline void incr_cntr64(u64 *cntr)
503 if (*cntr < (u64)-1LL)
507 static inline void incr_cntr32(u32 *cntr)
509 if (*cntr < (u32)-1LL)
513 #define MAX_NAME_SIZE 64
514 struct hfi1_msix_entry {
515 struct msix_entry msix;
517 char name[MAX_NAME_SIZE];
521 /* per-SL CCA information */
523 struct hrtimer hrtimer;
524 struct hfi1_pportdata *ppd; /* read-only */
525 int sl; /* read-only */
526 u16 ccti; /* read/write - current value of CCTI */
529 struct link_down_reason {
531 * SMA-facing value. Should be set from .latest when
532 * HLS_UP_* -> HLS_DN_* transition actually occurs.
544 struct vl_arb_cache {
546 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE];
550 * The structure below encapsulates data relevant to a physical IB Port.
551 * Current chips support only one such port, but the separation
552 * clarifies things a bit. Note that to conform to IB conventions,
553 * port-numbers are one-based. The first or only port is port1.
555 struct hfi1_pportdata {
556 struct hfi1_ibport ibport_data;
558 struct hfi1_devdata *dd;
559 struct kobject pport_cc_kobj;
560 struct kobject sc2vl_kobj;
561 struct kobject sl2sc_kobj;
562 struct kobject vl2mtu_kobj;
565 struct qsfp_data qsfp_info;
567 /* GUID for this interface, in host order */
569 /* GUID for peer interface, in host order */
572 /* up or down physical link state */
576 * this address is mapped read-only into user processes so they can
577 * get status cheaply, whenever they want. One qword of status per port
581 /* SendDMA related entries */
583 struct workqueue_struct *hfi1_wq;
585 /* move out of interrupt context */
586 struct work_struct link_vc_work;
587 struct work_struct link_up_work;
588 struct work_struct link_down_work;
589 struct work_struct sma_message_work;
590 struct work_struct freeze_work;
591 struct work_struct link_downgrade_work;
592 struct work_struct link_bounce_work;
593 /* host link state variables */
594 struct mutex hls_lock;
597 spinlock_t sdma_alllock ____cacheline_aligned_in_smp;
599 u32 lstate; /* logical link state */
601 /* these are the "32 bit" regs */
603 u32 ibmtu; /* The MTU programmed for this unit */
605 * Current max size IB packet (in bytes) including IB headers, that
606 * we can send. Changes when ibmtu changes.
609 u32 current_egress_rate; /* units [10^6 bits/sec] */
610 /* LID programmed for this instance */
612 /* list of pkeys programmed; 0 if not set */
613 u16 pkeys[MAX_PKEY_VALUES];
614 u16 link_width_supported;
615 u16 link_width_downgrade_supported;
616 u16 link_speed_supported;
617 u16 link_width_enabled;
618 u16 link_width_downgrade_enabled;
619 u16 link_speed_enabled;
620 u16 link_width_active;
621 u16 link_width_downgrade_tx_active;
622 u16 link_width_downgrade_rx_active;
623 u16 link_speed_active;
626 /* LID mask control */
628 /* Rx Polarity inversion (compensate for ~tx on partner) */
631 u8 hw_pidx; /* physical port index */
632 u8 port; /* IB port number and index into dd->pports - 1 */
633 /* type of neighbor node */
636 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */
637 u8 neighbor_port_number;
638 u8 is_sm_config_started;
639 u8 offline_disabled_reason;
640 u8 is_active_optimize_enabled;
641 u8 driver_link_ready; /* driver ready for active link */
642 u8 link_enabled; /* link enabled? */
644 u8 local_tx_rate; /* rate given to 8051 firmware */
646 /* placeholders for IB MAD packet settings */
647 u8 overrun_threshold;
648 u8 phy_error_threshold;
650 /* used to override LED behavior */
651 u8 led_override; /* Substituted for normal value, if non-zero */
652 u16 led_override_timeoff; /* delta to next timer event */
653 u8 led_override_vals[2]; /* Alternates per blink-frame */
654 u8 led_override_phase; /* Just counts, LSB picks from vals[] */
655 atomic_t led_override_timer_active;
656 /* Used to flash LEDs in override mode */
657 struct timer_list led_override_timer;
662 * cca_timer_lock protects access to the per-SL cca_timer
663 * structures (specifically the ccti member).
665 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp;
666 struct cca_timer cca_timer[OPA_MAX_SLS];
668 /* List of congestion control table entries */
669 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX];
671 /* congestion entries, each entry corresponding to a SL */
672 struct opa_congestion_setting_entry_shadow
673 congestion_entries[OPA_MAX_SLS];
676 * cc_state_lock protects (write) access to the per-port
679 spinlock_t cc_state_lock ____cacheline_aligned_in_smp;
681 struct cc_state __rcu *cc_state;
683 /* Total number of congestion control table entries */
686 /* Bit map identifying service level */
687 u32 cc_sl_control_map;
689 /* CA's max number of 64 entry units in the congestion control table */
690 u8 cc_max_table_entries;
692 /* begin congestion log related entries
693 * cc_log_lock protects all congestion log related data */
694 spinlock_t cc_log_lock ____cacheline_aligned_in_smp;
695 u8 threshold_cong_event_map[OPA_MAX_SLS/8];
696 u16 threshold_event_counter;
697 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS];
698 int cc_log_idx; /* index for logging events */
699 int cc_mad_idx; /* index for reporting events */
700 /* end congestion log related entries */
702 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE];
704 /* port relative counter buffer */
706 /* port relative synthetic counter buffer */
708 /* we synthesize port_xmit_discards from several egress errors */
709 u64 port_xmit_discards;
710 u64 port_xmit_constraint_errors;
711 u64 port_rcv_constraint_errors;
712 /* count of 'link_err' interrupts from DC */
714 /* number of times link retrained successfully */
716 /* number of times a link unknown frame was reported */
717 u64 unknown_frame_count;
718 /* port_ltp_crc_mode is returned in 'portinfo' MADs */
719 u16 port_ltp_crc_mode;
720 /* port_crc_mode_enabled is the crc we support */
721 u8 port_crc_mode_enabled;
722 /* mgmt_allowed is also returned in 'portinfo' MADs */
724 u8 part_enforce; /* partition enforcement flags */
725 struct link_down_reason local_link_down_reason;
726 struct link_down_reason neigh_link_down_reason;
727 /* Value to be sent to link peer on LinkDown .*/
728 u8 remote_link_down_reason;
729 /* Error events that will cause a port bounce. */
730 u32 port_error_action;
733 typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet);
735 typedef void (*opcode_handler)(struct hfi1_packet *packet);
737 /* return values for the RHF receive functions */
738 #define RHF_RCV_CONTINUE 0 /* keep going */
739 #define RHF_RCV_DONE 1 /* stop, this packet processed */
740 #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */
742 struct rcv_array_data {
750 struct send_context *sc;
753 /* 16 to directly index */
754 #define PER_VL_SEND_CONTEXTS 16
756 struct err_info_rcvport {
762 struct err_info_constraint {
769 unsigned int curr; /* current temperature */
770 unsigned int lo_lim; /* low temperature limit */
771 unsigned int hi_lim; /* high temperature limit */
772 unsigned int crit_lim; /* critical temperature limit */
773 u8 triggers; /* temperature triggers */
776 /* device data struct now contains only "general per-device" info.
777 * fields related to a physical IB port are in a hfi1_pportdata struct.
782 #define BOARD_VERS_MAX 96 /* how long the version string can be */
783 #define SERIAL_MAX 16 /* length of the serial number */
785 struct hfi1_devdata {
786 struct hfi1_ibdev verbs_dev; /* must be first */
787 struct list_head list;
788 /* pointers to related structs for this device */
789 /* pci access data structure */
790 struct pci_dev *pcidev;
791 struct cdev user_cdev;
792 struct cdev diag_cdev;
794 struct device *user_device;
795 struct device *diag_device;
796 struct device *ui_device;
798 /* mem-mapped pointer to base of chip regs */
799 u8 __iomem *kregbase;
800 /* end of mem-mapped chip space excluding sendbuf and user regs */
802 /* physical address of chip for io_remap, etc. */
803 resource_size_t physaddr;
804 /* receive context data */
805 struct hfi1_ctxtdata **rcd;
806 /* send context data */
807 struct send_context_info *send_contexts;
808 /* map hardware send contexts to software index */
810 /* spinlock for allocating and releasing send context resources */
812 /* Per VL data. Enough for all VLs but not all elements are set/used. */
813 struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
814 /* seqlock for sc2vl */
815 seqlock_t sc2vl_lock;
817 /* Send Context initialization lock. */
818 spinlock_t sc_init_lock;
820 /* fields common to all SDMA engines */
822 /* default flags to last descriptor */
824 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */
825 dma_addr_t sdma_heads_phys;
826 void *sdma_pad_dma; /* DMA'ed by chip */
827 dma_addr_t sdma_pad_phys;
828 /* for deallocation */
829 size_t sdma_heads_size;
830 /* number from the chip */
831 u32 chip_sdma_engines;
834 /* lock for sdma_map */
835 spinlock_t sde_map_lock;
836 /* array of engines sized by num_sdma */
837 struct sdma_engine *per_sdma;
838 /* array of vl maps */
839 struct sdma_vl_map __rcu *sdma_map;
840 /* SPC freeze waitqueue and variable */
841 wait_queue_head_t sdma_unfreeze_wq;
842 atomic_t sdma_unfreeze_count;
845 /* hfi1_pportdata, points to array of (physical) port-specific
846 * data structs, indexed by pidx (0..n-1)
848 struct hfi1_pportdata *pport;
850 /* mem-mapped pointer to base of PIO buffers */
851 void __iomem *piobase;
853 * write-combining mem-mapped pointer to base of RcvArray
856 void __iomem *rcvarray_wc;
858 * credit return base - a per-NUMA range of DMA address that
859 * the chip will use to update the per-context free counter
861 struct credit_return_base *cr_base;
863 /* send context numbers and sizes for each type */
864 struct sc_config_sizes sc_sizes[SC_MAX];
866 u32 lcb_access_count; /* count of LCB users */
868 char *boardname; /* human readable board info */
870 /* device (not port) flags, basically device capabilities */
876 /* percpu int_counter */
877 u64 __percpu *int_counter;
878 u64 __percpu *rcv_limit;
880 /* number of receive contexts in use by the driver */
881 u32 num_rcv_contexts;
882 /* number of pio send contexts in use by the driver */
883 u32 num_send_contexts;
885 * number of ctxts available for PSM open
888 /* base receive interrupt timeout, in CSR units */
889 u32 rcv_intr_timeout_csr;
891 u64 __iomem *egrtidbase;
892 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */
893 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */
894 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */
895 spinlock_t uctxt_lock; /* rcd and user context changes */
896 /* exclusive access to 8051 */
897 spinlock_t dc8051_lock;
898 /* exclusive access to 8051 memory */
899 spinlock_t dc8051_memlock;
900 int dc8051_timed_out; /* remember if the 8051 timed out */
902 * A page that will hold event notification bitmaps for all
903 * contexts. This page will be mapped into all processes.
905 unsigned long *events;
907 * per unit status, see also portdata statusp
908 * mapped read-only into user processes so they can get unit and
909 * IB link status cheaply
911 struct hfi1_status *status;
912 u32 freezelen; /* max length of freezemsg */
914 /* revision register shadow */
916 /* Base GUID for device (network order) */
919 /* these are the "32 bit" regs */
921 /* value we put in kr_rcvhdrsize */
923 /* number of receive contexts the chip supports */
924 u32 chip_rcv_contexts;
925 /* number of receive array entries */
926 u32 chip_rcv_array_count;
927 /* number of PIO send contexts the chip supports */
928 u32 chip_send_contexts;
929 /* number of bytes in the PIO memory buffer */
930 u32 chip_pio_mem_size;
931 /* number of bytes in the SDMA memory buffer */
932 u32 chip_sdma_mem_size;
934 /* size of each rcvegrbuffer */
937 u16 rcvegrbufsize_shift;
938 /* both sides of the PCIe link are gen3 capable */
939 u8 link_gen3_capable;
940 /* localbus width (1, 2,4,8,16,32) from config space */
942 /* localbus speed in MHz */
944 int unit; /* unit # of this chip */
945 int node; /* home node of this chip */
947 /* save these PCI fields to restore after a reset */
960 * ASCII serial number, from flash, large enough for original
961 * all digit strings, and longer serial number format
963 u8 serial[SERIAL_MAX];
964 /* human readable board version */
965 u8 boardversion[BOARD_VERS_MAX];
966 u8 lbus_info[32]; /* human readable localbus info */
967 /* chip major rev, from CceRevision */
969 /* chip minor rev, from CceRevision */
973 /* implementation code */
975 /* default link down value (poll/sleep) */
977 /* vAU of this device */
979 /* vCU of this device */
981 /* link credits of this device */
983 /* initial vl15 credits to use */
986 /* Misc small ints */
987 /* Number of physical ports available */
989 /* Lowest context number which can be used by user processes */
995 u16 rhf_offset; /* offset of RHF within receive header entry */
996 u16 irev; /* implementation revision */
997 u16 dc8051_ver; /* 8051 firmware version */
999 struct platform_config_cache pcfg_cache;
1000 /* control high-level access to qsfp */
1001 struct mutex qsfp_i2c_mutex;
1003 struct diag_client *diag_client;
1004 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */
1006 u8 psxmitwait_supported;
1007 /* cycle length of PS* counters in HW (in picoseconds) */
1008 u16 psxmitwait_check_rate;
1009 /* high volume overflow errors deferred to tasklet */
1010 struct tasklet_struct error_tasklet;
1011 /* per device cq worker */
1012 struct kthread_worker *worker;
1014 /* MSI-X information */
1015 struct hfi1_msix_entry *msix_entries;
1016 u32 num_msix_entries;
1018 /* INTx information */
1019 u32 requested_intx_irq; /* did we request one? */
1020 char intx_name[MAX_NAME_SIZE]; /* INTx name */
1022 /* general interrupt: mask of handled interrupts */
1023 u64 gi_mask[CCE_NUM_INT_CSRS];
1025 struct rcv_array_data rcv_entries;
1028 * 64 bit synthetic counters
1030 struct timer_list synth_stats_timer;
1036 size_t cntrnameslen;
1042 * remembered values for synthetic counters
1051 char *portcntrnames;
1052 size_t portcntrnameslen;
1054 struct hfi1_snoop_data hfi1_snoop;
1056 struct err_info_rcvport err_info_rcvport;
1057 struct err_info_constraint err_info_rcv_constraint;
1058 struct err_info_constraint err_info_xmit_constraint;
1059 u8 err_info_uncorrectable;
1060 u8 err_info_fmconfig;
1062 atomic_t drop_packet;
1066 * Software counters for the status bits defined by the
1067 * associated error status registers
1069 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS];
1070 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS];
1071 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS];
1072 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS];
1073 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS];
1074 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS];
1075 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS];
1077 /* Software counter that spans all contexts */
1078 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS];
1079 /* Software counter that spans all DMA engines */
1080 u64 sw_send_dma_eng_err_status_cnt[
1081 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS];
1082 /* Software counter that aggregates all cce_err_status errors */
1083 u64 sw_cce_err_status_aggregate;
1085 /* receive interrupt functions */
1086 rhf_rcv_function_ptr *rhf_rcv_function_map;
1087 rhf_rcv_function_ptr normal_rhf_rcv_functions[8];
1090 * Handlers for outgoing data so that snoop/capture does not
1091 * have to have its hooks in the send path
1093 int (*process_pio_send)(struct hfi1_qp *qp, struct hfi1_pkt_state *ps,
1095 int (*process_dma_send)(struct hfi1_qp *qp, struct hfi1_pkt_state *ps,
1097 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1098 u64 pbc, const void *from, size_t count);
1100 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */
1104 /* Timer and counter used to detect RcvBufOvflCnt changes */
1105 struct timer_list rcverr_timer;
1108 int assigned_node_id;
1109 wait_queue_head_t event_queue;
1111 /* Save the enabled LCB error bits */
1115 /* receive context tail dummy address */
1116 __le64 *rcvhdrtail_dummy_kvaddr;
1117 dma_addr_t rcvhdrtail_dummy_physaddr;
1120 /* 8051 firmware version helper */
1121 #define dc8051_ver(a, b) ((a) << 8 | (b))
1123 /* f_put_tid types */
1124 #define PT_EXPECTED 0
1126 #define PT_INVALID 2
1128 /* Private data for file operations */
1129 struct hfi1_filedata {
1130 struct hfi1_ctxtdata *uctxt;
1132 struct hfi1_user_sdma_comp_q *cq;
1133 struct hfi1_user_sdma_pkt_q *pq;
1134 /* for cpu affinity; -1 if none */
1138 extern struct list_head hfi1_dev_list;
1139 extern spinlock_t hfi1_devs_lock;
1140 struct hfi1_devdata *hfi1_lookup(int unit);
1141 extern u32 hfi1_cpulist_count;
1142 extern unsigned long *hfi1_cpulist;
1144 extern unsigned int snoop_drop_send;
1145 extern unsigned int snoop_force_capture;
1146 int hfi1_init(struct hfi1_devdata *, int);
1147 int hfi1_count_units(int *npresentp, int *nupp);
1148 int hfi1_count_active_units(void);
1150 int hfi1_diag_add(struct hfi1_devdata *);
1151 void hfi1_diag_remove(struct hfi1_devdata *);
1152 void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup);
1154 void handle_user_interrupt(struct hfi1_ctxtdata *rcd);
1156 int hfi1_create_rcvhdrq(struct hfi1_devdata *, struct hfi1_ctxtdata *);
1157 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *);
1158 int hfi1_create_ctxts(struct hfi1_devdata *dd);
1159 struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *, u32);
1160 void hfi1_init_pportdata(struct pci_dev *, struct hfi1_pportdata *,
1161 struct hfi1_devdata *, u8, u8);
1162 void hfi1_free_ctxtdata(struct hfi1_devdata *, struct hfi1_ctxtdata *);
1164 int handle_receive_interrupt(struct hfi1_ctxtdata *, int);
1165 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *, int);
1166 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *, int);
1168 /* receive packet handler dispositions */
1169 #define RCV_PKT_OK 0x0 /* keep going */
1170 #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */
1171 #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */
1173 /* calculate the current RHF address */
1174 static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd)
1176 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->dd->rhf_offset;
1179 int hfi1_reset_device(int);
1181 /* return the driver's idea of the logical OPA port state */
1182 static inline u32 driver_lstate(struct hfi1_pportdata *ppd)
1184 return ppd->lstate; /* use the cached value */
1187 static inline u16 generate_jkey(kuid_t uid)
1189 return from_kuid(current_user_ns(), uid) & 0xffff;
1193 * active_egress_rate
1195 * returns the active egress rate in units of [10^6 bits/sec]
1197 static inline u32 active_egress_rate(struct hfi1_pportdata *ppd)
1199 u16 link_speed = ppd->link_speed_active;
1200 u16 link_width = ppd->link_width_active;
1203 if (link_speed == OPA_LINK_SPEED_25G)
1204 egress_rate = 25000;
1205 else /* assume OPA_LINK_SPEED_12_5G */
1206 egress_rate = 12500;
1208 switch (link_width) {
1209 case OPA_LINK_WIDTH_4X:
1212 case OPA_LINK_WIDTH_3X:
1215 case OPA_LINK_WIDTH_2X:
1219 /* assume IB_WIDTH_1X */
1229 * Returns the number of 'fabric clock cycles' to egress a packet
1230 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock
1231 * rate is (approximately) 805 MHz, the units of the returned value
1234 static inline u32 egress_cycles(u32 len, u32 rate)
1241 * (length) [bits] / (rate) [bits/sec]
1242 * ---------------------------------------------------
1243 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec]
1246 cycles = len * 8; /* bits */
1253 void set_link_ipg(struct hfi1_pportdata *ppd);
1254 void process_becn(struct hfi1_pportdata *ppd, u8 sl, u16 rlid, u32 lqpn,
1255 u32 rqpn, u8 svc_type);
1256 void return_cnp(struct hfi1_ibport *ibp, struct hfi1_qp *qp, u32 remote_qpn,
1257 u32 pkey, u32 slid, u32 dlid, u8 sc5,
1258 const struct ib_grh *old_grh);
1260 #define PACKET_EGRESS_TIMEOUT 350
1261 static inline void pause_for_credit_return(struct hfi1_devdata *dd)
1263 /* Pause at least 1us, to ensure chip returns all credits */
1264 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000;
1266 udelay(usec ? usec : 1);
1270 * sc_to_vlt() reverse lookup sc to vl
1274 static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5)
1279 if (sc5 >= OPA_MAX_SCS)
1283 seq = read_seqbegin(&dd->sc2vl_lock);
1284 rval = *(((u8 *)dd->sc2vl) + sc5);
1285 } while (read_seqretry(&dd->sc2vl_lock, seq));
1290 #define PKEY_MEMBER_MASK 0x8000
1291 #define PKEY_LOW_15_MASK 0x7fff
1294 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1295 * being an entry from the ingress partition key table), return 0
1296 * otherwise. Use the matching criteria for ingress partition keys
1297 * specified in the OPAv1 spec., section 9.10.14.
1299 static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent)
1301 u16 mkey = pkey & PKEY_LOW_15_MASK;
1302 u16 ment = ent & PKEY_LOW_15_MASK;
1306 * If pkey[15] is clear (limited partition member),
1307 * is bit 15 in the corresponding table element
1308 * clear (limited member)?
1310 if (!(pkey & PKEY_MEMBER_MASK))
1311 return !!(ent & PKEY_MEMBER_MASK);
1318 * ingress_pkey_table_search - search the entire pkey table for
1319 * an entry which matches 'pkey'. return 0 if a match is found,
1322 static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey)
1326 for (i = 0; i < MAX_PKEY_VALUES; i++) {
1327 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1334 * ingress_pkey_table_fail - record a failure of ingress pkey validation,
1335 * i.e., increment port_rcv_constraint_errors for the port, and record
1336 * the 'error info' for this failure.
1338 static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey,
1341 struct hfi1_devdata *dd = ppd->dd;
1343 incr_cntr64(&ppd->port_rcv_constraint_errors);
1344 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) {
1345 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK;
1346 dd->err_info_rcv_constraint.slid = slid;
1347 dd->err_info_rcv_constraint.pkey = pkey;
1352 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1
1353 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx
1354 * is a hint as to the best place in the partition key table to begin
1355 * searching. This function should not be called on the data path because
1356 * of performance reasons. On datapath pkey check is expected to be done
1357 * by HW and rcv_pkey_check function should be called instead.
1359 static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1360 u8 sc5, u8 idx, u16 slid)
1362 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1365 /* If SC15, pkey[0:14] must be 0x7fff */
1366 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1369 /* Is the pkey = 0x0, or 0x8000? */
1370 if ((pkey & PKEY_LOW_15_MASK) == 0)
1373 /* The most likely matching pkey has index 'idx' */
1374 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx]))
1377 /* no match - try the whole table */
1378 if (!ingress_pkey_table_search(ppd, pkey))
1382 ingress_pkey_table_fail(ppd, pkey, slid);
1387 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1
1388 * otherwise. It only ensures pkey is vlid for QP0. This function
1389 * should be called on the data path instead of ingress_pkey_check
1390 * as on data path, pkey check is done by HW (except for QP0).
1392 static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1395 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1398 /* If SC15, pkey[0:14] must be 0x7fff */
1399 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1404 ingress_pkey_table_fail(ppd, pkey, slid);
1410 /* MTU enumeration, 256-4k match IB */
1412 #define OPA_MTU_256 1
1413 #define OPA_MTU_512 2
1414 #define OPA_MTU_1024 3
1415 #define OPA_MTU_2048 4
1416 #define OPA_MTU_4096 5
1418 u32 lrh_max_header_bytes(struct hfi1_devdata *dd);
1419 int mtu_to_enum(u32 mtu, int default_if_bad);
1420 u16 enum_to_mtu(int);
1421 static inline int valid_ib_mtu(unsigned int mtu)
1423 return mtu == 256 || mtu == 512 ||
1424 mtu == 1024 || mtu == 2048 ||
1427 static inline int valid_opa_max_mtu(unsigned int mtu)
1429 return mtu >= 2048 &&
1430 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240);
1433 int set_mtu(struct hfi1_pportdata *);
1435 int hfi1_set_lid(struct hfi1_pportdata *, u32, u8);
1436 void hfi1_disable_after_error(struct hfi1_devdata *);
1437 int hfi1_set_uevent_bits(struct hfi1_pportdata *, const int);
1438 int hfi1_rcvbuf_validate(u32, u8, u16 *);
1440 int fm_get_table(struct hfi1_pportdata *, int, void *);
1441 int fm_set_table(struct hfi1_pportdata *, int, void *);
1443 void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf);
1444 void reset_link_credits(struct hfi1_devdata *dd);
1445 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);
1447 int snoop_recv_handler(struct hfi1_packet *packet);
1448 int snoop_send_dma_handler(struct hfi1_qp *qp, struct hfi1_pkt_state *ps,
1450 int snoop_send_pio_handler(struct hfi1_qp *qp, struct hfi1_pkt_state *ps,
1452 void snoop_inline_pio_send(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1453 u64 pbc, const void *from, size_t count);
1455 static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd)
1460 static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev)
1462 return container_of(dev, struct hfi1_devdata, verbs_dev);
1465 static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev)
1467 return dd_from_dev(to_idev(ibdev));
1470 static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp)
1472 return container_of(ibp, struct hfi1_pportdata, ibport_data);
1475 static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port)
1477 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1478 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1480 WARN_ON(pidx >= dd->num_pports);
1481 return &dd->pport[pidx].ibport_data;
1485 * Return the indexed PKEY from the port PKEY table.
1487 static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index)
1489 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1492 if (index >= ARRAY_SIZE(ppd->pkeys))
1495 ret = ppd->pkeys[index];
1501 * Readers of cc_state must call get_cc_state() under rcu_read_lock().
1502 * Writers of cc_state must call get_cc_state() under cc_state_lock.
1504 static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd)
1506 return rcu_dereference(ppd->cc_state);
1510 * values for dd->flags (_device_ related flags)
1512 #define HFI1_INITTED 0x1 /* chip and driver up and initted */
1513 #define HFI1_PRESENT 0x2 /* chip accesses can be done */
1514 #define HFI1_FROZEN 0x4 /* chip in SPC freeze */
1515 #define HFI1_HAS_SDMA_TIMEOUT 0x8
1516 #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */
1517 #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */
1518 #define HFI1_DO_INIT_ASIC 0x100 /* This device will init the ASIC */
1520 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1521 #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1)
1524 /* ctxt_flag bit offsets */
1525 /* context has been setup */
1526 #define HFI1_CTXT_SETUP_DONE 1
1527 /* waiting for a packet to arrive */
1528 #define HFI1_CTXT_WAITING_RCV 2
1529 /* master has not finished initializing */
1530 #define HFI1_CTXT_MASTER_UNINIT 4
1531 /* waiting for an urgent packet to arrive */
1532 #define HFI1_CTXT_WAITING_URG 5
1534 /* free up any allocated data at closes */
1535 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *,
1536 const struct pci_device_id *);
1537 void hfi1_free_devdata(struct hfi1_devdata *);
1538 void cc_state_reclaim(struct rcu_head *rcu);
1539 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra);
1542 * Set LED override, only the two LSBs have "public" meaning, but
1543 * any non-zero value substitutes them for the Link and LinkTrain
1546 #define HFI1_LED_PHYS 1 /* Physical (linktraining) GREEN LED */
1547 #define HFI1_LED_LOG 2 /* Logical (link) YELLOW LED */
1548 void hfi1_set_led_override(struct hfi1_pportdata *ppd, unsigned int val);
1550 #define HFI1_CREDIT_RETURN_RATE (100)
1553 * The number of words for the KDETH protocol field. If this is
1554 * larger then the actual field used, then part of the payload
1555 * will be in the header.
1557 * Optimally, we want this sized so that a typical case will
1558 * use full cache lines. The typical local KDETH header would
1569 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS
1571 #define DEFAULT_RCVHDRSIZE 9
1574 * Maximal header byte count:
1585 * We also want to maintain a cache line alignment to assist DMA'ing
1586 * of the header bytes. Round up to a good size.
1588 #define DEFAULT_RCVHDR_ENTSIZE 32
1590 int hfi1_acquire_user_pages(unsigned long, size_t, bool, struct page **);
1591 void hfi1_release_user_pages(struct page **, size_t, bool);
1593 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1595 *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL;
1598 static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1601 * volatile because it's a DMA target from the chip, routine is
1602 * inlined, and don't want register caching or reordering.
1604 return (u32) le64_to_cpu(*rcd->rcvhdrtail_kvaddr);
1611 extern const char ib_hfi1_version[];
1613 int hfi1_device_create(struct hfi1_devdata *);
1614 void hfi1_device_remove(struct hfi1_devdata *);
1616 int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
1617 struct kobject *kobj);
1618 int hfi1_verbs_register_sysfs(struct hfi1_devdata *);
1619 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *);
1620 /* Hook for sysfs read of QSFP */
1621 int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len);
1623 int hfi1_pcie_init(struct pci_dev *, const struct pci_device_id *);
1624 void hfi1_pcie_cleanup(struct pci_dev *);
1625 int hfi1_pcie_ddinit(struct hfi1_devdata *, struct pci_dev *,
1626 const struct pci_device_id *);
1627 void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
1628 void hfi1_pcie_flr(struct hfi1_devdata *);
1629 int pcie_speeds(struct hfi1_devdata *);
1630 void request_msix(struct hfi1_devdata *, u32 *, struct hfi1_msix_entry *);
1631 void hfi1_enable_intx(struct pci_dev *);
1632 void restore_pci_variables(struct hfi1_devdata *dd);
1633 int do_pcie_gen3_transition(struct hfi1_devdata *dd);
1634 int parse_platform_config(struct hfi1_devdata *dd);
1635 int get_platform_config_field(struct hfi1_devdata *dd,
1636 enum platform_config_table_type_encoding table_type,
1637 int table_index, int field_index, u32 *data, u32 len);
1639 dma_addr_t hfi1_map_page(struct pci_dev *, struct page *, unsigned long,
1641 const char *get_unit_name(int unit);
1644 * Flush write combining store buffers (if present) and perform a write
1647 static inline void flush_wc(void)
1649 asm volatile("sfence" : : : "memory");
1652 void handle_eflags(struct hfi1_packet *packet);
1653 int process_receive_ib(struct hfi1_packet *packet);
1654 int process_receive_bypass(struct hfi1_packet *packet);
1655 int process_receive_error(struct hfi1_packet *packet);
1656 int kdeth_process_expected(struct hfi1_packet *packet);
1657 int kdeth_process_eager(struct hfi1_packet *packet);
1658 int process_receive_invalid(struct hfi1_packet *packet);
1660 extern rhf_rcv_function_ptr snoop_rhf_rcv_functions[8];
1662 void update_sge(struct hfi1_sge_state *ss, u32 length);
1664 /* global module parameter variables */
1665 extern unsigned int hfi1_max_mtu;
1666 extern unsigned int hfi1_cu;
1667 extern unsigned int user_credit_return_threshold;
1668 extern int num_user_contexts;
1669 extern unsigned n_krcvqs;
1671 extern int krcvqsset;
1672 extern uint kdeth_qp;
1673 extern uint loopback;
1674 extern uint quick_linkup;
1675 extern uint rcv_intr_timeout;
1676 extern uint rcv_intr_count;
1677 extern uint rcv_intr_dynamic;
1678 extern ushort link_crc_mask;
1680 extern struct mutex hfi1_mutex;
1682 /* Number of seconds before our card status check... */
1683 #define STATUS_TIMEOUT 60
1685 #define DRIVER_NAME "hfi1"
1686 #define HFI1_USER_MINOR_BASE 0
1687 #define HFI1_TRACE_MINOR 127
1688 #define HFI1_DIAGPKT_MINOR 128
1689 #define HFI1_DIAG_MINOR_BASE 129
1690 #define HFI1_SNOOP_CAPTURE_BASE 200
1691 #define HFI1_NMINORS 255
1693 #define PCI_VENDOR_ID_INTEL 0x8086
1694 #define PCI_DEVICE_ID_INTEL0 0x24f0
1695 #define PCI_DEVICE_ID_INTEL1 0x24f1
1697 #define HFI1_PKT_USER_SC_INTEGRITY \
1698 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \
1699 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \
1700 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK)
1702 #define HFI1_PKT_KERNEL_SC_INTEGRITY \
1703 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK)
1705 static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,
1708 u64 base_sc_integrity =
1709 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
1710 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
1711 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
1712 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
1713 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
1714 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK
1715 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
1716 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
1717 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
1718 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK
1719 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
1720 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
1721 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
1722 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
1723 | SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK
1724 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
1725 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;
1727 if (ctxt_type == SC_USER)
1728 base_sc_integrity |= HFI1_PKT_USER_SC_INTEGRITY;
1730 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY;
1733 /* turn off send-side job key checks - A0 erratum */
1734 return base_sc_integrity &
1735 ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
1736 return base_sc_integrity;
1739 static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)
1741 u64 base_sdma_integrity =
1742 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
1743 | SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
1744 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
1745 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
1746 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
1747 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
1748 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
1749 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
1750 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK
1751 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
1752 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
1753 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
1754 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
1755 | SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK
1756 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
1757 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;
1760 /* turn off send-side job key checks - A0 erratum */
1761 return base_sdma_integrity &
1762 ~SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
1763 return base_sdma_integrity;
1767 * hfi1_early_err is used (only!) to print early errors before devdata is
1768 * allocated, or when dd->pcidev may not be valid, and at the tail end of
1769 * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is
1770 * the same as dd_dev_err, but is used when the message really needs
1771 * the IB port# to be definitive as to what's happening..
1773 #define hfi1_early_err(dev, fmt, ...) \
1774 dev_err(dev, fmt, ##__VA_ARGS__)
1776 #define hfi1_early_info(dev, fmt, ...) \
1777 dev_info(dev, fmt, ##__VA_ARGS__)
1779 #define dd_dev_emerg(dd, fmt, ...) \
1780 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \
1781 get_unit_name((dd)->unit), ##__VA_ARGS__)
1782 #define dd_dev_err(dd, fmt, ...) \
1783 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
1784 get_unit_name((dd)->unit), ##__VA_ARGS__)
1785 #define dd_dev_warn(dd, fmt, ...) \
1786 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
1787 get_unit_name((dd)->unit), ##__VA_ARGS__)
1789 #define dd_dev_warn_ratelimited(dd, fmt, ...) \
1790 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
1791 get_unit_name((dd)->unit), ##__VA_ARGS__)
1793 #define dd_dev_info(dd, fmt, ...) \
1794 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \
1795 get_unit_name((dd)->unit), ##__VA_ARGS__)
1797 #define hfi1_dev_porterr(dd, port, fmt, ...) \
1798 dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \
1799 get_unit_name((dd)->unit), (dd)->unit, (port), \
1803 * this is used for formatting hw error messages...
1805 struct hfi1_hwerror_msgs {
1812 void hfi1_format_hwerrors(u64 hwerrs,
1813 const struct hfi1_hwerror_msgs *hwerrmsgs,
1814 size_t nhwerrmsgs, char *msg, size_t lmsg);
1816 #define USER_OPCODE_CHECK_VAL 0xC0
1817 #define USER_OPCODE_CHECK_MASK 0xC0
1818 #define OPCODE_CHECK_VAL_DISABLED 0x0
1819 #define OPCODE_CHECK_MASK_DISABLED 0x0
1821 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd)
1823 struct hfi1_pportdata *ppd;
1826 dd->z_int_counter = get_all_cpu_total(dd->int_counter);
1827 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit);
1829 ppd = (struct hfi1_pportdata *)(dd + 1);
1830 for (i = 0; i < dd->num_pports; i++, ppd++) {
1831 ppd->ibport_data.z_rc_acks =
1832 get_all_cpu_total(ppd->ibport_data.rc_acks);
1833 ppd->ibport_data.z_rc_qacks =
1834 get_all_cpu_total(ppd->ibport_data.rc_qacks);
1838 /* Control LED state */
1839 static inline void setextled(struct hfi1_devdata *dd, u32 on)
1842 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
1844 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
1847 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp);
1849 #endif /* _HFI1_KERNEL_H */