3 * This file is provided under a dual BSD/GPLv2 license. When using or
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8 * Copyright(c) 2015 Intel Corporation.
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51 #include <linux/delay.h>
56 #define SC_CTXT_PACKET_EGRESS_TIMEOUT 350 /* in chip cycles */
58 #define SC(name) SEND_CTXT_##name
60 * Send Context functions
62 static void sc_wait_for_packet_egress(struct send_context *sc, int pause);
65 * Set the CM reset bit and wait for it to clear. Use the provided
66 * sendctrl register. This routine has no locking.
68 void __cm_reset(struct hfi1_devdata *dd, u64 sendctrl)
70 write_csr(dd, SEND_CTRL, sendctrl | SEND_CTRL_CM_RESET_SMASK);
73 sendctrl = read_csr(dd, SEND_CTRL);
74 if ((sendctrl & SEND_CTRL_CM_RESET_SMASK) == 0)
79 /* defined in header release 48 and higher */
80 #ifndef SEND_CTRL_UNSUPPORTED_VL_SHIFT
81 #define SEND_CTRL_UNSUPPORTED_VL_SHIFT 3
82 #define SEND_CTRL_UNSUPPORTED_VL_MASK 0xffull
83 #define SEND_CTRL_UNSUPPORTED_VL_SMASK (SEND_CTRL_UNSUPPORTED_VL_MASK \
84 << SEND_CTRL_UNSUPPORTED_VL_SHIFT)
87 /* global control of PIO send */
88 void pio_send_control(struct hfi1_devdata *dd, int op)
92 int write = 1; /* write sendctrl back */
93 int flush = 0; /* re-read sendctrl to make sure it is flushed */
95 spin_lock_irqsave(&dd->sendctrl_lock, flags);
97 reg = read_csr(dd, SEND_CTRL);
99 case PSC_GLOBAL_ENABLE:
100 reg |= SEND_CTRL_SEND_ENABLE_SMASK;
102 case PSC_DATA_VL_ENABLE:
103 /* Disallow sending on VLs not enabled */
104 mask = (((~0ull)<<num_vls) & SEND_CTRL_UNSUPPORTED_VL_MASK)<<
105 SEND_CTRL_UNSUPPORTED_VL_SHIFT;
106 reg = (reg & ~SEND_CTRL_UNSUPPORTED_VL_SMASK) | mask;
108 case PSC_GLOBAL_DISABLE:
109 reg &= ~SEND_CTRL_SEND_ENABLE_SMASK;
111 case PSC_GLOBAL_VLARB_ENABLE:
112 reg |= SEND_CTRL_VL_ARBITER_ENABLE_SMASK;
114 case PSC_GLOBAL_VLARB_DISABLE:
115 reg &= ~SEND_CTRL_VL_ARBITER_ENABLE_SMASK;
119 write = 0; /* CSR already written (and flushed) */
121 case PSC_DATA_VL_DISABLE:
122 reg |= SEND_CTRL_UNSUPPORTED_VL_SMASK;
126 dd_dev_err(dd, "%s: invalid control %d\n", __func__, op);
131 write_csr(dd, SEND_CTRL, reg);
133 (void) read_csr(dd, SEND_CTRL); /* flush write */
136 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
139 /* number of send context memory pools */
140 #define NUM_SC_POOLS 2
142 /* Send Context Size (SCS) wildcards */
143 #define SCS_POOL_0 -1
144 #define SCS_POOL_1 -2
145 /* Send Context Count (SCC) wildcards */
146 #define SCC_PER_VL -1
147 #define SCC_PER_CPU -2
149 #define SCC_PER_KRCVQ -3
150 #define SCC_ACK_CREDITS 32
152 #define PIO_WAIT_BATCH_SIZE 5
154 /* default send context sizes */
155 static struct sc_config_sizes sc_config_sizes[SC_MAX] = {
156 [SC_KERNEL] = { .size = SCS_POOL_0, /* even divide, pool 0 */
157 .count = SCC_PER_VL },/* one per NUMA */
158 [SC_ACK] = { .size = SCC_ACK_CREDITS,
159 .count = SCC_PER_KRCVQ },
160 [SC_USER] = { .size = SCS_POOL_0, /* even divide, pool 0 */
161 .count = SCC_PER_CPU }, /* one per CPU */
165 /* send context memory pool configuration */
166 struct mem_pool_config {
167 int centipercent; /* % of memory, in 100ths of 1% */
168 int absolute_blocks; /* absolute block count */
171 /* default memory pool configuration: 100% in pool 0 */
172 static struct mem_pool_config sc_mem_pool_config[NUM_SC_POOLS] = {
173 /* centi%, abs blocks */
174 { 10000, -1 }, /* pool 0 */
175 { 0, -1 }, /* pool 1 */
178 /* memory pool information, used when calculating final sizes */
179 struct mem_pool_info {
180 int centipercent; /* 100th of 1% of memory to use, -1 if blocks
182 int count; /* count of contexts in the pool */
183 int blocks; /* block size of the pool */
184 int size; /* context size, in blocks */
188 * Convert a pool wildcard to a valid pool index. The wildcards
189 * start at -1 and increase negatively. Map them as:
194 * Return -1 on non-wildcard input, otherwise convert to a pool number.
196 static int wildcard_to_pool(int wc)
199 return -1; /* non-wildcard */
203 static const char *sc_type_names[SC_MAX] = {
209 static const char *sc_type_name(int index)
211 if (index < 0 || index >= SC_MAX)
213 return sc_type_names[index];
217 * Read the send context memory pool configuration and send context
218 * size configuration. Replace any wildcards and come up with final
219 * counts and sizes for the send context types.
221 int init_sc_pools_and_sizes(struct hfi1_devdata *dd)
223 struct mem_pool_info mem_pool_info[NUM_SC_POOLS] = { { 0 } };
224 int total_blocks = (dd->chip_pio_mem_size / PIO_BLOCK_SIZE) - 1;
225 int total_contexts = 0;
229 int cp_total; /* centipercent total */
230 int ab_total; /* absolute block total */
236 * - copy the centipercents/absolute sizes from the pool config
237 * - sanity check these values
238 * - add up centipercents, then later check for full value
239 * - add up absolute blocks, then later check for over-commit
243 for (i = 0; i < NUM_SC_POOLS; i++) {
244 int cp = sc_mem_pool_config[i].centipercent;
245 int ab = sc_mem_pool_config[i].absolute_blocks;
248 * A negative value is "unused" or "invalid". Both *can*
249 * be valid, but centipercent wins, so check that first
251 if (cp >= 0) { /* centipercent valid */
253 } else if (ab >= 0) { /* absolute blocks valid */
255 } else { /* neither valid */
258 "Send context memory pool %d: both the block count and centipercent are invalid\n",
263 mem_pool_info[i].centipercent = cp;
264 mem_pool_info[i].blocks = ab;
267 /* do not use both % and absolute blocks for different pools */
268 if (cp_total != 0 && ab_total != 0) {
271 "All send context memory pools must be described as either centipercent or blocks, no mixing between pools\n");
275 /* if any percentages are present, they must add up to 100% x 100 */
276 if (cp_total != 0 && cp_total != 10000) {
279 "Send context memory pool centipercent is %d, expecting 10000\n",
284 /* the absolute pool total cannot be more than the mem total */
285 if (ab_total > total_blocks) {
288 "Send context memory pool absolute block count %d is larger than the memory size %d\n",
289 ab_total, total_blocks);
295 * - copy from the context size config
296 * - replace context type wildcard counts with real values
297 * - add up non-memory pool block sizes
298 * - add up memory pool user counts
301 for (i = 0; i < SC_MAX; i++) {
302 int count = sc_config_sizes[i].count;
303 int size = sc_config_sizes[i].size;
307 * Sanity check count: Either a positive value or
308 * one of the expected wildcards is valid. The positive
309 * value is checked later when we compare against total
313 count = dd->n_krcv_queues;
314 } else if (i == SC_KERNEL) {
315 count = num_vls + 1 /* VL15 */;
316 } else if (count == SCC_PER_CPU) {
317 count = dd->num_rcv_contexts - dd->n_krcv_queues;
318 } else if (count < 0) {
321 "%s send context invalid count wildcard %d\n",
322 sc_type_name(i), count);
325 if (total_contexts + count > dd->chip_send_contexts)
326 count = dd->chip_send_contexts - total_contexts;
328 total_contexts += count;
331 * Sanity check pool: The conversion will return a pool
332 * number or -1 if a fixed (non-negative) value. The fixed
333 * value is checked later when we compare against
334 * total memory available.
336 pool = wildcard_to_pool(size);
337 if (pool == -1) { /* non-wildcard */
338 fixed_blocks += size * count;
339 } else if (pool < NUM_SC_POOLS) { /* valid wildcard */
340 mem_pool_info[pool].count += count;
341 } else { /* invalid wildcard */
344 "%s send context invalid pool wildcard %d\n",
345 sc_type_name(i), size);
349 dd->sc_sizes[i].count = count;
350 dd->sc_sizes[i].size = size;
352 if (fixed_blocks > total_blocks) {
355 "Send context fixed block count, %u, larger than total block count %u\n",
356 fixed_blocks, total_blocks);
360 /* step 3: calculate the blocks in the pools, and pool context sizes */
361 pool_blocks = total_blocks - fixed_blocks;
362 if (ab_total > pool_blocks) {
365 "Send context fixed pool sizes, %u, larger than pool block count %u\n",
366 ab_total, pool_blocks);
369 /* subtract off the fixed pool blocks */
370 pool_blocks -= ab_total;
372 for (i = 0; i < NUM_SC_POOLS; i++) {
373 struct mem_pool_info *pi = &mem_pool_info[i];
375 /* % beats absolute blocks */
376 if (pi->centipercent >= 0)
377 pi->blocks = (pool_blocks * pi->centipercent) / 10000;
379 if (pi->blocks == 0 && pi->count != 0) {
382 "Send context memory pool %d has %u contexts, but no blocks\n",
386 if (pi->count == 0) {
387 /* warn about wasted blocks */
391 "Send context memory pool %d has %u blocks, but zero contexts\n",
395 pi->size = pi->blocks / pi->count;
399 /* step 4: fill in the context type sizes from the pool sizes */
401 for (i = 0; i < SC_MAX; i++) {
402 if (dd->sc_sizes[i].size < 0) {
403 unsigned pool = wildcard_to_pool(dd->sc_sizes[i].size);
405 WARN_ON_ONCE(pool >= NUM_SC_POOLS);
406 dd->sc_sizes[i].size = mem_pool_info[pool].size;
408 /* make sure we are not larger than what is allowed by the HW */
409 #define PIO_MAX_BLOCKS 1024
410 if (dd->sc_sizes[i].size > PIO_MAX_BLOCKS)
411 dd->sc_sizes[i].size = PIO_MAX_BLOCKS;
413 /* calculate our total usage */
414 used_blocks += dd->sc_sizes[i].size * dd->sc_sizes[i].count;
416 extra = total_blocks - used_blocks;
418 dd_dev_info(dd, "unused send context blocks: %d\n", extra);
420 return total_contexts;
423 int init_send_contexts(struct hfi1_devdata *dd)
426 int ret, i, j, context;
428 ret = init_credit_return(dd);
432 dd->hw_to_sw = kmalloc_array(TXE_NUM_CONTEXTS, sizeof(u8),
434 dd->send_contexts = kcalloc(dd->num_send_contexts,
435 sizeof(struct send_context_info),
437 if (!dd->send_contexts || !dd->hw_to_sw) {
439 kfree(dd->send_contexts);
440 free_credit_return(dd);
444 /* hardware context map starts with invalid send context indices */
445 for (i = 0; i < TXE_NUM_CONTEXTS; i++)
446 dd->hw_to_sw[i] = INVALID_SCI;
449 * All send contexts have their credit sizes. Allocate credits
450 * for each context one after another from the global space.
454 for (i = 0; i < SC_MAX; i++) {
455 struct sc_config_sizes *scs = &dd->sc_sizes[i];
457 for (j = 0; j < scs->count; j++) {
458 struct send_context_info *sci =
459 &dd->send_contexts[context];
462 sci->credits = scs->size;
473 * Allocate a software index and hardware context of the given type.
475 * Must be called with dd->sc_lock held.
477 static int sc_hw_alloc(struct hfi1_devdata *dd, int type, u32 *sw_index,
480 struct send_context_info *sci;
484 for (index = 0, sci = &dd->send_contexts[0];
485 index < dd->num_send_contexts; index++, sci++) {
486 if (sci->type == type && sci->allocated == 0) {
488 /* use a 1:1 mapping, but make them non-equal */
489 context = dd->chip_send_contexts - index - 1;
490 dd->hw_to_sw[context] = index;
492 *hw_context = context;
493 return 0; /* success */
496 dd_dev_err(dd, "Unable to locate a free type %d send context\n", type);
501 * Free the send context given by its software index.
503 * Must be called with dd->sc_lock held.
505 static void sc_hw_free(struct hfi1_devdata *dd, u32 sw_index, u32 hw_context)
507 struct send_context_info *sci;
509 sci = &dd->send_contexts[sw_index];
510 if (!sci->allocated) {
511 dd_dev_err(dd, "%s: sw_index %u not allocated? hw_context %u\n",
512 __func__, sw_index, hw_context);
515 dd->hw_to_sw[hw_context] = INVALID_SCI;
518 /* return the base context of a context in a group */
519 static inline u32 group_context(u32 context, u32 group)
521 return (context >> group) << group;
524 /* return the size of a group */
525 static inline u32 group_size(u32 group)
531 * Obtain the credit return addresses, kernel virtual and physical, for the
534 * To understand this routine:
535 * o va and pa are arrays of struct credit_return. One for each physical
536 * send context, per NUMA.
537 * o Each send context always looks in its relative location in a struct
538 * credit_return for its credit return.
539 * o Each send context in a group must have its return address CSR programmed
540 * with the same value. Use the address of the first send context in the
543 static void cr_group_addresses(struct send_context *sc, dma_addr_t *pa)
545 u32 gc = group_context(sc->hw_context, sc->group);
546 u32 index = sc->hw_context & 0x7;
548 sc->hw_free = &sc->dd->cr_base[sc->node].va[gc].cr[index];
549 *pa = (unsigned long)
550 &((struct credit_return *)sc->dd->cr_base[sc->node].pa)[gc];
554 * Work queue function triggered in error interrupt routine for
557 static void sc_halted(struct work_struct *work)
559 struct send_context *sc;
561 sc = container_of(work, struct send_context, halt_work);
566 * Calculate PIO block threshold for this send context using the given MTU.
567 * Trigger a return when one MTU plus optional header of credits remain.
569 * Parameter mtu is in bytes.
570 * Parameter hdrqentsize is in DWORDs.
572 * Return value is what to write into the CSR: trigger return when
573 * unreturned credits pass this count.
575 u32 sc_mtu_to_threshold(struct send_context *sc, u32 mtu, u32 hdrqentsize)
580 /* add in the header size, then divide by the PIO block size */
581 mtu += hdrqentsize << 2;
582 release_credits = DIV_ROUND_UP(mtu, PIO_BLOCK_SIZE);
584 /* check against this context's credits */
585 if (sc->credits <= release_credits)
588 threshold = sc->credits - release_credits;
594 * Calculate credit threshold in terms of percent of the allocated credits.
595 * Trigger when unreturned credits equal or exceed the percentage of the whole.
597 * Return value is what to write into the CSR: trigger return when
598 * unreturned credits pass this count.
600 static u32 sc_percent_to_threshold(struct send_context *sc, u32 percent)
602 return (sc->credits * percent) / 100;
606 * Set the credit return threshold.
608 void sc_set_cr_threshold(struct send_context *sc, u32 new_threshold)
612 int force_return = 0;
614 spin_lock_irqsave(&sc->credit_ctrl_lock, flags);
616 old_threshold = (sc->credit_ctrl >>
617 SC(CREDIT_CTRL_THRESHOLD_SHIFT))
618 & SC(CREDIT_CTRL_THRESHOLD_MASK);
620 if (new_threshold != old_threshold) {
623 & ~SC(CREDIT_CTRL_THRESHOLD_SMASK))
625 & SC(CREDIT_CTRL_THRESHOLD_MASK))
626 << SC(CREDIT_CTRL_THRESHOLD_SHIFT));
627 write_kctxt_csr(sc->dd, sc->hw_context,
628 SC(CREDIT_CTRL), sc->credit_ctrl);
630 /* force a credit return on change to avoid a possible stall */
634 spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
637 sc_return_credits(sc);
643 * Set the CHECK_ENABLE register for the send context 'sc'.
645 void set_pio_integrity(struct send_context *sc)
647 struct hfi1_devdata *dd = sc->dd;
649 u32 hw_context = sc->hw_context;
653 * No integrity checks if HFI1_CAP_NO_INTEGRITY is set, or if
656 if (likely(!HFI1_CAP_IS_KSET(NO_INTEGRITY)) &&
657 dd->hfi1_snoop.mode_flag != HFI1_PORT_SNOOP_MODE)
658 reg = hfi1_pkt_default_send_ctxt_mask(dd, type);
660 write_kctxt_csr(dd, hw_context, SC(CHECK_ENABLE), reg);
663 static u32 get_buffers_allocated(struct send_context *sc)
668 for_each_possible_cpu(cpu)
669 ret += *per_cpu_ptr(sc->buffers_allocated, cpu);
673 static void reset_buffers_allocated(struct send_context *sc)
677 for_each_possible_cpu(cpu)
678 (*per_cpu_ptr(sc->buffers_allocated, cpu)) = 0;
682 * Allocate a NUMA relative send context structure of the given type along
685 struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
686 uint hdrqentsize, int numa)
688 struct send_context_info *sci;
689 struct send_context *sc = NULL;
699 /* do not allocate while frozen */
700 if (dd->flags & HFI1_FROZEN)
703 sc = kzalloc_node(sizeof(struct send_context), GFP_KERNEL, numa);
707 sc->buffers_allocated = alloc_percpu(u32);
708 if (!sc->buffers_allocated) {
711 "Cannot allocate buffers_allocated per cpu counters\n"
716 spin_lock_irqsave(&dd->sc_lock, flags);
717 ret = sc_hw_alloc(dd, type, &sw_index, &hw_context);
719 spin_unlock_irqrestore(&dd->sc_lock, flags);
720 free_percpu(sc->buffers_allocated);
725 sci = &dd->send_contexts[sw_index];
731 spin_lock_init(&sc->alloc_lock);
732 spin_lock_init(&sc->release_lock);
733 spin_lock_init(&sc->credit_ctrl_lock);
734 INIT_LIST_HEAD(&sc->piowait);
735 INIT_WORK(&sc->halt_work, sc_halted);
736 init_waitqueue_head(&sc->halt_wait);
738 /* grouping is always single context for now */
741 sc->sw_index = sw_index;
742 sc->hw_context = hw_context;
743 cr_group_addresses(sc, &pa);
744 sc->credits = sci->credits;
746 /* PIO Send Memory Address details */
747 #define PIO_ADDR_CONTEXT_MASK 0xfful
748 #define PIO_ADDR_CONTEXT_SHIFT 16
749 sc->base_addr = dd->piobase + ((hw_context & PIO_ADDR_CONTEXT_MASK)
750 << PIO_ADDR_CONTEXT_SHIFT);
752 /* set base and credits */
753 reg = ((sci->credits & SC(CTRL_CTXT_DEPTH_MASK))
754 << SC(CTRL_CTXT_DEPTH_SHIFT))
755 | ((sci->base & SC(CTRL_CTXT_BASE_MASK))
756 << SC(CTRL_CTXT_BASE_SHIFT));
757 write_kctxt_csr(dd, hw_context, SC(CTRL), reg);
759 set_pio_integrity(sc);
761 /* unmask all errors */
762 write_kctxt_csr(dd, hw_context, SC(ERR_MASK), (u64)-1);
764 /* set the default partition key */
765 write_kctxt_csr(dd, hw_context, SC(CHECK_PARTITION_KEY),
767 SC(CHECK_PARTITION_KEY_VALUE_MASK))
768 << SC(CHECK_PARTITION_KEY_VALUE_SHIFT));
770 /* per context type checks */
771 if (type == SC_USER) {
772 opval = USER_OPCODE_CHECK_VAL;
773 opmask = USER_OPCODE_CHECK_MASK;
775 opval = OPCODE_CHECK_VAL_DISABLED;
776 opmask = OPCODE_CHECK_MASK_DISABLED;
779 /* set the send context check opcode mask and value */
780 write_kctxt_csr(dd, hw_context, SC(CHECK_OPCODE),
781 ((u64)opmask << SC(CHECK_OPCODE_MASK_SHIFT)) |
782 ((u64)opval << SC(CHECK_OPCODE_VALUE_SHIFT)));
784 /* set up credit return */
785 reg = pa & SC(CREDIT_RETURN_ADDR_ADDRESS_SMASK);
786 write_kctxt_csr(dd, hw_context, SC(CREDIT_RETURN_ADDR), reg);
789 * Calculate the initial credit return threshold.
791 * For Ack contexts, set a threshold for half the credits.
792 * For User contexts use the given percentage. This has been
793 * sanitized on driver start-up.
794 * For Kernel contexts, use the default MTU plus a header.
796 if (type == SC_ACK) {
797 thresh = sc_percent_to_threshold(sc, 50);
798 } else if (type == SC_USER) {
799 thresh = sc_percent_to_threshold(sc,
800 user_credit_return_threshold);
801 } else { /* kernel */
802 thresh = sc_mtu_to_threshold(sc, hfi1_max_mtu, hdrqentsize);
804 reg = thresh << SC(CREDIT_CTRL_THRESHOLD_SHIFT);
805 /* add in early return */
806 if (type == SC_USER && HFI1_CAP_IS_USET(EARLY_CREDIT_RETURN))
807 reg |= SC(CREDIT_CTRL_EARLY_RETURN_SMASK);
808 else if (HFI1_CAP_IS_KSET(EARLY_CREDIT_RETURN)) /* kernel, ack */
809 reg |= SC(CREDIT_CTRL_EARLY_RETURN_SMASK);
811 /* set up write-through credit_ctrl */
812 sc->credit_ctrl = reg;
813 write_kctxt_csr(dd, hw_context, SC(CREDIT_CTRL), reg);
815 /* User send contexts should not allow sending on VL15 */
816 if (type == SC_USER) {
818 write_kctxt_csr(dd, hw_context, SC(CHECK_VL), reg);
821 spin_unlock_irqrestore(&dd->sc_lock, flags);
824 * Allocate shadow ring to track outstanding PIO buffers _after_
825 * unlocking. We don't know the size until the lock is held and
826 * we can't allocate while the lock is held. No one is using
827 * the context yet, so allocate it now.
829 * User contexts do not get a shadow ring.
831 if (type != SC_USER) {
833 * Size the shadow ring 1 larger than the number of credits
834 * so head == tail can mean empty.
836 sc->sr_size = sci->credits + 1;
837 sc->sr = kzalloc_node(sizeof(union pio_shadow_ring) *
838 sc->sr_size, GFP_KERNEL, numa);
846 "Send context %u(%u) %s group %u credits %u credit_ctrl 0x%llx threshold %u\n",
859 /* free a per-NUMA send context structure */
860 void sc_free(struct send_context *sc)
862 struct hfi1_devdata *dd;
870 sc->flags |= SCF_IN_FREE; /* ensure no restarts */
872 if (!list_empty(&sc->piowait))
873 dd_dev_err(dd, "piowait list not empty!\n");
874 sw_index = sc->sw_index;
875 hw_context = sc->hw_context;
876 sc_disable(sc); /* make sure the HW is disabled */
877 flush_work(&sc->halt_work);
879 spin_lock_irqsave(&dd->sc_lock, flags);
880 dd->send_contexts[sw_index].sc = NULL;
882 /* clear/disable all registers set in sc_alloc */
883 write_kctxt_csr(dd, hw_context, SC(CTRL), 0);
884 write_kctxt_csr(dd, hw_context, SC(CHECK_ENABLE), 0);
885 write_kctxt_csr(dd, hw_context, SC(ERR_MASK), 0);
886 write_kctxt_csr(dd, hw_context, SC(CHECK_PARTITION_KEY), 0);
887 write_kctxt_csr(dd, hw_context, SC(CHECK_OPCODE), 0);
888 write_kctxt_csr(dd, hw_context, SC(CREDIT_RETURN_ADDR), 0);
889 write_kctxt_csr(dd, hw_context, SC(CREDIT_CTRL), 0);
891 /* release the index and context for re-use */
892 sc_hw_free(dd, sw_index, hw_context);
893 spin_unlock_irqrestore(&dd->sc_lock, flags);
896 free_percpu(sc->buffers_allocated);
900 /* disable the context */
901 void sc_disable(struct send_context *sc)
905 struct pio_buf *pbuf;
910 /* do all steps, even if already disabled */
911 spin_lock_irqsave(&sc->alloc_lock, flags);
912 reg = read_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL));
913 reg &= ~SC(CTRL_CTXT_ENABLE_SMASK);
914 sc->flags &= ~SCF_ENABLED;
915 sc_wait_for_packet_egress(sc, 1);
916 write_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL), reg);
917 spin_unlock_irqrestore(&sc->alloc_lock, flags);
920 * Flush any waiters. Once the context is disabled,
921 * credit return interrupts are stopped (although there
922 * could be one in-process when the context is disabled).
923 * Wait one microsecond for any lingering interrupts, then
924 * proceed with the flush.
927 spin_lock_irqsave(&sc->release_lock, flags);
928 if (sc->sr) { /* this context has a shadow ring */
929 while (sc->sr_tail != sc->sr_head) {
930 pbuf = &sc->sr[sc->sr_tail].pbuf;
932 (*pbuf->cb)(pbuf->arg, PRC_SC_DISABLE);
934 if (sc->sr_tail >= sc->sr_size)
938 spin_unlock_irqrestore(&sc->release_lock, flags);
941 /* return SendEgressCtxtStatus.PacketOccupancy */
942 #define packet_occupancy(r) \
943 (((r) & SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SMASK)\
944 >> SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SHIFT)
946 /* is egress halted on the context? */
947 #define egress_halted(r) \
948 ((r) & SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_HALT_STATUS_SMASK)
950 /* wait for packet egress, optionally pause for credit return */
951 static void sc_wait_for_packet_egress(struct send_context *sc, int pause)
953 struct hfi1_devdata *dd = sc->dd;
960 reg = read_csr(dd, sc->hw_context * 8 +
961 SEND_EGRESS_CTXT_STATUS);
962 /* done if egress is stopped */
963 if (egress_halted(reg))
965 reg = packet_occupancy(reg);
968 /* counter is reset if occupancy count changes */
972 /* timed out - bounce the link */
974 "%s: context %u(%u) timeout waiting for packets to egress, remaining count %u, bouncing link\n",
975 __func__, sc->sw_index,
976 sc->hw_context, (u32)reg);
977 queue_work(dd->pport->hfi1_wq,
978 &dd->pport->link_bounce_work);
986 /* Add additional delay to ensure chip returns all credits */
987 pause_for_credit_return(dd);
990 void sc_wait(struct hfi1_devdata *dd)
994 for (i = 0; i < dd->num_send_contexts; i++) {
995 struct send_context *sc = dd->send_contexts[i].sc;
999 sc_wait_for_packet_egress(sc, 0);
1004 * Restart a context after it has been halted due to error.
1006 * If the first step fails - wait for the halt to be asserted, return early.
1007 * Otherwise complain about timeouts but keep going.
1009 * It is expected that allocations (enabled flag bit) have been shut off
1010 * already (only applies to kernel contexts).
1012 int sc_restart(struct send_context *sc)
1014 struct hfi1_devdata *dd = sc->dd;
1019 /* bounce off if not halted, or being free'd */
1020 if (!(sc->flags & SCF_HALTED) || (sc->flags & SCF_IN_FREE))
1023 dd_dev_info(dd, "restarting send context %u(%u)\n", sc->sw_index,
1027 * Step 1: Wait for the context to actually halt.
1029 * The error interrupt is asynchronous to actually setting halt
1034 reg = read_kctxt_csr(dd, sc->hw_context, SC(STATUS));
1035 if (reg & SC(STATUS_CTXT_HALTED_SMASK))
1038 dd_dev_err(dd, "%s: context %u(%u) not halting, skipping\n",
1039 __func__, sc->sw_index, sc->hw_context);
1047 * Step 2: Ensure no users are still trying to write to PIO.
1049 * For kernel contexts, we have already turned off buffer allocation.
1050 * Now wait for the buffer count to go to zero.
1052 * For user contexts, the user handling code has cut off write access
1053 * to the context's PIO pages before calling this routine and will
1054 * restore write access after this routine returns.
1056 if (sc->type != SC_USER) {
1057 /* kernel context */
1060 count = get_buffers_allocated(sc);
1065 "%s: context %u(%u) timeout waiting for PIO buffers to zero, remaining %d\n",
1066 __func__, sc->sw_index,
1067 sc->hw_context, count);
1075 * Step 3: Wait for all packets to egress.
1076 * This is done while disabling the send context
1078 * Step 4: Disable the context
1080 * This is a superset of the halt. After the disable, the
1081 * errors can be cleared.
1086 * Step 5: Enable the context
1088 * This enable will clear the halted flag and per-send context
1091 return sc_enable(sc);
1095 * PIO freeze processing. To be called after the TXE block is fully frozen.
1096 * Go through all frozen send contexts and disable them. The contexts are
1097 * already stopped by the freeze.
1099 void pio_freeze(struct hfi1_devdata *dd)
1101 struct send_context *sc;
1104 for (i = 0; i < dd->num_send_contexts; i++) {
1105 sc = dd->send_contexts[i].sc;
1107 * Don't disable unallocated, unfrozen, or user send contexts.
1108 * User send contexts will be disabled when the process
1109 * calls into the driver to reset its context.
1111 if (!sc || !(sc->flags & SCF_FROZEN) || sc->type == SC_USER)
1114 /* only need to disable, the context is already stopped */
1120 * Unfreeze PIO for kernel send contexts. The precondition for calling this
1121 * is that all PIO send contexts have been disabled and the SPC freeze has
1122 * been cleared. Now perform the last step and re-enable each kernel context.
1123 * User (PSM) processing will occur when PSM calls into the kernel to
1124 * acknowledge the freeze.
1126 void pio_kernel_unfreeze(struct hfi1_devdata *dd)
1128 struct send_context *sc;
1131 for (i = 0; i < dd->num_send_contexts; i++) {
1132 sc = dd->send_contexts[i].sc;
1133 if (!sc || !(sc->flags & SCF_FROZEN) || sc->type == SC_USER)
1136 sc_enable(sc); /* will clear the sc frozen flag */
1141 * Wait for the SendPioInitCtxt.PioInitInProgress bit to clear.
1143 * -ETIMEDOUT - if we wait too long
1144 * -EIO - if there was an error
1146 static int pio_init_wait_progress(struct hfi1_devdata *dd)
1151 /* max is the longest possible HW init time / delay */
1152 max = (dd->icode == ICODE_FPGA_EMULATION) ? 120 : 5;
1154 reg = read_csr(dd, SEND_PIO_INIT_CTXT);
1155 if (!(reg & SEND_PIO_INIT_CTXT_PIO_INIT_IN_PROGRESS_SMASK))
1163 return reg & SEND_PIO_INIT_CTXT_PIO_INIT_ERR_SMASK ? -EIO : 0;
1167 * Reset all of the send contexts to their power-on state. Used
1168 * only during manual init - no lock against sc_enable needed.
1170 void pio_reset_all(struct hfi1_devdata *dd)
1174 /* make sure the init engine is not busy */
1175 ret = pio_init_wait_progress(dd);
1176 /* ignore any timeout */
1178 /* clear the error */
1179 write_csr(dd, SEND_PIO_ERR_CLEAR,
1180 SEND_PIO_ERR_CLEAR_PIO_INIT_SM_IN_ERR_SMASK);
1183 /* reset init all */
1184 write_csr(dd, SEND_PIO_INIT_CTXT,
1185 SEND_PIO_INIT_CTXT_PIO_ALL_CTXT_INIT_SMASK);
1187 ret = pio_init_wait_progress(dd);
1190 "PIO send context init %s while initializing all PIO blocks\n",
1191 ret == -ETIMEDOUT ? "is stuck" : "had an error");
1195 /* enable the context */
1196 int sc_enable(struct send_context *sc)
1198 u64 sc_ctrl, reg, pio;
1199 struct hfi1_devdata *dd;
1200 unsigned long flags;
1208 * Obtain the allocator lock to guard against any allocation
1209 * attempts (which should not happen prior to context being
1210 * enabled). On the release/disable side we don't need to
1211 * worry about locking since the releaser will not do anything
1212 * if the context accounting values have not changed.
1214 spin_lock_irqsave(&sc->alloc_lock, flags);
1215 sc_ctrl = read_kctxt_csr(dd, sc->hw_context, SC(CTRL));
1216 if ((sc_ctrl & SC(CTRL_CTXT_ENABLE_SMASK)))
1217 goto unlock; /* already enabled */
1219 /* IMPORTANT: only clear free and fill if transitioning 0 -> 1 */
1228 /* the alloc lock insures no fast path allocation */
1229 reset_buffers_allocated(sc);
1232 * Clear all per-context errors. Some of these will be set when
1233 * we are re-enabling after a context halt. Now that the context
1234 * is disabled, the halt will not clear until after the PIO init
1235 * engine runs below.
1237 reg = read_kctxt_csr(dd, sc->hw_context, SC(ERR_STATUS));
1239 write_kctxt_csr(dd, sc->hw_context, SC(ERR_CLEAR),
1243 * The HW PIO initialization engine can handle only one init
1244 * request at a time. Serialize access to each device's engine.
1246 spin_lock(&dd->sc_init_lock);
1248 * Since access to this code block is serialized and
1249 * each access waits for the initialization to complete
1250 * before releasing the lock, the PIO initialization engine
1251 * should not be in use, so we don't have to wait for the
1252 * InProgress bit to go down.
1254 pio = ((sc->hw_context & SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_MASK) <<
1255 SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_SHIFT) |
1256 SEND_PIO_INIT_CTXT_PIO_SINGLE_CTXT_INIT_SMASK;
1257 write_csr(dd, SEND_PIO_INIT_CTXT, pio);
1259 * Wait until the engine is done. Give the chip the required time
1260 * so, hopefully, we read the register just once.
1263 ret = pio_init_wait_progress(dd);
1264 spin_unlock(&dd->sc_init_lock);
1267 "sctxt%u(%u): Context not enabled due to init failure %d\n",
1268 sc->sw_index, sc->hw_context, ret);
1273 * All is well. Enable the context.
1275 sc_ctrl |= SC(CTRL_CTXT_ENABLE_SMASK);
1276 write_kctxt_csr(dd, sc->hw_context, SC(CTRL), sc_ctrl);
1278 * Read SendCtxtCtrl to force the write out and prevent a timing
1279 * hazard where a PIO write may reach the context before the enable.
1281 read_kctxt_csr(dd, sc->hw_context, SC(CTRL));
1282 sc->flags |= SCF_ENABLED;
1285 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1290 /* force a credit return on the context */
1291 void sc_return_credits(struct send_context *sc)
1296 /* a 0->1 transition schedules a credit return */
1297 write_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE),
1298 SC(CREDIT_FORCE_FORCE_RETURN_SMASK));
1300 * Ensure that the write is flushed and the credit return is
1301 * scheduled. We care more about the 0 -> 1 transition.
1303 read_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE));
1304 /* set back to 0 for next time */
1305 write_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE), 0);
1308 /* allow all in-flight packets to drain on the context */
1309 void sc_flush(struct send_context *sc)
1314 sc_wait_for_packet_egress(sc, 1);
1317 /* drop all packets on the context, no waiting until they are sent */
1318 void sc_drop(struct send_context *sc)
1323 dd_dev_info(sc->dd, "%s: context %u(%u) - not implemented\n",
1324 __func__, sc->sw_index, sc->hw_context);
1328 * Start the software reaction to a context halt or SPC freeze:
1329 * - mark the context as halted or frozen
1330 * - stop buffer allocations
1332 * Called from the error interrupt. Other work is deferred until
1333 * out of the interrupt.
1335 void sc_stop(struct send_context *sc, int flag)
1337 unsigned long flags;
1339 /* mark the context */
1342 /* stop buffer allocations */
1343 spin_lock_irqsave(&sc->alloc_lock, flags);
1344 sc->flags &= ~SCF_ENABLED;
1345 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1346 wake_up(&sc->halt_wait);
1349 #define BLOCK_DWORDS (PIO_BLOCK_SIZE/sizeof(u32))
1350 #define dwords_to_blocks(x) DIV_ROUND_UP(x, BLOCK_DWORDS)
1353 * The send context buffer "allocator".
1355 * @sc: the PIO send context we are allocating from
1356 * @len: length of whole packet - including PBC - in dwords
1357 * @cb: optional callback to call when the buffer is finished sending
1358 * @arg: argument for cb
1360 * Return a pointer to a PIO buffer if successful, NULL if not enough room.
1362 struct pio_buf *sc_buffer_alloc(struct send_context *sc, u32 dw_len,
1363 pio_release_cb cb, void *arg)
1365 struct pio_buf *pbuf = NULL;
1366 unsigned long flags;
1367 unsigned long avail;
1368 unsigned long blocks = dwords_to_blocks(dw_len);
1369 unsigned long start_fill;
1373 spin_lock_irqsave(&sc->alloc_lock, flags);
1374 if (!(sc->flags & SCF_ENABLED)) {
1375 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1380 avail = (unsigned long)sc->credits - (sc->fill - sc->alloc_free);
1381 if (blocks > avail) {
1382 /* not enough room */
1383 if (unlikely(trycount)) { /* already tried to get more room */
1384 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1387 /* copy from receiver cache line and recalculate */
1388 sc->alloc_free = ACCESS_ONCE(sc->free);
1390 (unsigned long)sc->credits -
1391 (sc->fill - sc->alloc_free);
1392 if (blocks > avail) {
1393 /* still no room, actively update */
1394 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1395 sc_release_update(sc);
1396 spin_lock_irqsave(&sc->alloc_lock, flags);
1397 sc->alloc_free = ACCESS_ONCE(sc->free);
1403 /* there is enough room */
1406 this_cpu_inc(*sc->buffers_allocated);
1408 /* read this once */
1411 /* "allocate" the buffer */
1412 start_fill = sc->fill;
1416 * Fill the parts that the releaser looks at before moving the head.
1417 * The only necessary piece is the sent_at field. The credits
1418 * we have just allocated cannot have been returned yet, so the
1419 * cb and arg will not be looked at for a "while". Put them
1420 * on this side of the memory barrier anyway.
1422 pbuf = &sc->sr[head].pbuf;
1423 pbuf->sent_at = sc->fill;
1426 pbuf->sc = sc; /* could be filled in at sc->sr init time */
1427 /* make sure this is in memory before updating the head */
1429 /* calculate next head index, do not store */
1431 if (next >= sc->sr_size)
1433 /* update the head - must be last! - the releaser can look at fields
1434 in pbuf once we move the head */
1437 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1439 /* finish filling in the buffer outside the lock */
1440 pbuf->start = sc->base_addr + ((start_fill % sc->credits)
1442 pbuf->size = sc->credits * PIO_BLOCK_SIZE;
1443 pbuf->end = sc->base_addr + pbuf->size;
1444 pbuf->block_count = blocks;
1445 pbuf->qw_written = 0;
1446 pbuf->carry_bytes = 0;
1447 pbuf->carry.val64 = 0;
1453 * There are at least two entities that can turn on credit return
1454 * interrupts and they can overlap. Avoid problems by implementing
1455 * a count scheme that is enforced by a lock. The lock is needed because
1456 * the count and CSR write must be paired.
1460 * Start credit return interrupts. This is managed by a count. If already
1461 * on, just increment the count.
1463 void sc_add_credit_return_intr(struct send_context *sc)
1465 unsigned long flags;
1467 /* lock must surround both the count change and the CSR update */
1468 spin_lock_irqsave(&sc->credit_ctrl_lock, flags);
1469 if (sc->credit_intr_count == 0) {
1470 sc->credit_ctrl |= SC(CREDIT_CTRL_CREDIT_INTR_SMASK);
1471 write_kctxt_csr(sc->dd, sc->hw_context,
1472 SC(CREDIT_CTRL), sc->credit_ctrl);
1474 sc->credit_intr_count++;
1475 spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
1479 * Stop credit return interrupts. This is managed by a count. Decrement the
1480 * count, if the last user, then turn the credit interrupts off.
1482 void sc_del_credit_return_intr(struct send_context *sc)
1484 unsigned long flags;
1486 WARN_ON(sc->credit_intr_count == 0);
1488 /* lock must surround both the count change and the CSR update */
1489 spin_lock_irqsave(&sc->credit_ctrl_lock, flags);
1490 sc->credit_intr_count--;
1491 if (sc->credit_intr_count == 0) {
1492 sc->credit_ctrl &= ~SC(CREDIT_CTRL_CREDIT_INTR_SMASK);
1493 write_kctxt_csr(sc->dd, sc->hw_context,
1494 SC(CREDIT_CTRL), sc->credit_ctrl);
1496 spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
1500 * The caller must be careful when calling this. All needint calls
1501 * must be paired with !needint.
1503 void hfi1_sc_wantpiobuf_intr(struct send_context *sc, u32 needint)
1506 sc_add_credit_return_intr(sc);
1508 sc_del_credit_return_intr(sc);
1509 trace_hfi1_wantpiointr(sc, needint, sc->credit_ctrl);
1512 sc_return_credits(sc);
1517 * sc_piobufavail - callback when a PIO buffer is available
1518 * @sc: the send context
1520 * This is called from the interrupt handler when a PIO buffer is
1521 * available after hfi1_verbs_send() returned an error that no buffers were
1522 * available. Disable the interrupt if there are no more QPs waiting.
1524 static void sc_piobufavail(struct send_context *sc)
1526 struct hfi1_devdata *dd = sc->dd;
1527 struct hfi1_ibdev *dev = &dd->verbs_dev;
1528 struct list_head *list;
1529 struct hfi1_qp *qps[PIO_WAIT_BATCH_SIZE];
1531 unsigned long flags;
1534 if (dd->send_contexts[sc->sw_index].type != SC_KERNEL)
1536 list = &sc->piowait;
1538 * Note: checking that the piowait list is empty and clearing
1539 * the buffer available interrupt needs to be atomic or we
1540 * could end up with QPs on the wait list with the interrupt
1543 write_seqlock_irqsave(&dev->iowait_lock, flags);
1544 while (!list_empty(list)) {
1545 struct iowait *wait;
1547 if (n == ARRAY_SIZE(qps))
1549 wait = list_first_entry(list, struct iowait, list);
1550 qp = container_of(wait, struct hfi1_qp, s_iowait);
1551 list_del_init(&qp->s_iowait.list);
1552 /* refcount held until actual wake up */
1556 * Counting: only call wantpiobuf_intr() if there were waiters and they
1560 hfi1_sc_wantpiobuf_intr(sc, 0);
1562 write_sequnlock_irqrestore(&dev->iowait_lock, flags);
1564 for (i = 0; i < n; i++)
1565 hfi1_qp_wakeup(qps[i], HFI1_S_WAIT_PIO);
1568 /* translate a send credit update to a bit code of reasons */
1569 static inline int fill_code(u64 hw_free)
1573 if (hw_free & CR_STATUS_SMASK)
1574 code |= PRC_STATUS_ERR;
1575 if (hw_free & CR_CREDIT_RETURN_DUE_TO_PBC_SMASK)
1577 if (hw_free & CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SMASK)
1578 code |= PRC_THRESHOLD;
1579 if (hw_free & CR_CREDIT_RETURN_DUE_TO_ERR_SMASK)
1580 code |= PRC_FILL_ERR;
1581 if (hw_free & CR_CREDIT_RETURN_DUE_TO_FORCE_SMASK)
1582 code |= PRC_SC_DISABLE;
1586 /* use the jiffies compare to get the wrap right */
1587 #define sent_before(a, b) time_before(a, b) /* a < b */
1590 * The send context buffer "releaser".
1592 void sc_release_update(struct send_context *sc)
1594 struct pio_buf *pbuf;
1597 unsigned long old_free;
1599 unsigned long extra;
1600 unsigned long flags;
1606 spin_lock_irqsave(&sc->release_lock, flags);
1608 hw_free = le64_to_cpu(*sc->hw_free); /* volatile read */
1609 old_free = sc->free;
1610 extra = (((hw_free & CR_COUNTER_SMASK) >> CR_COUNTER_SHIFT)
1611 - (old_free & CR_COUNTER_MASK))
1613 free = old_free + extra;
1614 trace_hfi1_piofree(sc, extra);
1616 /* call sent buffer callbacks */
1617 code = -1; /* code not yet set */
1618 head = ACCESS_ONCE(sc->sr_head); /* snapshot the head */
1620 while (head != tail) {
1621 pbuf = &sc->sr[tail].pbuf;
1623 if (sent_before(free, pbuf->sent_at)) {
1628 if (code < 0) /* fill in code on first user */
1629 code = fill_code(hw_free);
1630 (*pbuf->cb)(pbuf->arg, code);
1634 if (tail >= sc->sr_size)
1638 /* make sure tail is updated before free */
1641 spin_unlock_irqrestore(&sc->release_lock, flags);
1646 * Send context group releaser. Argument is the send context that caused
1647 * the interrupt. Called from the send context interrupt handler.
1649 * Call release on all contexts in the group.
1651 * This routine takes the sc_lock without an irqsave because it is only
1652 * called from an interrupt handler. Adjust if that changes.
1654 void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context)
1656 struct send_context *sc;
1660 spin_lock(&dd->sc_lock);
1661 sw_index = dd->hw_to_sw[hw_context];
1662 if (unlikely(sw_index >= dd->num_send_contexts)) {
1663 dd_dev_err(dd, "%s: invalid hw (%u) to sw (%u) mapping\n",
1664 __func__, hw_context, sw_index);
1667 sc = dd->send_contexts[sw_index].sc;
1671 gc = group_context(hw_context, sc->group);
1672 gc_end = gc + group_size(sc->group);
1673 for (; gc < gc_end; gc++) {
1674 sw_index = dd->hw_to_sw[gc];
1675 if (unlikely(sw_index >= dd->num_send_contexts)) {
1677 "%s: invalid hw (%u) to sw (%u) mapping\n",
1678 __func__, hw_context, sw_index);
1681 sc_release_update(dd->send_contexts[sw_index].sc);
1684 spin_unlock(&dd->sc_lock);
1687 int init_pervl_scs(struct hfi1_devdata *dd)
1690 u64 mask, all_vl_mask = (u64) 0x80ff; /* VLs 0-7, 15 */
1693 dd->vld[15].sc = sc_alloc(dd, SC_KERNEL,
1694 dd->rcd[0]->rcvhdrqentsize, dd->node);
1695 if (!dd->vld[15].sc)
1697 hfi1_init_ctxt(dd->vld[15].sc);
1698 dd->vld[15].mtu = enum_to_mtu(OPA_MTU_2048);
1699 for (i = 0; i < num_vls; i++) {
1701 * Since this function does not deal with a specific
1702 * receive context but we need the RcvHdrQ entry size,
1703 * use the size from rcd[0]. It is guaranteed to be
1704 * valid at this point and will remain the same for all
1707 dd->vld[i].sc = sc_alloc(dd, SC_KERNEL,
1708 dd->rcd[0]->rcvhdrqentsize, dd->node);
1712 hfi1_init_ctxt(dd->vld[i].sc);
1714 /* non VL15 start with the max MTU */
1715 dd->vld[i].mtu = hfi1_max_mtu;
1717 sc_enable(dd->vld[15].sc);
1718 ctxt = dd->vld[15].sc->hw_context;
1719 mask = all_vl_mask & ~(1LL << 15);
1720 write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask);
1722 "Using send context %u(%u) for VL15\n",
1723 dd->vld[15].sc->sw_index, ctxt);
1724 for (i = 0; i < num_vls; i++) {
1725 sc_enable(dd->vld[i].sc);
1726 ctxt = dd->vld[i].sc->hw_context;
1727 mask = all_vl_mask & ~(1LL << i);
1728 write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask);
1732 sc_free(dd->vld[15].sc);
1733 for (i = 0; i < num_vls; i++)
1734 sc_free(dd->vld[i].sc);
1738 int init_credit_return(struct hfi1_devdata *dd)
1744 num_numa = num_online_nodes();
1745 /* enforce the expectation that the numas are compact */
1746 for (i = 0; i < num_numa; i++) {
1747 if (!node_online(i)) {
1748 dd_dev_err(dd, "NUMA nodes are not compact\n");
1754 dd->cr_base = kcalloc(
1756 sizeof(struct credit_return_base),
1759 dd_dev_err(dd, "Unable to allocate credit return base\n");
1763 for (i = 0; i < num_numa; i++) {
1764 int bytes = TXE_NUM_CONTEXTS * sizeof(struct credit_return);
1766 set_dev_node(&dd->pcidev->dev, i);
1767 dd->cr_base[i].va = dma_zalloc_coherent(
1772 if (dd->cr_base[i].va == NULL) {
1773 set_dev_node(&dd->pcidev->dev, dd->node);
1775 "Unable to allocate credit return DMA range for NUMA %d\n",
1781 set_dev_node(&dd->pcidev->dev, dd->node);
1788 void free_credit_return(struct hfi1_devdata *dd)
1796 num_numa = num_online_nodes();
1797 for (i = 0; i < num_numa; i++) {
1798 if (dd->cr_base[i].va) {
1799 dma_free_coherent(&dd->pcidev->dev,
1801 * sizeof(struct credit_return),