1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
9 * You should have received a copy of the GNU General Public License along with
10 * this program; if not, write to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
13 * The full GNU General Public License is included in this distribution in the
14 * file called LICENSE.
16 * Contact Information:
17 * wlanfae <wlanfae@realtek.com>
18 ******************************************************************************/
21 #include "r8192E_hw.h"
22 #include "r8192E_phyreg.h"
23 #include "r8190P_rtl8256.h"
24 #include "r8192E_phy.h"
27 #include "r8192E_hwimg.h"
29 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
47 /*************************Define local function prototype**********************/
49 static u32 phy_FwRFSerialRead(struct net_device *dev,
50 enum rf90_radio_path eRFPath,
52 static void phy_FwRFSerialWrite(struct net_device *dev,
53 enum rf90_radio_path eRFPath,
54 u32 Offset, u32 Data);
56 static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
60 for (i = 0; i <= 31; i++) {
61 if (((dwBitMask >> i) & 0x1) == 1)
67 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
70 struct r8192_priv *priv = rtllib_priv(dev);
72 if (priv->rf_type == RF_2T4R)
74 else if (priv->rf_type == RF_1T2R) {
75 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
77 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
83 void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
87 u32 OriginalValue, BitShift, NewValue;
89 if (dwBitMask != bMaskDWord) {
90 OriginalValue = read_nic_dword(dev, dwRegAddr);
91 BitShift = rtl8192_CalculateBitShift(dwBitMask);
92 NewValue = (((OriginalValue) & (~dwBitMask)) |
93 (dwData << BitShift));
94 write_nic_dword(dev, dwRegAddr, NewValue);
96 write_nic_dword(dev, dwRegAddr, dwData);
100 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
102 u32 Ret = 0, OriginalValue, BitShift;
104 OriginalValue = read_nic_dword(dev, dwRegAddr);
105 BitShift = rtl8192_CalculateBitShift(dwBitMask);
106 Ret = (OriginalValue & dwBitMask) >> BitShift;
110 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
111 enum rf90_radio_path eRFPath, u32 Offset)
113 struct r8192_priv *priv = rtllib_priv(dev);
116 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
120 if (priv->rf_chip == RF_8256) {
121 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
123 priv->RfReg0Value[eRFPath] |= 0x140;
124 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
126 (priv->RfReg0Value[eRFPath]<<16));
127 NewOffset = Offset - 30;
128 } else if (Offset >= 16) {
129 priv->RfReg0Value[eRFPath] |= 0x100;
130 priv->RfReg0Value[eRFPath] &= (~0x40);
131 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
133 (priv->RfReg0Value[eRFPath]<<16));
135 NewOffset = Offset - 15;
139 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need"
143 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
145 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
146 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
150 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
153 if (priv->rf_chip == RF_8256) {
154 priv->RfReg0Value[eRFPath] &= 0xebf;
156 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
157 (priv->RfReg0Value[eRFPath] << 16));
159 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
167 static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
168 enum rf90_radio_path eRFPath, u32 Offset,
171 struct r8192_priv *priv = rtllib_priv(dev);
172 u32 DataAndAddr = 0, NewOffset = 0;
173 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
176 if (priv->rf_chip == RF_8256) {
177 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
180 priv->RfReg0Value[eRFPath] |= 0x140;
181 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
183 (priv->RfReg0Value[eRFPath] << 16));
184 NewOffset = Offset - 30;
185 } else if (Offset >= 16) {
186 priv->RfReg0Value[eRFPath] |= 0x100;
187 priv->RfReg0Value[eRFPath] &= (~0x40);
188 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
190 (priv->RfReg0Value[eRFPath] << 16));
191 NewOffset = Offset - 15;
195 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be"
200 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
202 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
205 priv->RfReg0Value[eRFPath] = Data;
207 if (priv->rf_chip == RF_8256) {
209 priv->RfReg0Value[eRFPath] &= 0xebf;
212 pPhyReg->rf3wireOffset,
214 (priv->RfReg0Value[eRFPath] << 16));
216 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
221 void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
222 u32 RegAddr, u32 BitMask, u32 Data)
224 struct r8192_priv *priv = rtllib_priv(dev);
225 u32 Original_Value, BitShift, New_Value;
227 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
229 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
232 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
233 if (priv->Rf_Mode == RF_OP_By_FW) {
234 if (BitMask != bMask12Bits) {
235 Original_Value = phy_FwRFSerialRead(dev, eRFPath,
237 BitShift = rtl8192_CalculateBitShift(BitMask);
238 New_Value = (((Original_Value) & (~BitMask)) |
241 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
243 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
247 if (BitMask != bMask12Bits) {
248 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
250 BitShift = rtl8192_CalculateBitShift(BitMask);
251 New_Value = (((Original_Value) & (~BitMask)) |
254 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr,
257 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
262 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
263 u32 RegAddr, u32 BitMask)
265 u32 Original_Value, Readback_Value, BitShift;
266 struct r8192_priv *priv = rtllib_priv(dev);
268 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
270 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
273 if (priv->Rf_Mode == RF_OP_By_FW) {
274 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
277 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
280 BitShift = rtl8192_CalculateBitShift(BitMask);
281 Readback_Value = (Original_Value & BitMask) >> BitShift;
283 return Readback_Value;
286 static u32 phy_FwRFSerialRead(struct net_device *dev,
287 enum rf90_radio_path eRFPath, u32 Offset)
292 Data |= ((Offset & 0xFF) << 12);
293 Data |= ((eRFPath & 0x3) << 20);
295 while (read_nic_dword(dev, QPNR)&0x80000000) {
301 write_nic_dword(dev, QPNR, Data);
302 while (read_nic_dword(dev, QPNR) & 0x80000000) {
308 return read_nic_dword(dev, RF_DATA);
310 } /* phy_FwRFSerialRead */
312 static void phy_FwRFSerialWrite(struct net_device *dev,
313 enum rf90_radio_path eRFPath,
314 u32 Offset, u32 Data)
318 Data |= ((Offset & 0xFF) << 12);
319 Data |= ((eRFPath & 0x3) << 20);
323 while (read_nic_dword(dev, QPNR) & 0x80000000) {
329 write_nic_dword(dev, QPNR, Data);
331 } /* phy_FwRFSerialWrite */
334 void rtl8192_phy_configmac(struct net_device *dev)
336 u32 dwArrayLen = 0, i = 0;
337 u32 *pdwArray = NULL;
338 struct r8192_priv *priv = rtllib_priv(dev);
340 if (priv->bTXPowerDataReadFromEEPORM) {
341 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
342 dwArrayLen = MACPHY_Array_PGLength;
343 pdwArray = Rtl819XMACPHY_Array_PG;
346 RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n");
347 dwArrayLen = MACPHY_ArrayLength;
348 pdwArray = Rtl819XMACPHY_Array;
350 for (i = 0; i < dwArrayLen; i += 3) {
351 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MAC"
352 "PHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
353 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
354 if (pdwArray[i] == 0x318)
355 pdwArray[i+2] = 0x00000800;
356 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
363 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
366 u32 *Rtl819XPHY_REGArray_Table = NULL;
367 u32 *Rtl819XAGCTAB_Array_Table = NULL;
368 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
369 struct r8192_priv *priv = rtllib_priv(dev);
371 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
372 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
373 if (priv->rf_type == RF_2T4R) {
374 PHY_REGArrayLen = PHY_REGArrayLength;
375 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
376 } else if (priv->rf_type == RF_1T2R) {
377 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
378 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
381 if (ConfigType == BaseBand_Config_PHY_REG) {
382 for (i = 0; i < PHY_REGArrayLen; i += 2) {
383 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i],
385 Rtl819XPHY_REGArray_Table[i+1]);
386 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray"
387 "[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",
388 i, Rtl819XPHY_REGArray_Table[i],
389 Rtl819XPHY_REGArray_Table[i+1]);
391 } else if (ConfigType == BaseBand_Config_AGC_TAB) {
392 for (i = 0; i < AGCTAB_ArrayLen; i += 2) {
393 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i],
395 Rtl819XAGCTAB_Array_Table[i+1]);
396 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] "
397 "is %x rtl819XAGCTAB_Array[1] is %x\n", i,
398 Rtl819XAGCTAB_Array_Table[i],
399 Rtl819XAGCTAB_Array_Table[i+1]);
405 static void rtl8192_InitBBRFRegDef(struct net_device *dev)
407 struct r8192_priv *priv = rtllib_priv(dev);
409 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
410 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
411 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
412 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
414 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
415 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
416 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
417 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
419 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
420 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
421 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
422 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
424 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
425 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
426 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
427 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
429 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
430 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
431 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
432 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
434 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
435 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
436 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
437 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
439 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
440 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
441 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
442 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
444 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
445 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
446 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
447 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
449 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
450 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
451 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
452 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
454 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
455 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
456 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
457 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
459 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
460 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
461 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
462 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
464 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
465 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
466 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
467 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
469 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
470 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
471 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
472 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
474 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
475 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
476 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
477 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
479 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
480 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
481 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
482 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
484 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
485 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
486 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
487 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
489 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
490 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
491 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
492 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
496 bool rtl8192_phy_checkBBAndRF(struct net_device *dev,
497 enum hw90_block CheckBlock,
498 enum rf90_radio_path eRFPath)
501 u32 i, CheckTimes = 4, dwRegRead = 0;
503 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
505 WriteAddr[HW90_BLOCK_MAC] = 0x100;
506 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
507 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
508 WriteAddr[HW90_BLOCK_RF] = 0x3;
509 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__,
511 for (i = 0; i < CheckTimes; i++) {
512 switch (CheckBlock) {
514 RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write "
518 case HW90_BLOCK_PHY0:
519 case HW90_BLOCK_PHY1:
520 write_nic_dword(dev, WriteAddr[CheckBlock],
522 dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
526 WriteData[i] &= 0xfff;
527 rtl8192_phy_SetRFReg(dev, eRFPath,
528 WriteAddr[HW90_BLOCK_RF],
529 bMask12Bits, WriteData[i]);
531 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath,
532 WriteAddr[HW90_BLOCK_RF],
543 if (dwRegRead != WriteData[i]) {
544 RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, "
545 "WriteData: %x\n", dwRegRead, WriteData[i]);
554 static bool rtl8192_BB_Config_ParaFile(struct net_device *dev)
556 struct r8192_priv *priv = rtllib_priv(dev);
557 bool rtStatus = true;
558 u8 bRegValue = 0, eCheckItem = 0;
561 bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
562 write_nic_byte(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT));
564 dwRegValue = read_nic_dword(dev, CPU_GEN);
565 write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
567 for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0;
568 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
569 rtStatus = rtl8192_phy_checkBBAndRF(dev,
570 (enum hw90_block)eCheckItem,
571 (enum rf90_radio_path)0);
573 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():"
574 "Check PHY%d Fail!!\n", eCheckItem-1);
578 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
579 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
581 dwRegValue = read_nic_dword(dev, CPU_GEN);
582 write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
584 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
586 if (priv->IC_Cut > VERSION_8190_BD) {
587 if (priv->rf_type == RF_2T4R)
588 dwRegValue = (priv->AntennaTxPwDiff[2]<<8 |
589 priv->AntennaTxPwDiff[1]<<4 |
590 priv->AntennaTxPwDiff[0]);
593 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
594 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
597 dwRegValue = priv->CrystalCap;
598 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x,
604 bool rtl8192_BBConfig(struct net_device *dev)
606 rtl8192_InitBBRFRegDef(dev);
607 return rtl8192_BB_Config_ParaFile(dev);
610 void rtl8192_phy_getTxPower(struct net_device *dev)
612 struct r8192_priv *priv = rtllib_priv(dev);
614 priv->MCSTxPowerLevelOriginalOffset[0] =
615 read_nic_dword(dev, rTxAGC_Rate18_06);
616 priv->MCSTxPowerLevelOriginalOffset[1] =
617 read_nic_dword(dev, rTxAGC_Rate54_24);
618 priv->MCSTxPowerLevelOriginalOffset[2] =
619 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
620 priv->MCSTxPowerLevelOriginalOffset[3] =
621 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
622 priv->MCSTxPowerLevelOriginalOffset[4] =
623 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
624 priv->MCSTxPowerLevelOriginalOffset[5] =
625 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
627 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
628 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
629 priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
630 priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
631 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, "
632 "c60=0x%x, c68=0x%x)\n",
633 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
634 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
636 priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
637 priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2);
638 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
639 rOFDM0_RxDetector3, priv->framesync);
640 priv->SifsTime = read_nic_word(dev, SIFS);
644 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
646 struct r8192_priv *priv = rtllib_priv(dev);
647 u8 powerlevel = 0, powerlevelOFDM24G = 0;
651 if (priv->epromtype == EEPROM_93C46) {
652 powerlevel = priv->TxPowerLevelCCK[channel-1];
653 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
654 } else if (priv->epromtype == EEPROM_93C56) {
655 if (priv->rf_type == RF_1T2R) {
656 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
657 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
658 } else if (priv->rf_type == RF_2T4R) {
659 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
660 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
662 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
663 - priv->TxPowerLevelOFDM24G_A[channel-1];
665 priv->RF_C_TxPwDiff = ant_pwr_diff;
669 priv->AntennaTxPwDiff[2] = 0;
670 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);
671 priv->AntennaTxPwDiff[0] = 0;
673 u4RegValue = (priv->AntennaTxPwDiff[2]<<8 |
674 priv->AntennaTxPwDiff[1]<<4 |
675 priv->AntennaTxPwDiff[0]);
677 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
678 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
681 switch (priv->rf_chip) {
685 PHY_SetRF8256CCKTxPower(dev, powerlevel);
686 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
691 RT_TRACE(COMP_ERR, "unknown rf chip in function %s()\n",
698 bool rtl8192_phy_RFConfig(struct net_device *dev)
700 struct r8192_priv *priv = rtllib_priv(dev);
701 bool rtStatus = true;
703 switch (priv->rf_chip) {
707 rtStatus = PHY_RF8256_Config(dev);
716 RT_TRACE(COMP_ERR, "error chip id\n");
722 void rtl8192_phy_updateInitGain(struct net_device *dev)
727 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
728 enum rf90_radio_path eRFPath)
735 for (i = 0; i < RadioA_ArrayLength; i += 2) {
736 if (Rtl819XRadioA_Array[i] == 0xfe) {
740 rtl8192_phy_SetRFReg(dev, eRFPath,
741 Rtl819XRadioA_Array[i],
743 Rtl819XRadioA_Array[i+1]);
748 for (i = 0; i < RadioB_ArrayLength; i += 2) {
749 if (Rtl819XRadioB_Array[i] == 0xfe) {
753 rtl8192_phy_SetRFReg(dev, eRFPath,
754 Rtl819XRadioB_Array[i],
756 Rtl819XRadioB_Array[i+1]);
761 for (i = 0; i < RadioC_ArrayLength; i += 2) {
762 if (Rtl819XRadioC_Array[i] == 0xfe) {
766 rtl8192_phy_SetRFReg(dev, eRFPath,
767 Rtl819XRadioC_Array[i],
769 Rtl819XRadioC_Array[i+1]);
774 for (i = 0; i < RadioD_ArrayLength; i += 2) {
775 if (Rtl819XRadioD_Array[i] == 0xfe) {
779 rtl8192_phy_SetRFReg(dev, eRFPath,
780 Rtl819XRadioD_Array[i], bMask12Bits,
781 Rtl819XRadioD_Array[i+1]);
792 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
794 struct r8192_priv *priv = rtllib_priv(dev);
795 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
796 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
798 switch (priv->rf_chip) {
803 PHY_SetRF8256CCKTxPower(dev, powerlevel);
804 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
810 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPower"
817 static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable,
818 u32 CmdTableIdx, u32 CmdTableSz,
819 enum sw_chnl_cmd_id CmdID,
820 u32 Para1, u32 Para2, u32 msDelay)
822 struct sw_chnl_cmd *pCmd;
824 if (CmdTable == NULL) {
825 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot "
829 if (CmdTableIdx >= CmdTableSz) {
830 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid"
831 " index, please check size of the table, CmdTableIdx:"
832 "%d, CmdTableSz:%d\n",
833 CmdTableIdx, CmdTableSz);
837 pCmd = CmdTable + CmdTableIdx;
841 pCmd->msDelay = msDelay;
846 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
847 u8 *stage, u8 *step, u32 *delay)
849 struct r8192_priv *priv = rtllib_priv(dev);
850 struct rtllib_device *ieee = priv->rtllib;
852 u32 PostCommonCmdCnt;
854 struct sw_chnl_cmd *CurrentCmd = NULL;
857 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n",
858 __func__, *stage, *step, channel);
860 if (!rtllib_legal_channel(priv->rtllib, channel)) {
861 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n",
868 rtl8192_phy_SetSwChnlCmdArray(ieee->PreCommonCmd,
870 MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
872 rtl8192_phy_SetSwChnlCmdArray(ieee->PreCommonCmd,
874 MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
876 PostCommonCmdCnt = 0;
878 rtl8192_phy_SetSwChnlCmdArray(ieee->PostCommonCmd,
880 MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
883 switch (priv->rf_chip) {
885 if (!(channel >= 1 && channel <= 14)) {
886 RT_TRACE(COMP_ERR, "illegal channel for Zebra "
887 "8225: %d\n", channel);
890 rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
891 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
892 CmdID_RF_WriteReg, rZebra1_Channel,
893 RF_CHANNEL_TABLE_ZEBRA[channel], 10);
894 rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
895 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
900 if (!(channel >= 1 && channel <= 14)) {
901 RT_TRACE(COMP_ERR, "illegal channel for Zebra"
902 " 8256: %d\n", channel);
905 rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
906 RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
907 CmdID_RF_WriteReg, rZebra1_Channel, channel,
909 rtl8192_phy_SetSwChnlCmdArray(ieee->RfDependCmd,
920 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n",
930 CurrentCmd = &ieee->PreCommonCmd[*step];
933 CurrentCmd = &ieee->RfDependCmd[*step];
936 CurrentCmd = &ieee->PostCommonCmd[*step];
940 if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) {
952 switch (CurrentCmd->CmdID) {
953 case CmdID_SetTxPowerLevel:
954 if (priv->IC_Cut > (u8)VERSION_8190_BD)
955 rtl8192_SetTxPowerLevel(dev, channel);
957 case CmdID_WritePortUlong:
958 write_nic_dword(dev, CurrentCmd->Para1,
961 case CmdID_WritePortUshort:
962 write_nic_word(dev, CurrentCmd->Para1,
963 (u16)CurrentCmd->Para2);
965 case CmdID_WritePortUchar:
966 write_nic_byte(dev, CurrentCmd->Para1,
967 (u8)CurrentCmd->Para2);
969 case CmdID_RF_WriteReg:
970 for (eRFPath = 0; eRFPath <
971 priv->NumTotalRFPath; eRFPath++)
972 rtl8192_phy_SetRFReg(dev,
973 (enum rf90_radio_path)eRFPath,
974 CurrentCmd->Para1, bMask12Bits,
975 CurrentCmd->Para2<<7);
983 } /*for (Number of RF paths)*/
985 (*delay) = CurrentCmd->msDelay;
990 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
992 struct r8192_priv *priv = rtllib_priv(dev);
995 while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
996 &priv->SwChnlStep, &delay)) {
999 if (IS_NIC_DOWN(priv))
1003 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1006 struct r8192_priv *priv = rtllib_priv(dev);
1008 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
1010 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__,
1013 rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
1015 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
1018 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1020 struct r8192_priv *priv = rtllib_priv(dev);
1022 RT_TRACE(COMP_PHY, "=====>%s()\n", __func__);
1023 if (IS_NIC_DOWN(priv)) {
1024 RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n", __func__);
1027 if (priv->SwChnlInProgress)
1031 switch (priv->rtllib->mode) {
1032 case WIRELESS_MODE_A:
1033 case WIRELESS_MODE_N_5G:
1034 if (channel <= 14) {
1035 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
1039 case WIRELESS_MODE_B:
1041 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
1045 case WIRELESS_MODE_G:
1046 case WIRELESS_MODE_N_24G:
1048 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
1054 priv->SwChnlInProgress = true;
1058 priv->chan = channel;
1060 priv->SwChnlStage = 0;
1061 priv->SwChnlStep = 0;
1063 if (!IS_NIC_DOWN(priv))
1064 rtl8192_SwChnl_WorkItem(dev);
1065 priv->SwChnlInProgress = false;
1069 static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev)
1071 struct r8192_priv *priv = rtllib_priv(dev);
1073 switch (priv->CurrentChannelBW) {
1074 case HT_CHANNEL_WIDTH_20:
1075 priv->CCKPresentAttentuation =
1076 priv->CCKPresentAttentuation_20Mdefault +
1077 priv->CCKPresentAttentuation_difference;
1079 if (priv->CCKPresentAttentuation >
1080 (CCKTxBBGainTableLength-1))
1081 priv->CCKPresentAttentuation =
1082 CCKTxBBGainTableLength-1;
1083 if (priv->CCKPresentAttentuation < 0)
1084 priv->CCKPresentAttentuation = 0;
1086 RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresent"
1087 "Attentuation = %d\n",
1088 priv->CCKPresentAttentuation);
1090 if (priv->rtllib->current_network.channel == 14 &&
1091 !priv->bcck_in_ch14) {
1092 priv->bcck_in_ch14 = true;
1093 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1094 } else if (priv->rtllib->current_network.channel !=
1095 14 && priv->bcck_in_ch14) {
1096 priv->bcck_in_ch14 = false;
1097 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1099 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1103 case HT_CHANNEL_WIDTH_20_40:
1104 priv->CCKPresentAttentuation =
1105 priv->CCKPresentAttentuation_40Mdefault +
1106 priv->CCKPresentAttentuation_difference;
1108 RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresent"
1109 "Attentuation = %d\n",
1110 priv->CCKPresentAttentuation);
1111 if (priv->CCKPresentAttentuation >
1112 (CCKTxBBGainTableLength - 1))
1113 priv->CCKPresentAttentuation =
1114 CCKTxBBGainTableLength-1;
1115 if (priv->CCKPresentAttentuation < 0)
1116 priv->CCKPresentAttentuation = 0;
1118 if (priv->rtllib->current_network.channel == 14 &&
1119 !priv->bcck_in_ch14) {
1120 priv->bcck_in_ch14 = true;
1121 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1122 } else if (priv->rtllib->current_network.channel != 14
1123 && priv->bcck_in_ch14) {
1124 priv->bcck_in_ch14 = false;
1125 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1127 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1133 static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
1135 struct r8192_priv *priv = rtllib_priv(dev);
1137 if (priv->rtllib->current_network.channel == 14 &&
1138 !priv->bcck_in_ch14)
1139 priv->bcck_in_ch14 = true;
1140 else if (priv->rtllib->current_network.channel != 14 &&
1142 priv->bcck_in_ch14 = false;
1144 switch (priv->CurrentChannelBW) {
1145 case HT_CHANNEL_WIDTH_20:
1146 if (priv->Record_CCK_20Mindex == 0)
1147 priv->Record_CCK_20Mindex = 6;
1148 priv->CCK_index = priv->Record_CCK_20Mindex;
1149 RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_"
1150 "Switch_ThermalMeter(),CCK_index = %d\n",
1154 case HT_CHANNEL_WIDTH_20_40:
1155 priv->CCK_index = priv->Record_CCK_40Mindex;
1156 RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_"
1157 "Switch_ThermalMeter(), CCK_index = %d\n",
1161 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1164 static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
1166 struct r8192_priv *priv = rtllib_priv(dev);
1168 if (priv->IC_Cut >= IC_VersionCut_D)
1169 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
1171 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
1174 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1177 struct r8192_priv *priv = rtllib_priv(dev);
1180 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s "
1181 "bandwidth\n", priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ?
1185 if (priv->rf_chip == RF_PSEUDO_11N) {
1186 priv->SetBWModeInProgress = false;
1189 if (IS_NIC_DOWN(priv)) {
1190 RT_TRACE(COMP_ERR, "%s(): ERR!! driver is not up\n", __func__);
1193 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
1195 switch (priv->CurrentChannelBW) {
1196 case HT_CHANNEL_WIDTH_20:
1197 regBwOpMode |= BW_OPMODE_20MHZ;
1198 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1201 case HT_CHANNEL_WIDTH_20_40:
1202 regBwOpMode &= ~BW_OPMODE_20MHZ;
1203 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1207 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown "
1208 "Bandwidth: %#X\n", priv->CurrentChannelBW);
1212 switch (priv->CurrentChannelBW) {
1213 case HT_CHANNEL_WIDTH_20:
1214 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1215 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1217 if (!priv->btxpower_tracking) {
1218 write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
1219 write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
1220 write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
1222 CCK_Tx_Power_Track_BW_Switch(dev);
1225 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
1228 case HT_CHANNEL_WIDTH_20_40:
1229 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1230 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1232 if (!priv->btxpower_tracking) {
1233 write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
1234 write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
1235 write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
1237 CCK_Tx_Power_Track_BW_Switch(dev);
1240 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1241 (priv->nCur40MhzPrimeSC>>1));
1242 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1243 priv->nCur40MhzPrimeSC);
1245 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1248 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown "
1249 "Bandwidth: %#X\n", priv->CurrentChannelBW);
1254 switch (priv->rf_chip) {
1259 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1269 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1273 atomic_dec(&(priv->rtllib->atm_swbw));
1274 priv->SetBWModeInProgress = false;
1276 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
1279 void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth,
1280 enum ht_extchnl_offset Offset)
1282 struct r8192_priv *priv = rtllib_priv(dev);
1285 if (priv->SetBWModeInProgress)
1288 atomic_inc(&(priv->rtllib->atm_swbw));
1289 priv->SetBWModeInProgress = true;
1291 priv->CurrentChannelBW = Bandwidth;
1293 if (Offset == HT_EXTCHNL_OFFSET_LOWER)
1294 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1295 else if (Offset == HT_EXTCHNL_OFFSET_UPPER)
1296 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1298 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1300 rtl8192_SetBWModeWorkItem(dev);
1304 void InitialGain819xPci(struct net_device *dev, u8 Operation)
1306 #define SCAN_RX_INITIAL_GAIN 0x17
1307 #define POWER_DETECTION_TH 0x08
1308 struct r8192_priv *priv = rtllib_priv(dev);
1312 if (!IS_NIC_DOWN(priv)) {
1313 switch (Operation) {
1315 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial"
1317 initial_gain = SCAN_RX_INITIAL_GAIN;
1318 BitMask = bMaskByte0;
1319 if (dm_digtable.dig_algorithm ==
1320 DIG_ALGO_BY_FALSE_ALARM)
1321 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1322 priv->initgain_backup.xaagccore1 =
1323 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1,
1325 priv->initgain_backup.xbagccore1 =
1326 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1,
1328 priv->initgain_backup.xcagccore1 =
1329 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1,
1331 priv->initgain_backup.xdagccore1 =
1332 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1,
1334 BitMask = bMaskByte2;
1335 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev,
1336 rCCK0_CCA, BitMask);
1338 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is"
1339 " %x\n", priv->initgain_backup.xaagccore1);
1340 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is"
1341 " %x\n", priv->initgain_backup.xbagccore1);
1342 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is"
1343 " %x\n", priv->initgain_backup.xcagccore1);
1344 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is"
1345 " %x\n", priv->initgain_backup.xdagccore1);
1346 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is"
1347 " %x\n", priv->initgain_backup.cca);
1349 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1351 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1352 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1353 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1354 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1355 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1356 POWER_DETECTION_TH);
1357 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1360 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial "
1363 if (dm_digtable.dig_algorithm ==
1364 DIG_ALGO_BY_FALSE_ALARM)
1365 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1367 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask,
1368 (u32)priv->initgain_backup.xaagccore1);
1369 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask,
1370 (u32)priv->initgain_backup.xbagccore1);
1371 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask,
1372 (u32)priv->initgain_backup.xcagccore1);
1373 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask,
1374 (u32)priv->initgain_backup.xdagccore1);
1375 BitMask = bMaskByte2;
1376 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask,
1377 (u32)priv->initgain_backup.cca);
1379 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50"
1380 " is %x\n", priv->initgain_backup.xaagccore1);
1381 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58"
1382 " is %x\n", priv->initgain_backup.xbagccore1);
1383 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60"
1384 " is %x\n", priv->initgain_backup.xcagccore1);
1385 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68"
1386 " is %x\n", priv->initgain_backup.xdagccore1);
1387 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a"
1388 " is %x\n", priv->initgain_backup.cca);
1390 rtl8192_phy_setTxPower(dev,
1391 priv->rtllib->current_network.channel);
1393 if (dm_digtable.dig_algorithm ==
1394 DIG_ALGO_BY_FALSE_ALARM)
1395 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1398 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
1404 void PHY_SetRtl8192eRfOff(struct net_device *dev)
1407 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
1408 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0);
1409 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0);
1410 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1411 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1412 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
1413 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
1414 write_nic_byte(dev, ANAPAR_FOR_8192PciE, 0x07);
1418 static bool SetRFPowerState8190(struct net_device *dev,
1419 enum rt_rf_power_state eRFPowerState)
1421 struct r8192_priv *priv = rtllib_priv(dev);
1422 struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)
1423 (&(priv->rtllib->PowerSaveControl));
1424 bool bResult = true;
1425 u8 i = 0, QueueID = 0;
1426 struct rtl8192_tx_ring *ring = NULL;
1428 if (priv->SetRFPowerStateInProgress)
1430 RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n");
1431 priv->SetRFPowerStateInProgress = true;
1433 switch (priv->rf_chip) {
1435 switch (eRFPowerState) {
1437 RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn!\n");
1438 if ((priv->rtllib->eRFPowerState == eRfOff) &&
1439 RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1440 bool rtstatus = true;
1441 u32 InitilizeCount = 3;
1445 priv->RegRfOff = false;
1446 rtstatus = NicIFEnableNIC(dev);
1447 } while (!rtstatus && (InitilizeCount > 0));
1450 RT_TRACE(COMP_ERR, "%s():Initialize Ada"
1451 "pter fail,return\n",
1453 priv->SetRFPowerStateInProgress = false;
1457 RT_CLEAR_PS_LEVEL(pPSC,
1458 RT_RF_OFF_LEVL_HALT_NIC);
1460 write_nic_byte(dev, ANAPAR, 0x37);
1462 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1464 priv->bHwRfOffAction = 0;
1466 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE,
1468 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4,
1470 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1472 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3,
1474 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3,
1476 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1484 if (priv->rtllib->eRFPowerState == eRfOff)
1488 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1489 ring = &priv->tx_ring[QueueID];
1491 if (skb_queue_len(&ring->queue) == 0) {
1495 RT_TRACE((COMP_POWER|COMP_RF), "eRf Off"
1496 "/Sleep: %d times TcbBusyQueue"
1497 "[%d] !=0 before doze!\n",
1503 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1504 RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! "
1505 "SetRFPowerState8190(): eRfOff"
1506 ": %d times TcbBusyQueue[%d] "
1508 MAX_DOZE_WAITING_TIMES_9x,
1513 PHY_SetRtl8192eRfOff(dev);
1517 RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/"
1520 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1521 ring = &priv->tx_ring[QueueID];
1523 if (skb_queue_len(&ring->queue) == 0) {
1527 RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d"
1528 " times TcbBusyQueue[%d] !=0 b"
1529 "efore doze!\n", (i+1),
1535 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1536 RT_TRACE(COMP_POWER, "\n\n\n SetZebra: "
1537 "RFPowerState8185B(): eRfOff:"
1538 " %d times TcbBusyQueue[%d] "
1540 MAX_DOZE_WAITING_TIMES_9x,
1546 if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC &&
1547 !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1548 NicIFDisableNIC(dev);
1549 RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
1550 } else if (!(pPSC->RegRfPsLevel &
1551 RT_RF_OFF_LEVL_HALT_NIC)) {
1552 PHY_SetRtl8192eRfOff(dev);
1559 RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknown state"
1560 " to set: 0x%X!!!\n", eRFPowerState);
1567 RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n");
1572 priv->rtllib->eRFPowerState = eRFPowerState;
1574 switch (priv->rf_chip) {
1579 RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown "
1585 priv->SetRFPowerStateInProgress = false;
1586 RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n",
1591 bool SetRFPowerState(struct net_device *dev,
1592 enum rt_rf_power_state eRFPowerState)
1594 struct r8192_priv *priv = rtllib_priv(dev);
1596 bool bResult = false;
1598 RT_TRACE(COMP_PS, "---------> SetRFPowerState(): eRFPowerState(%d)\n",
1600 if (eRFPowerState == priv->rtllib->eRFPowerState &&
1601 priv->bHwRfOffAction == 0) {
1602 RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): discard the "
1603 "request for eRFPowerState(%d) is the same.\n",
1608 bResult = SetRFPowerState8190(dev, eRFPowerState);
1610 RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n",
1616 void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation)
1618 struct r8192_priv *priv = rtllib_priv(dev);
1621 switch (Operation) {
1622 case SCAN_OPT_BACKUP:
1623 priv->rtllib->InitialGainHandler(dev, IG_Backup);
1626 case SCAN_OPT_RESTORE:
1627 priv->rtllib->InitialGainHandler(dev, IG_Restore);
1631 RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n");