drivers/staging/rtl8192e/rtl8192e/rtl_dm.h

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * This program is distributed in the hope that it will be useful, but WITHOUT
   5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   7  * more details.
   8  *
   9  * You should have received a copy of the GNU General Public License along with
  10  * this program; if not, write to the Free Software Foundation, Inc.,
  11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  12  *
  13  * The full GNU General Public License is included in this distribution in the
  14  * file called LICENSE.
  15  *
  16  * Contact Information:
  17  * wlanfae <wlanfae@realtek.com>
  18 ******************************************************************************/
  19 #ifndef __R8192UDM_H__
  20 #define __R8192UDM_H__
  21
  22
  23 /*--------------------------Define Parameters-------------------------------*/
  24 #define                 OFDM_Table_Length       19
  25 #define         CCK_Table_length        12
  26
  27 #define         DM_DIG_THRESH_HIGH                                      40
  28 #define         DM_DIG_THRESH_LOW                                       35
  29
  30 #define         DM_FALSEALARM_THRESH_LOW        40
  31 #define         DM_FALSEALARM_THRESH_HIGH       1000
  32
  33 #define         DM_DIG_HIGH_PWR_THRESH_HIGH             75
  34 #define         DM_DIG_HIGH_PWR_THRESH_LOW              70
  35
  36 #define         BW_AUTO_SWITCH_HIGH_LOW                 25
  37 #define         BW_AUTO_SWITCH_LOW_HIGH                 30
  38
  39 #define         DM_check_fsync_time_interval                            500
  40
  41
  42 #define         DM_DIG_BACKOFF                          12
  43 #define         DM_DIG_MAX                                      0x36
  44 #define         DM_DIG_MIN                                      0x1c
  45 #define         DM_DIG_MIN_Netcore                      0x12
  46
  47 #define         DM_DIG_BACKOFF_MAX                      12
  48 #define         DM_DIG_BACKOFF_MIN                      -4
  49
  50 #define         RxPathSelection_SS_TH_low               30
  51 #define         RxPathSelection_diff_TH                 18
  52
  53 #define         RateAdaptiveTH_High                     50
  54 #define         RateAdaptiveTH_Low_20M          30
  55 #define         RateAdaptiveTH_Low_40M          10
  56 #define         VeryLowRSSI                                     15
  57
  58 #define         CTSToSelfTHVal                                  35
  59
  60 #define         WAIotTHVal                                              25
  61
  62 #define         E_FOR_TX_POWER_TRACK           300
  63 #define         TX_POWER_NEAR_FIELD_THRESH_HIGH         68
  64 #define         TX_POWER_NEAR_FIELD_THRESH_LOW          62
  65 #define  TX_POWER_ATHEROAP_THRESH_HIGH     78
  66 #define         TX_POWER_ATHEROAP_THRESH_LOW            72
  67
  68 #define                 Current_Tx_Rate_Reg      0x1e0
  69 #define                 Initial_Tx_Rate_Reg      0x1e1
  70 #define                 Tx_Retry_Count_Reg       0x1ac
  71 #define         RegC38_TH                                20
  72
  73 #define         TX_POWER_NEAR_FIELD_THRESH_LVL2 74
  74 #define         TX_POWER_NEAR_FIELD_THRESH_LVL1 67
  75
  76 #define         TxHighPwrLevel_Normal           0
  77 #define         TxHighPwrLevel_Level1           1
  78 #define         TxHighPwrLevel_Level2           2
  79
  80 #define         DM_Type_ByFW                    0
  81 #define         DM_Type_ByDriver                1
  82
  83 /*--------------------------Define Parameters-------------------------------*/
  84
  85
  86 /*------------------------------Define structure----------------------------*/
  87 struct dig_t {
  88         u8              dig_enable_flag;
  89         u8              dig_algorithm;
  90         u8              dbg_mode;
  91         u8              dig_algorithm_switch;
  92
  93         long            rssi_low_thresh;
  94         long            rssi_high_thresh;
  95
  96         long            rssi_high_power_lowthresh;
  97         long            rssi_high_power_highthresh;
  98
  99         u8              dig_state;
 100         u8              dig_highpwr_state;
 101         u8              CurSTAConnectState;
 102         u8              PreSTAConnectState;
 103
 104         u8              curpd_thstate;
 105         u8              prepd_thstate;
 106         u8              curcs_ratio_state;
 107         u8              precs_ratio_state;
 108
 109         u32             pre_ig_value;
 110         u32             cur_ig_value;
 111
 112         u8              backoff_val;
 113         u8              rx_gain_range_max;
 114         u8              rx_gain_range_min;
 115
 116         long            rssi_val;
 117 };
 118
 119 enum dm_dig_sta {
 120         DM_STA_DIG_OFF = 0,
 121         DM_STA_DIG_ON,
 122         DM_STA_DIG_MAX
 123 };
 124
 125
 126 enum dm_ratr_sta {
 127         DM_RATR_STA_HIGH = 0,
 128         DM_RATR_STA_MIDDLE = 1,
 129         DM_RATR_STA_LOW = 2,
 130         DM_RATR_STA_MAX
 131 };
 132
 133 enum dm_dig_op_sta {
 134         DIG_TYPE_THRESH_HIGH    = 0,
 135         DIG_TYPE_THRESH_LOW     = 1,
 136         DIG_TYPE_THRESH_HIGHPWR_HIGH    = 2,
 137         DIG_TYPE_THRESH_HIGHPWR_LOW     = 3,
 138         DIG_TYPE_DBG_MODE                               = 4,
 139         DIG_TYPE_RSSI                                           = 5,
 140         DIG_TYPE_ALGORITHM                              = 6,
 141         DIG_TYPE_BACKOFF                                        = 7,
 142         DIG_TYPE_PWDB_FACTOR                    = 8,
 143         DIG_TYPE_RX_GAIN_MIN                            = 9,
 144         DIG_TYPE_RX_GAIN_MAX                            = 10,
 145         DIG_TYPE_ENABLE                 = 20,
 146         DIG_TYPE_DISABLE                = 30,
 147         DIG_OP_TYPE_MAX
 148 };
 149
 150 enum dm_dig_alg {
 151         DIG_ALGO_BY_FALSE_ALARM = 0,
 152         DIG_ALGO_BY_RSSI        = 1,
 153         DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM = 2,
 154         DIG_ALGO_BY_TOW_PORT = 3,
 155         DIG_ALGO_MAX
 156 };
 157
 158 enum dm_dig_connect {
 159         DIG_STA_DISCONNECT = 0,
 160         DIG_STA_CONNECT = 1,
 161         DIG_STA_BEFORE_CONNECT = 2,
 162         DIG_AP_DISCONNECT = 3,
 163         DIG_AP_CONNECT = 4,
 164         DIG_AP_ADD_STATION = 5,
 165         DIG_CONNECT_MAX
 166 };
 167
 168 enum dm_dig_pd_th {
 169         DIG_PD_AT_LOW_POWER = 0,
 170         DIG_PD_AT_NORMAL_POWER = 1,
 171         DIG_PD_AT_HIGH_POWER = 2,
 172         DIG_PD_MAX
 173 };
 174
 175 enum dm_dig_cs_ratio {
 176         DIG_CS_RATIO_LOWER = 0,
 177         DIG_CS_RATIO_HIGHER = 1,
 178         DIG_CS_MAX
 179 };
 180
 181 struct drx_path_sel {
 182         u8              Enable;
 183         u8              DbgMode;
 184         u8              cck_method;
 185         u8              cck_Rx_path;
 186
 187         u8              SS_TH_low;
 188         u8              diff_TH;
 189         u8              disabledRF;
 190         u8              reserved;
 191
 192         u8              rf_rssi[4];
 193         u8              rf_enable_rssi_th[4];
 194         long            cck_pwdb_sta[4];
 195 };
 196
 197 enum dm_cck_rx_path_method {
 198         CCK_Rx_Version_1 = 0,
 199         CCK_Rx_Version_2 = 1,
 200         CCK_Rx_Version_MAX
 201 };
 202
 203
 204 enum dm_dbg {
 205         DM_DBG_OFF = 0,
 206         DM_DBG_ON = 1,
 207         DM_DBG_MAX
 208 };
 209
 210 struct dcmd_txcmd {
 211         u32     Op;
 212         u32     Length;
 213         u32     Value;
 214 };
 215 /*------------------------------Define structure----------------------------*/
 216
 217
 218 /*------------------------Export global variable----------------------------*/
 219 extern  struct dig_t dm_digtable;
 220 extern struct drx_path_sel DM_RxPathSelTable;
 221
 222 /* Pre-calculated gain tables */
 223 extern const u32 dm_tx_bb_gain[TxBBGainTableLength];
 224 extern const u8 dm_cck_tx_bb_gain[CCKTxBBGainTableLength][8];
 225 extern const u8 dm_cck_tx_bb_gain_ch14[CCKTxBBGainTableLength][8];
 226 /* Maps table index to iq amplify gain (dB, 12 to -24dB) */
 227 #define dm_tx_bb_gain_idx_to_amplify(idx) (-idx + 12)
 228
 229 /*------------------------Export global variable----------------------------*/
 230
 231
 232 /*--------------------------Exported Function prototype---------------------*/
 233 /*--------------------------Exported Function prototype---------------------*/
 234
 235 extern  void    init_hal_dm(struct net_device *dev);
 236 extern  void deinit_hal_dm(struct net_device *dev);
 237
 238 extern void hal_dm_watchdog(struct net_device *dev);
 239
 240
 241 extern  void    init_rate_adaptive(struct net_device *dev);
 242 extern  void    dm_txpower_trackingcallback(void *data);
 243
 244 extern  void dm_cck_txpower_adjust(struct net_device *dev, bool binch14);
 245
 246 extern  void    dm_restore_dynamic_mechanism_state(struct net_device *dev);
 247 extern  void    dm_backup_dynamic_mechanism_state(struct net_device *dev);
 248 extern  void    dm_init_edca_turbo(struct net_device *dev);
 249 extern  void    dm_rf_pathcheck_workitemcallback(void *data);
 250 extern  void dm_fsync_timer_callback(unsigned long data);
 251 extern  void dm_check_fsync(struct net_device *dev);
 252 extern  void dm_initialize_txpower_tracking(struct net_device *dev);
 253 extern  void    dm_CheckRfCtrlGPIO(void *data);
 254 #endif  /*__R8192UDM_H__ */