drivers/staging/rtl8192ee/rtl8192ee/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "dm.h"
  37 #include "fw.h"
  38 #include "led.h"
  39 #include "hw.h"
  40 #include "pwrseqcmd.h"
  41 #include "pwrseq.h"
  42
  43 #define LLT_CONFIG      5
  44
  45 static void _rtl92ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  46                                       u8 set_bits, u8 clear_bits)
  47 {
  48         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  49         struct rtl_priv *rtlpriv = rtl_priv(hw);
  50
  51         rtlpci->reg_bcn_ctrl_val |= set_bits;
  52         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  53
  54         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  55 }
  56
  57 static void _rtl92ee_stop_tx_beacon(struct ieee80211_hw *hw)
  58 {
  59         struct rtl_priv *rtlpriv = rtl_priv(hw);
  60         u8 tmp;
  61
  62         tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  63         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp & (~BIT(6)));
  64         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  65         tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  66         tmp &= ~(BIT(0));
  67         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp);
  68 }
  69
  70 static void _rtl92ee_resume_tx_beacon(struct ieee80211_hw *hw)
  71 {
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73         u8 tmp;
  74
  75         tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  76         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp | BIT(6));
  77         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  78         tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  79         tmp |= BIT(0);
  80         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp);
  81 }
  82
  83 static void _rtl92ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
  84 {
  85         _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
  86 }
  87
  88 static void _rtl92ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
  89 {
  90         struct rtl_priv *rtlpriv = rtl_priv(hw);
  91         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  92         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  93
  94         while (skb_queue_len(&ring->queue)) {
  95                 struct rtl_tx_buffer_desc *entry =
  96                                                 &ring->buffer_desc[ring->idx];
  97                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  98
  99                 pci_unmap_single(rtlpci->pdev,
 100                                  rtlpriv->cfg->ops->get_desc(
 101                                  (u8 *) entry, true, HW_DESC_TXBUFF_ADDR),
 102                                  skb->len, PCI_DMA_TODEVICE);
 103                 kfree_skb(skb);
 104                 ring->idx = (ring->idx + 1) % ring->entries;
 105         }
 106
 107 }
 108 static void _rtl92ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
 109 {
 110         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
 111 }
 112
 113 static void _rtl92ee_set_fw_clock_on(struct ieee80211_hw *hw,
 114         u8 rpwm_val, bool b_need_turn_off_ckk)
 115 {
 116         struct rtl_priv *rtlpriv = rtl_priv(hw);
 117         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 118         bool b_support_remote_wake_up;
 119         u32 count = 0 , isr_regaddr , content;
 120         bool b_schedule_timer = b_need_turn_off_ckk;
 121         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 122                                       (u8 *) (&b_support_remote_wake_up));
 123
 124         if (!rtlhal->bfw_ready)
 125                 return;
 126         if (!rtlpriv->psc.b_fw_current_inpsmode)
 127                 return;
 128
 129         while (1) {
 130                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 131                 if (rtlhal->bfw_clk_change_in_progress) {
 132                         while (rtlhal->bfw_clk_change_in_progress) {
 133                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 134                                 count++;
 135                                 udelay(100);
 136                                 if (count > 1000)
 137                                         return;
 138                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 139                         }
 140                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 141                 } else {
 142                         rtlhal->bfw_clk_change_in_progress = false;
 143                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 144                         break;
 145                 }
 146         }
 147
 148         if (IS_IN_LOW_POWER_STATE_92E(rtlhal->fw_ps_state)) {
 149                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 150                                               (u8 *) (&rpwm_val));
 151                 if (FW_PS_IS_ACK(rpwm_val)) {
 152                         isr_regaddr = REG_HISR;
 153                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 154                         while (!(content & IMR_CPWM) && (count < 500)) {
 155                                 udelay(50);
 156                                 count++;
 157                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 158                         }
 159
 160                         if (content & IMR_CPWM) {
 161                                 rtl_write_word(rtlpriv , isr_regaddr, 0x0100);
 162                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_92E;
 163                                 RT_TRACE(COMP_POWER, DBG_LOUD,
 164                                          "Receive CPWM INT!!! PSState = %X\n",
 165                                          rtlhal->fw_ps_state);
 166                         }
 167                 }
 168
 169                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 170                 rtlhal->bfw_clk_change_in_progress = false;
 171                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 172                 if (b_schedule_timer) {
 173                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 174                                   jiffies + MSECS(10));
 175                 }
 176
 177         } else  {
 178                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 179                 rtlhal->bfw_clk_change_in_progress = false;
 180                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 181         }
 182
 183
 184 }
 185
 186 static void _rtl92ee_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
 187 {
 188         struct rtl_priv *rtlpriv = rtl_priv(hw);
 189         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 190         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 191         struct rtl8192_tx_ring *ring;
 192         enum rf_pwrstate rtstate;
 193         bool b_schedule_timer = false;
 194         u8 queue;
 195
 196         if (!rtlhal->bfw_ready)
 197                 return;
 198         if (!rtlpriv->psc.b_fw_current_inpsmode)
 199                 return;
 200         if (!rtlhal->ballow_sw_to_change_hwclc)
 201                 return;
 202
 203         rtlpriv->cfg->ops->get_hw_reg(hw , HW_VAR_RF_STATE , (u8 *)(&rtstate));
 204         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 205                 return;
 206
 207         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 208                 ring = &rtlpci->tx_ring[queue];
 209                 if (skb_queue_len(&ring->queue)) {
 210                         b_schedule_timer = true;
 211                         break;
 212                 }
 213         }
 214
 215         if (b_schedule_timer) {
 216                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 217                           jiffies + MSECS(10));
 218                 return;
 219         }
 220
 221         if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
 222                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 223                 if (!rtlhal->bfw_clk_change_in_progress) {
 224                         rtlhal->bfw_clk_change_in_progress = true;
 225                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 226                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 227                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 228                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 229                                                       (u8 *) (&rpwm_val));
 230                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 231                         rtlhal->bfw_clk_change_in_progress = false;
 232                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 233                 } else {
 234                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 235                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 236                                   jiffies + MSECS(10));
 237                 }
 238         }
 239 }
 240
 241 static void _rtl92ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 242 {
 243         u8 rpwm_val = 0;
 244         rpwm_val |= (FW_PS_STATE_RF_OFF_92E | FW_PS_ACK);
 245         _rtl92ee_set_fw_clock_on(hw, rpwm_val, true);
 246 }
 247
 248 static void _rtl92ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
 249 {
 250         u8 rpwm_val = 0;
 251         rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR;
 252         _rtl92ee_set_fw_clock_off(hw, rpwm_val);
 253 }
 254 void rtl92ee_fw_clk_off_timer_callback(unsigned long data)
 255 {
 256         struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
 257
 258         _rtl92ee_set_fw_ps_rf_off_low_power(hw);
 259 }
 260
 261 static void _rtl92ee_fwlps_leave(struct ieee80211_hw *hw)
 262 {
 263         struct rtl_priv *rtlpriv = rtl_priv(hw);
 264         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 265         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 266         bool b_fw_current_inps = false;
 267         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 268
 269         if (ppsc->b_low_power_enable) {
 270                 rpwm_val = (FW_PS_STATE_ALL_ON_92E | FW_PS_ACK);/* RF on */
 271                 _rtl92ee_set_fw_clock_on(hw, rpwm_val, false);
 272                 rtlhal->ballow_sw_to_change_hwclc = false;
 273                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 274                                               (u8 *) (&fw_pwrmode));
 275                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 276                                               (u8 *) (&b_fw_current_inps));
 277         } else {
 278                 rpwm_val = FW_PS_STATE_ALL_ON_92E;      /* RF on */
 279                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 280                                               (u8 *) (&rpwm_val));
 281                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 282                                               (u8 *) (&fw_pwrmode));
 283                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 284                                               (u8 *) (&b_fw_current_inps));
 285         }
 286 }
 287
 288 static void _rtl92ee_fwlps_enter(struct ieee80211_hw *hw)
 289 {
 290         struct rtl_priv *rtlpriv = rtl_priv(hw);
 291         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 292         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 293         bool b_fw_current_inps = true;
 294         u8 rpwm_val;
 295
 296         if (ppsc->b_low_power_enable) {
 297                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR;  /* RF off */
 298                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 299                                               (u8 *) (&b_fw_current_inps));
 300                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 301                                               (u8 *) (&ppsc->fwctrl_psmode));
 302                 rtlhal->ballow_sw_to_change_hwclc = true;
 303                 _rtl92ee_set_fw_clock_off(hw, rpwm_val);
 304         } else {
 305                 rpwm_val = FW_PS_STATE_RF_OFF_92E;      /* RF off */
 306                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 307                                               (u8 *) (&b_fw_current_inps));
 308                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 309                                               (u8 *) (&ppsc->fwctrl_psmode));
 310                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 311                                               (u8 *) (&rpwm_val));
 312         }
 313 }
 314
 315 void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 316 {
 317         struct rtl_priv *rtlpriv = rtl_priv(hw);
 318         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 319         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 320
 321         switch (variable) {
 322         case HW_VAR_RCR:
 323                 *((u32 *) (val)) = rtlpci->receive_config;
 324                 break;
 325         case HW_VAR_RF_STATE:
 326                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 327                 break;
 328         case HW_VAR_FWLPS_RF_ON:{
 329                 enum rf_pwrstate rfState;
 330                 u32 val_rcr;
 331
 332                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
 333                                               (u8 *) (&rfState));
 334                 if (rfState == ERFOFF) {
 335                         *((bool *) (val)) = true;
 336                 } else {
 337                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 338                         val_rcr &= 0x00070000;
 339                         if (val_rcr)
 340                                 *((bool *) (val)) = false;
 341                         else
 342                                 *((bool *) (val)) = true;
 343                 }
 344                 break; }
 345         case HW_VAR_FW_PSMODE_STATUS:
 346                 *((bool *) (val)) = ppsc->b_fw_current_inpsmode;
 347                 break;
 348         case HW_VAR_CORRECT_TSF:{
 349                 u64 tsf;
 350                 u32 *ptsf_low = (u32 *) &tsf;
 351                 u32 *ptsf_high = ((u32 *) &tsf) + 1;
 352
 353                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 354                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 355
 356                 *((u64 *) (val)) = tsf;
 357
 358                 break; }
 359         default:
 360                 RT_TRACE(COMP_ERR, DBG_LOUD, "switch case not processed %x\n",
 361                          variable);
 362                 break;
 363         }
 364 }
 365
 366 static void _rtl92ee_download_rsvd_page(struct ieee80211_hw *hw)
 367 {
 368         struct rtl_priv *rtlpriv = rtl_priv(hw);
 369         u8 tmp_regcr, tmp_reg422;
 370         u8 bcnvalid_reg, txbc_reg;
 371         u8 count = 0, dlbcn_count = 0;
 372         bool b_recover = false;
 373
 374         /*Set REG_CR bit 8. DMA beacon by SW.*/
 375         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 376         rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr | BIT(0));
 377
 378         /* Disable Hw protection for a time which revserd for Hw sending beacon.
 379          * Fix download reserved page packet fail
 380          * that access collision with the protection time.
 381          * 2010.05.11. Added by tynli. */
 382         _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 383         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
 384
 385         /* Set FWHW_TXQ_CTRL 0x422[6]= 0 to
 386          * tell Hw the packet is not a real beacon frame.
 387          */
 388         tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 389         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
 390
 391         if (tmp_reg422 & BIT(6))
 392                 b_recover = true;
 393
 394         do {
 395                 /* Clear beacon valid check bit */
 396                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2);
 397                 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2,
 398                                bcnvalid_reg | BIT(0));
 399
 400                 /* Return Beacon TCB */
 401                 _rtl92ee_return_beacon_queue_skb(hw);
 402
 403                 /* download rsvd page */
 404                 rtl92ee_set_fw_rsvdpagepkt(hw, false);
 405
 406                 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3);
 407                 count = 0;
 408                 while ((txbc_reg & BIT(4)) && count < 20) {
 409                         count++;
 410                         udelay(10);
 411                         txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3);
 412                 }
 413                 rtl_write_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3,
 414                                txbc_reg | BIT(4));
 415
 416                 /* check rsvd page download OK. */
 417                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2);
 418                 count = 0;
 419                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 420                         count++;
 421                         udelay(50);
 422                         bcnvalid_reg = rtl_read_byte(rtlpriv,
 423                                                      REG_DWBCN0_CTRL + 2);
 424                 }
 425
 426                 if (bcnvalid_reg & BIT(0))
 427                         rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2, BIT(0));
 428
 429                 dlbcn_count++;
 430         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 431
 432         if (!(bcnvalid_reg & BIT(0)))
 433                 RT_TRACE(COMP_INIT, DBG_LOUD, "Download RSVD page failed!\n");
 434
 435         /* Enable Bcn */
 436         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 437         _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
 438
 439         if (b_recover)
 440                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
 441
 442         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 443         rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr & (~BIT(0)));
 444
 445 }
 446
 447 void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 448 {
 449         struct rtl_priv *rtlpriv = rtl_priv(hw);
 450         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 451         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 452         struct rtl_efuse *efuse = rtl_efuse(rtl_priv(hw));
 453         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 454         u8 idx;
 455
 456         switch (variable) {
 457         case HW_VAR_ETHER_ADDR:{
 458                 for (idx = 0; idx < ETH_ALEN; idx++) {
 459                         rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
 460                 }
 461                 break; }
 462         case HW_VAR_BASIC_RATE:{
 463                 u16 b_rate_cfg = ((u16 *) val)[0];
 464                 b_rate_cfg = b_rate_cfg & 0x15f;
 465                 b_rate_cfg |= 0x01;
 466                 b_rate_cfg = (b_rate_cfg | 0xd) & (~BIT(1));
 467                 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 468                 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
 469                 break; }
 470         case HW_VAR_BSSID:
 471                 for (idx = 0; idx < ETH_ALEN; idx++) {
 472                         rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
 473                 }
 474                 break;
 475         case HW_VAR_SIFS:
 476                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 477                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 478
 479                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 480                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 481
 482                 if (!mac->ht_enable)
 483                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
 484                 else
 485                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 486                                        *((u16 *) val));
 487                 break;
 488         case HW_VAR_SLOT_TIME:{
 489                 u8 e_aci;
 490
 491                 RT_TRACE(COMP_MLME, DBG_TRACE, "HW_VAR_SLOT_TIME %x\n", val[0]);
 492
 493                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 494
 495                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 496                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 497                                                       (u8 *) (&e_aci));
 498                 }
 499                 break; }
 500         case HW_VAR_ACK_PREAMBLE:{
 501                 u8 reg_tmp;
 502                 u8 short_preamble = (bool) (*(u8 *) val);
 503                 reg_tmp = (rtlpriv->mac80211.cur_40_prime_sc) << 5;
 504                 if (short_preamble)
 505                         reg_tmp |= 0x80;
 506                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 507                 rtlpriv->mac80211.short_preamble = short_preamble;
 508                 break; }
 509         case HW_VAR_WPA_CONFIG:
 510                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
 511                 break;
 512         case HW_VAR_AMPDU_FACTOR:{
 513                 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
 514                 u8 fac;
 515                 u8 *reg = NULL;
 516                 u8 i = 0;
 517
 518                 reg = regtoset_normal;
 519
 520                 fac = *((u8 *) val);
 521                 if (fac <= 3) {
 522                         fac = (1 << (fac + 2));
 523                         if (fac > 0xf)
 524                                 fac = 0xf;
 525                                 for (i = 0; i < 4; i++) {
 526                                 if ((reg[i] & 0xf0) > (fac << 4))
 527                                         reg[i] = (reg[i] & 0x0f) | (fac << 4);
 528                                 if ((reg[i] & 0x0f) > fac)
 529                                         reg[i] = (reg[i] & 0xf0) | fac;
 530                                         rtl_write_byte(rtlpriv,
 531                                                        (REG_AGGLEN_LMT + i),
 532                                                        reg[i]);
 533                                 }
 534                                 RT_TRACE(COMP_MLME, DBG_LOUD,
 535                                          "Set HW_VAR_AMPDU_FACTOR:%#x\n", fac);
 536                 }
 537                 break; }
 538         case HW_VAR_AC_PARAM:{
 539                 u8 e_aci = *((u8 *) val);
 540
 541                 if (rtlpci->acm_method != eAcmWay2_SW)
 542                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
 543                                                       (u8 *) (&e_aci));
 544                 break; }
 545         case HW_VAR_ACM_CTRL:{
 546                 u8 e_aci = *((u8 *) val);
 547                 union aci_aifsn *aifs = (union aci_aifsn *)(&(mac->ac[0].aifs));
 548
 549                 u8 acm = aifs->f.acm;
 550                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 551
 552                 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 553
 554                 if (acm) {
 555                         switch (e_aci) {
 556                         case AC0_BE:
 557                                 acm_ctrl |= AcmHw_BeqEn;
 558                                 break;
 559                         case AC2_VI:
 560                                 acm_ctrl |= AcmHw_ViqEn;
 561                                 break;
 562                         case AC3_VO:
 563                                 acm_ctrl |= AcmHw_VoqEn;
 564                                 break;
 565                         default:
 566                                 RT_TRACE(COMP_ERR, DBG_WARNING,
 567                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 568                                          acm);
 569                                 break;
 570                         }
 571                 } else {
 572                         switch (e_aci) {
 573                         case AC0_BE:
 574                                 acm_ctrl &= (~AcmHw_BeqEn);
 575                                 break;
 576                         case AC2_VI:
 577                                 acm_ctrl &= (~AcmHw_ViqEn);
 578                                 break;
 579                         case AC3_VO:
 580                                 acm_ctrl &= (~AcmHw_BeqEn);
 581                                 break;
 582                         default:
 583                                 RT_TRACE(COMP_ERR, DBG_LOUD,
 584                                          "switch case not processed\n");
 585                                 break;
 586                         }
 587                 }
 588
 589                 RT_TRACE(COMP_QOS, DBG_TRACE,
 590                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 591                          acm_ctrl);
 592                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 593                 break; }
 594         case HW_VAR_RCR:{
 595                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
 596                 rtlpci->receive_config = ((u32 *) (val))[0];
 597                 break; }
 598         case HW_VAR_RETRY_LIMIT:{
 599                 u8 retry_limit = ((u8 *) (val))[0];
 600
 601                 rtl_write_word(rtlpriv, REG_RETRY_LIMIT,
 602                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 603                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 604                 break; }
 605         case HW_VAR_DUAL_TSF_RST:
 606                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 607                 break;
 608         case HW_VAR_EFUSE_BYTES:
 609                 efuse->efuse_usedbytes = *((u16 *) val);
 610                 break;
 611         case HW_VAR_EFUSE_USAGE:
 612                 efuse->efuse_usedpercentage = *((u8 *) val);
 613                 break;
 614         case HW_VAR_IO_CMD:
 615                 rtl92ee_phy_set_io_cmd(hw, (*(enum io_type *)val));
 616                 break;
 617         case HW_VAR_SET_RPWM:{
 618                 u8 rpwm_val;
 619
 620                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 621                 udelay(1);
 622
 623                 if (rpwm_val & BIT(7)) {
 624                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *) val));
 625                 } else {
 626                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 627                                        ((*(u8 *) val) | BIT(7)));
 628                 }
 629                 break; }
 630         case HW_VAR_H2C_FW_PWRMODE:
 631                 rtl92ee_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
 632                 break;
 633         case HW_VAR_FW_PSMODE_STATUS:
 634                 ppsc->b_fw_current_inpsmode = *((bool *) val);
 635                 break;
 636         case HW_VAR_RESUME_CLK_ON:
 637                 _rtl92ee_set_fw_ps_rf_on(hw);
 638                 break;
 639         case HW_VAR_FW_LPS_ACTION:{
 640                 bool b_enter_fwlps = *((bool *) val);
 641
 642                 if (b_enter_fwlps)
 643                         _rtl92ee_fwlps_enter(hw);
 644                 else
 645                         _rtl92ee_fwlps_leave(hw);
 646                 break; }
 647         case HW_VAR_H2C_FW_JOINBSSRPT:{
 648                 u8 mstatus = (*(u8 *) val);
 649
 650                 if (mstatus == RT_MEDIA_CONNECT) {
 651                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
 652                         _rtl92ee_download_rsvd_page(hw);
 653                 }
 654                 rtl92ee_set_fw_media_status_rpt_cmd(hw, mstatus);
 655                 break; }
 656         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 657                 rtl92ee_set_p2p_ps_offload_cmd(hw , (*(u8 *) val));
 658                 break;
 659         case HW_VAR_AID:{
 660                 u16 u2btmp;
 661                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 662                 u2btmp &= 0xC000;
 663                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
 664                                (u2btmp | mac->assoc_id));
 665                 break; }
 666         case HW_VAR_CORRECT_TSF:{
 667                 u8 btype_ibss = ((u8 *) (val))[0];
 668
 669                 if (btype_ibss == true)
 670                         _rtl92ee_stop_tx_beacon(hw);
 671
 672                 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 673
 674                 rtl_write_dword(rtlpriv, REG_TSFTR,
 675                                 (u32) (mac->tsf & 0xffffffff));
 676                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 677                                 (u32) ((mac->tsf >> 32) & 0xffffffff));
 678
 679                 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 680
 681                 if (btype_ibss == true)
 682                         _rtl92ee_resume_tx_beacon(hw);
 683                 break; }
 684         case HW_VAR_KEEP_ALIVE: {
 685                 u8 array[2];
 686                 array[0] = 0xff;
 687                 array[1] = *((u8 *)val);
 688                 rtl92ee_fill_h2c_cmd(hw, H2C_92E_KEEP_ALIVE_CTRL, 2, array);
 689                 break; }
 690         default:
 691                 RT_TRACE(COMP_ERR, DBG_LOUD, "switch case not processed %x\n",
 692                          variable);
 693                 break;
 694         }
 695 }
 696
 697 static bool _rtl92ee_llt_table_init(struct ieee80211_hw *hw)
 698 {
 699         struct rtl_priv *rtlpriv = rtl_priv(hw);
 700         u8 txpktbuf_bndy;
 701         u8 u8tmp, testcnt = 0;
 702
 703         txpktbuf_bndy = 0xFA;
 704
 705         rtl_write_dword(rtlpriv, REG_RQPN, 0x80E90808);
 706
 707         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 708         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x3d00 - 1);
 709
 710         rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 1, txpktbuf_bndy);
 711         rtl_write_byte(rtlpriv, REG_DWBCN1_CTRL + 1, txpktbuf_bndy);
 712
 713         rtl_write_byte(rtlpriv, REG_BCNQ_BDNY, txpktbuf_bndy);
 714         rtl_write_byte(rtlpriv, REG_BCNQ1_BDNY, txpktbuf_bndy);
 715
 716         rtl_write_byte(rtlpriv, REG_MGQ_BDNY, txpktbuf_bndy);
 717         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 718
 719         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 720         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 721
 722         u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2);
 723         rtl_write_byte(rtlpriv, REG_AUTO_LLT + 2, u8tmp | BIT(0));
 724
 725         while (u8tmp & BIT(0)) {
 726                 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2);
 727                 udelay(10);
 728                 testcnt++;
 729                 if (testcnt > 10)
 730                         break;
 731         }
 732
 733         return true;
 734 }
 735
 736 static void _rtl92ee_gen_refresh_led_state(struct ieee80211_hw *hw)
 737 {
 738         struct rtl_priv *rtlpriv = rtl_priv(hw);
 739         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 740         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 741         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 742
 743         if (rtlpriv->rtlhal.up_first_time)
 744                 return;
 745
 746         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 747                 rtl92ee_sw_led_on(hw, pLed0);
 748         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 749                 rtl92ee_sw_led_on(hw, pLed0);
 750         else
 751                 rtl92ee_sw_led_off(hw, pLed0);
 752 }
 753
 754 static bool _rtl92ee_init_mac(struct ieee80211_hw *hw)
 755 {
 756         struct rtl_priv *rtlpriv = rtl_priv(hw);
 757         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 758         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 759
 760         u8 bytetmp;
 761         u16 wordtmp;
 762         u32 dwordtmp;
 763
 764         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
 765
 766         dwordtmp = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
 767         if (dwordtmp & BIT(24)) {
 768                 rtl_write_byte(rtlpriv, 0x7c, 0xc3);
 769         } else {
 770                 bytetmp = rtl_read_byte(rtlpriv, 0x16);
 771                 rtl_write_byte(rtlpriv, 0x16, bytetmp | BIT(4) | BIT(6));
 772                 rtl_write_byte(rtlpriv, 0x7c, 0x83);
 773         }
 774         /* 1. 40Mhz crystal source*/
 775         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2);
 776         bytetmp &= 0xfb;
 777         rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp);
 778
 779         dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4);
 780         dwordtmp &= 0xfffffc7f;
 781         rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp);
 782
 783         /* 2. 92E AFE parameter
 784           *MP chip then check version */
 785         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2);
 786         bytetmp &= 0xbf;
 787         rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp);
 788
 789         dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4);
 790         dwordtmp &= 0xffdfffff;
 791         rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp);
 792
 793         /* HW Power on sequence */
 794         if (!rtl92e_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
 795                 PWR_INTF_PCI_MSK, Rtl8192E_NIC_ENABLE_FLOW)) {
 796                 RT_TRACE(COMP_INIT, DBG_LOUD,
 797                          "init MAC Fail as rtl92e_hal_pwrseqcmdparsing\n");
 798                 return false;
 799         }
 800
 801         /* Release MAC IO register reset */
 802         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 803         bytetmp = 0xff;
 804         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 805         mdelay(2);
 806         bytetmp = 0x7f;
 807         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 808         mdelay(2);
 809
 810         /* Add for wakeup online */
 811         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
 812         rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
 813         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 814         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
 815         /* Release MAC IO register reset */
 816         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 817
 818         if (!rtlhal->b_mac_func_enable) {
 819                 if (_rtl92ee_llt_table_init(hw) == false) {
 820                         RT_TRACE(COMP_INIT, DBG_LOUD, "LLT table init fail\n");
 821                         return false;
 822                 }
 823         }
 824
 825         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 826         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 827
 828         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 829         wordtmp &= 0xf;
 830         wordtmp |= 0xF5B1;
 831         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 832         /* Reported Tx status from HW for rate adaptive.*/
 833         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 834
 835         /* Set RCR register */
 836         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 837         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
 838
 839         /* Set TCR register */
 840         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 841
 842         /* Set TX/RX descriptor physical address(from OS API). */
 843         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 844                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) &
 845                         DMA_BIT_MASK(32));
 846         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 847                         (u64) rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma &
 848                         DMA_BIT_MASK(32));
 849         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 850                         (u64) rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma &
 851                         DMA_BIT_MASK(32));
 852         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 853                         (u64) rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma &
 854                         DMA_BIT_MASK(32));
 855
 856         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 857                         (u64) rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma &
 858                         DMA_BIT_MASK(32));
 859
 860         dwordtmp = rtl_read_dword(rtlpriv, REG_BEQ_DESA);
 861
 862         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 863                         (u64) rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma &
 864                         DMA_BIT_MASK(32));
 865         rtl_write_dword(rtlpriv, REG_HQ0_DESA,
 866                         (u64) rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma &
 867                         DMA_BIT_MASK(32));
 868
 869         rtl_write_dword(rtlpriv, REG_RX_DESA,
 870                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 871                         DMA_BIT_MASK(32));
 872
 873         /* if we want to support 64 bit DMA, we should set it here,
 874          * but now we do not support 64 bit DMA*/
 875
 876
 877         rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0x3fffffff);
 878
 879         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
 880         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0xF7);
 881
 882         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 883
 884         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 885
 886         rtl_write_word(rtlpriv, REG_MGQ_TXBD_NUM,
 887                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 888         rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM,
 889                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 890         rtl_write_word(rtlpriv, REG_VIQ_TXBD_NUM,
 891                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 892         rtl_write_word(rtlpriv, REG_BEQ_TXBD_NUM,
 893                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 894         rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM,
 895                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 896         rtl_write_word(rtlpriv, REG_BKQ_TXBD_NUM,
 897                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 898         rtl_write_word(rtlpriv, REG_HI0Q_TXBD_NUM,
 899                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 900         rtl_write_word(rtlpriv, REG_HI1Q_TXBD_NUM,
 901                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 902         rtl_write_word(rtlpriv, REG_HI2Q_TXBD_NUM,
 903                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 904         rtl_write_word(rtlpriv, REG_HI3Q_TXBD_NUM,
 905                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 906         rtl_write_word(rtlpriv, REG_HI4Q_TXBD_NUM,
 907                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 908         rtl_write_word(rtlpriv, REG_HI5Q_TXBD_NUM,
 909                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 910         rtl_write_word(rtlpriv, REG_HI6Q_TXBD_NUM,
 911                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 912         rtl_write_word(rtlpriv, REG_HI7Q_TXBD_NUM,
 913                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 914         /*Rx*/
 915 #if (DMA_IS_64BIT == 1)
 916         rtl_write_word(rtlpriv, REG_RX_RXBD_NUM,
 917                        RX_DESC_NUM_92E |
 918                        ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x8000);
 919 #else
 920         rtl_write_word(rtlpriv, REG_RX_RXBD_NUM,
 921                        RX_DESC_NUM_92E |
 922                        ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x0000);
 923 #endif
 924
 925         rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0XFFFFFFFF);
 926
 927         _rtl92ee_gen_refresh_led_state(hw);
 928         return true;
 929 }
 930
 931 static void _rtl92ee_hw_configure(struct ieee80211_hw *hw)
 932 {
 933         struct rtl_priv *rtlpriv = rtl_priv(hw);
 934         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 935         u32 reg_rrsr;
 936
 937         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 938         /* Init value for RRSR. */
 939         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
 940
 941         /* ARFB table 9 for 11ac 5G 2SS */
 942         rtl_write_dword(rtlpriv, REG_ARFR0, 0x00000010);
 943         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0x3e0ff000);
 944
 945         /* ARFB table 10 for 11ac 5G 1SS */
 946         rtl_write_dword(rtlpriv, REG_ARFR1, 0x00000010);
 947         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x000ff000);
 948
 949         /* Set SLOT time */
 950         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 951
 952         /* CF-End setting. */
 953         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 954
 955         /* Set retry limit */
 956         rtl_write_word(rtlpriv, REG_RETRY_LIMIT, 0x0707);
 957
 958         /* BAR settings */
 959         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x0201ffff);
 960
 961         /* Set Data / Response auto rate fallack retry count */
 962         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 963         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 964         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 965         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 966
 967         /* Beacon related, for rate adaptive */
 968         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 969         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
 970
 971         rtlpci->reg_bcn_ctrl_val = 0x1d;
 972         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 973
 974         /* Marked out by Bruce, 2010-09-09.
 975          * This register is configured for the 2nd Beacon (multiple BSSID).
 976          * We shall disable this register if we only support 1 BSSID.
 977          * vivi guess 92d also need this, also 92d now doesnot set this reg
 978          */
 979         rtl_write_byte(rtlpriv, REG_BCN_CTRL_1, 0);
 980
 981         /* TBTT prohibit hold time. Suggested by designer TimChen. */
 982         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1 , 0xff); /* 8 ms */
 983
 984         rtl_write_byte(rtlpriv, REG_PIFS, 0);
 985         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 986
 987         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
 988         rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x08ff);
 989
 990         /* For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
 991         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 992
 993         /* ACKTO for IOT issue. */
 994         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 995
 996         /* Set Spec SIFS (used in NAV) */
 997         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x100a);
 998         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x100a);
 999
1000         /* Set SIFS for CCK */
1001         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x100a);
1002
1003         /* Set SIFS for OFDM */
1004         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x100a);
1005
1006         /* Note Data sheet don't define */
1007         rtl_write_word(rtlpriv, 0x4C7, 0x80);
1008
1009         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1010
1011         rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1717);
1012
1013         /* Set Multicast Address. 2009.01.07. by tynli. */
1014         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
1015         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
1016 }
1017
1018 static void _rtl92ee_enable_aspm_back_door(struct ieee80211_hw *hw)
1019 {
1020         struct rtl_priv *rtlpriv = rtl_priv(hw);
1021         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1022         u32 tmp32 = 0, count = 0;
1023         u8 tmp8 = 0;
1024
1025         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x78);
1026         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1027         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1028         count = 0;
1029         while (tmp8 && count < 20) {
1030                 udelay(10);
1031                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1032                 count++;
1033         }
1034
1035         if (0 == tmp8) {
1036                 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1037                 if ((tmp32 & 0xff00) != 0x2000) {
1038                         tmp32 &= 0xffff00ff;
1039                         rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1040                                         tmp32 | BIT(13));
1041                         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf078);
1042                         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1043
1044                         tmp8 = rtl_read_byte(rtlpriv , REG_BACKDOOR_DBI_DATA + 2);
1045                         count = 0;
1046                         while (tmp8 && count < 20) {
1047                                 udelay(10);
1048                                 tmp8 = rtl_read_byte(rtlpriv,
1049                                                      REG_BACKDOOR_DBI_DATA + 2);
1050                                 count++;
1051                         }
1052                 }
1053         }
1054
1055         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x70c);
1056         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1057         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1058         count = 0;
1059         while (tmp8 && count < 20) {
1060                 udelay(10);
1061                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1062                 count++;
1063         }
1064         if (0 == tmp8) {
1065                 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1066                 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1067                                 tmp32 | BIT(31));
1068                 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf70c);
1069                 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1070         }
1071
1072         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1073         count = 0;
1074         while (tmp8 && count < 20) {
1075                 udelay(10);
1076                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1077                 count++;
1078         }
1079
1080
1081         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x718);
1082         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1083         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1084         count = 0;
1085         while (tmp8 && count < 20) {
1086                 udelay(10);
1087                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1088                 count++;
1089         }
1090         if (ppsc->b_support_backdoor || (0 == tmp8)) {
1091                 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1092                 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1093                                 tmp32 | BIT(11) | BIT(12));
1094                 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf718);
1095                 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1096         }
1097         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1098         count = 0;
1099         while (tmp8 && count < 20) {
1100                 udelay(10);
1101                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1102                 count++;
1103         }
1104 }
1105
1106 void rtl92ee_enable_hw_security_config(struct ieee80211_hw *hw)
1107 {
1108         struct rtl_priv *rtlpriv = rtl_priv(hw);
1109         u8 sec_reg_value;
1110         u8 tmp;
1111
1112         RT_TRACE(COMP_INIT, DBG_DMESG,
1113                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1114                  rtlpriv->sec.pairwise_enc_algorithm,
1115                  rtlpriv->sec.group_enc_algorithm);
1116
1117         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1118                 RT_TRACE(COMP_SEC, DBG_DMESG, "not open hw encryption\n");
1119                 return;
1120         }
1121
1122         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
1123
1124         if (rtlpriv->sec.use_defaultkey) {
1125                 sec_reg_value |= SCR_TxUseDK;
1126                 sec_reg_value |= SCR_RxUseDK;
1127         }
1128
1129         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1130
1131         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1132         rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1133
1134         RT_TRACE(COMP_SEC, DBG_DMESG, "The SECR-value %x\n", sec_reg_value);
1135
1136         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1137
1138 }
1139
1140 int rtl92ee_hw_init(struct ieee80211_hw *hw)
1141 {
1142         struct rtl_priv *rtlpriv = rtl_priv(hw);
1143         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1144         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1145         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1146         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1147         bool rtstatus = true;
1148         int err = 0;
1149         u8 tmp_u1b , u1byte;
1150         u32 tmp_u4b;
1151
1152         RT_TRACE(COMP_INIT, DBG_LOUD, " Rtl8192EE hw init\n");
1153         rtlpriv->rtlhal.being_init_adapter = true;
1154         rtlpriv->intf_ops->disable_aspm(hw);
1155
1156         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1157         u1byte = rtl_read_byte(rtlpriv, REG_CR);
1158         if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1159                 rtlhal->b_mac_func_enable = true;
1160         } else {
1161                 rtlhal->b_mac_func_enable = false;
1162                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E;
1163         }
1164
1165         rtstatus = _rtl92ee_init_mac(hw);
1166
1167         rtl_write_byte(rtlpriv, 0x577, 0x03);
1168
1169         /*for Crystal 40 Mhz setting */
1170         rtl_write_byte(rtlpriv, REG_AFE_CTRL4, 0x2A);
1171         rtl_write_byte(rtlpriv, REG_AFE_CTRL4 + 1, 0x00);
1172         rtl_write_byte(rtlpriv, REG_AFE_CTRL2, 0x83);
1173
1174         /*Forced the antenna b to wifi */
1175         if (rtlpriv->btcoexist.btc_info.btcoexist == 1) {
1176                 rtl_write_byte(rtlpriv, 0x64, 0);
1177                 rtl_write_byte(rtlpriv, 0x65, 1);
1178         }
1179         if (rtstatus != true) {
1180                 RT_TRACE(COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1181                 err = 1;
1182                 return err;
1183         }
1184         rtlhal->rx_tag = 0;
1185         rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, 0x8000);
1186         err = rtl92ee_download_fw(hw , false);
1187         if (err) {
1188                 RT_TRACE(COMP_ERR, DBG_WARNING,
1189                          "Failed to download FW. Init HW without FW now..\n");
1190                 err = 1;
1191                 rtlhal->bfw_ready = false;
1192                 return err;
1193         } else {
1194                 rtlhal->bfw_ready = true;
1195         }
1196         /*fw related variable initialize */
1197         ppsc->b_fw_current_inpsmode = false;
1198         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E;
1199         rtlhal->bfw_clk_change_in_progress = false;
1200         rtlhal->ballow_sw_to_change_hwclc = false;
1201         rtlhal->last_hmeboxnum = 0;
1202
1203
1204         rtl92ee_phy_mac_config(hw);
1205
1206         rtl92ee_phy_bb_config(hw);
1207
1208         rtl92ee_phy_rf_config(hw);
1209
1210         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, RF90_PATH_A,
1211                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1212         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, RF90_PATH_B,
1213                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1214         rtlphy->backup_rf_0x1a = (u32) rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,
1215                                                      RFREG_OFFSET_MASK);
1216         rtlphy->rfreg_chnlval[0] = (rtlphy->rfreg_chnlval[0] & 0xfffff3ff) |
1217                                    BIT(10) | BIT(11);
1218
1219         rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
1220                       rtlphy->rfreg_chnlval[0]);
1221         rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
1222                       rtlphy->rfreg_chnlval[0]);
1223
1224         /*---- Set CCK and OFDM Block "ON"----*/
1225         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1226         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1227
1228         /* Must set this,
1229          * otherwise the rx sensitivity will be very pool. Maddest
1230          */
1231         rtl_set_rfreg(hw, RF90_PATH_A, 0xB1, RFREG_OFFSET_MASK, 0x54418);
1232
1233         /*Set Hardware(MAC default setting.)*/
1234         _rtl92ee_hw_configure(hw);
1235
1236         rtlhal->b_mac_func_enable = true;
1237
1238         stg_rtl_cam_reset_all_entry(hw);
1239         rtl92ee_enable_hw_security_config(hw);
1240
1241         ppsc->rfpwr_state = ERFON;
1242
1243         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1244         _rtl92ee_enable_aspm_back_door(hw);
1245         rtlpriv->intf_ops->enable_aspm(hw);
1246
1247         rtl92ee_bt_hw_init(hw);
1248
1249         rtlpriv->rtlhal.being_init_adapter = false;
1250
1251         if (ppsc->rfpwr_state == ERFON) {
1252                 if (rtlphy->iqk_initialized) {
1253                         rtl92ee_phy_iq_calibrate(hw, true);
1254                 } else {
1255                         rtl92ee_phy_iq_calibrate(hw, false);
1256                         rtlphy->iqk_initialized = true;
1257                 }
1258         }
1259
1260         rtlphy->rfpath_rx_enable[0] = true;
1261         if (rtlphy->rf_type == RF_2T2R)
1262                 rtlphy->rfpath_rx_enable[1] = true;
1263
1264         stg_efuse_one_byte_read(hw, 0x1FA, &tmp_u1b);
1265         if (!(tmp_u1b & BIT(0))) {
1266                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1267                 RT_TRACE(COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1268         }
1269
1270         if ((!(tmp_u1b & BIT(1))) && (rtlphy->rf_type == RF_2T2R)) {
1271                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1272                 RT_TRACE(COMP_INIT, DBG_LOUD, "PA BIAS path B\n");
1273         }
1274
1275         rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
1276
1277         /*Fixed LDPC rx hang issue. */
1278         tmp_u4b = rtl_read_dword(rtlpriv, REG_SYS_SWR_CTRL1);
1279         rtl_write_byte(rtlpriv, REG_SYS_SWR_CTRL2, 0x75);
1280         tmp_u4b =  (tmp_u4b & 0xfff00fff) | (0x7E << 12);
1281         rtl_write_dword(rtlpriv, REG_SYS_SWR_CTRL1, tmp_u4b);
1282
1283         rtl92ee_dm_init(hw);
1284
1285         rtl_write_dword(rtlpriv, 0x4fc, 0);
1286
1287         RT_TRACE(COMP_INIT, DBG_LOUD, "end of Rtl8192EE hw init %x\n", err);
1288         return 0;
1289 }
1290
1291 static enum version_8192e _rtl92ee_read_chip_version(struct ieee80211_hw *hw)
1292 {
1293         struct rtl_priv *rtlpriv = rtl_priv(hw);
1294         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1295         enum version_8192e version = VERSION_UNKNOWN;
1296         u32 value32;
1297
1298         rtlphy->rf_type = RF_2T2R;
1299
1300         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1301         if (value32 & TRP_VAUX_EN)
1302                 version = (enum version_8192e) VERSION_TEST_CHIP_2T2R_8192E;
1303         else
1304                 version = (enum version_8192e) VERSION_NORMAL_CHIP_2T2R_8192E;
1305
1306         RT_TRACE(COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1307                  rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
1308
1309         return version;
1310 }
1311
1312 static int _rtl92ee_set_media_status(struct ieee80211_hw *hw,
1313                                      enum nl80211_iftype type)
1314 {
1315         struct rtl_priv *rtlpriv = rtl_priv(hw);
1316         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1317         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1318         u8 mode = MSR_NOLINK;
1319         bt_msr &= 0xfc;
1320
1321         switch (type) {
1322         case NL80211_IFTYPE_UNSPECIFIED:
1323                 mode = MSR_NOLINK;
1324                 RT_TRACE(COMP_INIT, DBG_TRACE,
1325                          "Set Network type to NO LINK!\n");
1326                 break;
1327         case NL80211_IFTYPE_ADHOC:
1328         case NL80211_IFTYPE_MESH_POINT:
1329                 mode = MSR_ADHOC;
1330                 RT_TRACE(COMP_INIT, DBG_TRACE, "Set Network type to Ad Hoc!\n");
1331                 break;
1332         case NL80211_IFTYPE_STATION:
1333                 mode = MSR_INFRA;
1334                 ledaction = LED_CTL_LINK;
1335                 RT_TRACE(COMP_INIT, DBG_TRACE, "Set Network type to STA!\n");
1336                 break;
1337         case NL80211_IFTYPE_AP:
1338                 mode = MSR_AP;
1339                 ledaction = LED_CTL_LINK;
1340                 RT_TRACE(COMP_INIT, DBG_TRACE, "Set Network type to AP!\n");
1341                 break;
1342         default:
1343                 RT_TRACE(COMP_ERR, DBG_EMERG, "Network type %d not support!\n",
1344                          type);
1345                 return 1;
1346                 break;
1347         }
1348
1349         /* MSR_INFRA == Link in infrastructure network;
1350          * MSR_ADHOC == Link in ad hoc network;
1351          * Therefore, check link state is necessary.
1352          *
1353          * MSR_AP == AP mode; link state is not cared here.
1354          */
1355         if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1356                 mode = MSR_NOLINK;
1357                 ledaction = LED_CTL_NO_LINK;
1358         }
1359
1360         if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1361                 _rtl92ee_stop_tx_beacon(hw);
1362                 _rtl92ee_enable_bcn_sub_func(hw);
1363         } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1364                 _rtl92ee_resume_tx_beacon(hw);
1365                 _rtl92ee_disable_bcn_sub_func(hw);
1366         } else {
1367                 RT_TRACE(COMP_ERR, DBG_WARNING,
1368                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1369                          mode);
1370         }
1371
1372         rtl_write_byte(rtlpriv, (MSR), bt_msr | mode);
1373         rtlpriv->cfg->ops->led_control(hw, ledaction);
1374         if (mode == MSR_AP)
1375                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1376         else
1377                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1378         return 0;
1379 }
1380
1381 void rtl92ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1382 {
1383         struct rtl_priv *rtlpriv = rtl_priv(hw);
1384         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1385         u32 reg_rcr = rtlpci->receive_config;
1386
1387         if (rtlpriv->psc.rfpwr_state != ERFON)
1388                 return;
1389
1390         if (check_bssid == true) {
1391                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1392                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1393                                               (u8 *) (&reg_rcr));
1394                 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1395         } else if (check_bssid == false) {
1396                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1397                 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1398                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1399                                               (u8 *) (&reg_rcr));
1400         }
1401 }
1402
1403 int rtl92ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1404 {
1405         struct rtl_priv *rtlpriv = rtl_priv(hw);
1406
1407         if (_rtl92ee_set_media_status(hw, type))
1408                 return -EOPNOTSUPP;
1409
1410         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1411                 if (type != NL80211_IFTYPE_AP &&
1412                     type != NL80211_IFTYPE_MESH_POINT)
1413                         rtl92ee_set_check_bssid(hw, true);
1414         } else {
1415                 rtl92ee_set_check_bssid(hw, false);
1416         }
1417
1418         return 0;
1419 }
1420
1421 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1422 void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci)
1423 {
1424         struct rtl_priv *rtlpriv = rtl_priv(hw);
1425         rtl92ee_dm_init_edca_turbo(hw);
1426         switch (aci) {
1427         case AC1_BK:
1428                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1429                 break;
1430         case AC0_BE:
1431                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1432                 break;
1433         case AC2_VI:
1434                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1435                 break;
1436         case AC3_VO:
1437                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1438                 break;
1439         default:
1440                 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1441                 break;
1442         }
1443 }
1444
1445 static void rtl92ee_clear_interrupt(struct ieee80211_hw *hw)
1446 {
1447         struct rtl_priv *rtlpriv = rtl_priv(hw);
1448         u32 tmp;
1449
1450         tmp = rtl_read_dword(rtlpriv, REG_HISR);
1451         rtl_write_dword(rtlpriv, REG_HISR, tmp);
1452
1453         tmp = rtl_read_dword(rtlpriv, REG_HISRE);
1454         rtl_write_dword(rtlpriv, REG_HISRE, tmp);
1455
1456         tmp = rtl_read_dword(rtlpriv, REG_HSISR);
1457         rtl_write_dword(rtlpriv, REG_HSISR, tmp);
1458 }
1459
1460 void rtl92ee_enable_interrupt(struct ieee80211_hw *hw)
1461 {
1462         struct rtl_priv *rtlpriv = rtl_priv(hw);
1463         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1464
1465         rtl92ee_clear_interrupt(hw);/*clear it here first*/
1466
1467         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1468         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1469         rtlpci->irq_enabled = true;
1470 }
1471
1472 void rtl92ee_disable_interrupt(struct ieee80211_hw *hw)
1473 {
1474         struct rtl_priv *rtlpriv = rtl_priv(hw);
1475         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1476
1477         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1478         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1479         rtlpci->irq_enabled = false;
1480         /*synchronize_irq(rtlpci->pdev->irq);*/
1481 }
1482
1483 static void _rtl92ee_poweroff_adapter(struct ieee80211_hw *hw)
1484 {
1485         struct rtl_priv *rtlpriv = rtl_priv(hw);
1486         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1487         u8 u1b_tmp;
1488         rtlhal->b_mac_func_enable = false;
1489
1490         RT_TRACE(COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1491
1492         /* Run LPS WL RFOFF flow */
1493         rtl92e_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1494                                  PWR_INTF_PCI_MSK, Rtl8192E_NIC_LPS_ENTER_FLOW);
1495         /* turn off RF */
1496         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1497
1498         /* ==== Reset digital sequence   ======  */
1499         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->bfw_ready)
1500                 rtl92ee_firmware_selfreset(hw);
1501
1502         /* Reset MCU  */
1503         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1504         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1505
1506         /* reset MCU ready status */
1507         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1508
1509         /* HW card disable configuration. */
1510         rtl92e_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1511                                  PWR_INTF_PCI_MSK, Rtl8192E_NIC_DISABLE_FLOW);
1512
1513         /* Reset MCU IO Wrapper */
1514         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1515         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1516         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1517         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0)));
1518
1519         /* lock ISO/CLK/Power control register */
1520         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1521 }
1522
1523 void rtl92ee_card_disable(struct ieee80211_hw *hw)
1524 {
1525         struct rtl_priv *rtlpriv = rtl_priv(hw);
1526         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1527         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1528         enum nl80211_iftype opmode;
1529
1530         RT_TRACE(COMP_INIT, DBG_LOUD, "RTL8192ee card disable\n");
1531
1532         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1533
1534         mac->link_state = MAC80211_NOLINK;
1535         opmode = NL80211_IFTYPE_UNSPECIFIED;
1536
1537         _rtl92ee_set_media_status(hw, opmode);
1538
1539         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1540             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1541                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1542
1543         _rtl92ee_poweroff_adapter(hw);
1544
1545         /* after power off we should do iqk again */
1546         rtlpriv->phy.iqk_initialized = false;
1547 }
1548
1549 void rtl92ee_interrupt_recognized(struct ieee80211_hw *hw,
1550                                   u32 *p_inta, u32 *p_intb)
1551 {
1552         struct rtl_priv *rtlpriv = rtl_priv(hw);
1553         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1554
1555         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1556         rtl_write_dword(rtlpriv, ISR, *p_inta);
1557
1558         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1559         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1560 }
1561
1562 void rtl92ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1563 {
1564
1565         struct rtl_priv *rtlpriv = rtl_priv(hw);
1566         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1567         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1568         u16 bcn_interval, atim_window;
1569
1570         bcn_interval = mac->beacon_interval;
1571         atim_window = 2;        /*FIX MERGE */
1572         rtl92ee_disable_interrupt(hw);
1573         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1574         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1575         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1576         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1577         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1578         rtl_write_byte(rtlpriv, 0x606, 0x30);
1579         rtlpci->reg_bcn_ctrl_val |= BIT(3);
1580         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1581 }
1582
1583 void rtl92ee_set_beacon_interval(struct ieee80211_hw *hw)
1584 {
1585         struct rtl_priv *rtlpriv = rtl_priv(hw);
1586         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1587         u16 bcn_interval = mac->beacon_interval;
1588
1589         RT_TRACE(COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n", bcn_interval);
1590         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1591 }
1592
1593 void rtl92ee_update_interrupt_mask(struct ieee80211_hw *hw,
1594                                    u32 add_msr, u32 rm_msr)
1595 {
1596         struct rtl_priv *rtlpriv = rtl_priv(hw);
1597         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1598
1599         RT_TRACE(COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1600                  add_msr, rm_msr);
1601
1602         if (add_msr)
1603                 rtlpci->irq_mask[0] |= add_msr;
1604         if (rm_msr)
1605                 rtlpci->irq_mask[0] &= (~rm_msr);
1606         rtl92ee_disable_interrupt(hw);
1607         rtl92ee_enable_interrupt(hw);
1608 }
1609
1610 static u8 _rtl92ee_get_chnl_group(u8 chnl)
1611 {
1612         u8 group = 0;
1613
1614         if (chnl <= 14) {
1615                 if (1 <= chnl && chnl <= 2)
1616                         group = 0;
1617                 else if (3 <= chnl && chnl <= 5)
1618                         group = 1;
1619                 else if (6 <= chnl && chnl <= 8)
1620                         group = 2;
1621                 else if (9 <= chnl && chnl <= 11)
1622                         group = 3;
1623                 else if (12 <= chnl && chnl <= 14)
1624                         group = 4;
1625         } else {
1626                 if (36 <= chnl && chnl <= 42)
1627                         group = 0;
1628                 else if (44 <= chnl && chnl <= 48)
1629                         group = 1;
1630                 else if (50 <= chnl && chnl <= 58)
1631                         group = 2;
1632                 else if (60 <= chnl && chnl <= 64)
1633                         group = 3;
1634                 else if (100 <= chnl && chnl <= 106)
1635                         group = 4;
1636                 else if (108 <= chnl && chnl <= 114)
1637                         group = 5;
1638                 else if (116 <= chnl && chnl <= 122)
1639                         group = 6;
1640                 else if (124 <= chnl && chnl <= 130)
1641                         group = 7;
1642                 else if (132 <= chnl && chnl <= 138)
1643                         group = 8;
1644                 else if (140 <= chnl && chnl <= 144)
1645                         group = 9;
1646                 else if (149 <= chnl && chnl <= 155)
1647                         group = 10;
1648                 else if (157 <= chnl && chnl <= 161)
1649                         group = 11;
1650                 else if (165 <= chnl && chnl <= 171)
1651                         group = 12;
1652                 else if (173 <= chnl && chnl <= 177)
1653                         group = 13;
1654         }
1655         return group;
1656 }
1657
1658 static void _rtl8192ee_read_power_value_fromprom(struct ieee80211_hw *hw,
1659                                                  struct txpower_info_2g *pwr2g,
1660                                                  struct txpower_info_5g *pwr5g,
1661                                                  bool autoload_fail, u8 *hwinfo)
1662 {
1663         struct rtl_priv *rtlpriv = rtl_priv(hw);
1664         u32 rf, addr = EEPROM_TX_PWR_INX, group, i = 0;
1665
1666         RT_TRACE(COMP_INIT, DBG_LOUD,
1667                  "hal_ReadPowerValueFromPROM92E(): PROMContent[0x%x]= 0x%x\n",
1668                  (addr + 1), hwinfo[addr + 1]);
1669         if (0xFF == hwinfo[addr+1])  /*YJ, add, 120316*/
1670                 autoload_fail = true;
1671
1672         if (autoload_fail) {
1673                 RT_TRACE(COMP_INIT, DBG_LOUD,
1674                          "auto load fail : Use Default value!\n");
1675                 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) {
1676                         /* 2.4G default value */
1677                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1678                                 pwr2g->index_cck_base[rf][group] = 0x2D;
1679                                 pwr2g->index_bw40_base[rf][group] = 0x2D;
1680                         }
1681                         for (i = 0; i < MAX_TX_COUNT; i++) {
1682                                 if (i == 0) {
1683                                         pwr2g->bw20_diff[rf][0] = 0x02;
1684                                         pwr2g->ofdm_diff[rf][0] = 0x04;
1685                                 } else {
1686                                         pwr2g->bw20_diff[rf][i] = 0xFE;
1687                                         pwr2g->bw40_diff[rf][i] = 0xFE;
1688                                         pwr2g->cck_diff[rf][i] = 0xFE;
1689                                         pwr2g->ofdm_diff[rf][i] = 0xFE;
1690                                 }
1691                         }
1692
1693                         /*5G default value*/
1694                         for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
1695                                 pwr5g->index_bw40_base[rf][group] = 0x2A;
1696
1697                         for (i = 0; i < MAX_TX_COUNT; i++) {
1698                                 if (i == 0) {
1699                                         pwr5g->ofdm_diff[rf][0] = 0x04;
1700                                         pwr5g->bw20_diff[rf][0] = 0x00;
1701                                         pwr5g->bw80_diff[rf][0] = 0xFE;
1702                                         pwr5g->bw160_diff[rf][0] = 0xFE;
1703                                 } else {
1704                                         pwr5g->ofdm_diff[rf][0] = 0xFE;
1705                                         pwr5g->bw20_diff[rf][0] = 0xFE;
1706                                         pwr5g->bw40_diff[rf][0] = 0xFE;
1707                                         pwr5g->bw80_diff[rf][0] = 0xFE;
1708                                         pwr5g->bw160_diff[rf][0] = 0xFE;
1709                                 }
1710                         }
1711                 }
1712                 return;
1713         }
1714
1715         rtl_priv(hw)->efuse.b_txpwr_fromeprom = true;
1716
1717         for (rf = 0 ; rf < MAX_RF_PATH ; rf++) {
1718                 /*2.4G default value*/
1719                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1720                         pwr2g->index_cck_base[rf][group] = hwinfo[addr++];
1721                         if (pwr2g->index_cck_base[rf][group] == 0xFF)
1722                                 pwr2g->index_cck_base[rf][group] = 0x2D;
1723
1724                 }
1725                 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
1726                         pwr2g->index_bw40_base[rf][group] = hwinfo[addr++];
1727                         if (pwr2g->index_bw40_base[rf][group] == 0xFF)
1728                                 pwr2g->index_bw40_base[rf][group] = 0x2D;
1729                 }
1730                 for (i = 0; i < MAX_TX_COUNT; i++) {
1731                         if (i == 0) {
1732                                 pwr2g->bw40_diff[rf][i] = 0;
1733                                 if (hwinfo[addr] == 0xFF) {
1734                                         pwr2g->bw20_diff[rf][i] = 0x02;
1735                                 } else {
1736                                         pwr2g->bw20_diff[rf][i] = (hwinfo[addr]
1737                                                                    & 0xf0) >> 4;
1738                                         if (pwr2g->bw20_diff[rf][i] & BIT(3))
1739                                                 pwr2g->bw20_diff[rf][i] |= 0xF0;
1740                                 }
1741
1742                                 if (hwinfo[addr] == 0xFF) {
1743                                         pwr2g->ofdm_diff[rf][i] = 0x04;
1744                                 } else {
1745                                         pwr2g->ofdm_diff[rf][i] = (hwinfo[addr]
1746                                                                    & 0x0f);
1747                                         if (pwr2g->ofdm_diff[rf][i] & BIT(3))
1748                                                 pwr2g->ofdm_diff[rf][i] |= 0xF0;
1749                                 }
1750                                 pwr2g->cck_diff[rf][i] = 0;
1751                                 addr++;
1752                         } else {
1753                                 if (hwinfo[addr] == 0xFF) {
1754                                         pwr2g->bw40_diff[rf][i] = 0xFE;
1755                                 } else {
1756                                         pwr2g->bw40_diff[rf][i] = (hwinfo[addr]
1757                                                                    & 0xf0) >> 4;
1758                                         if (pwr2g->bw40_diff[rf][i] & BIT(3))
1759                                                 pwr2g->bw40_diff[rf][i] |= 0xF0;
1760                                 }
1761
1762                                 if (hwinfo[addr] == 0xFF) {
1763                                         pwr2g->bw20_diff[rf][i] = 0xFE;
1764                                 } else {
1765                                         pwr2g->bw20_diff[rf][i] = (hwinfo[addr]
1766                                                                    & 0x0f);
1767                                         if (pwr2g->bw20_diff[rf][i] & BIT(3))
1768                                                 pwr2g->bw20_diff[rf][i] |= 0xF0;
1769                                 }
1770                                 addr++;
1771
1772                                 if (hwinfo[addr] == 0xFF) {
1773                                         pwr2g->ofdm_diff[rf][i] = 0xFE;
1774                                 } else {
1775                                         pwr2g->ofdm_diff[rf][i] = (hwinfo[addr]
1776                                                                    & 0xf0) >> 4;
1777                                         if (pwr2g->ofdm_diff[rf][i] & BIT(3))
1778                                                 pwr2g->ofdm_diff[rf][i] |= 0xF0;
1779                                 }
1780
1781                                 if (hwinfo[addr] == 0xFF) {
1782                                         pwr2g->cck_diff[rf][i] = 0xFE;
1783                                 } else {
1784                                         pwr2g->cck_diff[rf][i] = (hwinfo[addr]
1785                                                                   & 0x0f);
1786                                         if (pwr2g->cck_diff[rf][i] & BIT(3))
1787                                                 pwr2g->cck_diff[rf][i] |= 0xF0;
1788                                 }
1789                                 addr++;
1790                         }
1791                 }
1792
1793                 /*5G default value*/
1794                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1795                         pwr5g->index_bw40_base[rf][group] = hwinfo[addr++];
1796                         if (pwr5g->index_bw40_base[rf][group] == 0xFF)
1797                                 pwr5g->index_bw40_base[rf][group] = 0xFE;
1798                 }
1799
1800                 for (i = 0; i < MAX_TX_COUNT; i++) {
1801                         if (i == 0) {
1802                                 pwr5g->bw40_diff[rf][i] = 0;
1803
1804                                 if (hwinfo[addr] == 0xFF) {
1805                                         pwr5g->bw20_diff[rf][i] = 0;
1806                                 } else {
1807                                         pwr5g->bw20_diff[rf][0] = (hwinfo[addr]
1808                                                                    & 0xf0) >> 4;
1809                                         if (pwr5g->bw20_diff[rf][i] & BIT(3))
1810                                                 pwr5g->bw20_diff[rf][i] |= 0xF0;
1811                                 }
1812
1813                                 if (hwinfo[addr] == 0xFF) {
1814                                         pwr5g->ofdm_diff[rf][i] = 0x04;
1815                                 } else {
1816                                         pwr5g->ofdm_diff[rf][0] = (hwinfo[addr]
1817                                                                    & 0x0f);
1818                                         if (pwr5g->ofdm_diff[rf][i] & BIT(3))
1819                                                 pwr5g->ofdm_diff[rf][i] |= 0xF0;
1820                                 }
1821                                 addr++;
1822                         } else {
1823                                 if (hwinfo[addr] == 0xFF) {
1824                                         pwr5g->bw40_diff[rf][i] = 0xFE;
1825                                 } else {
1826                                         pwr5g->bw40_diff[rf][i] = (hwinfo[addr]
1827                                                                   & 0xf0) >> 4;
1828                                         if (pwr5g->bw40_diff[rf][i] & BIT(3))
1829                                         pwr5g->bw40_diff[rf][i] |= 0xF0;
1830                                 }
1831
1832                                 if (hwinfo[addr] == 0xFF) {
1833                                         pwr5g->bw20_diff[rf][i] = 0xFE;
1834                                 } else {
1835                                         pwr5g->bw20_diff[rf][i] = (hwinfo[addr]
1836                                                                    & 0x0f);
1837                                         if (pwr5g->bw20_diff[rf][i] & BIT(3))
1838                                         pwr5g->bw20_diff[rf][i] |= 0xF0;
1839                                 }
1840                                 addr++;
1841                         }
1842                 }
1843
1844                 if (hwinfo[addr] == 0xFF) {
1845                         pwr5g->ofdm_diff[rf][1] = 0xFE;
1846                         pwr5g->ofdm_diff[rf][2] = 0xFE;
1847                 } else {
1848                         pwr5g->ofdm_diff[rf][1] = (hwinfo[addr] & 0xf0) >> 4;
1849                         pwr5g->ofdm_diff[rf][2] = (hwinfo[addr] & 0x0f);
1850                 }
1851                 addr++;
1852
1853                 if (hwinfo[addr] == 0xFF)
1854                         pwr5g->ofdm_diff[rf][3] = 0xFE;
1855                 else
1856                         pwr5g->ofdm_diff[rf][3] = (hwinfo[addr] & 0x0f);
1857                 addr++;
1858
1859                 for (i = 1; i < MAX_TX_COUNT; i++) {
1860                         if (pwr5g->ofdm_diff[rf][i] == 0xFF)
1861                                 pwr5g->ofdm_diff[rf][i] = 0xFE;
1862                         else if (pwr5g->ofdm_diff[rf][i] & BIT(3))
1863                                 pwr5g->ofdm_diff[rf][i] |= 0xF0;
1864                 }
1865
1866                 for (i = 0; i < MAX_TX_COUNT; i++) {
1867                         if (hwinfo[addr] == 0xFF) {
1868                                 pwr5g->bw80_diff[rf][i] = 0xFE;
1869                         } else {
1870                                 pwr5g->bw80_diff[rf][i] = (hwinfo[addr] & 0xf0)
1871                                                           >> 4;
1872                                 if (pwr5g->bw80_diff[rf][i] & BIT(3))
1873                                         pwr5g->bw80_diff[rf][i] |= 0xF0;
1874                         }
1875
1876                         if (hwinfo[addr] == 0xFF) {
1877                                 pwr5g->bw160_diff[rf][i] = 0xFE;
1878                         } else {
1879                                 pwr5g->bw160_diff[rf][i] = (hwinfo[addr] & 0x0f);
1880                                 if (pwr5g->bw160_diff[rf][i] & BIT(3))
1881                                         pwr5g->bw160_diff[rf][i] |= 0xF0;
1882                         }
1883                         addr++;
1884                 }
1885         }
1886 }
1887 static void _rtl92ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1888                                                  bool autoload_fail, u8 *hwinfo)
1889 {
1890         struct rtl_priv *rtlpriv = rtl_priv(hw);
1891         struct rtl_efuse *efu = rtl_efuse(rtl_priv(hw));
1892         struct txpower_info_2g pwr2g;
1893         struct txpower_info_5g pwr5g;
1894         u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
1895                 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
1896                 56, 58, 60, 62, 64, 100, 102, 104, 106,
1897                 108, 110, 112, 114, 116, 118, 120, 122,
1898                 124, 126, 128, 130, 132, 134, 136, 138,
1899                 140, 142, 144, 149, 151, 153, 155, 157,
1900                 159, 161, 163, 165, 167, 168, 169, 171,
1901                 173, 175, 177};
1902         u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {
1903                 42, 58, 106, 122, 138, 155, 171};
1904         u8 rf, idx;
1905         u8 i;
1906
1907         _rtl8192ee_read_power_value_fromprom(hw, &pwr2g, &pwr5g,
1908                                              autoload_fail, hwinfo);
1909
1910         for (rf = 0; rf < MAX_RF_PATH; rf++) {
1911                 for (i = 0; i < 14; i++) {
1912                         idx = _rtl92ee_get_chnl_group(i + 1);
1913
1914                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
1915                                 efu->txpwrlevel_cck[rf][i] =
1916                                                 pwr2g.index_cck_base[rf][5];
1917                                 efu->txpwrlevel_ht40_1s[rf][i] =
1918                                                 pwr2g.index_bw40_base[rf][idx];
1919                         } else {
1920                                 efu->txpwrlevel_cck[rf][i] =
1921                                                 pwr2g.index_cck_base[rf][idx];
1922                                 efu->txpwrlevel_ht40_1s[rf][i] =
1923                                                 pwr2g.index_bw40_base[rf][idx];
1924                         }
1925                 }
1926                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
1927                         idx = _rtl92ee_get_chnl_group(channel5g[i]);
1928                         efu->txpwr_5g_bw40base[rf][i] =
1929                                         pwr5g.index_bw40_base[rf][idx];
1930                 }
1931                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
1932                         u8 upper, lower;
1933                         idx = _rtl92ee_get_chnl_group(channel5g_80m[i]);
1934                         upper = pwr5g.index_bw40_base[rf][idx];
1935                         lower = pwr5g.index_bw40_base[rf][idx + 1];
1936
1937                         efu->txpwr_5g_bw80base[rf][i] = (upper + lower) / 2;
1938                 }
1939                 for (i = 0; i < MAX_TX_COUNT; i++) {
1940                         efu->txpwr_cckdiff[rf][i] = pwr2g.cck_diff[rf][i];
1941                         efu->txpwr_legacyhtdiff[rf][i] = pwr2g.ofdm_diff[rf][i];
1942                         efu->txpwr_ht20diff[rf][i] = pwr2g.bw20_diff[rf][i];
1943                         efu->txpwr_ht40diff[rf][i] = pwr2g.bw40_diff[rf][i];
1944
1945                         efu->txpwr_5g_ofdmdiff[rf][i] = pwr5g.ofdm_diff[rf][i];
1946                         efu->txpwr_5g_bw20diff[rf][i] = pwr5g.bw20_diff[rf][i];
1947                         efu->txpwr_5g_bw40diff[rf][i] = pwr5g.bw40_diff[rf][i];
1948                         efu->txpwr_5g_bw80diff[rf][i] = pwr5g.bw80_diff[rf][i];
1949                 }
1950         }
1951
1952         if (!autoload_fail)
1953                 efu->eeprom_thermalmeter = hwinfo[EEPROM_THERMAL_METER_92E];
1954         else
1955                 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1956
1957         if (efu->eeprom_thermalmeter == 0xff || autoload_fail) {
1958                 efu->b_apk_thermalmeterignore = true;
1959                 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1960         }
1961
1962         efu->thermalmeter[0] = efu->eeprom_thermalmeter;
1963         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1964                 "thermalmeter = 0x%x\n", efu->eeprom_thermalmeter);
1965
1966         if (!autoload_fail) {
1967                 efu->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION_92E]
1968                                          & 0x07;
1969                 if (hwinfo[EEPROM_RF_BOARD_OPTION_92E] == 0xFF)
1970                         efu->eeprom_regulatory = 0;
1971         } else {
1972                 efu->eeprom_regulatory = 0;
1973         }
1974         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1975                 "eeprom_regulatory = 0x%x\n", efu->eeprom_regulatory);
1976 }
1977
1978 static void _rtl92ee_read_adapter_info(struct ieee80211_hw *hw)
1979 {
1980         struct rtl_priv *rtlpriv = rtl_priv(hw);
1981         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1982         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1983         u16 i, usvalue;
1984         u8 hwinfo[HWSET_MAX_SIZE];
1985         u16 eeprom_id;
1986
1987         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1988                 stg_rtl_efuse92e_shadow_map_update(hw);
1989
1990                 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1991                        HWSET_MAX_SIZE);
1992         } else if (rtlefuse->epromtype == EEPROM_93C46) {
1993                 RT_TRACE(COMP_ERR, DBG_EMERG,
1994                          "RTL819X Not boot from eeprom, check it !!\n");
1995                 return;
1996         }  else {
1997                 RT_TRACE(COMP_ERR, DBG_EMERG,
1998                          "boot from neither eeprom nor efuse, check it !!\n");
1999                 return;
2000         }
2001
2002         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, "MAP \n",
2003                       hwinfo, HWSET_MAX_SIZE);
2004
2005         eeprom_id = *((u16 *) &hwinfo[0]);
2006         if (eeprom_id != RTL8192E_EEPROM_ID) {
2007                 RT_TRACE(COMP_ERR, DBG_WARNING, "EEPROM ID(%#x) is invalid!!\n",
2008                          eeprom_id);
2009                 rtlefuse->autoload_failflag = true;
2010         } else {
2011                 RT_TRACE(COMP_INIT, DBG_LOUD, "Autoload OK\n");
2012                 rtlefuse->autoload_failflag = false;
2013         }
2014
2015         if (rtlefuse->autoload_failflag == true)
2016                 return;
2017         /*VID DID SVID SDID*/
2018         rtlefuse->eeprom_vid = *(u16 *) &hwinfo[EEPROM_VID];
2019         rtlefuse->eeprom_did = *(u16 *) &hwinfo[EEPROM_DID];
2020         rtlefuse->eeprom_svid = *(u16 *) &hwinfo[EEPROM_SVID];
2021         rtlefuse->eeprom_smid = *(u16 *) &hwinfo[EEPROM_SMID];
2022         RT_TRACE(COMP_INIT, DBG_LOUD, "EEPROMId = 0x%4x\n", eeprom_id);
2023         RT_TRACE(COMP_INIT, DBG_LOUD, "EEPROM VID = 0x%4x\n",
2024                  rtlefuse->eeprom_vid);
2025         RT_TRACE(COMP_INIT, DBG_LOUD, "EEPROM DID = 0x%4x\n",
2026                  rtlefuse->eeprom_did);
2027         RT_TRACE(COMP_INIT, DBG_LOUD, "EEPROM SVID = 0x%4x\n",
2028                  rtlefuse->eeprom_svid);
2029         RT_TRACE(COMP_INIT, DBG_LOUD, "EEPROM SMID = 0x%4x\n",
2030                  rtlefuse->eeprom_smid);
2031         /*customer ID*/
2032         rtlefuse->eeprom_oemid = *(u8 *) &hwinfo[EEPROM_CUSTOMER_ID];
2033         if (rtlefuse->eeprom_oemid == 0xFF)
2034                 rtlefuse->eeprom_oemid = 0;
2035
2036         RT_TRACE(COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
2037                  rtlefuse->eeprom_oemid);
2038         /*EEPROM version*/
2039         rtlefuse->eeprom_version = *(u8 *) &hwinfo[EEPROM_VERSION];
2040         /*mac address*/
2041         for (i = 0; i < 6; i += 2) {
2042                 usvalue = *(u16 *) &hwinfo[EEPROM_MAC_ADDR + i];
2043                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
2044         }
2045
2046         RT_TRACE(COMP_INIT, DBG_DMESG, "dev_addr: %pM\n", rtlefuse->dev_addr);
2047         /*channel plan */
2048         rtlefuse->eeprom_channelplan = *(u8 *) &hwinfo[EEPROM_CHANNELPLAN];
2049         /* set channel paln to world wide 13 */
2050         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
2051         /*tx power*/
2052         _rtl92ee_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2053                                              hwinfo);
2054
2055         rtl92ee_read_bt_coexist_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2056                                                hwinfo);
2057
2058         /*board type*/
2059         rtlefuse->board_type = (((*(u8 *) &hwinfo[EEPROM_RF_BOARD_OPTION_92E])
2060                                 & 0xE0) >> 5);
2061         if ((*(u8 *) &hwinfo[EEPROM_RF_BOARD_OPTION_92E]) == 0xFF)
2062                 rtlefuse->board_type = 0;
2063
2064         rtlhal->boad_type = rtlefuse->board_type;
2065         /*parse xtal*/
2066         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_92E];
2067         if (hwinfo[EEPROM_XTAL_92E] == 0xFF)
2068                 rtlefuse->crystalcap = 0x20;
2069
2070         /*antenna diversity*/
2071         rtlefuse->antenna_div_type = NO_ANTDIV;
2072         rtlefuse->antenna_div_cfg = 0;
2073
2074         if (rtlhal->oem_id == RT_CID_DEFAULT) {
2075                 switch (rtlefuse->eeprom_oemid) {
2076                 case EEPROM_CID_DEFAULT:
2077                         if (rtlefuse->eeprom_did == 0x818B) {
2078                                 if ((rtlefuse->eeprom_svid == 0x10EC) &&
2079                                     (rtlefuse->eeprom_smid == 0x001B))
2080                                         rtlhal->oem_id = RT_CID_819x_Lenovo;
2081                         } else {
2082                                 rtlhal->oem_id = RT_CID_DEFAULT;
2083                         }
2084                         break;
2085                 default:
2086                         rtlhal->oem_id = RT_CID_DEFAULT;
2087                         break;
2088                 }
2089         }
2090 }
2091
2092 static void _rtl92ee_hal_customized_behavior(struct ieee80211_hw *hw)
2093 {
2094         struct rtl_priv *rtlpriv = rtl_priv(hw);
2095         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2096         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2097
2098         pcipriv->ledctl.bled_opendrain = true;
2099
2100         RT_TRACE(COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
2101                  rtlhal->oem_id);
2102 }
2103
2104 void rtl92ee_read_eeprom_info(struct ieee80211_hw *hw)
2105 {
2106         struct rtl_priv *rtlpriv = rtl_priv(hw);
2107         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2108         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2109         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2110         u8 tmp_u1b;
2111
2112         rtlhal->version = _rtl92ee_read_chip_version(hw);
2113         if (get_rf_type(rtlphy) == RF_1T1R)
2114                 rtlpriv->dm.brfpath_rxenable[0] = true;
2115         else
2116                 rtlpriv->dm.brfpath_rxenable[0] =
2117                     rtlpriv->dm.brfpath_rxenable[1] = true;
2118         RT_TRACE(COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2119                  rtlhal->version);
2120         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2121         if (tmp_u1b & BIT(4)) {
2122                 RT_TRACE(COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2123                 rtlefuse->epromtype = EEPROM_93C46;
2124         } else {
2125                 RT_TRACE(COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2126                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2127         }
2128         if (tmp_u1b & BIT(5)) {
2129                 RT_TRACE(COMP_INIT, DBG_LOUD, "Autoload OK\n");
2130                 rtlefuse->autoload_failflag = false;
2131                 _rtl92ee_read_adapter_info(hw);
2132         } else {
2133                 RT_TRACE(COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2134         }
2135         _rtl92ee_hal_customized_behavior(hw);
2136
2137         rtlphy->rfpath_rx_enable[0] = true;
2138         if (rtlphy->rf_type == RF_2T2R)
2139                 rtlphy->rfpath_rx_enable[1] = true;
2140 }
2141
2142 static u8 _rtl92ee_mrate_idx_to_arfr_id(struct ieee80211_hw *hw, u8 rate_index)
2143 {
2144         u8 ret = 0;
2145
2146         switch (rate_index) {
2147         case RATR_INX_WIRELESS_NGB:
2148                 ret = 0;
2149                 break;
2150         case RATR_INX_WIRELESS_N:
2151         case RATR_INX_WIRELESS_NG:
2152                 ret = 4;
2153                 break;
2154         case RATR_INX_WIRELESS_NB:
2155                 ret = 2;
2156                 break;
2157         case RATR_INX_WIRELESS_GB:
2158                 ret = 6;
2159                 break;
2160         case RATR_INX_WIRELESS_G:
2161                 ret = 7;
2162                 break;
2163         case RATR_INX_WIRELESS_B:
2164                 ret = 8;
2165                 break;
2166         default:
2167                 ret = 0;
2168                 break;
2169         }
2170         return ret;
2171 }
2172
2173 static void rtl92ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2174                                          struct ieee80211_sta *sta,
2175                                          u8 rssi_level)
2176 {
2177         struct rtl_priv *rtlpriv = rtl_priv(hw);
2178         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2179         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2180         struct rtl_sta_info *sta_entry = NULL;
2181         u32 ratr_bitmap;
2182         u8 ratr_index;
2183         u8 b_curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2184                              ? 1 : 0;
2185         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2186                                 1 : 0;
2187         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2188                                 1 : 0;
2189         enum wireless_mode wirelessmode = 0;
2190         bool b_shortgi = false;
2191         u8 rate_mask[7] = {0};
2192         u8 macid = 0;
2193         /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2194         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2195         wirelessmode = sta_entry->wireless_mode;
2196         if (mac->opmode == NL80211_IFTYPE_STATION ||
2197             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2198                 b_curtxbw_40mhz = mac->bw_40;
2199         else if (mac->opmode == NL80211_IFTYPE_AP ||
2200                  mac->opmode == NL80211_IFTYPE_ADHOC)
2201                 macid = sta->aid + 1;
2202
2203         ratr_bitmap = sta->supp_rates[0];
2204         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2205                 ratr_bitmap = 0xfff;
2206
2207         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2208                         sta->ht_cap.mcs.rx_mask[0] << 12);
2209
2210         switch (wirelessmode) {
2211         case WIRELESS_MODE_B:
2212                 ratr_index = RATR_INX_WIRELESS_B;
2213                 if (ratr_bitmap & 0x0000000c)
2214                         ratr_bitmap &= 0x0000000d;
2215                 else
2216                         ratr_bitmap &= 0x0000000f;
2217                 break;
2218         case WIRELESS_MODE_G:
2219                 ratr_index = RATR_INX_WIRELESS_GB;
2220
2221                 if (rssi_level == 1)
2222                         ratr_bitmap &= 0x00000f00;
2223                 else if (rssi_level == 2)
2224                         ratr_bitmap &= 0x00000ff0;
2225                 else
2226                         ratr_bitmap &= 0x00000ff5;
2227                 break;
2228         case WIRELESS_MODE_N_24G:
2229                 if (b_curtxbw_40mhz)
2230                         ratr_index = RATR_INX_WIRELESS_NGB;
2231                 else
2232                         ratr_index = RATR_INX_WIRELESS_NB;
2233
2234                 if (rtlphy->rf_type == RF_1T1R) {
2235                         if (b_curtxbw_40mhz) {
2236                                 if (rssi_level == 1)
2237                                         ratr_bitmap &= 0x000f0000;
2238                                 else if (rssi_level == 2)
2239                                         ratr_bitmap &= 0x000ff000;
2240                                 else
2241                                         ratr_bitmap &= 0x000ff015;
2242                         } else {
2243                                 if (rssi_level == 1)
2244                                         ratr_bitmap &= 0x000f0000;
2245                                 else if (rssi_level == 2)
2246                                         ratr_bitmap &= 0x000ff000;
2247                                 else
2248                                         ratr_bitmap &= 0x000ff005;
2249                         }
2250                 } else {
2251                         if (b_curtxbw_40mhz) {
2252                                 if (rssi_level == 1)
2253                                         ratr_bitmap &= 0x0f8f0000;
2254                                 else if (rssi_level == 2)
2255                                         ratr_bitmap &= 0x0ffff000;
2256                                 else
2257                                         ratr_bitmap &= 0x0ffff015;
2258                         } else {
2259                                 if (rssi_level == 1)
2260                                         ratr_bitmap &= 0x0f8f0000;
2261                                 else if (rssi_level == 2)
2262                                         ratr_bitmap &= 0x0ffff000;
2263                                 else
2264                                         ratr_bitmap &= 0x0ffff005;
2265                         }
2266                 }
2267
2268                 if ((b_curtxbw_40mhz && b_curshortgi_40mhz) ||
2269                     (!b_curtxbw_40mhz && b_curshortgi_20mhz)) {
2270
2271                         if (macid == 0)
2272                                 b_shortgi = true;
2273                         else if (macid == 1)
2274                                 b_shortgi = false;
2275                 }
2276                 break;
2277         default:
2278                 ratr_index = RATR_INX_WIRELESS_NGB;
2279
2280                 if (rtlphy->rf_type == RF_1T1R)
2281                         ratr_bitmap &= 0x000ff0ff;
2282                 else
2283                         ratr_bitmap &= 0x0f8ff0ff;
2284                 break;
2285         }
2286         ratr_index = _rtl92ee_mrate_idx_to_arfr_id(hw, ratr_index);
2287         sta_entry->ratr_index = ratr_index;
2288
2289         RT_TRACE(COMP_RATR, DBG_DMESG, "ratr_bitmap:%x\n", ratr_bitmap);
2290         *(u32 *) &rate_mask = (ratr_bitmap & 0x0fffffff) |
2291                                        (ratr_index << 28);
2292         rate_mask[0] = macid;
2293         rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
2294         rate_mask[2] = b_curtxbw_40mhz;
2295         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2296         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2297         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2298         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2299         RT_TRACE(COMP_RATR, DBG_DMESG,
2300                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2301                  ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1],
2302                  rate_mask[2], rate_mask[3], rate_mask[4],
2303                  rate_mask[5], rate_mask[6]);
2304         rtl92ee_fill_h2c_cmd(hw, H2C_92E_RA_MASK, 7, rate_mask);
2305         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2306 }
2307
2308
2309 void rtl92ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2310                                  struct ieee80211_sta *sta, u8 rssi_level)
2311 {
2312         struct rtl_priv *rtlpriv = rtl_priv(hw);
2313
2314         if (rtlpriv->dm.b_useramask)
2315                 rtl92ee_update_hal_rate_mask(hw, sta, rssi_level);
2316 }
2317
2318 void rtl92ee_update_channel_access_setting(struct ieee80211_hw *hw)
2319 {
2320         struct rtl_priv *rtlpriv = rtl_priv(hw);
2321         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2322         u16 sifs_timer;
2323
2324         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2325                                       (u8 *) &mac->slot_time);
2326         if (!mac->ht_enable)
2327                 sifs_timer = 0x0a0a;
2328         else
2329                 sifs_timer = 0x0e0e;
2330         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *) &sifs_timer);
2331 }
2332
2333 bool rtl92ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2334 {
2335         *valid = 1;
2336         return true;
2337 }
2338
2339 void rtl92ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2340                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2341                      bool is_wepkey, bool clear_all)
2342 {
2343         struct rtl_priv *rtlpriv = rtl_priv(hw);
2344         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2345         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2346         u8 *macaddr = p_macaddr;
2347         u32 entry_id = 0;
2348         bool is_pairwise = false;
2349
2350         static u8 cam_const_addr[4][6] = {
2351                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2352                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2353                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2354                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2355         };
2356         static u8 cam_const_broad[] = {
2357                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2358         };
2359
2360         if (clear_all) {
2361                 u8 idx = 0;
2362                 u8 cam_offset = 0;
2363                 u8 clear_number = 5;
2364
2365                 RT_TRACE(COMP_SEC, DBG_DMESG, "clear_all\n");
2366
2367                 for (idx = 0; idx < clear_number; idx++) {
2368                         stg_rtl_cam_mark_invalid(hw, cam_offset + idx);
2369                         stg_rtl_cam_empty_entry(hw, cam_offset + idx);
2370
2371                         if (idx < 5) {
2372                                 memset(rtlpriv->sec.key_buf[idx], 0,
2373                                        MAX_KEY_LEN);
2374                                 rtlpriv->sec.key_len[idx] = 0;
2375                         }
2376                 }
2377
2378         } else {
2379                 switch (enc_algo) {
2380                 case WEP40_ENCRYPTION:
2381                         enc_algo = CAM_WEP40;
2382                         break;
2383                 case WEP104_ENCRYPTION:
2384                         enc_algo = CAM_WEP104;
2385                         break;
2386                 case TKIP_ENCRYPTION:
2387                         enc_algo = CAM_TKIP;
2388                         break;
2389                 case AESCCMP_ENCRYPTION:
2390                         enc_algo = CAM_AES;
2391                         break;
2392                 default:
2393                         RT_TRACE(COMP_ERR, DBG_LOUD,
2394                                  "switch case not processed\n");
2395                         enc_algo = CAM_TKIP;
2396                         break;
2397                 }
2398
2399                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2400                         macaddr = cam_const_addr[key_index];
2401                         entry_id = key_index;
2402                 } else {
2403                         if (is_group) {
2404                                 macaddr = cam_const_broad;
2405                                 entry_id = key_index;
2406                         } else {
2407                                 if (mac->opmode == NL80211_IFTYPE_AP ||
2408                                     mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2409                                         entry_id = stg_rtl_cam_get_free_entry(hw,
2410                                                                      p_macaddr);
2411                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2412                                                 RT_TRACE(COMP_SEC, DBG_EMERG,
2413                                                          "Can not find free hw security cam entry\n");
2414                                                 return;
2415                                         }
2416                                 } else {
2417                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2418                                 }
2419
2420                                 key_index = PAIRWISE_KEYIDX;
2421                                 is_pairwise = true;
2422                         }
2423                 }
2424
2425                 if (rtlpriv->sec.key_len[key_index] == 0) {
2426                         RT_TRACE(COMP_SEC, DBG_DMESG,
2427                                  "delete one entry, entry_id is %d\n",
2428                                  entry_id);
2429                         if (mac->opmode == NL80211_IFTYPE_AP ||
2430                             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2431                                 stg_rtl_cam_del_entry(hw, p_macaddr);
2432                         stg_rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2433                 } else {
2434                         RT_TRACE(COMP_SEC, DBG_DMESG, "add one entry\n");
2435                         if (is_pairwise) {
2436                                 RT_TRACE(COMP_SEC, DBG_DMESG,
2437                                          "set Pairwise key\n");
2438
2439                                 stg_rtl_cam_add_one_entry(hw, macaddr, key_index,
2440                                                entry_id, enc_algo,
2441                                                CAM_CONFIG_NO_USEDK,
2442                                                rtlpriv->sec.key_buf[key_index]);
2443                         } else {
2444                                 RT_TRACE(COMP_SEC, DBG_DMESG,
2445                                          "set group key\n");
2446
2447                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2448                                         stg_rtl_cam_add_one_entry(hw,
2449                                                 rtlefuse->dev_addr,
2450                                                 PAIRWISE_KEYIDX,
2451                                                 CAM_PAIRWISE_KEY_POSITION,
2452                                                 enc_algo, CAM_CONFIG_NO_USEDK,
2453                                                 rtlpriv->sec.key_buf[entry_id]);
2454                                 }
2455
2456                                 stg_rtl_cam_add_one_entry(hw, macaddr, key_index,
2457                                                 entry_id, enc_algo,
2458                                                 CAM_CONFIG_NO_USEDK,
2459                                                 rtlpriv->sec.key_buf[entry_id]);
2460                         }
2461                 }
2462         }
2463 }
2464
2465 void rtl92ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2466                                             bool auto_load_fail, u8 *hwinfo)
2467 {
2468         struct rtl_priv *rtlpriv = rtl_priv(hw);
2469         u8 value;
2470
2471         if (!auto_load_fail) {
2472                 value = hwinfo[EEPROM_RF_BOARD_OPTION_92E];
2473                 if (((value & 0xe0) >> 5) == 0x1)
2474                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
2475                 else
2476                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
2477
2478                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E;
2479                 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X2;
2480         } else {
2481                 rtlpriv->btcoexist.btc_info.btcoexist = 1;
2482                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E;
2483                 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X1;
2484         }
2485 }
2486
2487 void rtl92ee_bt_reg_init(struct ieee80211_hw *hw)
2488 {
2489         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2490
2491         /* 0:Low, 1:High, 2:From Efuse. */
2492         rtlpcipriv->btcoexist.b_reg_bt_iso = 2;
2493         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2494         rtlpcipriv->btcoexist.b_reg_bt_sco = 3;
2495         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2496         rtlpcipriv->btcoexist.b_reg_bt_sco = 0;
2497 }
2498
2499 void rtl92ee_bt_hw_init(struct ieee80211_hw *hw)
2500 {
2501         struct rtl_priv *rtlpriv = rtl_priv(hw);
2502
2503         if (rtlpriv->cfg->ops->get_btc_status()) {
2504                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2505         }
2506 }
2507
2508 void rtl92ee_suspend(struct ieee80211_hw *hw)
2509 {
2510 }
2511
2512 void rtl92ee_resume(struct ieee80211_hw *hw)
2513 {
2514 }
2515
2516 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
2517 void rtl92ee_allow_all_destaddr(struct ieee80211_hw *hw,
2518                                 bool allow_all_da, bool write_into_reg)
2519 {
2520         struct rtl_priv *rtlpriv = rtl_priv(hw);
2521         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2522
2523         if (allow_all_da)       /* Set BIT0 */
2524                 rtlpci->receive_config |= RCR_AAP;
2525         else                    /* Clear BIT0 */
2526                 rtlpci->receive_config &= ~RCR_AAP;
2527
2528         if (write_into_reg)
2529                 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
2530
2531         RT_TRACE(COMP_TURBO | COMP_INIT, DBG_LOUD,
2532                  "receive_config = 0x%08X, write_into_reg =%d\n",
2533                  rtlpci->receive_config, write_into_reg);
2534 }