1 #ifndef __RTL92E_PWRSEQCMD_H__
2 #define __RTL92E_PWRSEQCMD_H__
5 /*---------------------------------------------*/
6 /* The value of cmd: 4 bits */
7 /*---------------------------------------------*/
8 #define PWR_CMD_READ 0x00
9 #define PWR_CMD_WRITE 0x01
10 #define PWR_CMD_POLLING 0x02
11 #define PWR_CMD_DELAY 0x03
12 #define PWR_CMD_END 0x04
14 /* define the base address of each block */
15 #define PWR_BASEADDR_MAC 0x00
16 #define PWR_BASEADDR_USB 0x01
17 #define PWR_BASEADDR_PCIE 0x02
18 #define PWR_BASEADDR_SDIO 0x03
20 #define PWR_INTF_SDIO_MSK BIT(0)
21 #define PWR_INTF_USB_MSK BIT(1)
22 #define PWR_INTF_PCI_MSK BIT(2)
23 #define PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
25 #define PWR_FAB_TSMC_MSK BIT(0)
26 #define PWR_FAB_UMC_MSK BIT(1)
27 #define PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
29 #define PWR_CUT_TESTCHIP_MSK BIT(0)
30 #define PWR_CUT_A_MSK BIT(1)
31 #define PWR_CUT_B_MSK BIT(2)
32 #define PWR_CUT_C_MSK BIT(3)
33 #define PWR_CUT_D_MSK BIT(4)
34 #define PWR_CUT_E_MSK BIT(5)
35 #define PWR_CUT_F_MSK BIT(6)
36 #define PWR_CUT_G_MSK BIT(7)
37 #define PWR_CUT_ALL_MSK 0xFF
40 enum pwrseq_delay_unit {
56 #define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
57 #define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
58 #define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
59 #define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
60 #define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
61 #define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
62 #define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
63 #define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
65 bool rtl92e_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
66 u8 fab_version, u8 interface_type,
67 struct wlan_pwr_cfg pwrcfgcmd[]);