drivers/staging/rtl8192u/r819xU_phy.c

   1 #include "r8192U.h"
   2 #include "r8192U_hw.h"
   3 #include "r819xU_phy.h"
   4 #include "r819xU_phyreg.h"
   5 #include "r8190_rtl8256.h"
   6 #include "r8192U_dm.h"
   7 #include "r819xU_firmware_img.h"
   8
   9 #include "dot11d.h"
  10 #include <linux/bitops.h>
  11
  12 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
  13         0,
  14         0x085c, /* 2412 1  */
  15         0x08dc, /* 2417 2  */
  16         0x095c, /* 2422 3  */
  17         0x09dc, /* 2427 4  */
  18         0x0a5c, /* 2432 5  */
  19         0x0adc, /* 2437 6  */
  20         0x0b5c, /* 2442 7  */
  21         0x0bdc, /* 2447 8  */
  22         0x0c5c, /* 2452 9  */
  23         0x0cdc, /* 2457 10 */
  24         0x0d5c, /* 2462 11 */
  25         0x0ddc, /* 2467 12 */
  26         0x0e5c, /* 2472 13 */
  27         0x0f72, /* 2484    */
  28 };
  29
  30
  31 #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
  32 #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
  33 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
  34 #define rtl819XRadioA_Array  Rtl8192UsbRadioA_Array
  35 #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array
  36 #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array
  37 #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array
  38 #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
  39
  40 /******************************************************************************
  41  * function: This function reads BB parameters from header file we generate,
  42  *           and does register read/write
  43  * input:    u32        bitmask  //taget bit pos in the addr to be modified
  44  * output:   none
  45  * return:   u32        return the shift bit position of the mask
  46  ******************************************************************************/
  47 u32 rtl8192_CalculateBitShift(u32 bitmask)
  48 {
  49         u32 i;
  50
  51         i = ffs(bitmask) - 1;
  52         return i;
  53 }
  54
  55 /******************************************************************************
  56  * function:  This function checks different RF type to execute legal judgement.
  57  *            If RF Path is illegal, we will return false.
  58  * input:     net_device         *dev
  59  *            u32                eRFPath
  60  * output:    none
  61  * return:    0(illegal, false), 1(legal, true)
  62  *****************************************************************************/
  63 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
  64 {
  65         u8 ret = 1;
  66         struct r8192_priv *priv = ieee80211_priv(dev);
  67
  68         if (priv->rf_type == RF_2T4R) {
  69                 ret = 0;
  70         } else if (priv->rf_type == RF_1T2R) {
  71                 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
  72                         ret = 1;
  73                 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
  74                         ret = 0;
  75         }
  76         return ret;
  77 }
  78
  79 /******************************************************************************
  80  * function:  This function sets specific bits to BB register
  81  * input:     net_device *dev
  82  *            u32        reg_addr   //target addr to be modified
  83  *            u32        bitmask    //taget bit pos to be modified
  84  *            u32        data       //value to be write
  85  * output:    none
  86  * return:    none
  87  * notice:
  88  ******************************************************************************/
  89 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
  90                       u32 data)
  91 {
  92
  93         u32 reg, bitshift;
  94
  95         if (bitmask != bMaskDWord) {
  96                 read_nic_dword(dev, reg_addr, &reg);
  97                 bitshift = rtl8192_CalculateBitShift(bitmask);
  98                 reg &= ~bitmask;
  99                 reg |= data << bitshift;
 100                 write_nic_dword(dev, reg_addr, reg);
 101         } else {
 102                 write_nic_dword(dev, reg_addr, data);
 103         }
 104         return;
 105 }
 106
 107 /******************************************************************************
 108  * function:  This function reads specific bits from BB register
 109  * input:     net_device        *dev
 110  *            u32               reg_addr   //target addr to be readback
 111  *            u32               bitmask    //taget bit pos to be readback
 112  * output:    none
 113  * return:    u32               data       //the readback register value
 114  * notice:
 115  ******************************************************************************/
 116 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask)
 117 {
 118         u32 reg, bitshift;
 119
 120         read_nic_dword(dev, reg_addr, &reg);
 121         bitshift = rtl8192_CalculateBitShift(bitmask);
 122
 123         return (reg & bitmask) >> bitshift;
 124 }
 125
 126 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 127                               u32 offset);
 128
 129 static void phy_FwRFSerialWrite(struct net_device *dev,
 130                                 RF90_RADIO_PATH_E eRFPath, u32  offset,
 131                                 u32  data);
 132
 133 /******************************************************************************
 134  * function:  This function reads register from RF chip
 135  * input:     net_device        *dev
 136  *            RF90_RADIO_PATH_E eRFPath    //radio path of A/B/C/D
 137  *            u32               offset     //target address to be read
 138  * output:    none
 139  * return:    u32               readback value
 140  * notice:    There are three types of serial operations:
 141  *            (1) Software serial write.
 142  *            (2)Hardware LSSI-Low Speed Serial Interface.
 143  *            (3)Hardware HSSI-High speed serial write.
 144  *            Driver here need to implement (1) and (2)
 145  *            ---need more spec for this information.
 146  ******************************************************************************/
 147 u32 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 148                              u32 offset)
 149 {
 150         struct r8192_priv *priv = ieee80211_priv(dev);
 151         u32 ret = 0;
 152         u32 new_offset = 0;
 153         BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
 154
 155         rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
 156         /* Make sure RF register offset is correct */
 157         offset &= 0x3f;
 158
 159         /* Switch page for 8256 RF IC */
 160         if (priv->rf_chip == RF_8256) {
 161                 if (offset >= 31) {
 162                         priv->RfReg0Value[eRFPath] |= 0x140;
 163                         /* Switch to Reg_Mode2 for Reg 31-45 */
 164                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 165                                          bMaskDWord,
 166                                          priv->RfReg0Value[eRFPath]<<16);
 167                         /* Modify offset */
 168                         new_offset = offset - 30;
 169                 } else if (offset >= 16) {
 170                         priv->RfReg0Value[eRFPath] |= 0x100;
 171                         priv->RfReg0Value[eRFPath] &= (~0x40);
 172                         /* Switch to Reg_Mode1 for Reg16-30 */
 173                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 174                                          bMaskDWord,
 175                                          priv->RfReg0Value[eRFPath]<<16);
 176
 177                         new_offset = offset - 15;
 178                 } else {
 179                         new_offset = offset;
 180                 }
 181         } else {
 182                 RT_TRACE((COMP_PHY|COMP_ERR),
 183                          "check RF type here, need to be 8256\n");
 184                 new_offset = offset;
 185         }
 186         /* Put desired read addr to LSSI control Register */
 187         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
 188                          new_offset);
 189         /* Issue a posedge trigger */
 190         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
 191         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 192
 193
 194         /* TODO: we should not delay such a long time. Ask for help from SD3 */
 195         usleep_range(1000, 1000);
 196
 197         ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
 198                                  bLSSIReadBackData);
 199
 200
 201         /* Switch back to Reg_Mode0 */
 202         if (priv->rf_chip == RF_8256) {
 203                 priv->RfReg0Value[eRFPath] &= 0xebf;
 204
 205                 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
 206                                  priv->RfReg0Value[eRFPath] << 16);
 207         }
 208
 209         return ret;
 210 }
 211
 212 /******************************************************************************
 213  * function:  This function writes data to RF register
 214  * input:     net_device        *dev
 215  *            RF90_RADIO_PATH_E eRFPath  //radio path of A/B/C/D
 216  *            u32               offset   //target address to be written
 217  *            u32               data     //the new register data to be written
 218  * output:    none
 219  * return:    none
 220  * notice:    For RF8256 only.
 221  * ===========================================================================
 222  * Reg Mode     RegCTL[1]       RegCTL[0]               Note
 223  *              (Reg00[12])     (Reg00[10])
 224  * ===========================================================================
 225  * Reg_Mode0    0               x                       Reg 0 ~ 15(0x0 ~ 0xf)
 226  * ---------------------------------------------------------------------------
 227  * Reg_Mode1    1               0                       Reg 16 ~ 30(0x1 ~ 0xf)
 228  * ---------------------------------------------------------------------------
 229  * Reg_Mode2    1               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 230  * ---------------------------------------------------------------------------
 231  *****************************************************************************/
 232 void rtl8192_phy_RFSerialWrite(struct net_device *dev,
 233                                RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data)
 234 {
 235         struct r8192_priv *priv = ieee80211_priv(dev);
 236         u32 DataAndAddr = 0, new_offset = 0;
 237         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
 238
 239         offset &= 0x3f;
 240         if (priv->rf_chip == RF_8256) {
 241
 242                 if (offset >= 31) {
 243                         priv->RfReg0Value[eRFPath] |= 0x140;
 244                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 245                                          bMaskDWord,
 246                                          priv->RfReg0Value[eRFPath] << 16);
 247                         new_offset = offset - 30;
 248                 } else if (offset >= 16) {
 249                         priv->RfReg0Value[eRFPath] |= 0x100;
 250                         priv->RfReg0Value[eRFPath] &= (~0x40);
 251                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 252                                          bMaskDWord,
 253                                          priv->RfReg0Value[eRFPath]<<16);
 254                         new_offset = offset - 15;
 255                 } else {
 256                         new_offset = offset;
 257                 }
 258         } else {
 259                 RT_TRACE((COMP_PHY|COMP_ERR),
 260                          "check RF type here, need to be 8256\n");
 261                 new_offset = offset;
 262         }
 263
 264         /* Put write addr in [5:0] and write data in [31:16] */
 265         DataAndAddr = (data<<16) | (new_offset&0x3f);
 266
 267         /* Write operation */
 268         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 269
 270
 271         if (offset == 0x0)
 272                 priv->RfReg0Value[eRFPath] = data;
 273
 274         /* Switch back to Reg_Mode0 */
 275         if (priv->rf_chip == RF_8256) {
 276                 if (offset != 0) {
 277                         priv->RfReg0Value[eRFPath] &= 0xebf;
 278                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 279                                          bMaskDWord,
 280                                          priv->RfReg0Value[eRFPath] << 16);
 281                 }
 282         }
 283         return;
 284 }
 285
 286 /******************************************************************************
 287  * function:  This function set specific bits to RF register
 288  * input:     net_device        dev
 289  *            RF90_RADIO_PATH_E eRFPath  //radio path of A/B/C/D
 290  *            u32               reg_addr //target addr to be modified
 291  *            u32               bitmask  //taget bit pos to be modified
 292  *            u32               data     //value to be written
 293  * output:    none
 294  * return:    none
 295  * notice:
 296  *****************************************************************************/
 297 void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 298                           u32 reg_addr, u32 bitmask, u32 data)
 299 {
 300         struct r8192_priv *priv = ieee80211_priv(dev);
 301         u32 reg, bitshift;
 302
 303         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 304                 return;
 305
 306         if (priv->Rf_Mode == RF_OP_By_FW) {
 307                 if (bitmask != bMask12Bits) {
 308                         /* RF data is 12 bits only */
 309                         reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
 310                         bitshift =  rtl8192_CalculateBitShift(bitmask);
 311                         reg &= ~bitmask;
 312                         reg |= data << bitshift;
 313
 314                         phy_FwRFSerialWrite(dev, eRFPath, reg_addr, reg);
 315                 } else {
 316                         phy_FwRFSerialWrite(dev, eRFPath, reg_addr, data);
 317                 }
 318
 319                 udelay(200);
 320
 321         } else {
 322                 if (bitmask != bMask12Bits) {
 323                         /* RF data is 12 bits only */
 324                         reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
 325                         bitshift =  rtl8192_CalculateBitShift(bitmask);
 326                         reg &= ~bitmask;
 327                         reg |= data << bitshift;
 328
 329                         rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, reg);
 330                 } else {
 331                         rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, data);
 332                 }
 333         }
 334         return;
 335 }
 336
 337 /******************************************************************************
 338  * function:  This function reads specific bits from RF register
 339  * input:     net_device        *dev
 340  *            u32               reg_addr //target addr to be readback
 341  *            u32               bitmask  //taget bit pos to be readback
 342  * output:    none
 343  * return:    u32               data     //the readback register value
 344  * notice:
 345  *****************************************************************************/
 346 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 347                            u32 reg_addr, u32 bitmask)
 348 {
 349         u32 reg, bitshift;
 350         struct r8192_priv *priv = ieee80211_priv(dev);
 351
 352
 353         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 354                 return 0;
 355         if (priv->Rf_Mode == RF_OP_By_FW) {
 356                 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
 357                 bitshift =  rtl8192_CalculateBitShift(bitmask);
 358                 reg = (reg & bitmask) >> bitshift;
 359                 udelay(200);
 360                 return reg;
 361         } else {
 362                 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
 363                 bitshift =  rtl8192_CalculateBitShift(bitmask);
 364                 reg = (reg & bitmask) >> bitshift;
 365                 return reg;
 366         }
 367 }
 368
 369 /******************************************************************************
 370  * function:  We support firmware to execute RF-R/W.
 371  * input:     net_device        *dev
 372  *            RF90_RADIO_PATH_E eRFPath
 373  *            u32               offset
 374  * output:    none
 375  * return:    u32
 376  * notice:
 377  ****************************************************************************/
 378 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 379                               u32 offset)
 380 {
 381         u32             reg = 0;
 382         u32             data = 0;
 383         u8              time = 0;
 384         u32             tmp;
 385
 386         /* Firmware RF Write control.
 387          * We can not execute the scheme in the initial step.
 388          * Otherwise, RF-R/W will waste much time.
 389          * This is only for site survey. */
 390         /* 1. Read operation need not insert data. bit 0-11 */
 391         /* 2. Write RF register address. bit 12-19 */
 392         data |= ((offset&0xFF)<<12);
 393         /* 3. Write RF path.  bit 20-21 */
 394         data |= ((eRFPath&0x3)<<20);
 395         /* 4. Set RF read indicator. bit 22=0 */
 396         /* 5. Trigger Fw to operate the command. bit 31 */
 397         data |= 0x80000000;
 398         /* 6. We can not execute read operation if bit 31 is 1. */
 399         read_nic_dword(dev, QPNR, &tmp);
 400         while (tmp & 0x80000000) {
 401                 /* If FW can not finish RF-R/W for more than ?? times.
 402                    We must reset FW. */
 403                 if (time++ < 100) {
 404                         udelay(10);
 405                         read_nic_dword(dev, QPNR, &tmp);
 406                 } else {
 407                         break;
 408                 }
 409         }
 410         /* 7. Execute read operation. */
 411         write_nic_dword(dev, QPNR, data);
 412         /* 8. Check if firmware send back RF content. */
 413         read_nic_dword(dev, QPNR, &tmp);
 414         while (tmp & 0x80000000) {
 415                 /* If FW can not finish RF-R/W for more than ?? times.
 416                    We must reset FW. */
 417                 if (time++ < 100) {
 418                         udelay(10);
 419                         read_nic_dword(dev, QPNR, &tmp);
 420                 } else {
 421                         return 0;
 422                 }
 423         }
 424         read_nic_dword(dev, RF_DATA, &reg);
 425
 426         return reg;
 427 }
 428
 429 /******************************************************************************
 430  * function:  We support firmware to execute RF-R/W.
 431  * input:     net_device        *dev
 432  *            RF90_RADIO_PATH_E eRFPath
 433  *            u32               offset
 434  *            u32               data
 435  * output:    none
 436  * return:    none
 437  * notice:
 438  ****************************************************************************/
 439 static void phy_FwRFSerialWrite(struct net_device *dev,
 440                                 RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data)
 441 {
 442         u8      time = 0;
 443         u32     tmp;
 444
 445         /* Firmware RF Write control.
 446          * We can not execute the scheme in the initial step.
 447          * Otherwise, RF-R/W will waste much time.
 448          * This is only for site survey. */
 449
 450         /* 1. Set driver write bit and 12 bit data. bit 0-11 */
 451         /* 2. Write RF register address. bit 12-19 */
 452         data |= ((offset&0xFF)<<12);
 453         /* 3. Write RF path.  bit 20-21 */
 454         data |= ((eRFPath&0x3)<<20);
 455         /* 4. Set RF write indicator. bit 22=1 */
 456         data |= 0x400000;
 457         /* 5. Trigger Fw to operate the command. bit 31=1 */
 458         data |= 0x80000000;
 459
 460         /* 6. Write operation. We can not write if bit 31 is 1. */
 461         read_nic_dword(dev, QPNR, &tmp);
 462         while (tmp & 0x80000000) {
 463                 /* If FW can not finish RF-R/W for more than ?? times.
 464                    We must reset FW. */
 465                 if (time++ < 100) {
 466                         udelay(10);
 467                         read_nic_dword(dev, QPNR, &tmp);
 468                 } else {
 469                         break;
 470                 }
 471         }
 472         /* 7. No matter check bit. We always force the write.
 473            Because FW will not accept the command. */
 474         write_nic_dword(dev, QPNR, data);
 475         /* According to test, we must delay 20us to wait firmware
 476            to finish RF write operation. */
 477         /* We support delay in firmware side now. */
 478 }
 479
 480 /******************************************************************************
 481  * function:  This function reads BB parameters from header file we generate,
 482  *            and do register read/write
 483  * input:     net_device        *dev
 484  * output:    none
 485  * return:    none
 486  * notice:    BB parameters may change all the time, so please make
 487  *            sure it has been synced with the newest.
 488  *****************************************************************************/
 489 void rtl8192_phy_configmac(struct net_device *dev)
 490 {
 491         u32 dwArrayLen = 0, i;
 492         u32 *pdwArray = NULL;
 493         struct r8192_priv *priv = ieee80211_priv(dev);
 494
 495         if (priv->btxpowerdata_readfromEEPORM) {
 496                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
 497                 dwArrayLen = MACPHY_Array_PGLength;
 498                 pdwArray = rtl819XMACPHY_Array_PG;
 499
 500         } else {
 501                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
 502                 dwArrayLen = MACPHY_ArrayLength;
 503                 pdwArray = rtl819XMACPHY_Array;
 504         }
 505         for (i = 0; i < dwArrayLen; i = i+3) {
 506                 if (pdwArray[i] == 0x318) {
 507                         pdwArray[i+2] = 0x00000800;
 508                 }
 509
 510                 RT_TRACE(COMP_DBG,
 511                          "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n",
 512                          pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
 513                 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
 514                                  pdwArray[i+2]);
 515         }
 516         return;
 517 }
 518
 519 /******************************************************************************
 520  * function:  This function does dirty work
 521  * input:     net_device        *dev
 522  *            u8                ConfigType
 523  * output:    none
 524  * return:    none
 525  * notice:    BB parameters may change all the time, so please make
 526  *            sure it has been synced with the newest.
 527  *****************************************************************************/
 528 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
 529 {
 530         u32 i;
 531
 532 #ifdef TO_DO_LIST
 533         u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
 534
 535         if (Adapter->bInHctTest) {
 536                 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
 537                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
 538                 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
 539                 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
 540         }
 541 #endif
 542         if (ConfigType == BaseBand_Config_PHY_REG) {
 543                 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) {
 544                         rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i],
 545                                          bMaskDWord,
 546                                          rtl819XPHY_REG_1T2RArray[i+1]);
 547                         RT_TRACE(COMP_DBG,
 548                                  "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n",
 549                                  i, rtl819XPHY_REG_1T2RArray[i],
 550                                  rtl819XPHY_REG_1T2RArray[i+1]);
 551                 }
 552         } else if (ConfigType == BaseBand_Config_AGC_TAB) {
 553                 for (i = 0; i < AGCTAB_ArrayLength; i += 2) {
 554                         rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i],
 555                                          bMaskDWord, rtl819XAGCTAB_Array[i+1]);
 556                         RT_TRACE(COMP_DBG,
 557                                  "i: %x, rtl819XAGCTAB_Array[0]=%x rtl819XAGCTAB_Array[1]=%x\n",
 558                                  i, rtl819XAGCTAB_Array[i],
 559                                  rtl819XAGCTAB_Array[i+1]);
 560                 }
 561         }
 562         return;
 563 }
 564
 565 /******************************************************************************
 566  * function:  This function initializes Register definition offset for
 567  *            Radio Path A/B/C/D
 568  * input:     net_device        *dev
 569  * output:    none
 570  * return:    none
 571  * notice:    Initialization value here is constant and it should never
 572  *            be changed
 573  *****************************************************************************/
 574 void rtl8192_InitBBRFRegDef(struct net_device *dev)
 575 {
 576         struct r8192_priv *priv = ieee80211_priv(dev);
 577
 578         /* RF Interface Software Control */
 579         /* 16 LSBs if read 32-bit from 0x870 */
 580         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 581         /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
 582         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 583         /* 16 LSBs if read 32-bit from 0x874 */
 584         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 585         /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
 586         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 587
 588         /* RF Interface Readback Value */
 589         /* 16 LSBs if read 32-bit from 0x8E0 */
 590         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 591         /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
 592         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 593         /* 16 LSBs if read 32-bit from 0x8E4 */
 594         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 595         /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
 596         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 597
 598         /* RF Interface Output (and Enable) */
 599         /* 16 LSBs if read 32-bit from 0x860 */
 600         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
 601         /* 16 LSBs if read 32-bit from 0x864 */
 602         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
 603         /* 16 LSBs if read 32-bit from 0x868 */
 604         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
 605         /* 16 LSBs if read 32-bit from 0x86C */
 606         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
 607
 608         /* RF Interface (Output and) Enable */
 609         /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
 610         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
 611         /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
 612         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
 613         /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */
 614         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
 615         /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */
 616         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
 617
 618         /* Addr of LSSI. Write RF register by driver */
 619         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
 620         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 621         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
 622         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
 623
 624         /* RF parameter */
 625         /* BB Band Select */
 626         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 627         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 628         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 629         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 630
 631         /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
 632         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
 633         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
 634         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
 635         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
 636
 637         /* Tranceiver A~D HSSI Parameter-1 */
 638         /* wire control parameter1 */
 639         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
 640         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
 641         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
 642         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
 643
 644         /* Tranceiver A~D HSSI Parameter-2 */
 645         /* wire control parameter2 */
 646         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
 647         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
 648         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
 649         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
 650
 651         /* RF Switch Control */
 652         /* TR/Ant switch control */
 653         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 654         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 655         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 656         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 657
 658         /* AGC control 1 */
 659         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
 660         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
 661         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
 662         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
 663
 664         /* AGC control 2 */
 665         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
 666         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
 667         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
 668         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
 669
 670         /* RX AFE control 1 */
 671         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
 672         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
 673         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
 674         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
 675
 676         /* RX AFE control 1 */
 677         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
 678         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
 679         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
 680         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
 681
 682         /* Tx AFE control 1 */
 683         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
 684         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
 685         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
 686         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
 687
 688         /* Tx AFE control 2 */
 689         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
 690         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
 691         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
 692         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
 693
 694         /* Tranceiver LSSI Readback */
 695         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 696         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 697         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
 698         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
 699 }
 700
 701 /******************************************************************************
 702  * function:  This function is to write register and then readback to make
 703  *            sure whether BB and RF is OK
 704  * input:     net_device        *dev
 705  *            HW90_BLOCK_E      CheckBlock
 706  *            RF90_RADIO_PATH_E eRFPath  //only used when checkblock is
 707  *                                       //HW90_BLOCK_RF
 708  * output:    none
 709  * return:    return whether BB and RF is ok (0:OK, 1:Fail)
 710  * notice:    This function may be removed in the ASIC
 711  ******************************************************************************/
 712 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock,
 713                             RF90_RADIO_PATH_E eRFPath)
 714 {
 715         u8 ret = 0;
 716         u32 i, CheckTimes = 4, reg = 0;
 717         u32 WriteAddr[4];
 718         u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
 719
 720         /* Initialize register address offset to be checked */
 721         WriteAddr[HW90_BLOCK_MAC] = 0x100;
 722         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
 723         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
 724         WriteAddr[HW90_BLOCK_RF] = 0x3;
 725         RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock);
 726         for (i = 0; i < CheckTimes; i++) {
 727
 728                 /* Write data to register and readback */
 729                 switch (CheckBlock) {
 730                 case HW90_BLOCK_MAC:
 731                         RT_TRACE(COMP_ERR,
 732                                  "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
 733                         break;
 734
 735                 case HW90_BLOCK_PHY0:
 736                 case HW90_BLOCK_PHY1:
 737                         write_nic_dword(dev, WriteAddr[CheckBlock],
 738                                         WriteData[i]);
 739                         read_nic_dword(dev, WriteAddr[CheckBlock], &reg);
 740                         break;
 741
 742                 case HW90_BLOCK_RF:
 743                         WriteData[i] &= 0xfff;
 744                         rtl8192_phy_SetRFReg(dev, eRFPath,
 745                                              WriteAddr[HW90_BLOCK_RF],
 746                                              bMask12Bits, WriteData[i]);
 747                         /* TODO: we should not delay for such a long time.
 748                            Ask SD3 */
 749                         usleep_range(1000, 1000);
 750                         reg = rtl8192_phy_QueryRFReg(dev, eRFPath,
 751                                                      WriteAddr[HW90_BLOCK_RF],
 752                                                      bMask12Bits);
 753                         usleep_range(1000, 1000);
 754                         break;
 755
 756                 default:
 757                         ret = 1;
 758                         break;
 759                 }
 760
 761
 762                 /* Check whether readback data is correct */
 763                 if (reg != WriteData[i]) {
 764                         RT_TRACE((COMP_PHY|COMP_ERR),
 765                                  "error reg: %x, WriteData: %x\n",
 766                                  reg, WriteData[i]);
 767                         ret = 1;
 768                         break;
 769                 }
 770         }
 771
 772         return ret;
 773 }
 774
 775 /******************************************************************************
 776  * function:  This function initializes BB&RF
 777  * input:     net_device        *dev
 778  * output:    none
 779  * return:    none
 780  * notice:    Initialization value may change all the time, so please make
 781  *            sure it has been synced with the newest.
 782  ******************************************************************************/
 783 void rtl8192_BB_Config_ParaFile(struct net_device *dev)
 784 {
 785         struct r8192_priv *priv = ieee80211_priv(dev);
 786         u8 reg_u8 = 0, eCheckItem = 0, status = 0;
 787         u32 reg_u32 = 0;
 788
 789         /**************************************
 790          * <1> Initialize BaseBand
 791          *************************************/
 792
 793         /* --set BB Global Reset-- */
 794         read_nic_byte(dev, BB_GLOBAL_RESET, &reg_u8);
 795         write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT));
 796         mdelay(50);
 797         /* ---set BB reset Active--- */
 798         read_nic_dword(dev, CPU_GEN, &reg_u32);
 799         write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST)));
 800
 801         /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */
 802         /* TODO: this function should be removed on ASIC */
 803         for (eCheckItem = (HW90_BLOCK_E)HW90_BLOCK_PHY0;
 804              eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
 805                 /* don't care RF path */
 806                 status = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem,
 807                                                   (RF90_RADIO_PATH_E)0);
 808                 if (status != 0) {
 809                         RT_TRACE((COMP_ERR | COMP_PHY),
 810                                  "PHY_RF8256_Config(): Check PHY%d Fail!!\n",
 811                                  eCheckItem-1);
 812                         return;
 813                 }
 814         }
 815         /* ---- Set CCK and OFDM Block "OFF"---- */
 816         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
 817         /* ----BB Register Initilazation---- */
 818         /* ==m==>Set PHY REG From Header<==m== */
 819         rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
 820
 821         /* ----Set BB reset de-Active---- */
 822         read_nic_dword(dev, CPU_GEN, &reg_u32);
 823         write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST));
 824
 825         /* ----BB AGC table Initialization---- */
 826         /* ==m==>Set PHY REG From Header<==m== */
 827         rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
 828
 829         /* ----Enable XSTAL ---- */
 830         write_nic_byte_E(dev, 0x5e, 0x00);
 831         if (priv->card_8192_version == (u8)VERSION_819xU_A) {
 832                 /* Antenna gain offset from B/C/D to A */
 833                 reg_u32 = (priv->AntennaTxPwDiff[1]<<4 |
 834                            priv->AntennaTxPwDiff[0]);
 835                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC),
 836                                  reg_u32);
 837
 838                 /* XSTALLCap */
 839                 reg_u32 = priv->CrystalCap & 0xf;
 840                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap,
 841                                  reg_u32);
 842         }
 843
 844         /* Check if the CCK HighPower is turned ON.
 845            This is used to calculate PWDB. */
 846         priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev,
 847                                                      rFPGA0_XA_HSSIParameter2,
 848                                                      0x200);
 849         return;
 850 }
 851
 852 /******************************************************************************
 853  * function:  This function initializes BB&RF
 854  * input:     net_device        *dev
 855  * output:    none
 856  * return:    none
 857  * notice:    Initialization value may change all the time, so please make
 858  *            sure it has been synced with the newest.
 859  *****************************************************************************/
 860 void rtl8192_BBConfig(struct net_device *dev)
 861 {
 862         rtl8192_InitBBRFRegDef(dev);
 863         /* config BB&RF. As hardCode based initialization has not been well
 864          * implemented, so use file first.
 865          * FIXME: should implement it for hardcode? */
 866         rtl8192_BB_Config_ParaFile(dev);
 867         return;
 868 }
 869
 870
 871 /******************************************************************************
 872  * function:  This function obtains the initialization value of Tx power Level
 873  *            offset
 874  * input:     net_device        *dev
 875  * output:    none
 876  * return:    none
 877  *****************************************************************************/
 878 void rtl8192_phy_getTxPower(struct net_device *dev)
 879 {
 880         struct r8192_priv *priv = ieee80211_priv(dev);
 881         u8 tmp;
 882
 883         read_nic_dword(dev, rTxAGC_Rate18_06,
 884                        &priv->MCSTxPowerLevelOriginalOffset[0]);
 885         read_nic_dword(dev, rTxAGC_Rate54_24,
 886                        &priv->MCSTxPowerLevelOriginalOffset[1]);
 887         read_nic_dword(dev, rTxAGC_Mcs03_Mcs00,
 888                        &priv->MCSTxPowerLevelOriginalOffset[2]);
 889         read_nic_dword(dev, rTxAGC_Mcs07_Mcs04,
 890                        &priv->MCSTxPowerLevelOriginalOffset[3]);
 891         read_nic_dword(dev, rTxAGC_Mcs11_Mcs08,
 892                        &priv->MCSTxPowerLevelOriginalOffset[4]);
 893         read_nic_dword(dev, rTxAGC_Mcs15_Mcs12,
 894                        &priv->MCSTxPowerLevelOriginalOffset[5]);
 895
 896         /* Read rx initial gain */
 897         read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
 898         read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
 899         read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
 900         read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
 901         RT_TRACE(COMP_INIT,
 902                  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
 903                  priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
 904                  priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
 905
 906         /* Read framesync */
 907         read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
 908         read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
 909         priv->framesyncC34 = tmp;
 910         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
 911                 rOFDM0_RxDetector3, priv->framesync);
 912
 913         /* Read SIFS (save the value read fome MACPHY_REG.txt) */
 914         read_nic_word(dev, SIFS, &priv->SifsTime);
 915
 916         return;
 917 }
 918
 919 /******************************************************************************
 920  * function:  This function sets the initialization value of Tx power Level
 921  *            offset
 922  * input:     net_device        *dev
 923  *            u8                channel
 924  * output:    none
 925  * return:    none
 926  ******************************************************************************/
 927 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
 928 {
 929         struct r8192_priv *priv = ieee80211_priv(dev);
 930         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
 931         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 932
 933         switch (priv->rf_chip) {
 934         case RF_8256:
 935                 /* need further implement */
 936                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
 937                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
 938                 break;
 939         default:
 940                 RT_TRACE((COMP_PHY|COMP_ERR),
 941                          "error RF chipID(8225 or 8258) in function %s()\n",
 942                          __func__);
 943                 break;
 944         }
 945         return;
 946 }
 947
 948 /******************************************************************************
 949  * function:  This function checks Rf chip to do RF config
 950  * input:     net_device        *dev
 951  * output:    none
 952  * return:    only 8256 is supported
 953  ******************************************************************************/
 954 void rtl8192_phy_RFConfig(struct net_device *dev)
 955 {
 956         struct r8192_priv *priv = ieee80211_priv(dev);
 957
 958         switch (priv->rf_chip) {
 959                 case RF_8256:
 960                         PHY_RF8256_Config(dev);
 961                         break;
 962                 default:
 963                         RT_TRACE(COMP_ERR, "error chip id\n");
 964                         break;
 965         }
 966         return;
 967 }
 968
 969 /******************************************************************************
 970  * function:  This function updates Initial gain
 971  * input:     net_device        *dev
 972  * output:    none
 973  * return:    As Windows has not implemented this, wait for complement
 974  ******************************************************************************/
 975 void rtl8192_phy_updateInitGain(struct net_device *dev)
 976 {
 977         return;
 978 }
 979
 980 /******************************************************************************
 981  * function:  This function read RF parameters from general head file,
 982  *            and do RF 3-wire
 983  * input:     net_device        *dev
 984  *            RF90_RADIO_PATH_E eRFPath
 985  * output:    none
 986  * return:    return code show if RF configuration is successful(0:pass, 1:fail)
 987  * notice:    Delay may be required for RF configuration
 988  *****************************************************************************/
 989 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
 990                                       RF90_RADIO_PATH_E eRFPath)
 991 {
 992
 993         int i;
 994         u8 ret = 0;
 995
 996         switch (eRFPath) {
 997         case RF90_PATH_A:
 998                 for (i = 0; i < RadioA_ArrayLength; i = i+2) {
 999
1000                         if (rtl819XRadioA_Array[i] == 0xfe) {
1001                                 mdelay(100);
1002                                 continue;
1003                         }
1004                         rtl8192_phy_SetRFReg(dev, eRFPath,
1005                                              rtl819XRadioA_Array[i],
1006                                              bMask12Bits,
1007                                              rtl819XRadioA_Array[i+1]);
1008                         mdelay(1);
1009
1010                 }
1011                 break;
1012         case RF90_PATH_B:
1013                 for (i = 0; i < RadioB_ArrayLength; i = i+2) {
1014
1015                         if (rtl819XRadioB_Array[i] == 0xfe) {
1016                                 mdelay(100);
1017                                 continue;
1018                         }
1019                         rtl8192_phy_SetRFReg(dev, eRFPath,
1020                                              rtl819XRadioB_Array[i],
1021                                              bMask12Bits,
1022                                              rtl819XRadioB_Array[i+1]);
1023                         mdelay(1);
1024
1025                 }
1026                 break;
1027         case RF90_PATH_C:
1028                 for (i = 0; i < RadioC_ArrayLength; i = i+2) {
1029
1030                         if (rtl819XRadioC_Array[i] == 0xfe) {
1031                                 mdelay(100);
1032                                 continue;
1033                         }
1034                         rtl8192_phy_SetRFReg(dev, eRFPath,
1035                                              rtl819XRadioC_Array[i],
1036                                              bMask12Bits,
1037                                              rtl819XRadioC_Array[i+1]);
1038                         mdelay(1);
1039
1040                 }
1041                 break;
1042         case RF90_PATH_D:
1043                 for (i = 0; i < RadioD_ArrayLength; i = i+2) {
1044
1045                         if (rtl819XRadioD_Array[i] == 0xfe) {
1046                                 mdelay(100);
1047                                 continue;
1048                         }
1049                         rtl8192_phy_SetRFReg(dev, eRFPath,
1050                                              rtl819XRadioD_Array[i],
1051                                              bMask12Bits,
1052                                              rtl819XRadioD_Array[i+1]);
1053                         mdelay(1);
1054
1055                 }
1056                 break;
1057         default:
1058                 break;
1059         }
1060
1061         return ret;
1062
1063 }
1064
1065 /******************************************************************************
1066  * function:  This function sets Tx Power of the channel
1067  * input:     net_device        *dev
1068  *            u8                channel
1069  * output:    none
1070  * return:    none
1071  * notice:
1072  ******************************************************************************/
1073 void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
1074 {
1075         struct r8192_priv *priv = ieee80211_priv(dev);
1076         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
1077         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1078
1079         switch (priv->rf_chip) {
1080         case RF_8225:
1081 #ifdef TO_DO_LIST
1082                 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
1083                 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
1084 #endif
1085                 break;
1086
1087         case RF_8256:
1088                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1089                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1090                 break;
1091
1092         case RF_8258:
1093                 break;
1094         default:
1095                 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__);
1096                 break;
1097         }
1098         return;
1099 }
1100
1101 /******************************************************************************
1102  * function:  This function sets RF state on or off
1103  * input:     net_device         *dev
1104  *            RT_RF_POWER_STATE  eRFPowerState  //Power State to set
1105  * output:    none
1106  * return:    none
1107  * notice:
1108  *****************************************************************************/
1109 bool rtl8192_SetRFPowerState(struct net_device *dev,
1110                              RT_RF_POWER_STATE eRFPowerState)
1111 {
1112         bool                            bResult = true;
1113         struct r8192_priv *priv = ieee80211_priv(dev);
1114
1115         if (eRFPowerState == priv->ieee80211->eRFPowerState)
1116                 return false;
1117
1118         if (priv->SetRFPowerStateInProgress == true)
1119                 return false;
1120
1121         priv->SetRFPowerStateInProgress = true;
1122
1123         switch (priv->rf_chip) {
1124         case RF_8256:
1125                 switch (eRFPowerState) {
1126                 case eRfOn:
1127                         /* RF-A, RF-B */
1128                         /* enable RF-Chip A/B - 0x860[4] */
1129                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4,
1130                                          0x1);
1131                         /* analog to digital on - 0x88c[9:8] */
1132                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300,
1133                                          0x3);
1134                         /* digital to analog on - 0x880[4:3] */
1135                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1136                                          0x3);
1137                         /* rx antenna on - 0xc04[1:0] */
1138                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
1139                         /* rx antenna on - 0xd04[1:0] */
1140                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
1141                         /* analog to digital part2 on - 0x880[6:5] */
1142                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1143                                          0x3);
1144
1145                         break;
1146
1147                 case eRfSleep:
1148
1149                         break;
1150
1151                 case eRfOff:
1152                         /* RF-A, RF-B */
1153                         /* disable RF-Chip A/B - 0x860[4] */
1154                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4,
1155                                          0x0);
1156                         /* analog to digital off, for power save */
1157                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00,
1158                                          0x0); /* 0x88c[11:8] */
1159                         /* digital to analog off, for power save - 0x880[4:3] */
1160                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1161                                          0x0);
1162                         /* rx antenna off - 0xc04[3:0] */
1163                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1164                         /* rx antenna off - 0xd04[3:0] */
1165                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1166                         /* analog to digital part2 off, for power save */
1167                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1168                                          0x0); /* 0x880[6:5] */
1169
1170                         break;
1171
1172                 default:
1173                         bResult = false;
1174                         RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n",
1175                                  __func__, eRFPowerState);
1176                         break;
1177                 }
1178                 break;
1179         default:
1180                 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1181                 break;
1182         }
1183 #ifdef TO_DO_LIST
1184         if (bResult) {
1185                 /* Update current RF state variable. */
1186                 pHalData->eRFPowerState = eRFPowerState;
1187                 switch (pHalData->RFChipID) {
1188                 case RF_8256:
1189                         switch (pHalData->eRFPowerState) {
1190                         case eRfOff:
1191                                 /* If Rf off reason is from IPS,
1192                                    LED should blink with no link */
1193                                 if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS)
1194                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1195                                 else
1196                                         /* Turn off LED if RF is not ON. */
1197                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
1198                                 break;
1199
1200                         case eRfOn:
1201                                 /* Turn on RF we are still linked, which might
1202                                    happen when we quickly turn off and on HW RF.
1203                                  */
1204                                 if (pMgntInfo->bMediaConnect == TRUE)
1205                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1206                                 else
1207                                         /* Turn off LED if RF is not ON. */
1208                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1209                                 break;
1210
1211                         default:
1212                                 break;
1213                         }
1214                         break;
1215
1216                 default:
1217                         RT_TRACE(COMP_RF, DBG_LOUD, "%s(): Unknown RF type\n",
1218                                  __func__);
1219                         break;
1220                 }
1221
1222         }
1223 #endif
1224         priv->SetRFPowerStateInProgress = false;
1225
1226         return bResult;
1227 }
1228
1229 /******************************************************************************
1230  * function:  This function sets command table variable (struct SwChnlCmd).
1231  * input:     SwChnlCmd      *CmdTable    //table to be set
1232  *            u32            CmdTableIdx  //variable index in table to be set
1233  *            u32            CmdTableSz   //table size
1234  *            SwChnlCmdID    CmdID        //command ID to set
1235  *            u32            Para1
1236  *            u32            Para2
1237  *            u32            msDelay
1238  * output:
1239  * return:    true if finished, false otherwise
1240  * notice:
1241  ******************************************************************************/
1242 u8 rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd *CmdTable, u32 CmdTableIdx,
1243                                  u32 CmdTableSz, SwChnlCmdID CmdID, u32 Para1,
1244                                  u32 Para2, u32 msDelay)
1245 {
1246         SwChnlCmd *pCmd;
1247
1248         if (CmdTable == NULL) {
1249                 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__);
1250                 return false;
1251         }
1252         if (CmdTableIdx >= CmdTableSz) {
1253                 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1254                          __func__, CmdTableIdx, CmdTableSz);
1255                 return false;
1256         }
1257
1258         pCmd = CmdTable + CmdTableIdx;
1259         pCmd->CmdID = CmdID;
1260         pCmd->Para1 = Para1;
1261         pCmd->Para2 = Para2;
1262         pCmd->msDelay = msDelay;
1263
1264         return true;
1265 }
1266
1267 /******************************************************************************
1268  * function:  This function sets channel step by step
1269  * input:     net_device        *dev
1270  *            u8                channel
1271  *            u8                *stage   //3 stages
1272  *            u8                *step
1273  *            u32               *delay   //whether need to delay
1274  * output:    store new stage, step and delay for next step
1275  *            (combine with function above)
1276  * return:    true if finished, false otherwise
1277  * notice:    Wait for simpler function to replace it
1278  *****************************************************************************/
1279 u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage,
1280                                 u8 *step, u32 *delay)
1281 {
1282         struct r8192_priv *priv = ieee80211_priv(dev);
1283         SwChnlCmd       PreCommonCmd[MAX_PRECMD_CNT];
1284         u32             PreCommonCmdCnt;
1285         SwChnlCmd       PostCommonCmd[MAX_POSTCMD_CNT];
1286         u32             PostCommonCmdCnt;
1287         SwChnlCmd       RfDependCmd[MAX_RFDEPENDCMD_CNT];
1288         u32             RfDependCmdCnt;
1289         SwChnlCmd       *CurrentCmd = NULL;
1290         u8              eRFPath;
1291
1292         RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n",
1293                  __func__, *stage, *step, channel);
1294         if (!IsLegalChannel(priv->ieee80211, channel)) {
1295                 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel);
1296                 /* return true to tell upper caller function this channel
1297                    setting is finished! Or it will in while loop. */
1298                 return true;
1299         }
1300         /* FIXME: need to check whether channel is legal or not here */
1301
1302
1303         /* <1> Fill up pre common command. */
1304         PreCommonCmdCnt = 0;
1305         rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1306                                       MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
1307                                       0, 0, 0);
1308         rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1309                                       MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
1310
1311         /* <2> Fill up post common command. */
1312         PostCommonCmdCnt = 0;
1313
1314         rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
1315                                       MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
1316
1317         /* <3> Fill up RF dependent command. */
1318         RfDependCmdCnt = 0;
1319         switch (priv->rf_chip) {
1320         case RF_8225:
1321                 if (!(channel >= 1 && channel <= 14)) {
1322                         RT_TRACE(COMP_ERR,
1323                                  "illegal channel for Zebra 8225: %d\n",
1324                                  channel);
1325                         return true;
1326                 }
1327                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1328                                               MAX_RFDEPENDCMD_CNT,
1329                                               CmdID_RF_WriteReg,
1330                                               rZebra1_Channel,
1331                                               RF_CHANNEL_TABLE_ZEBRA[channel],
1332                                               10);
1333                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1334                                               MAX_RFDEPENDCMD_CNT,
1335                                               CmdID_End, 0, 0, 0);
1336                 break;
1337
1338         case RF_8256:
1339                 /* TEST!! This is not the table for 8256!! */
1340                 if (!(channel >= 1 && channel <= 14)) {
1341                         RT_TRACE(COMP_ERR,
1342                                  "illegal channel for Zebra 8256: %d\n",
1343                                  channel);
1344                         return true;
1345                 }
1346                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1347                                               MAX_RFDEPENDCMD_CNT,
1348                                               CmdID_RF_WriteReg,
1349                                               rZebra1_Channel, channel, 10);
1350                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1351                                               MAX_RFDEPENDCMD_CNT,
1352                                               CmdID_End, 0, 0, 0);
1353                 break;
1354
1355         case RF_8258:
1356                 break;
1357
1358         default:
1359                 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1360                 return true;
1361                 break;
1362         }
1363
1364
1365         do {
1366                 switch (*stage) {
1367                 case 0:
1368                         CurrentCmd = &PreCommonCmd[*step];
1369                         break;
1370                 case 1:
1371                         CurrentCmd = &RfDependCmd[*step];
1372                         break;
1373                 case 2:
1374                         CurrentCmd = &PostCommonCmd[*step];
1375                         break;
1376                 }
1377
1378                 if (CurrentCmd->CmdID == CmdID_End) {
1379                         if ((*stage) == 2) {
1380                                 (*delay) = CurrentCmd->msDelay;
1381                                 return true;
1382                         } else {
1383                                 (*stage)++;
1384                                 (*step) = 0;
1385                                 continue;
1386                         }
1387                 }
1388
1389                 switch (CurrentCmd->CmdID) {
1390                 case CmdID_SetTxPowerLevel:
1391                         if (priv->card_8192_version == (u8)VERSION_819xU_A)
1392                                 /* consider it later! */
1393                                 rtl8192_SetTxPowerLevel(dev, channel);
1394                         break;
1395                 case CmdID_WritePortUlong:
1396                         write_nic_dword(dev, CurrentCmd->Para1,
1397                                         CurrentCmd->Para2);
1398                         break;
1399                 case CmdID_WritePortUshort:
1400                         write_nic_word(dev, CurrentCmd->Para1,
1401                                        (u16)CurrentCmd->Para2);
1402                         break;
1403                 case CmdID_WritePortUchar:
1404                         write_nic_byte(dev, CurrentCmd->Para1,
1405                                        (u8)CurrentCmd->Para2);
1406                         break;
1407                 case CmdID_RF_WriteReg:
1408                         for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
1409                                 rtl8192_phy_SetRFReg(dev,
1410                                                      (RF90_RADIO_PATH_E)eRFPath,
1411                                                      CurrentCmd->Para1,
1412                                                      bZebra1_ChannelNum,
1413                                                      CurrentCmd->Para2);
1414                         }
1415                         break;
1416                 default:
1417                         break;
1418                 }
1419
1420                 break;
1421         } while (true);
1422
1423         (*delay) = CurrentCmd->msDelay;
1424         (*step)++;
1425         return false;
1426 }
1427
1428 /******************************************************************************
1429  * function:  This function does actually set channel work
1430  * input:     net_device        *dev
1431  *            u8                channel
1432  * output:    none
1433  * return:    none
1434  * notice:    We should not call this function directly
1435  *****************************************************************************/
1436 void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1437 {
1438         struct r8192_priv *priv = ieee80211_priv(dev);
1439         u32     delay = 0;
1440
1441         while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
1442                                              &priv->SwChnlStep, &delay)) {
1443                 if (!priv->up)
1444                         break;
1445         }
1446 }
1447
1448 /******************************************************************************
1449  * function:  Callback routine of the work item for switch channel.
1450  * input:     net_device        *dev
1451  *
1452  * output:    none
1453  * return:    none
1454  *****************************************************************************/
1455 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1456 {
1457
1458         struct r8192_priv *priv = ieee80211_priv(dev);
1459
1460         RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n",
1461                  priv->chan);
1462
1463
1464         rtl8192_phy_FinishSwChnlNow(dev, priv->chan);
1465
1466         RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1467 }
1468
1469 /******************************************************************************
1470  * function:  This function scheduled actual work item to set channel
1471  * input:     net_device        *dev
1472  *            u8                channel   //channel to set
1473  * output:    none
1474  * return:    return code show if workitem is scheduled (1:pass, 0:fail)
1475  * notice:    Delay may be required for RF configuration
1476  ******************************************************************************/
1477 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1478 {
1479         struct r8192_priv *priv = ieee80211_priv(dev);
1480         RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__,
1481                  priv->SwChnlInProgress);
1482         if (!priv->up)
1483                 return false;
1484         if (priv->SwChnlInProgress)
1485                 return false;
1486
1487         /* -------------------------------------------- */
1488         switch (priv->ieee80211->mode) {
1489         case WIRELESS_MODE_A:
1490         case WIRELESS_MODE_N_5G:
1491                 if (channel <= 14) {
1492                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n");
1493                         return false;
1494                 }
1495                 break;
1496         case WIRELESS_MODE_B:
1497                 if (channel > 14) {
1498                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n");
1499                         return false;
1500                 }
1501                 break;
1502         case WIRELESS_MODE_G:
1503         case WIRELESS_MODE_N_24G:
1504                 if (channel > 14) {
1505                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n");
1506                         return false;
1507                 }
1508                 break;
1509         }
1510         /* -------------------------------------------- */
1511
1512         priv->SwChnlInProgress = true;
1513         if (channel == 0)
1514                 channel = 1;
1515
1516         priv->chan = channel;
1517
1518         priv->SwChnlStage = 0;
1519         priv->SwChnlStep = 0;
1520         if (priv->up)
1521                 rtl8192_SwChnl_WorkItem(dev);
1522
1523         priv->SwChnlInProgress = false;
1524         return true;
1525 }
1526
1527 /******************************************************************************
1528  * function:  Callback routine of the work item for set bandwidth mode.
1529  * input:     net_device         *dev
1530  * output:    none
1531  * return:    none
1532  * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
1533  *            test whether current work in the queue or not.//do I?
1534  *****************************************************************************/
1535 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1536 {
1537
1538         struct r8192_priv *priv = ieee80211_priv(dev);
1539         u8 regBwOpMode;
1540
1541         RT_TRACE(COMP_SWBW, "%s()  Switch to %s bandwidth\n", __func__,
1542                  priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
1543
1544
1545         if (priv->rf_chip == RF_PSEUDO_11N) {
1546                 priv->SetBWModeInProgress = false;
1547                 return;
1548         }
1549
1550         /* <1> Set MAC register */
1551         read_nic_byte(dev, BW_OPMODE, &regBwOpMode);
1552
1553         switch (priv->CurrentChannelBW) {
1554         case HT_CHANNEL_WIDTH_20:
1555                 regBwOpMode |= BW_OPMODE_20MHZ;
1556                 /* We have not verify whether this register works */
1557                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1558                 break;
1559
1560         case HT_CHANNEL_WIDTH_20_40:
1561                 regBwOpMode &= ~BW_OPMODE_20MHZ;
1562                 /* We have not verify whether this register works */
1563                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1564                 break;
1565
1566         default:
1567                 RT_TRACE(COMP_ERR,
1568                          "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1569                          priv->CurrentChannelBW);
1570                 break;
1571         }
1572
1573         /* <2> Set PHY related register */
1574         switch (priv->CurrentChannelBW) {
1575         case HT_CHANNEL_WIDTH_20:
1576                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1577                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1578                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1579                                  0x00100000, 1);
1580
1581                 /* Correct the tx power for CCK rate in 20M. */
1582                 priv->cck_present_attentuation =
1583                         priv->cck_present_attentuation_20Mdefault +
1584                         priv->cck_present_attentuation_difference;
1585
1586                 if (priv->cck_present_attentuation > 22)
1587                         priv->cck_present_attentuation = 22;
1588                 if (priv->cck_present_attentuation < 0)
1589                         priv->cck_present_attentuation = 0;
1590                 RT_TRACE(COMP_INIT,
1591                          "20M, pHalData->CCKPresentAttentuation = %d\n",
1592                          priv->cck_present_attentuation);
1593
1594                 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1595                         priv->bcck_in_ch14 = TRUE;
1596                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1597                 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1598                         priv->bcck_in_ch14 = FALSE;
1599                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1600                 } else {
1601                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1602                 }
1603
1604                 break;
1605         case HT_CHANNEL_WIDTH_20_40:
1606                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1607                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1608                 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1609                                  priv->nCur40MhzPrimeSC>>1);
1610                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1611                 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1612                                  priv->nCur40MhzPrimeSC);
1613                 priv->cck_present_attentuation =
1614                         priv->cck_present_attentuation_40Mdefault +
1615                         priv->cck_present_attentuation_difference;
1616
1617                 if (priv->cck_present_attentuation > 22)
1618                         priv->cck_present_attentuation = 22;
1619                 if (priv->cck_present_attentuation < 0)
1620                         priv->cck_present_attentuation = 0;
1621
1622                 RT_TRACE(COMP_INIT,
1623                          "40M, pHalData->CCKPresentAttentuation = %d\n",
1624                          priv->cck_present_attentuation);
1625                 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1626                         priv->bcck_in_ch14 = true;
1627                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1628                 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1629                         priv->bcck_in_ch14 = false;
1630                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1631                 } else {
1632                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1633                 }
1634
1635                 break;
1636         default:
1637                 RT_TRACE(COMP_ERR,
1638                          "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1639                          priv->CurrentChannelBW);
1640                 break;
1641
1642         }
1643         /* Skip over setting of J-mode in BB register here.
1644            Default value is "None J mode". */
1645
1646         /* <3> Set RF related register */
1647         switch (priv->rf_chip) {
1648         case RF_8225:
1649 #ifdef TO_DO_LIST
1650                 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
1651 #endif
1652                 break;
1653
1654         case RF_8256:
1655                 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1656                 break;
1657
1658         case RF_8258:
1659                 break;
1660
1661         case RF_PSEUDO_11N:
1662                 break;
1663
1664         default:
1665                 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1666                 break;
1667         }
1668         priv->SetBWModeInProgress = false;
1669
1670         RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n",
1671                  atomic_read(&priv->ieee80211->atm_swbw));
1672 }
1673
1674 /******************************************************************************
1675  * function:  This function schedules bandwidth switch work.
1676  * input:     struct net_deviceq   *dev
1677  *            HT_CHANNEL_WIDTH     bandwidth  //20M or 40M
1678  *            HT_EXTCHNL_OFFSET    offset     //Upper, Lower, or Don't care
1679  * output:    none
1680  * return:    none
1681  * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
1682  *            test whether current work in the queue or not.//do I?
1683  *****************************************************************************/
1684 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH bandwidth,
1685                        HT_EXTCHNL_OFFSET offset)
1686 {
1687         struct r8192_priv *priv = ieee80211_priv(dev);
1688
1689         if (priv->SetBWModeInProgress)
1690                 return;
1691         priv->SetBWModeInProgress = true;
1692
1693         priv->CurrentChannelBW = bandwidth;
1694
1695         if (offset == HT_EXTCHNL_OFFSET_LOWER)
1696                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1697         else if (offset == HT_EXTCHNL_OFFSET_UPPER)
1698                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1699         else
1700                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1701
1702         rtl8192_SetBWModeWorkItem(dev);
1703
1704 }
1705
1706 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1707 {
1708         struct r8192_priv *priv = ieee80211_priv(dev);
1709
1710         priv->InitialGainOperateType = Operation;
1711
1712         if (priv->up)
1713                 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0);
1714 }
1715
1716 void InitialGainOperateWorkItemCallBack(struct work_struct *work)
1717 {
1718         struct delayed_work *dwork = container_of(work, struct delayed_work,
1719                                                   work);
1720         struct r8192_priv *priv = container_of(dwork, struct r8192_priv,
1721                                                initialgain_operate_wq);
1722         struct net_device *dev = priv->ieee80211->dev;
1723 #define SCAN_RX_INITIAL_GAIN    0x17
1724 #define POWER_DETECTION_TH      0x08
1725         u32     bitmask;
1726         u8      initial_gain;
1727         u8      Operation;
1728
1729         Operation = priv->InitialGainOperateType;
1730
1731         switch (Operation) {
1732         case IG_Backup:
1733                 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1734                 initial_gain = SCAN_RX_INITIAL_GAIN;
1735                 bitmask = bMaskByte0;
1736                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1737                         /* FW DIG OFF */
1738                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1739                 priv->initgain_backup.xaagccore1 =
1740                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask);
1741                 priv->initgain_backup.xbagccore1 =
1742                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask);
1743                 priv->initgain_backup.xcagccore1 =
1744                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask);
1745                 priv->initgain_backup.xdagccore1 =
1746                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask);
1747                 bitmask = bMaskByte2;
1748                 priv->initgain_backup.cca =
1749                         (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask);
1750
1751                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",
1752                          priv->initgain_backup.xaagccore1);
1753                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",
1754                          priv->initgain_backup.xbagccore1);
1755                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",
1756                          priv->initgain_backup.xcagccore1);
1757                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",
1758                          priv->initgain_backup.xdagccore1);
1759                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",
1760                          priv->initgain_backup.cca);
1761
1762                 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n",
1763                          initial_gain);
1764                 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1765                 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1766                 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1767                 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1768                 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n",
1769                          POWER_DETECTION_TH);
1770                 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1771                 break;
1772         case IG_Restore:
1773                 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1774                 bitmask = 0x7f; /* Bit0 ~ Bit6 */
1775                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1776                         /* FW DIG OFF */
1777                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1778
1779                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask,
1780                                  (u32)priv->initgain_backup.xaagccore1);
1781                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask,
1782                                  (u32)priv->initgain_backup.xbagccore1);
1783                 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask,
1784                                  (u32)priv->initgain_backup.xcagccore1);
1785                 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask,
1786                                  (u32)priv->initgain_backup.xdagccore1);
1787                 bitmask  = bMaskByte2;
1788                 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask,
1789                                  (u32)priv->initgain_backup.cca);
1790
1791                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",
1792                          priv->initgain_backup.xaagccore1);
1793                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",
1794                          priv->initgain_backup.xbagccore1);
1795                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",
1796                          priv->initgain_backup.xcagccore1);
1797                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",
1798                          priv->initgain_backup.xdagccore1);
1799                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",
1800                          priv->initgain_backup.cca);
1801
1802                 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
1803
1804                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1805                         /* FW DIG ON */
1806                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1807                 break;
1808         default:
1809                 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
1810                 break;
1811         }
1812 }