drivers/staging/rtl8192u/r819xU_phy.c

   1 #include "r8192U.h"
   2 #include "r8192U_hw.h"
   3 #include "r819xU_phy.h"
   4 #include "r819xU_phyreg.h"
   5 #include "r8190_rtl8256.h"
   6 #include "r8192U_dm.h"
   7 #include "r819xU_firmware_img.h"
   8
   9 #include "dot11d.h"
  10 #include <linux/bitops.h>
  11
  12 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
  13         0,
  14         0x085c, /* 2412 1  */
  15         0x08dc, /* 2417 2  */
  16         0x095c, /* 2422 3  */
  17         0x09dc, /* 2427 4  */
  18         0x0a5c, /* 2432 5  */
  19         0x0adc, /* 2437 6  */
  20         0x0b5c, /* 2442 7  */
  21         0x0bdc, /* 2447 8  */
  22         0x0c5c, /* 2452 9  */
  23         0x0cdc, /* 2457 10 */
  24         0x0d5c, /* 2462 11 */
  25         0x0ddc, /* 2467 12 */
  26         0x0e5c, /* 2472 13 */
  27         0x0f72, /* 2484    */
  28 };
  29
  30
  31 #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
  32 #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
  33 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
  34 #define rtl819XRadioA_Array  Rtl8192UsbRadioA_Array
  35 #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array
  36 #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array
  37 #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array
  38 #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
  39
  40 /******************************************************************************
  41  * function: This function reads BB parameters from header file we generate,
  42  *           and does register read/write
  43  * input:    u32        bitmask  //taget bit pos in the addr to be modified
  44  * output:   none
  45  * return:   u32        return the shift bit position of the mask
  46  ******************************************************************************/
  47 static u32 rtl8192_CalculateBitShift(u32 bitmask)
  48 {
  49         u32 i;
  50
  51         i = ffs(bitmask) - 1;
  52         return i;
  53 }
  54
  55 /******************************************************************************
  56  * function:  This function checks different RF type to execute legal judgement.
  57  *            If RF Path is illegal, we will return false.
  58  * input:     net_device         *dev
  59  *            u32                eRFPath
  60  * output:    none
  61  * return:    0(illegal, false), 1(legal, true)
  62  *****************************************************************************/
  63 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
  64 {
  65         u8 ret = 1;
  66         struct r8192_priv *priv = ieee80211_priv(dev);
  67
  68         if (priv->rf_type == RF_2T4R) {
  69                 ret = 0;
  70         } else if (priv->rf_type == RF_1T2R) {
  71                 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
  72                         ret = 1;
  73                 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
  74                         ret = 0;
  75         }
  76         return ret;
  77 }
  78
  79 /******************************************************************************
  80  * function:  This function sets specific bits to BB register
  81  * input:     net_device *dev
  82  *            u32        reg_addr   //target addr to be modified
  83  *            u32        bitmask    //taget bit pos to be modified
  84  *            u32        data       //value to be write
  85  * output:    none
  86  * return:    none
  87  * notice:
  88  ******************************************************************************/
  89 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
  90                       u32 data)
  91 {
  92
  93         u32 reg, bitshift;
  94
  95         if (bitmask != bMaskDWord) {
  96                 read_nic_dword(dev, reg_addr, &reg);
  97                 bitshift = rtl8192_CalculateBitShift(bitmask);
  98                 reg &= ~bitmask;
  99                 reg |= data << bitshift;
 100                 write_nic_dword(dev, reg_addr, reg);
 101         } else {
 102                 write_nic_dword(dev, reg_addr, data);
 103         }
 104         return;
 105 }
 106
 107 /******************************************************************************
 108  * function:  This function reads specific bits from BB register
 109  * input:     net_device        *dev
 110  *            u32               reg_addr   //target addr to be readback
 111  *            u32               bitmask    //taget bit pos to be readback
 112  * output:    none
 113  * return:    u32               data       //the readback register value
 114  * notice:
 115  ******************************************************************************/
 116 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask)
 117 {
 118         u32 reg, bitshift;
 119
 120         read_nic_dword(dev, reg_addr, &reg);
 121         bitshift = rtl8192_CalculateBitShift(bitmask);
 122
 123         return (reg & bitmask) >> bitshift;
 124 }
 125
 126 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 127                               u32 offset);
 128
 129 static void phy_FwRFSerialWrite(struct net_device *dev,
 130                                 RF90_RADIO_PATH_E eRFPath, u32  offset,
 131                                 u32  data);
 132
 133 /******************************************************************************
 134  * function:  This function reads register from RF chip
 135  * input:     net_device        *dev
 136  *            RF90_RADIO_PATH_E eRFPath    //radio path of A/B/C/D
 137  *            u32               offset     //target address to be read
 138  * output:    none
 139  * return:    u32               readback value
 140  * notice:    There are three types of serial operations:
 141  *            (1) Software serial write.
 142  *            (2)Hardware LSSI-Low Speed Serial Interface.
 143  *            (3)Hardware HSSI-High speed serial write.
 144  *            Driver here need to implement (1) and (2)
 145  *            ---need more spec for this information.
 146  ******************************************************************************/
 147 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
 148                                     RF90_RADIO_PATH_E eRFPath, u32 offset)
 149 {
 150         struct r8192_priv *priv = ieee80211_priv(dev);
 151         u32 ret = 0;
 152         u32 new_offset = 0;
 153         BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
 154
 155         rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
 156         /* Make sure RF register offset is correct */
 157         offset &= 0x3f;
 158
 159         /* Switch page for 8256 RF IC */
 160         if (priv->rf_chip == RF_8256) {
 161                 if (offset >= 31) {
 162                         priv->RfReg0Value[eRFPath] |= 0x140;
 163                         /* Switch to Reg_Mode2 for Reg 31-45 */
 164                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 165                                          bMaskDWord,
 166                                          priv->RfReg0Value[eRFPath]<<16);
 167                         /* Modify offset */
 168                         new_offset = offset - 30;
 169                 } else if (offset >= 16) {
 170                         priv->RfReg0Value[eRFPath] |= 0x100;
 171                         priv->RfReg0Value[eRFPath] &= (~0x40);
 172                         /* Switch to Reg_Mode1 for Reg16-30 */
 173                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 174                                          bMaskDWord,
 175                                          priv->RfReg0Value[eRFPath]<<16);
 176
 177                         new_offset = offset - 15;
 178                 } else {
 179                         new_offset = offset;
 180                 }
 181         } else {
 182                 RT_TRACE((COMP_PHY|COMP_ERR),
 183                          "check RF type here, need to be 8256\n");
 184                 new_offset = offset;
 185         }
 186         /* Put desired read addr to LSSI control Register */
 187         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
 188                          new_offset);
 189         /* Issue a posedge trigger */
 190         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
 191         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 192
 193
 194         /* TODO: we should not delay such a long time. Ask for help from SD3 */
 195         usleep_range(1000, 1000);
 196
 197         ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
 198                                  bLSSIReadBackData);
 199
 200
 201         /* Switch back to Reg_Mode0 */
 202         if (priv->rf_chip == RF_8256) {
 203                 priv->RfReg0Value[eRFPath] &= 0xebf;
 204
 205                 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
 206                                  priv->RfReg0Value[eRFPath] << 16);
 207         }
 208
 209         return ret;
 210 }
 211
 212 /******************************************************************************
 213  * function:  This function writes data to RF register
 214  * input:     net_device        *dev
 215  *            RF90_RADIO_PATH_E eRFPath  //radio path of A/B/C/D
 216  *            u32               offset   //target address to be written
 217  *            u32               data     //the new register data to be written
 218  * output:    none
 219  * return:    none
 220  * notice:    For RF8256 only.
 221  * ===========================================================================
 222  * Reg Mode     RegCTL[1]       RegCTL[0]               Note
 223  *              (Reg00[12])     (Reg00[10])
 224  * ===========================================================================
 225  * Reg_Mode0    0               x                       Reg 0 ~ 15(0x0 ~ 0xf)
 226  * ---------------------------------------------------------------------------
 227  * Reg_Mode1    1               0                       Reg 16 ~ 30(0x1 ~ 0xf)
 228  * ---------------------------------------------------------------------------
 229  * Reg_Mode2    1               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 230  * ---------------------------------------------------------------------------
 231  *****************************************************************************/
 232 static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
 233                                       RF90_RADIO_PATH_E eRFPath, u32 offset,
 234                                       u32 data)
 235 {
 236         struct r8192_priv *priv = ieee80211_priv(dev);
 237         u32 DataAndAddr = 0, new_offset = 0;
 238         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
 239
 240         offset &= 0x3f;
 241         if (priv->rf_chip == RF_8256) {
 242
 243                 if (offset >= 31) {
 244                         priv->RfReg0Value[eRFPath] |= 0x140;
 245                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 246                                          bMaskDWord,
 247                                          priv->RfReg0Value[eRFPath] << 16);
 248                         new_offset = offset - 30;
 249                 } else if (offset >= 16) {
 250                         priv->RfReg0Value[eRFPath] |= 0x100;
 251                         priv->RfReg0Value[eRFPath] &= (~0x40);
 252                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 253                                          bMaskDWord,
 254                                          priv->RfReg0Value[eRFPath]<<16);
 255                         new_offset = offset - 15;
 256                 } else {
 257                         new_offset = offset;
 258                 }
 259         } else {
 260                 RT_TRACE((COMP_PHY|COMP_ERR),
 261                          "check RF type here, need to be 8256\n");
 262                 new_offset = offset;
 263         }
 264
 265         /* Put write addr in [5:0] and write data in [31:16] */
 266         DataAndAddr = (data<<16) | (new_offset&0x3f);
 267
 268         /* Write operation */
 269         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 270
 271
 272         if (offset == 0x0)
 273                 priv->RfReg0Value[eRFPath] = data;
 274
 275         /* Switch back to Reg_Mode0 */
 276         if (priv->rf_chip == RF_8256) {
 277                 if (offset != 0) {
 278                         priv->RfReg0Value[eRFPath] &= 0xebf;
 279                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
 280                                          bMaskDWord,
 281                                          priv->RfReg0Value[eRFPath] << 16);
 282                 }
 283         }
 284         return;
 285 }
 286
 287 /******************************************************************************
 288  * function:  This function set specific bits to RF register
 289  * input:     net_device        dev
 290  *            RF90_RADIO_PATH_E eRFPath  //radio path of A/B/C/D
 291  *            u32               reg_addr //target addr to be modified
 292  *            u32               bitmask  //taget bit pos to be modified
 293  *            u32               data     //value to be written
 294  * output:    none
 295  * return:    none
 296  * notice:
 297  *****************************************************************************/
 298 void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 299                           u32 reg_addr, u32 bitmask, u32 data)
 300 {
 301         struct r8192_priv *priv = ieee80211_priv(dev);
 302         u32 reg, bitshift;
 303
 304         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 305                 return;
 306
 307         if (priv->Rf_Mode == RF_OP_By_FW) {
 308                 if (bitmask != bMask12Bits) {
 309                         /* RF data is 12 bits only */
 310                         reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
 311                         bitshift =  rtl8192_CalculateBitShift(bitmask);
 312                         reg &= ~bitmask;
 313                         reg |= data << bitshift;
 314
 315                         phy_FwRFSerialWrite(dev, eRFPath, reg_addr, reg);
 316                 } else {
 317                         phy_FwRFSerialWrite(dev, eRFPath, reg_addr, data);
 318                 }
 319
 320                 udelay(200);
 321
 322         } else {
 323                 if (bitmask != bMask12Bits) {
 324                         /* RF data is 12 bits only */
 325                         reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
 326                         bitshift =  rtl8192_CalculateBitShift(bitmask);
 327                         reg &= ~bitmask;
 328                         reg |= data << bitshift;
 329
 330                         rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, reg);
 331                 } else {
 332                         rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, data);
 333                 }
 334         }
 335         return;
 336 }
 337
 338 /******************************************************************************
 339  * function:  This function reads specific bits from RF register
 340  * input:     net_device        *dev
 341  *            u32               reg_addr //target addr to be readback
 342  *            u32               bitmask  //taget bit pos to be readback
 343  * output:    none
 344  * return:    u32               data     //the readback register value
 345  * notice:
 346  *****************************************************************************/
 347 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 348                            u32 reg_addr, u32 bitmask)
 349 {
 350         u32 reg, bitshift;
 351         struct r8192_priv *priv = ieee80211_priv(dev);
 352
 353
 354         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 355                 return 0;
 356         if (priv->Rf_Mode == RF_OP_By_FW) {
 357                 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
 358                 bitshift =  rtl8192_CalculateBitShift(bitmask);
 359                 reg = (reg & bitmask) >> bitshift;
 360                 udelay(200);
 361                 return reg;
 362         } else {
 363                 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
 364                 bitshift =  rtl8192_CalculateBitShift(bitmask);
 365                 reg = (reg & bitmask) >> bitshift;
 366                 return reg;
 367         }
 368 }
 369
 370 /******************************************************************************
 371  * function:  We support firmware to execute RF-R/W.
 372  * input:     net_device        *dev
 373  *            RF90_RADIO_PATH_E eRFPath
 374  *            u32               offset
 375  * output:    none
 376  * return:    u32
 377  * notice:
 378  ****************************************************************************/
 379 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 380                               u32 offset)
 381 {
 382         u32             reg = 0;
 383         u32             data = 0;
 384         u8              time = 0;
 385         u32             tmp;
 386
 387         /* Firmware RF Write control.
 388          * We can not execute the scheme in the initial step.
 389          * Otherwise, RF-R/W will waste much time.
 390          * This is only for site survey. */
 391         /* 1. Read operation need not insert data. bit 0-11 */
 392         /* 2. Write RF register address. bit 12-19 */
 393         data |= ((offset&0xFF)<<12);
 394         /* 3. Write RF path.  bit 20-21 */
 395         data |= ((eRFPath&0x3)<<20);
 396         /* 4. Set RF read indicator. bit 22=0 */
 397         /* 5. Trigger Fw to operate the command. bit 31 */
 398         data |= 0x80000000;
 399         /* 6. We can not execute read operation if bit 31 is 1. */
 400         read_nic_dword(dev, QPNR, &tmp);
 401         while (tmp & 0x80000000) {
 402                 /* If FW can not finish RF-R/W for more than ?? times.
 403                    We must reset FW. */
 404                 if (time++ < 100) {
 405                         udelay(10);
 406                         read_nic_dword(dev, QPNR, &tmp);
 407                 } else {
 408                         break;
 409                 }
 410         }
 411         /* 7. Execute read operation. */
 412         write_nic_dword(dev, QPNR, data);
 413         /* 8. Check if firmware send back RF content. */
 414         read_nic_dword(dev, QPNR, &tmp);
 415         while (tmp & 0x80000000) {
 416                 /* If FW can not finish RF-R/W for more than ?? times.
 417                    We must reset FW. */
 418                 if (time++ < 100) {
 419                         udelay(10);
 420                         read_nic_dword(dev, QPNR, &tmp);
 421                 } else {
 422                         return 0;
 423                 }
 424         }
 425         read_nic_dword(dev, RF_DATA, &reg);
 426
 427         return reg;
 428 }
 429
 430 /******************************************************************************
 431  * function:  We support firmware to execute RF-R/W.
 432  * input:     net_device        *dev
 433  *            RF90_RADIO_PATH_E eRFPath
 434  *            u32               offset
 435  *            u32               data
 436  * output:    none
 437  * return:    none
 438  * notice:
 439  ****************************************************************************/
 440 static void phy_FwRFSerialWrite(struct net_device *dev,
 441                                 RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data)
 442 {
 443         u8      time = 0;
 444         u32     tmp;
 445
 446         /* Firmware RF Write control.
 447          * We can not execute the scheme in the initial step.
 448          * Otherwise, RF-R/W will waste much time.
 449          * This is only for site survey. */
 450
 451         /* 1. Set driver write bit and 12 bit data. bit 0-11 */
 452         /* 2. Write RF register address. bit 12-19 */
 453         data |= ((offset&0xFF)<<12);
 454         /* 3. Write RF path.  bit 20-21 */
 455         data |= ((eRFPath&0x3)<<20);
 456         /* 4. Set RF write indicator. bit 22=1 */
 457         data |= 0x400000;
 458         /* 5. Trigger Fw to operate the command. bit 31=1 */
 459         data |= 0x80000000;
 460
 461         /* 6. Write operation. We can not write if bit 31 is 1. */
 462         read_nic_dword(dev, QPNR, &tmp);
 463         while (tmp & 0x80000000) {
 464                 /* If FW can not finish RF-R/W for more than ?? times.
 465                    We must reset FW. */
 466                 if (time++ < 100) {
 467                         udelay(10);
 468                         read_nic_dword(dev, QPNR, &tmp);
 469                 } else {
 470                         break;
 471                 }
 472         }
 473         /* 7. No matter check bit. We always force the write.
 474            Because FW will not accept the command. */
 475         write_nic_dword(dev, QPNR, data);
 476         /* According to test, we must delay 20us to wait firmware
 477            to finish RF write operation. */
 478         /* We support delay in firmware side now. */
 479 }
 480
 481 /******************************************************************************
 482  * function:  This function reads BB parameters from header file we generate,
 483  *            and do register read/write
 484  * input:     net_device        *dev
 485  * output:    none
 486  * return:    none
 487  * notice:    BB parameters may change all the time, so please make
 488  *            sure it has been synced with the newest.
 489  *****************************************************************************/
 490 void rtl8192_phy_configmac(struct net_device *dev)
 491 {
 492         u32 dwArrayLen = 0, i;
 493         u32 *pdwArray = NULL;
 494         struct r8192_priv *priv = ieee80211_priv(dev);
 495
 496         if (priv->btxpowerdata_readfromEEPORM) {
 497                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
 498                 dwArrayLen = MACPHY_Array_PGLength;
 499                 pdwArray = rtl819XMACPHY_Array_PG;
 500
 501         } else {
 502                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
 503                 dwArrayLen = MACPHY_ArrayLength;
 504                 pdwArray = rtl819XMACPHY_Array;
 505         }
 506         for (i = 0; i < dwArrayLen; i = i+3) {
 507                 if (pdwArray[i] == 0x318)
 508                         pdwArray[i+2] = 0x00000800;
 509
 510                 RT_TRACE(COMP_DBG,
 511                          "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n",
 512                          pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
 513                 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
 514                                  pdwArray[i+2]);
 515         }
 516         return;
 517 }
 518
 519 /******************************************************************************
 520  * function:  This function does dirty work
 521  * input:     net_device        *dev
 522  *            u8                ConfigType
 523  * output:    none
 524  * return:    none
 525  * notice:    BB parameters may change all the time, so please make
 526  *            sure it has been synced with the newest.
 527  *****************************************************************************/
 528 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
 529 {
 530         u32 i;
 531
 532 #ifdef TO_DO_LIST
 533         u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
 534
 535         if (Adapter->bInHctTest) {
 536                 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
 537                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
 538                 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
 539                 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
 540         }
 541 #endif
 542         if (ConfigType == BaseBand_Config_PHY_REG) {
 543                 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) {
 544                         rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i],
 545                                          bMaskDWord,
 546                                          rtl819XPHY_REG_1T2RArray[i+1]);
 547                         RT_TRACE(COMP_DBG,
 548                                  "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n",
 549                                  i, rtl819XPHY_REG_1T2RArray[i],
 550                                  rtl819XPHY_REG_1T2RArray[i+1]);
 551                 }
 552         } else if (ConfigType == BaseBand_Config_AGC_TAB) {
 553                 for (i = 0; i < AGCTAB_ArrayLength; i += 2) {
 554                         rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i],
 555                                          bMaskDWord, rtl819XAGCTAB_Array[i+1]);
 556                         RT_TRACE(COMP_DBG,
 557                                  "i: %x, rtl819XAGCTAB_Array[0]=%x rtl819XAGCTAB_Array[1]=%x\n",
 558                                  i, rtl819XAGCTAB_Array[i],
 559                                  rtl819XAGCTAB_Array[i+1]);
 560                 }
 561         }
 562         return;
 563 }
 564
 565 /******************************************************************************
 566  * function:  This function initializes Register definition offset for
 567  *            Radio Path A/B/C/D
 568  * input:     net_device        *dev
 569  * output:    none
 570  * return:    none
 571  * notice:    Initialization value here is constant and it should never
 572  *            be changed
 573  *****************************************************************************/
 574 static void rtl8192_InitBBRFRegDef(struct net_device *dev)
 575 {
 576         struct r8192_priv *priv = ieee80211_priv(dev);
 577
 578         /* RF Interface Software Control */
 579         /* 16 LSBs if read 32-bit from 0x870 */
 580         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 581         /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
 582         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
 583         /* 16 LSBs if read 32-bit from 0x874 */
 584         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 585         /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
 586         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
 587
 588         /* RF Interface Readback Value */
 589         /* 16 LSBs if read 32-bit from 0x8E0 */
 590         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 591         /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
 592         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
 593         /* 16 LSBs if read 32-bit from 0x8E4 */
 594         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 595         /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
 596         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
 597
 598         /* RF Interface Output (and Enable) */
 599         /* 16 LSBs if read 32-bit from 0x860 */
 600         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
 601         /* 16 LSBs if read 32-bit from 0x864 */
 602         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
 603         /* 16 LSBs if read 32-bit from 0x868 */
 604         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
 605         /* 16 LSBs if read 32-bit from 0x86C */
 606         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
 607
 608         /* RF Interface (Output and) Enable */
 609         /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
 610         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
 611         /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
 612         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
 613         /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */
 614         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
 615         /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */
 616         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
 617
 618         /* Addr of LSSI. Write RF register by driver */
 619         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
 620         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 621         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
 622         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
 623
 624         /* RF parameter */
 625         /* BB Band Select */
 626         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 627         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 628         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 629         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 630
 631         /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
 632         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
 633         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
 634         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
 635         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
 636
 637         /* Tranceiver A~D HSSI Parameter-1 */
 638         /* wire control parameter1 */
 639         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
 640         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
 641         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
 642         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
 643
 644         /* Tranceiver A~D HSSI Parameter-2 */
 645         /* wire control parameter2 */
 646         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
 647         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
 648         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
 649         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
 650
 651         /* RF Switch Control */
 652         /* TR/Ant switch control */
 653         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 654         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 655         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 656         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 657
 658         /* AGC control 1 */
 659         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
 660         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
 661         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
 662         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
 663
 664         /* AGC control 2 */
 665         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
 666         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
 667         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
 668         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
 669
 670         /* RX AFE control 1 */
 671         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
 672         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
 673         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
 674         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
 675
 676         /* RX AFE control 1 */
 677         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
 678         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
 679         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
 680         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
 681
 682         /* Tx AFE control 1 */
 683         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
 684         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
 685         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
 686         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
 687
 688         /* Tx AFE control 2 */
 689         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
 690         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
 691         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
 692         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
 693
 694         /* Tranceiver LSSI Readback */
 695         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 696         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 697         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
 698         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
 699 }
 700
 701 /******************************************************************************
 702  * function:  This function is to write register and then readback to make
 703  *            sure whether BB and RF is OK
 704  * input:     net_device        *dev
 705  *            HW90_BLOCK_E      CheckBlock
 706  *            RF90_RADIO_PATH_E eRFPath  //only used when checkblock is
 707  *                                       //HW90_BLOCK_RF
 708  * output:    none
 709  * return:    return whether BB and RF is ok (0:OK, 1:Fail)
 710  * notice:    This function may be removed in the ASIC
 711  ******************************************************************************/
 712 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock,
 713                             RF90_RADIO_PATH_E eRFPath)
 714 {
 715         u8 ret = 0;
 716         u32 i, CheckTimes = 4, reg = 0;
 717         u32 WriteAddr[4];
 718         u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
 719
 720         /* Initialize register address offset to be checked */
 721         WriteAddr[HW90_BLOCK_MAC] = 0x100;
 722         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
 723         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
 724         WriteAddr[HW90_BLOCK_RF] = 0x3;
 725         RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock);
 726         for (i = 0; i < CheckTimes; i++) {
 727
 728                 /* Write data to register and readback */
 729                 switch (CheckBlock) {
 730                 case HW90_BLOCK_MAC:
 731                         RT_TRACE(COMP_ERR,
 732                                  "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
 733                         break;
 734
 735                 case HW90_BLOCK_PHY0:
 736                 case HW90_BLOCK_PHY1:
 737                         write_nic_dword(dev, WriteAddr[CheckBlock],
 738                                         WriteData[i]);
 739                         read_nic_dword(dev, WriteAddr[CheckBlock], &reg);
 740                         break;
 741
 742                 case HW90_BLOCK_RF:
 743                         WriteData[i] &= 0xfff;
 744                         rtl8192_phy_SetRFReg(dev, eRFPath,
 745                                              WriteAddr[HW90_BLOCK_RF],
 746                                              bMask12Bits, WriteData[i]);
 747                         /* TODO: we should not delay for such a long time.
 748                            Ask SD3 */
 749                         usleep_range(1000, 1000);
 750                         reg = rtl8192_phy_QueryRFReg(dev, eRFPath,
 751                                                      WriteAddr[HW90_BLOCK_RF],
 752                                                      bMask12Bits);
 753                         usleep_range(1000, 1000);
 754                         break;
 755
 756                 default:
 757                         ret = 1;
 758                         break;
 759                 }
 760
 761
 762                 /* Check whether readback data is correct */
 763                 if (reg != WriteData[i]) {
 764                         RT_TRACE((COMP_PHY|COMP_ERR),
 765                                  "error reg: %x, WriteData: %x\n",
 766                                  reg, WriteData[i]);
 767                         ret = 1;
 768                         break;
 769                 }
 770         }
 771
 772         return ret;
 773 }
 774
 775 /******************************************************************************
 776  * function:  This function initializes BB&RF
 777  * input:     net_device        *dev
 778  * output:    none
 779  * return:    none
 780  * notice:    Initialization value may change all the time, so please make
 781  *            sure it has been synced with the newest.
 782  ******************************************************************************/
 783 static void rtl8192_BB_Config_ParaFile(struct net_device *dev)
 784 {
 785         struct r8192_priv *priv = ieee80211_priv(dev);
 786         u8 reg_u8 = 0, eCheckItem = 0, status = 0;
 787         u32 reg_u32 = 0;
 788
 789         /**************************************
 790          * <1> Initialize BaseBand
 791          *************************************/
 792
 793         /* --set BB Global Reset-- */
 794         read_nic_byte(dev, BB_GLOBAL_RESET, &reg_u8);
 795         write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT));
 796         mdelay(50);
 797         /* ---set BB reset Active--- */
 798         read_nic_dword(dev, CPU_GEN, &reg_u32);
 799         write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST)));
 800
 801         /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */
 802         /* TODO: this function should be removed on ASIC */
 803         for (eCheckItem = (HW90_BLOCK_E)HW90_BLOCK_PHY0;
 804              eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
 805                 /* don't care RF path */
 806                 status = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem,
 807                                                   (RF90_RADIO_PATH_E)0);
 808                 if (status != 0) {
 809                         RT_TRACE((COMP_ERR | COMP_PHY),
 810                                  "PHY_RF8256_Config(): Check PHY%d Fail!!\n",
 811                                  eCheckItem-1);
 812                         return;
 813                 }
 814         }
 815         /* ---- Set CCK and OFDM Block "OFF"---- */
 816         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
 817         /* ----BB Register Initilazation---- */
 818         /* ==m==>Set PHY REG From Header<==m== */
 819         rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
 820
 821         /* ----Set BB reset de-Active---- */
 822         read_nic_dword(dev, CPU_GEN, &reg_u32);
 823         write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST));
 824
 825         /* ----BB AGC table Initialization---- */
 826         /* ==m==>Set PHY REG From Header<==m== */
 827         rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
 828
 829         /* ----Enable XSTAL ---- */
 830         write_nic_byte_E(dev, 0x5e, 0x00);
 831         if (priv->card_8192_version == (u8)VERSION_819xU_A) {
 832                 /* Antenna gain offset from B/C/D to A */
 833                 reg_u32 = (priv->AntennaTxPwDiff[1]<<4 |
 834                            priv->AntennaTxPwDiff[0]);
 835                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC),
 836                                  reg_u32);
 837
 838                 /* XSTALLCap */
 839                 reg_u32 = priv->CrystalCap & 0xf;
 840                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap,
 841                                  reg_u32);
 842         }
 843
 844         /* Check if the CCK HighPower is turned ON.
 845            This is used to calculate PWDB. */
 846         priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev,
 847                                                      rFPGA0_XA_HSSIParameter2,
 848                                                      0x200);
 849         return;
 850 }
 851
 852 /******************************************************************************
 853  * function:  This function initializes BB&RF
 854  * input:     net_device        *dev
 855  * output:    none
 856  * return:    none
 857  * notice:    Initialization value may change all the time, so please make
 858  *            sure it has been synced with the newest.
 859  *****************************************************************************/
 860 void rtl8192_BBConfig(struct net_device *dev)
 861 {
 862         rtl8192_InitBBRFRegDef(dev);
 863         /* config BB&RF. As hardCode based initialization has not been well
 864          * implemented, so use file first.
 865          * FIXME: should implement it for hardcode? */
 866         rtl8192_BB_Config_ParaFile(dev);
 867         return;
 868 }
 869
 870
 871 /******************************************************************************
 872  * function:  This function obtains the initialization value of Tx power Level
 873  *            offset
 874  * input:     net_device        *dev
 875  * output:    none
 876  * return:    none
 877  *****************************************************************************/
 878 void rtl8192_phy_getTxPower(struct net_device *dev)
 879 {
 880         struct r8192_priv *priv = ieee80211_priv(dev);
 881         u8 tmp;
 882
 883         read_nic_dword(dev, rTxAGC_Rate18_06,
 884                        &priv->MCSTxPowerLevelOriginalOffset[0]);
 885         read_nic_dword(dev, rTxAGC_Rate54_24,
 886                        &priv->MCSTxPowerLevelOriginalOffset[1]);
 887         read_nic_dword(dev, rTxAGC_Mcs03_Mcs00,
 888                        &priv->MCSTxPowerLevelOriginalOffset[2]);
 889         read_nic_dword(dev, rTxAGC_Mcs07_Mcs04,
 890                        &priv->MCSTxPowerLevelOriginalOffset[3]);
 891         read_nic_dword(dev, rTxAGC_Mcs11_Mcs08,
 892                        &priv->MCSTxPowerLevelOriginalOffset[4]);
 893         read_nic_dword(dev, rTxAGC_Mcs15_Mcs12,
 894                        &priv->MCSTxPowerLevelOriginalOffset[5]);
 895
 896         /* Read rx initial gain */
 897         read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
 898         read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
 899         read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
 900         read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
 901         RT_TRACE(COMP_INIT,
 902                  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
 903                  priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
 904                  priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
 905
 906         /* Read framesync */
 907         read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
 908         read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
 909         priv->framesyncC34 = tmp;
 910         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
 911                 rOFDM0_RxDetector3, priv->framesync);
 912
 913         /* Read SIFS (save the value read fome MACPHY_REG.txt) */
 914         read_nic_word(dev, SIFS, &priv->SifsTime);
 915
 916         return;
 917 }
 918
 919 /******************************************************************************
 920  * function:  This function sets the initialization value of Tx power Level
 921  *            offset
 922  * input:     net_device        *dev
 923  *            u8                channel
 924  * output:    none
 925  * return:    none
 926  ******************************************************************************/
 927 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
 928 {
 929         struct r8192_priv *priv = ieee80211_priv(dev);
 930         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
 931         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
 932
 933         switch (priv->rf_chip) {
 934         case RF_8256:
 935                 /* need further implement */
 936                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
 937                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
 938                 break;
 939         default:
 940                 RT_TRACE((COMP_PHY|COMP_ERR),
 941                          "error RF chipID(8225 or 8258) in function %s()\n",
 942                          __func__);
 943                 break;
 944         }
 945         return;
 946 }
 947
 948 /******************************************************************************
 949  * function:  This function checks Rf chip to do RF config
 950  * input:     net_device        *dev
 951  * output:    none
 952  * return:    only 8256 is supported
 953  ******************************************************************************/
 954 void rtl8192_phy_RFConfig(struct net_device *dev)
 955 {
 956         struct r8192_priv *priv = ieee80211_priv(dev);
 957
 958         switch (priv->rf_chip) {
 959                 case RF_8256:
 960                         PHY_RF8256_Config(dev);
 961                         break;
 962                 default:
 963                         RT_TRACE(COMP_ERR, "error chip id\n");
 964                         break;
 965         }
 966         return;
 967 }
 968
 969 /******************************************************************************
 970  * function:  This function updates Initial gain
 971  * input:     net_device        *dev
 972  * output:    none
 973  * return:    As Windows has not implemented this, wait for complement
 974  ******************************************************************************/
 975 void rtl8192_phy_updateInitGain(struct net_device *dev)
 976 {
 977         return;
 978 }
 979
 980 /******************************************************************************
 981  * function:  This function read RF parameters from general head file,
 982  *            and do RF 3-wire
 983  * input:     net_device        *dev
 984  *            RF90_RADIO_PATH_E eRFPath
 985  * output:    none
 986  * return:    return code show if RF configuration is successful(0:pass, 1:fail)
 987  * notice:    Delay may be required for RF configuration
 988  *****************************************************************************/
 989 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
 990                                       RF90_RADIO_PATH_E eRFPath)
 991 {
 992
 993         int i;
 994
 995         switch (eRFPath) {
 996         case RF90_PATH_A:
 997                 for (i = 0; i < RadioA_ArrayLength; i = i+2) {
 998
 999                         if (rtl819XRadioA_Array[i] == 0xfe) {
1000                                 mdelay(100);
1001                                 continue;
1002                         }
1003                         rtl8192_phy_SetRFReg(dev, eRFPath,
1004                                              rtl819XRadioA_Array[i],
1005                                              bMask12Bits,
1006                                              rtl819XRadioA_Array[i+1]);
1007                         mdelay(1);
1008
1009                 }
1010                 break;
1011         case RF90_PATH_B:
1012                 for (i = 0; i < RadioB_ArrayLength; i = i+2) {
1013
1014                         if (rtl819XRadioB_Array[i] == 0xfe) {
1015                                 mdelay(100);
1016                                 continue;
1017                         }
1018                         rtl8192_phy_SetRFReg(dev, eRFPath,
1019                                              rtl819XRadioB_Array[i],
1020                                              bMask12Bits,
1021                                              rtl819XRadioB_Array[i+1]);
1022                         mdelay(1);
1023
1024                 }
1025                 break;
1026         case RF90_PATH_C:
1027                 for (i = 0; i < RadioC_ArrayLength; i = i+2) {
1028
1029                         if (rtl819XRadioC_Array[i] == 0xfe) {
1030                                 mdelay(100);
1031                                 continue;
1032                         }
1033                         rtl8192_phy_SetRFReg(dev, eRFPath,
1034                                              rtl819XRadioC_Array[i],
1035                                              bMask12Bits,
1036                                              rtl819XRadioC_Array[i+1]);
1037                         mdelay(1);
1038
1039                 }
1040                 break;
1041         case RF90_PATH_D:
1042                 for (i = 0; i < RadioD_ArrayLength; i = i+2) {
1043
1044                         if (rtl819XRadioD_Array[i] == 0xfe) {
1045                                 mdelay(100);
1046                                 continue;
1047                         }
1048                         rtl8192_phy_SetRFReg(dev, eRFPath,
1049                                              rtl819XRadioD_Array[i],
1050                                              bMask12Bits,
1051                                              rtl819XRadioD_Array[i+1]);
1052                         mdelay(1);
1053
1054                 }
1055                 break;
1056         default:
1057                 break;
1058         }
1059
1060         return 0;
1061
1062 }
1063
1064 /******************************************************************************
1065  * function:  This function sets Tx Power of the channel
1066  * input:     net_device        *dev
1067  *            u8                channel
1068  * output:    none
1069  * return:    none
1070  * notice:
1071  ******************************************************************************/
1072 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
1073 {
1074         struct r8192_priv *priv = ieee80211_priv(dev);
1075         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
1076         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1077
1078         switch (priv->rf_chip) {
1079         case RF_8225:
1080 #ifdef TO_DO_LIST
1081                 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
1082                 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
1083 #endif
1084                 break;
1085
1086         case RF_8256:
1087                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1088                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1089                 break;
1090
1091         case RF_8258:
1092                 break;
1093         default:
1094                 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__);
1095                 break;
1096         }
1097         return;
1098 }
1099
1100 /******************************************************************************
1101  * function:  This function sets RF state on or off
1102  * input:     net_device         *dev
1103  *            RT_RF_POWER_STATE  eRFPowerState  //Power State to set
1104  * output:    none
1105  * return:    none
1106  * notice:
1107  *****************************************************************************/
1108 bool rtl8192_SetRFPowerState(struct net_device *dev,
1109                              RT_RF_POWER_STATE eRFPowerState)
1110 {
1111         bool                            bResult = true;
1112         struct r8192_priv *priv = ieee80211_priv(dev);
1113
1114         if (eRFPowerState == priv->ieee80211->eRFPowerState)
1115                 return false;
1116
1117         if (priv->SetRFPowerStateInProgress == true)
1118                 return false;
1119
1120         priv->SetRFPowerStateInProgress = true;
1121
1122         switch (priv->rf_chip) {
1123         case RF_8256:
1124                 switch (eRFPowerState) {
1125                 case eRfOn:
1126                         /* RF-A, RF-B */
1127                         /* enable RF-Chip A/B - 0x860[4] */
1128                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4,
1129                                          0x1);
1130                         /* analog to digital on - 0x88c[9:8] */
1131                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300,
1132                                          0x3);
1133                         /* digital to analog on - 0x880[4:3] */
1134                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1135                                          0x3);
1136                         /* rx antenna on - 0xc04[1:0] */
1137                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
1138                         /* rx antenna on - 0xd04[1:0] */
1139                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
1140                         /* analog to digital part2 on - 0x880[6:5] */
1141                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1142                                          0x3);
1143
1144                         break;
1145
1146                 case eRfSleep:
1147
1148                         break;
1149
1150                 case eRfOff:
1151                         /* RF-A, RF-B */
1152                         /* disable RF-Chip A/B - 0x860[4] */
1153                         rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4,
1154                                          0x0);
1155                         /* analog to digital off, for power save */
1156                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00,
1157                                          0x0); /* 0x88c[11:8] */
1158                         /* digital to analog off, for power save - 0x880[4:3] */
1159                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1160                                          0x0);
1161                         /* rx antenna off - 0xc04[3:0] */
1162                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1163                         /* rx antenna off - 0xd04[3:0] */
1164                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1165                         /* analog to digital part2 off, for power save */
1166                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1167                                          0x0); /* 0x880[6:5] */
1168
1169                         break;
1170
1171                 default:
1172                         bResult = false;
1173                         RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n",
1174                                  __func__, eRFPowerState);
1175                         break;
1176                 }
1177                 break;
1178         default:
1179                 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1180                 break;
1181         }
1182 #ifdef TO_DO_LIST
1183         if (bResult) {
1184                 /* Update current RF state variable. */
1185                 pHalData->eRFPowerState = eRFPowerState;
1186                 switch (pHalData->RFChipID) {
1187                 case RF_8256:
1188                         switch (pHalData->eRFPowerState) {
1189                         case eRfOff:
1190                                 /* If Rf off reason is from IPS,
1191                                    LED should blink with no link */
1192                                 if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS)
1193                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1194                                 else
1195                                         /* Turn off LED if RF is not ON. */
1196                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
1197                                 break;
1198
1199                         case eRfOn:
1200                                 /* Turn on RF we are still linked, which might
1201                                    happen when we quickly turn off and on HW RF.
1202                                  */
1203                                 if (pMgntInfo->bMediaConnect == TRUE)
1204                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1205                                 else
1206                                         /* Turn off LED if RF is not ON. */
1207                                         Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1208                                 break;
1209
1210                         default:
1211                                 break;
1212                         }
1213                         break;
1214
1215                 default:
1216                         RT_TRACE(COMP_RF, DBG_LOUD, "%s(): Unknown RF type\n",
1217                                  __func__);
1218                         break;
1219                 }
1220
1221         }
1222 #endif
1223         priv->SetRFPowerStateInProgress = false;
1224
1225         return bResult;
1226 }
1227
1228 /******************************************************************************
1229  * function:  This function sets command table variable (struct SwChnlCmd).
1230  * input:     SwChnlCmd      *CmdTable    //table to be set
1231  *            u32            CmdTableIdx  //variable index in table to be set
1232  *            u32            CmdTableSz   //table size
1233  *            SwChnlCmdID    CmdID        //command ID to set
1234  *            u32            Para1
1235  *            u32            Para2
1236  *            u32            msDelay
1237  * output:
1238  * return:    true if finished, false otherwise
1239  * notice:
1240  ******************************************************************************/
1241 static u8 rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd *CmdTable, u32 CmdTableIdx,
1242                                         u32 CmdTableSz, SwChnlCmdID CmdID,
1243                                         u32 Para1, u32 Para2, u32 msDelay)
1244 {
1245         SwChnlCmd *pCmd;
1246
1247         if (CmdTable == NULL) {
1248                 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__);
1249                 return false;
1250         }
1251         if (CmdTableIdx >= CmdTableSz) {
1252                 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1253                          __func__, CmdTableIdx, CmdTableSz);
1254                 return false;
1255         }
1256
1257         pCmd = CmdTable + CmdTableIdx;
1258         pCmd->CmdID = CmdID;
1259         pCmd->Para1 = Para1;
1260         pCmd->Para2 = Para2;
1261         pCmd->msDelay = msDelay;
1262
1263         return true;
1264 }
1265
1266 /******************************************************************************
1267  * function:  This function sets channel step by step
1268  * input:     net_device        *dev
1269  *            u8                channel
1270  *            u8                *stage   //3 stages
1271  *            u8                *step
1272  *            u32               *delay   //whether need to delay
1273  * output:    store new stage, step and delay for next step
1274  *            (combine with function above)
1275  * return:    true if finished, false otherwise
1276  * notice:    Wait for simpler function to replace it
1277  *****************************************************************************/
1278 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
1279                                        u8 *stage, u8 *step, u32 *delay)
1280 {
1281         struct r8192_priv *priv = ieee80211_priv(dev);
1282         SwChnlCmd       PreCommonCmd[MAX_PRECMD_CNT];
1283         u32             PreCommonCmdCnt;
1284         SwChnlCmd       PostCommonCmd[MAX_POSTCMD_CNT];
1285         u32             PostCommonCmdCnt;
1286         SwChnlCmd       RfDependCmd[MAX_RFDEPENDCMD_CNT];
1287         u32             RfDependCmdCnt;
1288         SwChnlCmd       *CurrentCmd = NULL;
1289         u8              eRFPath;
1290
1291         RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n",
1292                  __func__, *stage, *step, channel);
1293         if (!IsLegalChannel(priv->ieee80211, channel)) {
1294                 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel);
1295                 /* return true to tell upper caller function this channel
1296                    setting is finished! Or it will in while loop. */
1297                 return true;
1298         }
1299         /* FIXME: need to check whether channel is legal or not here */
1300
1301
1302         /* <1> Fill up pre common command. */
1303         PreCommonCmdCnt = 0;
1304         rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1305                                       MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
1306                                       0, 0, 0);
1307         rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1308                                       MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
1309
1310         /* <2> Fill up post common command. */
1311         PostCommonCmdCnt = 0;
1312
1313         rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
1314                                       MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
1315
1316         /* <3> Fill up RF dependent command. */
1317         RfDependCmdCnt = 0;
1318         switch (priv->rf_chip) {
1319         case RF_8225:
1320                 if (!(channel >= 1 && channel <= 14)) {
1321                         RT_TRACE(COMP_ERR,
1322                                  "illegal channel for Zebra 8225: %d\n",
1323                                  channel);
1324                         return true;
1325                 }
1326                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1327                                               MAX_RFDEPENDCMD_CNT,
1328                                               CmdID_RF_WriteReg,
1329                                               rZebra1_Channel,
1330                                               RF_CHANNEL_TABLE_ZEBRA[channel],
1331                                               10);
1332                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1333                                               MAX_RFDEPENDCMD_CNT,
1334                                               CmdID_End, 0, 0, 0);
1335                 break;
1336
1337         case RF_8256:
1338                 /* TEST!! This is not the table for 8256!! */
1339                 if (!(channel >= 1 && channel <= 14)) {
1340                         RT_TRACE(COMP_ERR,
1341                                  "illegal channel for Zebra 8256: %d\n",
1342                                  channel);
1343                         return true;
1344                 }
1345                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1346                                               MAX_RFDEPENDCMD_CNT,
1347                                               CmdID_RF_WriteReg,
1348                                               rZebra1_Channel, channel, 10);
1349                 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1350                                               MAX_RFDEPENDCMD_CNT,
1351                                               CmdID_End, 0, 0, 0);
1352                 break;
1353
1354         case RF_8258:
1355                 break;
1356
1357         default:
1358                 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1359                 return true;
1360                 break;
1361         }
1362
1363
1364         do {
1365                 switch (*stage) {
1366                 case 0:
1367                         CurrentCmd = &PreCommonCmd[*step];
1368                         break;
1369                 case 1:
1370                         CurrentCmd = &RfDependCmd[*step];
1371                         break;
1372                 case 2:
1373                         CurrentCmd = &PostCommonCmd[*step];
1374                         break;
1375                 }
1376
1377                 if (CurrentCmd->CmdID == CmdID_End) {
1378                         if ((*stage) == 2) {
1379                                 (*delay) = CurrentCmd->msDelay;
1380                                 return true;
1381                         } else {
1382                                 (*stage)++;
1383                                 (*step) = 0;
1384                                 continue;
1385                         }
1386                 }
1387
1388                 switch (CurrentCmd->CmdID) {
1389                 case CmdID_SetTxPowerLevel:
1390                         if (priv->card_8192_version == (u8)VERSION_819xU_A)
1391                                 /* consider it later! */
1392                                 rtl8192_SetTxPowerLevel(dev, channel);
1393                         break;
1394                 case CmdID_WritePortUlong:
1395                         write_nic_dword(dev, CurrentCmd->Para1,
1396                                         CurrentCmd->Para2);
1397                         break;
1398                 case CmdID_WritePortUshort:
1399                         write_nic_word(dev, CurrentCmd->Para1,
1400                                        (u16)CurrentCmd->Para2);
1401                         break;
1402                 case CmdID_WritePortUchar:
1403                         write_nic_byte(dev, CurrentCmd->Para1,
1404                                        (u8)CurrentCmd->Para2);
1405                         break;
1406                 case CmdID_RF_WriteReg:
1407                         for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
1408                                 rtl8192_phy_SetRFReg(dev,
1409                                                      (RF90_RADIO_PATH_E)eRFPath,
1410                                                      CurrentCmd->Para1,
1411                                                      bZebra1_ChannelNum,
1412                                                      CurrentCmd->Para2);
1413                         }
1414                         break;
1415                 default:
1416                         break;
1417                 }
1418
1419                 break;
1420         } while (true);
1421
1422         (*delay) = CurrentCmd->msDelay;
1423         (*step)++;
1424         return false;
1425 }
1426
1427 /******************************************************************************
1428  * function:  This function does actually set channel work
1429  * input:     net_device        *dev
1430  *            u8                channel
1431  * output:    none
1432  * return:    none
1433  * notice:    We should not call this function directly
1434  *****************************************************************************/
1435 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1436 {
1437         struct r8192_priv *priv = ieee80211_priv(dev);
1438         u32     delay = 0;
1439
1440         while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
1441                                              &priv->SwChnlStep, &delay)) {
1442                 if (!priv->up)
1443                         break;
1444         }
1445 }
1446
1447 /******************************************************************************
1448  * function:  Callback routine of the work item for switch channel.
1449  * input:     net_device        *dev
1450  *
1451  * output:    none
1452  * return:    none
1453  *****************************************************************************/
1454 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1455 {
1456
1457         struct r8192_priv *priv = ieee80211_priv(dev);
1458
1459         RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n",
1460                  priv->chan);
1461
1462
1463         rtl8192_phy_FinishSwChnlNow(dev, priv->chan);
1464
1465         RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1466 }
1467
1468 /******************************************************************************
1469  * function:  This function scheduled actual work item to set channel
1470  * input:     net_device        *dev
1471  *            u8                channel   //channel to set
1472  * output:    none
1473  * return:    return code show if workitem is scheduled (1:pass, 0:fail)
1474  * notice:    Delay may be required for RF configuration
1475  ******************************************************************************/
1476 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1477 {
1478         struct r8192_priv *priv = ieee80211_priv(dev);
1479         RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__,
1480                  priv->SwChnlInProgress);
1481         if (!priv->up)
1482                 return false;
1483         if (priv->SwChnlInProgress)
1484                 return false;
1485
1486         /* -------------------------------------------- */
1487         switch (priv->ieee80211->mode) {
1488         case WIRELESS_MODE_A:
1489         case WIRELESS_MODE_N_5G:
1490                 if (channel <= 14) {
1491                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n");
1492                         return false;
1493                 }
1494                 break;
1495         case WIRELESS_MODE_B:
1496                 if (channel > 14) {
1497                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n");
1498                         return false;
1499                 }
1500                 break;
1501         case WIRELESS_MODE_G:
1502         case WIRELESS_MODE_N_24G:
1503                 if (channel > 14) {
1504                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n");
1505                         return false;
1506                 }
1507                 break;
1508         }
1509         /* -------------------------------------------- */
1510
1511         priv->SwChnlInProgress = true;
1512         if (channel == 0)
1513                 channel = 1;
1514
1515         priv->chan = channel;
1516
1517         priv->SwChnlStage = 0;
1518         priv->SwChnlStep = 0;
1519         if (priv->up)
1520                 rtl8192_SwChnl_WorkItem(dev);
1521
1522         priv->SwChnlInProgress = false;
1523         return true;
1524 }
1525
1526 /******************************************************************************
1527  * function:  Callback routine of the work item for set bandwidth mode.
1528  * input:     net_device         *dev
1529  * output:    none
1530  * return:    none
1531  * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
1532  *            test whether current work in the queue or not.//do I?
1533  *****************************************************************************/
1534 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1535 {
1536
1537         struct r8192_priv *priv = ieee80211_priv(dev);
1538         u8 regBwOpMode;
1539
1540         RT_TRACE(COMP_SWBW, "%s()  Switch to %s bandwidth\n", __func__,
1541                  priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
1542
1543
1544         if (priv->rf_chip == RF_PSEUDO_11N) {
1545                 priv->SetBWModeInProgress = false;
1546                 return;
1547         }
1548
1549         /* <1> Set MAC register */
1550         read_nic_byte(dev, BW_OPMODE, &regBwOpMode);
1551
1552         switch (priv->CurrentChannelBW) {
1553         case HT_CHANNEL_WIDTH_20:
1554                 regBwOpMode |= BW_OPMODE_20MHZ;
1555                 /* We have not verify whether this register works */
1556                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1557                 break;
1558
1559         case HT_CHANNEL_WIDTH_20_40:
1560                 regBwOpMode &= ~BW_OPMODE_20MHZ;
1561                 /* We have not verify whether this register works */
1562                 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1563                 break;
1564
1565         default:
1566                 RT_TRACE(COMP_ERR,
1567                          "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1568                          priv->CurrentChannelBW);
1569                 break;
1570         }
1571
1572         /* <2> Set PHY related register */
1573         switch (priv->CurrentChannelBW) {
1574         case HT_CHANNEL_WIDTH_20:
1575                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1576                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1577                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1578                                  0x00100000, 1);
1579
1580                 /* Correct the tx power for CCK rate in 20M. */
1581                 priv->cck_present_attentuation =
1582                         priv->cck_present_attentuation_20Mdefault +
1583                         priv->cck_present_attentuation_difference;
1584
1585                 if (priv->cck_present_attentuation > 22)
1586                         priv->cck_present_attentuation = 22;
1587                 if (priv->cck_present_attentuation < 0)
1588                         priv->cck_present_attentuation = 0;
1589                 RT_TRACE(COMP_INIT,
1590                          "20M, pHalData->CCKPresentAttentuation = %d\n",
1591                          priv->cck_present_attentuation);
1592
1593                 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1594                         priv->bcck_in_ch14 = TRUE;
1595                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1596                 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1597                         priv->bcck_in_ch14 = FALSE;
1598                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1599                 } else {
1600                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1601                 }
1602
1603                 break;
1604         case HT_CHANNEL_WIDTH_20_40:
1605                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1606                 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1607                 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1608                                  priv->nCur40MhzPrimeSC>>1);
1609                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1610                 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1611                                  priv->nCur40MhzPrimeSC);
1612                 priv->cck_present_attentuation =
1613                         priv->cck_present_attentuation_40Mdefault +
1614                         priv->cck_present_attentuation_difference;
1615
1616                 if (priv->cck_present_attentuation > 22)
1617                         priv->cck_present_attentuation = 22;
1618                 if (priv->cck_present_attentuation < 0)
1619                         priv->cck_present_attentuation = 0;
1620
1621                 RT_TRACE(COMP_INIT,
1622                          "40M, pHalData->CCKPresentAttentuation = %d\n",
1623                          priv->cck_present_attentuation);
1624                 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1625                         priv->bcck_in_ch14 = true;
1626                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1627                 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1628                         priv->bcck_in_ch14 = false;
1629                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1630                 } else {
1631                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1632                 }
1633
1634                 break;
1635         default:
1636                 RT_TRACE(COMP_ERR,
1637                          "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1638                          priv->CurrentChannelBW);
1639                 break;
1640
1641         }
1642         /* Skip over setting of J-mode in BB register here.
1643            Default value is "None J mode". */
1644
1645         /* <3> Set RF related register */
1646         switch (priv->rf_chip) {
1647         case RF_8225:
1648 #ifdef TO_DO_LIST
1649                 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
1650 #endif
1651                 break;
1652
1653         case RF_8256:
1654                 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1655                 break;
1656
1657         case RF_8258:
1658                 break;
1659
1660         case RF_PSEUDO_11N:
1661                 break;
1662
1663         default:
1664                 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1665                 break;
1666         }
1667         priv->SetBWModeInProgress = false;
1668
1669         RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n",
1670                  atomic_read(&priv->ieee80211->atm_swbw));
1671 }
1672
1673 /******************************************************************************
1674  * function:  This function schedules bandwidth switch work.
1675  * input:     struct net_deviceq   *dev
1676  *            HT_CHANNEL_WIDTH     bandwidth  //20M or 40M
1677  *            HT_EXTCHNL_OFFSET    offset     //Upper, Lower, or Don't care
1678  * output:    none
1679  * return:    none
1680  * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
1681  *            test whether current work in the queue or not.//do I?
1682  *****************************************************************************/
1683 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH bandwidth,
1684                        HT_EXTCHNL_OFFSET offset)
1685 {
1686         struct r8192_priv *priv = ieee80211_priv(dev);
1687
1688         if (priv->SetBWModeInProgress)
1689                 return;
1690         priv->SetBWModeInProgress = true;
1691
1692         priv->CurrentChannelBW = bandwidth;
1693
1694         if (offset == HT_EXTCHNL_OFFSET_LOWER)
1695                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1696         else if (offset == HT_EXTCHNL_OFFSET_UPPER)
1697                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1698         else
1699                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1700
1701         rtl8192_SetBWModeWorkItem(dev);
1702
1703 }
1704
1705 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1706 {
1707         struct r8192_priv *priv = ieee80211_priv(dev);
1708
1709         priv->InitialGainOperateType = Operation;
1710
1711         if (priv->up)
1712                 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0);
1713 }
1714
1715 void InitialGainOperateWorkItemCallBack(struct work_struct *work)
1716 {
1717         struct delayed_work *dwork = container_of(work, struct delayed_work,
1718                                                   work);
1719         struct r8192_priv *priv = container_of(dwork, struct r8192_priv,
1720                                                initialgain_operate_wq);
1721         struct net_device *dev = priv->ieee80211->dev;
1722 #define SCAN_RX_INITIAL_GAIN    0x17
1723 #define POWER_DETECTION_TH      0x08
1724         u32     bitmask;
1725         u8      initial_gain;
1726         u8      Operation;
1727
1728         Operation = priv->InitialGainOperateType;
1729
1730         switch (Operation) {
1731         case IG_Backup:
1732                 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1733                 initial_gain = SCAN_RX_INITIAL_GAIN;
1734                 bitmask = bMaskByte0;
1735                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1736                         /* FW DIG OFF */
1737                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1738                 priv->initgain_backup.xaagccore1 =
1739                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask);
1740                 priv->initgain_backup.xbagccore1 =
1741                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask);
1742                 priv->initgain_backup.xcagccore1 =
1743                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask);
1744                 priv->initgain_backup.xdagccore1 =
1745                         (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask);
1746                 bitmask = bMaskByte2;
1747                 priv->initgain_backup.cca =
1748                         (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask);
1749
1750                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",
1751                          priv->initgain_backup.xaagccore1);
1752                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",
1753                          priv->initgain_backup.xbagccore1);
1754                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",
1755                          priv->initgain_backup.xcagccore1);
1756                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",
1757                          priv->initgain_backup.xdagccore1);
1758                 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",
1759                          priv->initgain_backup.cca);
1760
1761                 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n",
1762                          initial_gain);
1763                 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1764                 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1765                 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1766                 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1767                 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n",
1768                          POWER_DETECTION_TH);
1769                 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1770                 break;
1771         case IG_Restore:
1772                 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1773                 bitmask = 0x7f; /* Bit0 ~ Bit6 */
1774                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1775                         /* FW DIG OFF */
1776                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1777
1778                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask,
1779                                  (u32)priv->initgain_backup.xaagccore1);
1780                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask,
1781                                  (u32)priv->initgain_backup.xbagccore1);
1782                 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask,
1783                                  (u32)priv->initgain_backup.xcagccore1);
1784                 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask,
1785                                  (u32)priv->initgain_backup.xdagccore1);
1786                 bitmask  = bMaskByte2;
1787                 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask,
1788                                  (u32)priv->initgain_backup.cca);
1789
1790                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",
1791                          priv->initgain_backup.xaagccore1);
1792                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",
1793                          priv->initgain_backup.xbagccore1);
1794                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",
1795                          priv->initgain_backup.xcagccore1);
1796                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",
1797                          priv->initgain_backup.xdagccore1);
1798                 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",
1799                          priv->initgain_backup.cca);
1800
1801                 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
1802
1803                 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1804                         /* FW DIG ON */
1805                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1806                 break;
1807         default:
1808                 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
1809                 break;
1810         }
1811 }