drivers/staging/rts5208/rtsx_chip.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG (wei_wang@realsil.com.cn)
  20  *   Micky Ching (micky_ching@realsil.com.cn)
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/vmalloc.h>
  28
  29 #include "rtsx.h"
  30 #include "rtsx_transport.h"
  31 #include "rtsx_scsi.h"
  32 #include "rtsx_card.h"
  33 #include "rtsx_chip.h"
  34 #include "rtsx_sys.h"
  35 #include "general.h"
  36
  37 #include "sd.h"
  38 #include "xd.h"
  39 #include "ms.h"
  40
  41 static void rtsx_calibration(struct rtsx_chip *chip)
  42 {
  43         rtsx_write_phy_register(chip, 0x1B, 0x135E);
  44         wait_timeout(10);
  45         rtsx_write_phy_register(chip, 0x00, 0x0280);
  46         rtsx_write_phy_register(chip, 0x01, 0x7112);
  47         rtsx_write_phy_register(chip, 0x01, 0x7110);
  48         rtsx_write_phy_register(chip, 0x01, 0x7112);
  49         rtsx_write_phy_register(chip, 0x01, 0x7113);
  50         rtsx_write_phy_register(chip, 0x00, 0x0288);
  51 }
  52
  53 void rtsx_disable_card_int(struct rtsx_chip *chip)
  54 {
  55         u32 reg = rtsx_readl(chip, RTSX_BIER);
  56
  57         reg &= ~(XD_INT_EN | SD_INT_EN | MS_INT_EN);
  58         rtsx_writel(chip, RTSX_BIER, reg);
  59 }
  60
  61 void rtsx_enable_card_int(struct rtsx_chip *chip)
  62 {
  63         u32 reg = rtsx_readl(chip, RTSX_BIER);
  64         int i;
  65
  66         for (i = 0; i <= chip->max_lun; i++) {
  67                 if (chip->lun2card[i] & XD_CARD)
  68                         reg |= XD_INT_EN;
  69                 if (chip->lun2card[i] & SD_CARD)
  70                         reg |= SD_INT_EN;
  71                 if (chip->lun2card[i] & MS_CARD)
  72                         reg |= MS_INT_EN;
  73         }
  74         if (chip->hw_bypass_sd)
  75                 reg &= ~((u32)SD_INT_EN);
  76
  77         rtsx_writel(chip, RTSX_BIER, reg);
  78 }
  79
  80 void rtsx_enable_bus_int(struct rtsx_chip *chip)
  81 {
  82         u32 reg = 0;
  83 #ifndef DISABLE_CARD_INT
  84         int i;
  85 #endif
  86
  87         reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
  88
  89 #ifndef DISABLE_CARD_INT
  90         for (i = 0; i <= chip->max_lun; i++) {
  91                 dev_dbg(rtsx_dev(chip), "lun2card[%d] = 0x%02x\n",
  92                         i, chip->lun2card[i]);
  93
  94                 if (chip->lun2card[i] & XD_CARD)
  95                         reg |= XD_INT_EN;
  96                 if (chip->lun2card[i] & SD_CARD)
  97                         reg |= SD_INT_EN;
  98                 if (chip->lun2card[i] & MS_CARD)
  99                         reg |= MS_INT_EN;
 100         }
 101         if (chip->hw_bypass_sd)
 102                 reg &= ~((u32)SD_INT_EN);
 103 #endif
 104
 105         if (chip->ic_version >= IC_VER_C)
 106                 reg |= DELINK_INT_EN;
 107 #ifdef SUPPORT_OCP
 108         reg |= OC_INT_EN;
 109 #endif
 110         if (!chip->adma_mode)
 111                 reg |= DATA_DONE_INT_EN;
 112
 113         /* Enable Bus Interrupt */
 114         rtsx_writel(chip, RTSX_BIER, reg);
 115
 116         dev_dbg(rtsx_dev(chip), "RTSX_BIER: 0x%08x\n", reg);
 117 }
 118
 119 void rtsx_disable_bus_int(struct rtsx_chip *chip)
 120 {
 121         rtsx_writel(chip, RTSX_BIER, 0);
 122 }
 123
 124 static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip)
 125 {
 126         if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) {
 127                 if (chip->asic_code) {
 128                         RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
 129                                        MS_INS_PU | SD_WP_PU |
 130                                        SD_CD_PU | SD_CMD_PU);
 131                 } else {
 132                         RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF,
 133                                        FPGA_SD_PULL_CTL_EN);
 134                 }
 135                 RTSX_WRITE_REG(chip, CARD_SHARE_MODE, 0xFF, CARD_SHARE_48_SD);
 136
 137                 /* Enable SDIO internal clock */
 138                 RTSX_WRITE_REG(chip, 0xFF2C, 0x01, 0x01);
 139
 140                 RTSX_WRITE_REG(chip, SDIO_CTRL, 0xFF,
 141                                SDIO_BUS_CTRL | SDIO_CD_CTRL);
 142
 143                 chip->sd_int = 1;
 144                 chip->sd_io = 1;
 145         } else {
 146                 chip->need_reset |= SD_CARD;
 147         }
 148
 149         return STATUS_SUCCESS;
 150 }
 151
 152 #ifdef HW_AUTO_SWITCH_SD_BUS
 153 static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip)
 154 {
 155         u8 tmp;
 156         int sw_bypass_sd = 0;
 157         int retval;
 158
 159         if (chip->driver_first_load) {
 160                 if (CHECK_PID(chip, 0x5288)) {
 161                         RTSX_READ_REG(chip, 0xFE5A, &tmp);
 162                         if (tmp & 0x08)
 163                                 sw_bypass_sd = 1;
 164                 } else if (CHECK_PID(chip, 0x5208)) {
 165                         RTSX_READ_REG(chip, 0xFE70, &tmp);
 166                         if (tmp & 0x80)
 167                                 sw_bypass_sd = 1;
 168                 }
 169         } else {
 170                 if (chip->sdio_in_charge)
 171                         sw_bypass_sd = 1;
 172         }
 173         dev_dbg(rtsx_dev(chip), "chip->sdio_in_charge = %d\n",
 174                 chip->sdio_in_charge);
 175         dev_dbg(rtsx_dev(chip), "chip->driver_first_load = %d\n",
 176                 chip->driver_first_load);
 177         dev_dbg(rtsx_dev(chip), "sw_bypass_sd = %d\n",
 178                 sw_bypass_sd);
 179
 180         if (sw_bypass_sd) {
 181                 u8 cd_toggle_mask = 0;
 182
 183                 RTSX_READ_REG(chip, TLPTISTAT, &tmp);
 184                 cd_toggle_mask = 0x08;
 185
 186                 if (tmp & cd_toggle_mask) {
 187                         /* Disable sdio_bus_auto_switch */
 188                         if (CHECK_PID(chip, 0x5288))
 189                                 RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x00);
 190                         else if (CHECK_PID(chip, 0x5208))
 191                                 RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x00);
 192
 193                         RTSX_WRITE_REG(chip, TLPTISTAT, 0xFF, tmp);
 194
 195                         chip->need_reset |= SD_CARD;
 196                 } else {
 197                         dev_dbg(rtsx_dev(chip), "Chip inserted with SDIO!\n");
 198
 199                         if (chip->asic_code) {
 200                                 retval = sd_pull_ctl_enable(chip);
 201                                 if (retval != STATUS_SUCCESS)
 202                                         TRACE_RET(chip, STATUS_FAIL);
 203                         } else {
 204                                 RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
 205                                                FPGA_SD_PULL_CTL_BIT | 0x20, 0);
 206                         }
 207                         retval = card_share_mode(chip, SD_CARD);
 208                         if (retval != STATUS_SUCCESS)
 209                                 TRACE_RET(chip, STATUS_FAIL);
 210
 211                         /* Enable sdio_bus_auto_switch */
 212                         if (CHECK_PID(chip, 0x5288))
 213                                 RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x08);
 214                         else if (CHECK_PID(chip, 0x5208))
 215                                 RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x80);
 216
 217                         chip->chip_insert_with_sdio = 1;
 218                         chip->sd_io = 1;
 219                 }
 220         } else {
 221                 RTSX_WRITE_REG(chip, TLPTISTAT, 0x08, 0x08);
 222
 223                 chip->need_reset |= SD_CARD;
 224         }
 225
 226         return STATUS_SUCCESS;
 227 }
 228 #endif
 229
 230 static int rtsx_reset_aspm(struct rtsx_chip *chip)
 231 {
 232         int ret;
 233
 234         if (chip->dynamic_aspm) {
 235                 if (!CHK_SDIO_EXIST(chip) || !CHECK_PID(chip, 0x5288))
 236                         return STATUS_SUCCESS;
 237
 238                 ret = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF,
 239                                         chip->aspm_l0s_l1_en);
 240                 if (ret != STATUS_SUCCESS)
 241                         TRACE_RET(chip, STATUS_FAIL);
 242
 243                 return STATUS_SUCCESS;
 244         }
 245
 246         if (CHECK_PID(chip, 0x5208))
 247                 RTSX_WRITE_REG(chip, ASPM_FORCE_CTL, 0xFF, 0x3F);
 248         ret = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
 249         if (ret != STATUS_SUCCESS)
 250                 TRACE_RET(chip, STATUS_FAIL);
 251
 252         chip->aspm_level[0] = chip->aspm_l0s_l1_en;
 253         if (CHK_SDIO_EXIST(chip)) {
 254                 chip->aspm_level[1] = chip->aspm_l0s_l1_en;
 255                 ret = rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
 256                                         0xC0, 0xFF, chip->aspm_l0s_l1_en);
 257                 if (ret != STATUS_SUCCESS)
 258                         TRACE_RET(chip, STATUS_FAIL);
 259         }
 260
 261         chip->aspm_enabled = 1;
 262
 263         return STATUS_SUCCESS;
 264 }
 265
 266 static int rtsx_enable_pcie_intr(struct rtsx_chip *chip)
 267 {
 268         int ret;
 269
 270         if (!chip->asic_code || !CHECK_PID(chip, 0x5208)) {
 271                 rtsx_enable_bus_int(chip);
 272                 return STATUS_SUCCESS;
 273         }
 274
 275         if (chip->phy_debug_mode) {
 276                 RTSX_WRITE_REG(chip, CDRESUMECTL, 0x77, 0);
 277                 rtsx_disable_bus_int(chip);
 278         } else {
 279                 rtsx_enable_bus_int(chip);
 280         }
 281
 282         if (chip->ic_version >= IC_VER_D) {
 283                 u16 reg;
 284
 285                 ret = rtsx_read_phy_register(chip, 0x00, &reg);
 286                 if (ret != STATUS_SUCCESS)
 287                         TRACE_RET(chip, STATUS_FAIL);
 288
 289                 reg &= 0xFE7F;
 290                 reg |= 0x80;
 291                 ret = rtsx_write_phy_register(chip, 0x00, reg);
 292                 if (ret != STATUS_SUCCESS)
 293                         TRACE_RET(chip, STATUS_FAIL);
 294
 295                 ret = rtsx_read_phy_register(chip, 0x1C, &reg);
 296                 if (ret != STATUS_SUCCESS)
 297                         TRACE_RET(chip, STATUS_FAIL);
 298
 299                 reg &= 0xFFF7;
 300                 ret = rtsx_write_phy_register(chip, 0x1C, reg);
 301                 if (ret != STATUS_SUCCESS)
 302                         TRACE_RET(chip, STATUS_FAIL);
 303         }
 304
 305         if (chip->driver_first_load && (chip->ic_version < IC_VER_C))
 306                 rtsx_calibration(chip);
 307
 308         return STATUS_SUCCESS;
 309 }
 310
 311 int rtsx_reset_chip(struct rtsx_chip *chip)
 312 {
 313         int retval;
 314
 315         rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
 316
 317         rtsx_disable_aspm(chip);
 318
 319         RTSX_WRITE_REG(chip, HOST_SLEEP_STATE, 0x03, 0x00);
 320
 321         /* Disable card clock */
 322         RTSX_WRITE_REG(chip, CARD_CLK_EN, 0x1E, 0);
 323
 324 #ifdef SUPPORT_OCP
 325         /* SSC power on, OCD power on */
 326         if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
 327                 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, 0);
 328         else
 329                 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, MS_OC_POWER_DOWN);
 330
 331         RTSX_WRITE_REG(chip, OCPPARA1, OCP_TIME_MASK, OCP_TIME_800);
 332         RTSX_WRITE_REG(chip, OCPPARA2, OCP_THD_MASK, OCP_THD_244_946);
 333         RTSX_WRITE_REG(chip, OCPCTL, 0xFF, CARD_OC_INT_EN | CARD_DETECT_EN);
 334 #else
 335         /* OC power down */
 336         RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, OC_POWER_DOWN);
 337 #endif
 338
 339         if (!CHECK_PID(chip, 0x5288))
 340                 RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0xFF, 0x03);
 341
 342         /* Turn off LED */
 343         RTSX_WRITE_REG(chip, CARD_GPIO, 0xFF, 0x03);
 344
 345         /* Reset delink mode */
 346         RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x0A, 0);
 347
 348         /* Card driving select */
 349         RTSX_WRITE_REG(chip, CARD_DRIVE_SEL, 0xFF, chip->card_drive_sel);
 350
 351 #ifdef LED_AUTO_BLINK
 352         RTSX_WRITE_REG(chip, CARD_AUTO_BLINK, 0xFF,
 353                        LED_BLINK_SPEED | BLINK_EN | LED_GPIO0);
 354 #endif
 355
 356         if (chip->asic_code) {
 357                 /* Enable SSC Clock */
 358                 RTSX_WRITE_REG(chip, SSC_CTL1, 0xFF, SSC_8X_EN | SSC_SEL_4M);
 359                 RTSX_WRITE_REG(chip, SSC_CTL2, 0xFF, 0x12);
 360         }
 361
 362         /* Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0)
 363               0xFE5B
 364               bit[1]    u_cd_rst_core_en        rst_value = 0
 365               bit[2]    u_force_rst_core_en     rst_value = 0
 366               bit[5]    u_mac_phy_rst_n_dbg     rst_value = 1
 367               bit[4]    u_non_sticky_rst_n_dbg  rst_value = 0
 368         */
 369         RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x16, 0x10);
 370
 371         /* Enable ASPM */
 372         if (chip->aspm_l0s_l1_en) {
 373                 retval = rtsx_reset_aspm(chip);
 374                 if (retval != STATUS_SUCCESS)
 375                         TRACE_RET(chip, STATUS_FAIL);
 376         } else {
 377                 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 378                         retval = rtsx_write_phy_register(chip, 0x07, 0x0129);
 379                         if (retval != STATUS_SUCCESS)
 380                                 TRACE_RET(chip, STATUS_FAIL);
 381                 }
 382                 retval = rtsx_write_config_byte(chip, LCTLR,
 383                                                 chip->aspm_l0s_l1_en);
 384                 if (retval != STATUS_SUCCESS)
 385                         TRACE_RET(chip, STATUS_FAIL);
 386         }
 387
 388         retval = rtsx_write_config_byte(chip, 0x81, 1);
 389         if (retval != STATUS_SUCCESS)
 390                 TRACE_RET(chip, STATUS_FAIL);
 391
 392         if (CHK_SDIO_EXIST(chip)) {
 393                 retval = rtsx_write_cfg_dw(chip,
 394                                            CHECK_PID(chip, 0x5288) ? 2 : 1,
 395                                            0xC0, 0xFF00, 0x0100);
 396
 397                 if (retval != STATUS_SUCCESS)
 398                         TRACE_RET(chip, STATUS_FAIL);
 399         }
 400
 401         if (CHECK_PID(chip, 0x5288) && !CHK_SDIO_EXIST(chip)) {
 402                 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103);
 403                 if (retval != STATUS_SUCCESS)
 404                         TRACE_RET(chip, STATUS_FAIL);
 405
 406                 retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03);
 407                 if (retval != STATUS_SUCCESS)
 408                         TRACE_RET(chip, STATUS_FAIL);
 409         }
 410
 411         RTSX_WRITE_REG(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
 412
 413         RTSX_WRITE_REG(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80);
 414
 415         retval = rtsx_enable_pcie_intr(chip);
 416         if (retval != STATUS_SUCCESS)
 417                 TRACE_RET(chip, STATUS_FAIL);
 418
 419         chip->need_reset = 0;
 420
 421         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
 422
 423         if (chip->hw_bypass_sd)
 424                 goto nextcard;
 425         dev_dbg(rtsx_dev(chip), "In %s, chip->int_reg = 0x%x\n", __func__,
 426                 chip->int_reg);
 427         if (chip->int_reg & SD_EXIST) {
 428 #ifdef HW_AUTO_SWITCH_SD_BUS
 429                 if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C))
 430                         retval = rtsx_pre_handle_sdio_old(chip);
 431                 else
 432                         retval = rtsx_pre_handle_sdio_new(chip);
 433
 434                 dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x (rtsx_reset_chip)\n",
 435                         (unsigned int)(chip->need_reset));
 436 #else  /* HW_AUTO_SWITCH_SD_BUS */
 437                 retval = rtsx_pre_handle_sdio_old(chip);
 438 #endif  /* HW_AUTO_SWITCH_SD_BUS */
 439                 if (retval != STATUS_SUCCESS)
 440                         TRACE_RET(chip, STATUS_FAIL);
 441
 442         } else {
 443                 chip->sd_io = 0;
 444                 RTSX_WRITE_REG(chip, SDIO_CTRL, SDIO_BUS_CTRL | SDIO_CD_CTRL,
 445                                0);
 446         }
 447
 448 nextcard:
 449         if (chip->int_reg & XD_EXIST)
 450                 chip->need_reset |= XD_CARD;
 451         if (chip->int_reg & MS_EXIST)
 452                 chip->need_reset |= MS_CARD;
 453         if (chip->int_reg & CARD_EXIST)
 454                 RTSX_WRITE_REG(chip, SSC_CTL1, SSC_RSTB, SSC_RSTB);
 455
 456         dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__,
 457                 (unsigned int)(chip->need_reset));
 458
 459         RTSX_WRITE_REG(chip, RCCTL, 0x01, 0x00);
 460
 461         if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) {
 462                 /* Turn off main power when entering S3/S4 state */
 463                 RTSX_WRITE_REG(chip, MAIN_PWR_OFF_CTL, 0x03, 0x03);
 464         }
 465
 466         if (chip->remote_wakeup_en && !chip->auto_delink_en) {
 467                 RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x07);
 468                 if (chip->aux_pwr_exist)
 469                         RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x33);
 470         } else {
 471                 RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x04);
 472                 RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x30);
 473         }
 474
 475         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D))
 476                 RTSX_WRITE_REG(chip, PETXCFG, 0x1C, 0x14);
 477
 478         if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 479                 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2);
 480                 if (retval != STATUS_SUCCESS)
 481                         TRACE_RET(chip, STATUS_FAIL);
 482         }
 483
 484         if (chip->ft2_fast_mode) {
 485                 RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF,
 486                                MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON);
 487                 udelay(chip->pmos_pwr_on_interval);
 488                 RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF,
 489                                MS_POWER_ON | SD_POWER_ON);
 490
 491                 wait_timeout(200);
 492         }
 493
 494         /* Reset card */
 495         rtsx_reset_detected_cards(chip, 0);
 496
 497         chip->driver_first_load = 0;
 498
 499         return STATUS_SUCCESS;
 500 }
 501
 502 static inline int check_sd_speed_prior(u32 sd_speed_prior)
 503 {
 504         int i, fake_para = 0;
 505
 506         for (i = 0; i < 4; i++) {
 507                 u8 tmp = (u8)(sd_speed_prior >> (i*8));
 508
 509                 if ((tmp < 0x01) || (tmp > 0x04)) {
 510                         fake_para = 1;
 511                         break;
 512                 }
 513         }
 514
 515         return !fake_para;
 516 }
 517
 518 static inline int check_sd_current_prior(u32 sd_current_prior)
 519 {
 520         int i, fake_para = 0;
 521
 522         for (i = 0; i < 4; i++) {
 523                 u8 tmp = (u8)(sd_current_prior >> (i*8));
 524
 525                 if (tmp > 0x03) {
 526                         fake_para = 1;
 527                         break;
 528                 }
 529         }
 530
 531         return !fake_para;
 532 }
 533
 534 static int rts5208_init(struct rtsx_chip *chip)
 535 {
 536         int retval;
 537         u16 reg = 0;
 538         u8 val = 0;
 539
 540         RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03);
 541         RTSX_READ_REG(chip, CLK_SEL, &val);
 542         chip->asic_code = val == 0 ? 1 : 0;
 543
 544         if (chip->asic_code) {
 545                 retval = rtsx_read_phy_register(chip, 0x1C, &reg);
 546                 if (retval != STATUS_SUCCESS)
 547                         TRACE_RET(chip, STATUS_FAIL);
 548
 549                 dev_dbg(rtsx_dev(chip), "Value of phy register 0x1C is 0x%x\n",
 550                         reg);
 551                 chip->ic_version = (reg >> 4) & 0x07;
 552                 chip->phy_debug_mode = reg & PHY_DEBUG_MODE ? 1 : 0;
 553
 554         } else {
 555                 RTSX_READ_REG(chip, 0xFE80, &val);
 556                 chip->ic_version = val;
 557                 chip->phy_debug_mode = 0;
 558         }
 559
 560         RTSX_READ_REG(chip, PDINFO, &val);
 561         dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
 562         chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
 563
 564         RTSX_READ_REG(chip, 0xFE50, &val);
 565         chip->hw_bypass_sd = val & 0x01 ? 1 : 0;
 566
 567         rtsx_read_config_byte(chip, 0x0E, &val);
 568         if (val & 0x80)
 569                 SET_SDIO_EXIST(chip);
 570         else
 571                 CLR_SDIO_EXIST(chip);
 572
 573         if (chip->use_hw_setting) {
 574                 RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val);
 575                 chip->auto_delink_en = val & 0x80 ? 1 : 0;
 576         }
 577
 578         return STATUS_SUCCESS;
 579 }
 580
 581 static int rts5288_init(struct rtsx_chip *chip)
 582 {
 583         int retval;
 584         u8 val = 0, max_func;
 585         u32 lval = 0;
 586
 587         RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03);
 588         RTSX_READ_REG(chip, CLK_SEL, &val);
 589         chip->asic_code = val == 0 ? 1 : 0;
 590
 591         chip->ic_version = 0;
 592         chip->phy_debug_mode = 0;
 593
 594         RTSX_READ_REG(chip, PDINFO, &val);
 595         dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
 596         chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
 597
 598         RTSX_READ_REG(chip, CARD_SHARE_MODE, &val);
 599         dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val);
 600         chip->baro_pkg = val & 0x04 ? QFN : LQFP;
 601
 602         RTSX_READ_REG(chip, 0xFE5A, &val);
 603         chip->hw_bypass_sd = val & 0x10 ? 1 : 0;
 604
 605         retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval);
 606         if (retval != STATUS_SUCCESS)
 607                 TRACE_RET(chip, STATUS_FAIL);
 608
 609         max_func = (u8)((lval >> 29) & 0x07);
 610         dev_dbg(rtsx_dev(chip), "Max function number: %d\n", max_func);
 611         if (max_func == 0x02)
 612                 SET_SDIO_EXIST(chip);
 613         else
 614                 CLR_SDIO_EXIST(chip);
 615
 616         if (chip->use_hw_setting) {
 617                 RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val);
 618                 chip->auto_delink_en = val & 0x80 ? 1 : 0;
 619
 620                 if (CHECK_BARO_PKG(chip, LQFP))
 621                         chip->lun_mode = SD_MS_1LUN;
 622                 else
 623                         chip->lun_mode = DEFAULT_SINGLE;
 624         }
 625
 626         return STATUS_SUCCESS;
 627 }
 628
 629 int rtsx_init_chip(struct rtsx_chip *chip)
 630 {
 631         struct sd_info *sd_card = &chip->sd_card;
 632         struct xd_info *xd_card = &chip->xd_card;
 633         struct ms_info *ms_card = &chip->ms_card;
 634         int retval;
 635         unsigned int i;
 636
 637         dev_dbg(rtsx_dev(chip), "Vendor ID: 0x%04x, Product ID: 0x%04x\n",
 638                 chip->vendor_id, chip->product_id);
 639
 640         chip->ic_version = 0;
 641
 642 #ifdef _MSG_TRACE
 643         chip->msg_idx = 0;
 644 #endif
 645
 646         memset(xd_card, 0, sizeof(struct xd_info));
 647         memset(sd_card, 0, sizeof(struct sd_info));
 648         memset(ms_card, 0, sizeof(struct ms_info));
 649
 650         chip->xd_reset_counter = 0;
 651         chip->sd_reset_counter = 0;
 652         chip->ms_reset_counter = 0;
 653
 654         chip->xd_show_cnt = MAX_SHOW_CNT;
 655         chip->sd_show_cnt = MAX_SHOW_CNT;
 656         chip->ms_show_cnt = MAX_SHOW_CNT;
 657
 658         chip->sd_io = 0;
 659         chip->auto_delink_cnt = 0;
 660         chip->auto_delink_allowed = 1;
 661         rtsx_set_stat(chip, RTSX_STAT_INIT);
 662
 663         chip->aspm_enabled = 0;
 664         chip->chip_insert_with_sdio = 0;
 665         chip->sdio_aspm = 0;
 666         chip->sdio_idle = 0;
 667         chip->sdio_counter = 0;
 668         chip->cur_card = 0;
 669         chip->phy_debug_mode = 0;
 670         chip->sdio_func_exist = 0;
 671         memset(chip->sdio_raw_data, 0, 12);
 672
 673         for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) {
 674                 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE);
 675                 chip->rw_fail_cnt[i] = 0;
 676         }
 677
 678         if (!check_sd_speed_prior(chip->sd_speed_prior))
 679                 chip->sd_speed_prior = 0x01040203;
 680
 681         dev_dbg(rtsx_dev(chip), "sd_speed_prior = 0x%08x\n",
 682                 chip->sd_speed_prior);
 683
 684         if (!check_sd_current_prior(chip->sd_current_prior))
 685                 chip->sd_current_prior = 0x00010203;
 686
 687         dev_dbg(rtsx_dev(chip), "sd_current_prior = 0x%08x\n",
 688                 chip->sd_current_prior);
 689
 690         if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0))
 691                 chip->sd_ddr_tx_phase = 0;
 692
 693         if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0))
 694                 chip->mmc_ddr_tx_phase = 0;
 695
 696         RTSX_WRITE_REG(chip, FPDCTL, SSC_POWER_DOWN, 0);
 697         wait_timeout(200);
 698         RTSX_WRITE_REG(chip, CLK_DIV, 0x07, 0x07);
 699         dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n",
 700                 chip->use_hw_setting);
 701
 702         if (CHECK_PID(chip, 0x5208)) {
 703                 retval = rts5208_init(chip);
 704                 if (retval != STATUS_SUCCESS)
 705                         TRACE_RET(chip, STATUS_FAIL);
 706
 707         } else if (CHECK_PID(chip, 0x5288)) {
 708                 retval = rts5288_init(chip);
 709                 if (retval != STATUS_SUCCESS)
 710                         TRACE_RET(chip, STATUS_FAIL);
 711         }
 712
 713         if (chip->ss_en == 2)
 714                 chip->ss_en = 0;
 715
 716         dev_dbg(rtsx_dev(chip), "chip->asic_code = %d\n", chip->asic_code);
 717         dev_dbg(rtsx_dev(chip), "chip->ic_version = 0x%x\n", chip->ic_version);
 718         dev_dbg(rtsx_dev(chip), "chip->phy_debug_mode = %d\n",
 719                 chip->phy_debug_mode);
 720         dev_dbg(rtsx_dev(chip), "chip->aux_pwr_exist = %d\n",
 721                 chip->aux_pwr_exist);
 722         dev_dbg(rtsx_dev(chip), "chip->sdio_func_exist = %d\n",
 723                 chip->sdio_func_exist);
 724         dev_dbg(rtsx_dev(chip), "chip->hw_bypass_sd = %d\n",
 725                 chip->hw_bypass_sd);
 726         dev_dbg(rtsx_dev(chip), "chip->aspm_l0s_l1_en = %d\n",
 727                 chip->aspm_l0s_l1_en);
 728         dev_dbg(rtsx_dev(chip), "chip->lun_mode = %d\n", chip->lun_mode);
 729         dev_dbg(rtsx_dev(chip), "chip->auto_delink_en = %d\n",
 730                 chip->auto_delink_en);
 731         dev_dbg(rtsx_dev(chip), "chip->ss_en = %d\n", chip->ss_en);
 732         dev_dbg(rtsx_dev(chip), "chip->baro_pkg = %d\n", chip->baro_pkg);
 733
 734         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
 735                 chip->card2lun[SD_CARD] = 0;
 736                 chip->card2lun[MS_CARD] = 1;
 737                 chip->card2lun[XD_CARD] = 0xFF;
 738                 chip->lun2card[0] = SD_CARD;
 739                 chip->lun2card[1] = MS_CARD;
 740                 chip->max_lun = 1;
 741                 SET_SDIO_IGNORED(chip);
 742         } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
 743                 chip->card2lun[SD_CARD] = 0;
 744                 chip->card2lun[MS_CARD] = 0;
 745                 chip->card2lun[XD_CARD] = 0xFF;
 746                 chip->lun2card[0] = SD_CARD | MS_CARD;
 747                 chip->max_lun = 0;
 748         } else {
 749                 chip->card2lun[XD_CARD] = 0;
 750                 chip->card2lun[SD_CARD] = 0;
 751                 chip->card2lun[MS_CARD] = 0;
 752                 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD;
 753                 chip->max_lun = 0;
 754         }
 755
 756         retval = rtsx_reset_chip(chip);
 757         if (retval != STATUS_SUCCESS)
 758                 TRACE_RET(chip, STATUS_FAIL);
 759
 760         return STATUS_SUCCESS;
 761 }
 762
 763 void rtsx_release_chip(struct rtsx_chip *chip)
 764 {
 765         xd_free_l2p_tbl(chip);
 766         ms_free_l2p_tbl(chip);
 767         chip->card_exist = 0;
 768         chip->card_ready = 0;
 769 }
 770
 771 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
 772 static inline void rtsx_blink_led(struct rtsx_chip *chip)
 773 {
 774         if (chip->card_exist && chip->blink_led) {
 775                 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) {
 776                         chip->led_toggle_counter++;
 777                 } else {
 778                         chip->led_toggle_counter = 0;
 779                         toggle_gpio(chip, LED_GPIO);
 780                 }
 781         }
 782 }
 783 #endif
 784
 785 static void rtsx_monitor_aspm_config(struct rtsx_chip *chip)
 786 {
 787         int maybe_support_aspm, reg_changed;
 788         u32 tmp = 0;
 789         u8 reg0 = 0, reg1 = 0;
 790
 791         maybe_support_aspm = 0;
 792         reg_changed = 0;
 793         rtsx_read_config_byte(chip, LCTLR, &reg0);
 794         if (chip->aspm_level[0] != reg0) {
 795                 reg_changed = 1;
 796                 chip->aspm_level[0] = reg0;
 797         }
 798         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
 799                 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp);
 800                 reg1 = (u8)tmp;
 801                 if (chip->aspm_level[1] != reg1) {
 802                         reg_changed = 1;
 803                         chip->aspm_level[1] = reg1;
 804                 }
 805
 806                 if ((reg0 & 0x03) && (reg1 & 0x03))
 807                         maybe_support_aspm = 1;
 808
 809         } else {
 810                 if (reg0 & 0x03)
 811                         maybe_support_aspm = 1;
 812         }
 813
 814         if (reg_changed) {
 815                 if (maybe_support_aspm)
 816                         chip->aspm_l0s_l1_en = 0x03;
 817
 818                 dev_dbg(rtsx_dev(chip), "aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n",
 819                         chip->aspm_level[0], chip->aspm_level[1]);
 820
 821                 if (chip->aspm_l0s_l1_en) {
 822                         chip->aspm_enabled = 1;
 823                 } else {
 824                         chip->aspm_enabled = 0;
 825                         chip->sdio_aspm = 0;
 826                 }
 827                 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF,
 828                                     0x30 | chip->aspm_level[0] |
 829                                     (chip->aspm_level[1] << 2));
 830         }
 831 }
 832
 833 void rtsx_polling_func(struct rtsx_chip *chip)
 834 {
 835 #ifdef SUPPORT_SD_LOCK
 836         struct sd_info *sd_card = &chip->sd_card;
 837 #endif
 838         int ss_allowed;
 839
 840         if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND))
 841                 return;
 842
 843         if (rtsx_chk_stat(chip, RTSX_STAT_DELINK))
 844                 goto delink_stage;
 845
 846         if (chip->polling_config) {
 847                 u8 val;
 848
 849                 rtsx_read_config_byte(chip, 0, &val);
 850         }
 851
 852         if (rtsx_chk_stat(chip, RTSX_STAT_SS))
 853                 return;
 854
 855 #ifdef SUPPORT_OCP
 856         if (chip->ocp_int) {
 857                 rtsx_read_register(chip, OCPSTAT, &chip->ocp_stat);
 858
 859                 if (chip->card_exist & SD_CARD)
 860                         sd_power_off_card3v3(chip);
 861                 else if (chip->card_exist & MS_CARD)
 862                         ms_power_off_card3v3(chip);
 863                 else if (chip->card_exist & XD_CARD)
 864                         xd_power_off_card3v3(chip);
 865
 866                 chip->ocp_int = 0;
 867         }
 868 #endif
 869
 870 #ifdef SUPPORT_SD_LOCK
 871         if (sd_card->sd_erase_status) {
 872                 if (chip->card_exist & SD_CARD) {
 873                         u8 val;
 874
 875                         rtsx_read_register(chip, 0xFD30, &val);
 876                         if (val & 0x02) {
 877                                 sd_card->sd_erase_status = SD_NOT_ERASE;
 878                                 sd_card->sd_lock_notify = 1;
 879                                 chip->need_reinit |= SD_CARD;
 880                         }
 881                 } else {
 882                         sd_card->sd_erase_status = SD_NOT_ERASE;
 883                 }
 884         }
 885 #endif
 886
 887         rtsx_init_cards(chip);
 888
 889         if (chip->ss_en) {
 890                 ss_allowed = 1;
 891
 892                 if (CHECK_PID(chip, 0x5288)) {
 893                         ss_allowed = 0;
 894                 } else {
 895                         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
 896                                 u32 val;
 897
 898                                 rtsx_read_cfg_dw(chip, 1, 0x04, &val);
 899                                 if (val & 0x07)
 900                                         ss_allowed = 0;
 901                         }
 902                 }
 903         } else {
 904                 ss_allowed = 0;
 905         }
 906
 907         if (ss_allowed && !chip->sd_io) {
 908                 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
 909                         chip->ss_counter = 0;
 910                 } else {
 911                         if (chip->ss_counter <
 912                                 (chip->ss_idle_period / POLLING_INTERVAL)) {
 913                                 chip->ss_counter++;
 914                         } else {
 915                                 rtsx_exclusive_enter_ss(chip);
 916                                 return;
 917                         }
 918                 }
 919         }
 920
 921         if (CHECK_PID(chip, 0x5208)) {
 922                 rtsx_monitor_aspm_config(chip);
 923
 924 #ifdef SUPPORT_SDIO_ASPM
 925                 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) &&
 926                     chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
 927                         if (chip->sd_io) {
 928                                 dynamic_configure_sdio_aspm(chip);
 929                         } else {
 930                                 if (!chip->sdio_aspm) {
 931                                         dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n");
 932                                         rtsx_write_register(chip,
 933                                                 ASPM_FORCE_CTL, 0xFC,
 934                                                 0x30 |
 935                                                 (chip->aspm_level[1] << 2));
 936                                         chip->sdio_aspm = 1;
 937                                 }
 938                         }
 939                 }
 940 #endif
 941         }
 942
 943         if (chip->idle_counter < IDLE_MAX_COUNT) {
 944                 chip->idle_counter++;
 945         } else {
 946                 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
 947                         dev_dbg(rtsx_dev(chip), "Idle state!\n");
 948                         rtsx_set_stat(chip, RTSX_STAT_IDLE);
 949
 950 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
 951                         chip->led_toggle_counter = 0;
 952 #endif
 953                         rtsx_force_power_on(chip, SSC_PDCTL);
 954
 955                         turn_off_led(chip, LED_GPIO);
 956
 957                         if (chip->auto_power_down && !chip->card_ready &&
 958                             !chip->sd_io)
 959                                 rtsx_force_power_down(chip,
 960                                                       SSC_PDCTL | OC_PDCTL);
 961                 }
 962         }
 963
 964         switch (rtsx_get_stat(chip)) {
 965         case RTSX_STAT_RUN:
 966 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
 967                 rtsx_blink_led(chip);
 968 #endif
 969                 do_remaining_work(chip);
 970                 break;
 971
 972         case RTSX_STAT_IDLE:
 973                 if (chip->sd_io && !chip->sd_int)
 974                         try_to_switch_sdio_ctrl(chip);
 975
 976                 rtsx_enable_aspm(chip);
 977                 break;
 978
 979         default:
 980                 break;
 981         }
 982
 983 #ifdef SUPPORT_OCP
 984         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
 985                 if (chip->ocp_stat &
 986                         (SD_OC_NOW | SD_OC_EVER | MS_OC_NOW | MS_OC_EVER))
 987                         dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
 988                                 chip->ocp_stat);
 989
 990                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
 991                         if (chip->card_exist & SD_CARD) {
 992                                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN,
 993                                                     0);
 994                                 card_power_off(chip, SD_CARD);
 995                                 chip->card_fail |= SD_CARD;
 996                         }
 997                 }
 998                 if (chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER)) {
 999                         if (chip->card_exist & MS_CARD) {
1000                                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN,
1001                                                     0);
1002                                 card_power_off(chip, MS_CARD);
1003                                 chip->card_fail |= MS_CARD;
1004                         }
1005                 }
1006         } else {
1007                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
1008                         dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1009                                 chip->ocp_stat);
1010                         if (chip->card_exist & SD_CARD) {
1011                                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN,
1012                                                     0);
1013                                 chip->card_fail |= SD_CARD;
1014                         } else if (chip->card_exist & MS_CARD) {
1015                                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN,
1016                                                     0);
1017                                 chip->card_fail |= MS_CARD;
1018                         } else if (chip->card_exist & XD_CARD) {
1019                                 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN,
1020                                                     0);
1021                                 chip->card_fail |= XD_CARD;
1022                         }
1023                         card_power_off(chip, SD_CARD);
1024                 }
1025         }
1026 #endif
1027
1028 delink_stage:
1029         if (chip->auto_delink_en && chip->auto_delink_allowed &&
1030             !chip->card_ready && !chip->card_ejected && !chip->sd_io) {
1031                 int enter_L1 = chip->auto_delink_in_L1 && (
1032                         chip->aspm_l0s_l1_en || chip->ss_en);
1033                 int delink_stage1_cnt = chip->delink_stage1_step;
1034                 int delink_stage2_cnt = delink_stage1_cnt +
1035                         chip->delink_stage2_step;
1036                 int delink_stage3_cnt = delink_stage2_cnt +
1037                         chip->delink_stage3_step;
1038
1039                 if (chip->auto_delink_cnt <= delink_stage3_cnt) {
1040                         if (chip->auto_delink_cnt == delink_stage1_cnt) {
1041                                 rtsx_set_stat(chip, RTSX_STAT_DELINK);
1042
1043                                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1044                                         rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1045
1046                                 if (chip->card_exist) {
1047                                         dev_dbg(rtsx_dev(chip), "False card inserted, do force delink\n");
1048
1049                                         if (enter_L1)
1050                                                 rtsx_write_register(chip,
1051                                                               HOST_SLEEP_STATE,
1052                                                               0x03, 1);
1053
1054                                         rtsx_write_register(chip,
1055                                                             CHANGE_LINK_STATE,
1056                                                             0x0A, 0x0A);
1057
1058                                         if (enter_L1)
1059                                                 rtsx_enter_L1(chip);
1060
1061                                         chip->auto_delink_cnt =
1062                                                 delink_stage3_cnt + 1;
1063                                 } else {
1064                                         dev_dbg(rtsx_dev(chip), "No card inserted, do delink\n");
1065
1066                                         if (enter_L1)
1067                                                 rtsx_write_register(chip,
1068                                                               HOST_SLEEP_STATE,
1069                                                               0x03, 1);
1070
1071                                         rtsx_write_register(chip,
1072                                                             CHANGE_LINK_STATE,
1073                                                             0x02, 0x02);
1074
1075                                         if (enter_L1)
1076                                                 rtsx_enter_L1(chip);
1077                                 }
1078                         }
1079
1080                         if (chip->auto_delink_cnt == delink_stage2_cnt) {
1081                                 dev_dbg(rtsx_dev(chip), "Try to do force delink\n");
1082
1083                                 if (enter_L1)
1084                                         rtsx_exit_L1(chip);
1085
1086                                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1087                                         rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1088
1089                                 rtsx_write_register(chip, CHANGE_LINK_STATE,
1090                                                     0x0A, 0x0A);
1091                         }
1092
1093                         chip->auto_delink_cnt++;
1094                 }
1095         } else {
1096                 chip->auto_delink_cnt = 0;
1097         }
1098 }
1099
1100 void rtsx_undo_delink(struct rtsx_chip *chip)
1101 {
1102         chip->auto_delink_allowed = 0;
1103         rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x00);
1104 }
1105
1106 /**
1107  * rtsx_stop_cmd - stop command transfer and DMA transfer
1108  * @chip: Realtek's card reader chip
1109  * @card: flash card type
1110  *
1111  * Stop command transfer and DMA transfer.
1112  * This function is called in error handler.
1113  */
1114 void rtsx_stop_cmd(struct rtsx_chip *chip, int card)
1115 {
1116         int i;
1117
1118         for (i = 0; i <= 8; i++) {
1119                 int addr = RTSX_HCBAR + i * 4;
1120                 u32 reg;
1121
1122                 reg = rtsx_readl(chip, addr);
1123                 dev_dbg(rtsx_dev(chip), "BAR (0x%02x): 0x%08x\n", addr, reg);
1124         }
1125         rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD);
1126         rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA);
1127
1128         for (i = 0; i < 16; i++) {
1129                 u16 addr = 0xFE20 + (u16)i;
1130                 u8 val;
1131
1132                 rtsx_read_register(chip, addr, &val);
1133                 dev_dbg(rtsx_dev(chip), "0x%04X: 0x%02x\n", addr, val);
1134         }
1135
1136         rtsx_write_register(chip, DMACTL, 0x80, 0x80);
1137         rtsx_write_register(chip, RBCTL, 0x80, 0x80);
1138 }
1139
1140 #define MAX_RW_REG_CNT          1024
1141
1142 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data)
1143 {
1144         int i;
1145         u32 val = 3 << 30;
1146
1147         val |= (u32)(addr & 0x3FFF) << 16;
1148         val |= (u32)mask << 8;
1149         val |= (u32)data;
1150
1151         rtsx_writel(chip, RTSX_HAIMR, val);
1152
1153         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1154                 val = rtsx_readl(chip, RTSX_HAIMR);
1155                 if ((val & (1 << 31)) == 0) {
1156                         if (data != (u8)val)
1157                                 TRACE_RET(chip, STATUS_FAIL);
1158
1159                         return STATUS_SUCCESS;
1160                 }
1161         }
1162
1163         TRACE_RET(chip, STATUS_TIMEDOUT);
1164 }
1165
1166 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data)
1167 {
1168         u32 val = 2 << 30;
1169         int i;
1170
1171         if (data)
1172                 *data = 0;
1173
1174         val |= (u32)(addr & 0x3FFF) << 16;
1175
1176         rtsx_writel(chip, RTSX_HAIMR, val);
1177
1178         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1179                 val = rtsx_readl(chip, RTSX_HAIMR);
1180                 if ((val & (1 << 31)) == 0)
1181                         break;
1182         }
1183
1184         if (i >= MAX_RW_REG_CNT)
1185                 TRACE_RET(chip, STATUS_TIMEDOUT);
1186
1187         if (data)
1188                 *data = (u8)(val & 0xFF);
1189
1190         return STATUS_SUCCESS;
1191 }
1192
1193 int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask,
1194                       u32 val)
1195 {
1196         u8 mode = 0, tmp;
1197         int i;
1198
1199         for (i = 0; i < 4; i++) {
1200                 if (mask & 0xFF) {
1201                         RTSX_WRITE_REG(chip, CFGDATA0 + i,
1202                                        0xFF, (u8)(val & mask & 0xFF));
1203                         mode |= (1 << i);
1204                 }
1205                 mask >>= 8;
1206                 val >>= 8;
1207         }
1208
1209         if (mode) {
1210                 RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr);
1211                 RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1212
1213                 RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF,
1214                                0x80 | mode | ((func_no & 0x03) << 4));
1215
1216                 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1217                         RTSX_READ_REG(chip, CFGRWCTL, &tmp);
1218                         if ((tmp & 0x80) == 0)
1219                                 break;
1220                 }
1221         }
1222
1223         return STATUS_SUCCESS;
1224 }
1225
1226 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val)
1227 {
1228         int i;
1229         u8 tmp;
1230         u32 data = 0;
1231
1232         RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr);
1233         RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1234         RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF, 0x80 | ((func_no & 0x03) << 4));
1235
1236         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1237                 RTSX_READ_REG(chip, CFGRWCTL, &tmp);
1238                 if ((tmp & 0x80) == 0)
1239                         break;
1240         }
1241
1242         for (i = 0; i < 4; i++) {
1243                 RTSX_READ_REG(chip, CFGDATA0 + i, &tmp);
1244                 data |= (u32)tmp << (i * 8);
1245         }
1246
1247         if (val)
1248                 *val = data;
1249
1250         return STATUS_SUCCESS;
1251 }
1252
1253 int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1254                        int len)
1255 {
1256         u32 *data, *mask;
1257         u16 offset = addr % 4;
1258         u16 aligned_addr = addr - offset;
1259         int dw_len, i, j;
1260         int retval;
1261
1262         if (!buf)
1263                 TRACE_RET(chip, STATUS_NOMEM);
1264
1265         if ((len + offset) % 4)
1266                 dw_len = (len + offset) / 4 + 1;
1267         else
1268                 dw_len = (len + offset) / 4;
1269
1270         dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1271
1272         data = vzalloc(dw_len * 4);
1273         if (!data)
1274                 TRACE_RET(chip, STATUS_NOMEM);
1275
1276         mask = vzalloc(dw_len * 4);
1277         if (!mask) {
1278                 vfree(data);
1279                 TRACE_RET(chip, STATUS_NOMEM);
1280         }
1281
1282         j = 0;
1283         for (i = 0; i < len; i++) {
1284                 mask[j] |= 0xFF << (offset * 8);
1285                 data[j] |= buf[i] << (offset * 8);
1286                 if (++offset == 4) {
1287                         j++;
1288                         offset = 0;
1289                 }
1290         }
1291
1292         print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, mask,
1293                              dw_len * 4);
1294         print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, data,
1295                              dw_len * 4);
1296
1297         for (i = 0; i < dw_len; i++) {
1298                 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4,
1299                                            mask[i], data[i]);
1300                 if (retval != STATUS_SUCCESS) {
1301                         vfree(data);
1302                         vfree(mask);
1303                         TRACE_RET(chip, STATUS_FAIL);
1304                 }
1305         }
1306
1307         vfree(data);
1308         vfree(mask);
1309
1310         return STATUS_SUCCESS;
1311 }
1312
1313 int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1314                       int len)
1315 {
1316         u32 *data;
1317         u16 offset = addr % 4;
1318         u16 aligned_addr = addr - offset;
1319         int dw_len, i, j;
1320         int retval;
1321
1322         if ((len + offset) % 4)
1323                 dw_len = (len + offset) / 4 + 1;
1324         else
1325                 dw_len = (len + offset) / 4;
1326
1327         dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1328
1329         data = vmalloc(dw_len * 4);
1330         if (!data)
1331                 TRACE_RET(chip, STATUS_NOMEM);
1332
1333         for (i = 0; i < dw_len; i++) {
1334                 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4,
1335                                           data + i);
1336                 if (retval != STATUS_SUCCESS) {
1337                         vfree(data);
1338                         TRACE_RET(chip, STATUS_FAIL);
1339                 }
1340         }
1341
1342         if (buf) {
1343                 j = 0;
1344
1345                 for (i = 0; i < len; i++) {
1346                         buf[i] = (u8)(data[j] >> (offset * 8));
1347                         if (++offset == 4) {
1348                                 j++;
1349                                 offset = 0;
1350                         }
1351                 }
1352         }
1353
1354         vfree(data);
1355
1356         return STATUS_SUCCESS;
1357 }
1358
1359 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val)
1360 {
1361         int i, finished = 0;
1362         u8 tmp;
1363
1364         RTSX_WRITE_REG(chip, PHYDATA0, 0xFF, (u8)val);
1365         RTSX_WRITE_REG(chip, PHYDATA1, 0xFF, (u8)(val >> 8));
1366         RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr);
1367         RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x81);
1368
1369         for (i = 0; i < 100000; i++) {
1370                 RTSX_READ_REG(chip, PHYRWCTL, &tmp);
1371                 if (!(tmp & 0x80)) {
1372                         finished = 1;
1373                         break;
1374                 }
1375         }
1376
1377         if (!finished)
1378                 TRACE_RET(chip, STATUS_FAIL);
1379
1380         return STATUS_SUCCESS;
1381 }
1382
1383 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val)
1384 {
1385         int i, finished = 0;
1386         u16 data = 0;
1387         u8 tmp;
1388
1389         RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr);
1390         RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x80);
1391
1392         for (i = 0; i < 100000; i++) {
1393                 RTSX_READ_REG(chip, PHYRWCTL, &tmp);
1394                 if (!(tmp & 0x80)) {
1395                         finished = 1;
1396                         break;
1397                 }
1398         }
1399
1400         if (!finished)
1401                 TRACE_RET(chip, STATUS_FAIL);
1402
1403         RTSX_READ_REG(chip, PHYDATA0, &tmp);
1404         data = tmp;
1405         RTSX_READ_REG(chip, PHYDATA1, &tmp);
1406         data |= (u16)tmp << 8;
1407
1408         if (val)
1409                 *val = data;
1410
1411         return STATUS_SUCCESS;
1412 }
1413
1414 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val)
1415 {
1416         int i;
1417         u8 data = 0;
1418
1419         RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0x80|addr);
1420
1421         for (i = 0; i < 100; i++) {
1422                 RTSX_READ_REG(chip, EFUSE_CTRL, &data);
1423                 if (!(data & 0x80))
1424                         break;
1425                 udelay(1);
1426         }
1427
1428         if (data & 0x80)
1429                 TRACE_RET(chip, STATUS_TIMEDOUT);
1430
1431         RTSX_READ_REG(chip, EFUSE_DATA, &data);
1432         if (val)
1433                 *val = data;
1434
1435         return STATUS_SUCCESS;
1436 }
1437
1438 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val)
1439 {
1440         int i, j;
1441         u8 data = 0, tmp = 0xFF;
1442
1443         for (i = 0; i < 8; i++) {
1444                 if (val & (u8)(1 << i))
1445                         continue;
1446
1447                 tmp &= (~(u8)(1 << i));
1448                 dev_dbg(rtsx_dev(chip), "Write 0x%x to 0x%x\n", tmp, addr);
1449
1450                 RTSX_WRITE_REG(chip, EFUSE_DATA, 0xFF, tmp);
1451                 RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0xA0|addr);
1452
1453                 for (j = 0; j < 100; j++) {
1454                         RTSX_READ_REG(chip, EFUSE_CTRL, &data);
1455                         if (!(data & 0x80))
1456                                 break;
1457                         wait_timeout(3);
1458                 }
1459
1460                 if (data & 0x80)
1461                         TRACE_RET(chip, STATUS_TIMEDOUT);
1462
1463                 wait_timeout(5);
1464         }
1465
1466         return STATUS_SUCCESS;
1467 }
1468
1469 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1470 {
1471         int retval;
1472         u16 value;
1473
1474         retval = rtsx_read_phy_register(chip, reg, &value);
1475         if (retval != STATUS_SUCCESS)
1476                 TRACE_RET(chip, STATUS_FAIL);
1477
1478         if (value & (1 << bit)) {
1479                 value &= ~(1 << bit);
1480                 retval = rtsx_write_phy_register(chip, reg, value);
1481                 if (retval != STATUS_SUCCESS)
1482                         TRACE_RET(chip, STATUS_FAIL);
1483         }
1484
1485         return STATUS_SUCCESS;
1486 }
1487
1488 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1489 {
1490         int retval;
1491         u16 value;
1492
1493         retval = rtsx_read_phy_register(chip, reg, &value);
1494         if (retval != STATUS_SUCCESS)
1495                 TRACE_RET(chip, STATUS_FAIL);
1496
1497         if ((value & (1 << bit)) == 0) {
1498                 value |= (1 << bit);
1499                 retval = rtsx_write_phy_register(chip, reg, value);
1500                 if (retval != STATUS_SUCCESS)
1501                         TRACE_RET(chip, STATUS_FAIL);
1502         }
1503
1504         return STATUS_SUCCESS;
1505 }
1506
1507 int rtsx_check_link_ready(struct rtsx_chip *chip)
1508 {
1509         u8 val;
1510
1511         RTSX_READ_REG(chip, IRQSTAT0, &val);
1512
1513         dev_dbg(rtsx_dev(chip), "IRQSTAT0: 0x%x\n", val);
1514         if (val & LINK_RDY_INT) {
1515                 dev_dbg(rtsx_dev(chip), "Delinked!\n");
1516                 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
1517                 return STATUS_FAIL;
1518         }
1519
1520         return STATUS_SUCCESS;
1521 }
1522
1523 static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate)
1524 {
1525         u32 ultmp;
1526
1527         dev_dbg(rtsx_dev(chip), "%04x set pm_dstate to %d\n",
1528                 chip->product_id, dstate);
1529
1530         if (CHK_SDIO_EXIST(chip)) {
1531                 u8 func_no;
1532
1533                 if (CHECK_PID(chip, 0x5288))
1534                         func_no = 2;
1535                 else
1536                         func_no = 1;
1537
1538                 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp);
1539                 dev_dbg(rtsx_dev(chip), "pm_dstate of function %d: 0x%x\n",
1540                         (int)func_no, ultmp);
1541                 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate);
1542         }
1543
1544         rtsx_write_config_byte(chip, 0x44, dstate);
1545         rtsx_write_config_byte(chip, 0x45, 0);
1546 }
1547
1548 void rtsx_enter_L1(struct rtsx_chip *chip)
1549 {
1550         rtsx_handle_pm_dstate(chip, 2);
1551 }
1552
1553 void rtsx_exit_L1(struct rtsx_chip *chip)
1554 {
1555         rtsx_write_config_byte(chip, 0x44, 0);
1556         rtsx_write_config_byte(chip, 0x45, 0);
1557 }
1558
1559 void rtsx_enter_ss(struct rtsx_chip *chip)
1560 {
1561         dev_dbg(rtsx_dev(chip), "Enter Selective Suspend State!\n");
1562
1563         rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
1564
1565         if (chip->power_down_in_ss) {
1566                 rtsx_power_off_card(chip);
1567                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1568         }
1569
1570         if (CHK_SDIO_EXIST(chip))
1571                 rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
1572                                   0xC0, 0xFF00, 0x0100);
1573
1574         if (chip->auto_delink_en) {
1575                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01);
1576         } else {
1577                 if (!chip->phy_debug_mode) {
1578                         u32 tmp;
1579
1580                         tmp = rtsx_readl(chip, RTSX_BIER);
1581                         tmp |= CARD_INT;
1582                         rtsx_writel(chip, RTSX_BIER, tmp);
1583                 }
1584
1585                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0);
1586         }
1587
1588         rtsx_enter_L1(chip);
1589
1590         RTSX_CLR_DELINK(chip);
1591         rtsx_set_stat(chip, RTSX_STAT_SS);
1592 }
1593
1594 void rtsx_exit_ss(struct rtsx_chip *chip)
1595 {
1596         dev_dbg(rtsx_dev(chip), "Exit Selective Suspend State!\n");
1597
1598         rtsx_exit_L1(chip);
1599
1600         if (chip->power_down_in_ss) {
1601                 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
1602                 udelay(1000);
1603         }
1604
1605         if (RTSX_TST_DELINK(chip)) {
1606                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1607                 rtsx_reinit_cards(chip, 1);
1608                 RTSX_CLR_DELINK(chip);
1609         } else if (chip->power_down_in_ss) {
1610                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1611                 rtsx_reinit_cards(chip, 0);
1612         }
1613 }
1614
1615 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip)
1616 {
1617         u32 status, int_enable;
1618         int exit_ss = 0;
1619 #ifdef SUPPORT_OCP
1620         u32 ocp_int = 0;
1621
1622         ocp_int = OC_INT;
1623 #endif
1624
1625         if (chip->ss_en) {
1626                 chip->ss_counter = 0;
1627                 if (rtsx_get_stat(chip) == RTSX_STAT_SS) {
1628                         exit_ss = 1;
1629                         rtsx_exit_L1(chip);
1630                         rtsx_set_stat(chip, RTSX_STAT_RUN);
1631                 }
1632         }
1633
1634         int_enable = rtsx_readl(chip, RTSX_BIER);
1635         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
1636
1637         if (((chip->int_reg & int_enable) == 0) ||
1638             (chip->int_reg == 0xFFFFFFFF))
1639                 return STATUS_FAIL;
1640
1641         status = chip->int_reg &= (int_enable | 0x7FFFFF);
1642
1643         if (status & CARD_INT) {
1644                 chip->auto_delink_cnt = 0;
1645
1646                 if (status & SD_INT) {
1647                         if (status & SD_EXIST) {
1648                                 set_bit(SD_NR, &chip->need_reset);
1649                         } else {
1650                                 set_bit(SD_NR, &chip->need_release);
1651                                 chip->sd_reset_counter = 0;
1652                                 chip->sd_show_cnt = 0;
1653                                 clear_bit(SD_NR, &chip->need_reset);
1654                         }
1655                 } else {
1656                         /* If multi-luns, it's possible that
1657                            when plugging/unplugging one card
1658                            there is another card which still
1659                            exists in the slot. In this case,
1660                            all existed cards should be reset.
1661                         */
1662                         if (exit_ss && (status & SD_EXIST))
1663                                 set_bit(SD_NR, &chip->need_reinit);
1664                 }
1665                 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) {
1666                         if (status & XD_INT) {
1667                                 if (status & XD_EXIST) {
1668                                         set_bit(XD_NR, &chip->need_reset);
1669                                 } else {
1670                                         set_bit(XD_NR, &chip->need_release);
1671                                         chip->xd_reset_counter = 0;
1672                                         chip->xd_show_cnt = 0;
1673                                         clear_bit(XD_NR, &chip->need_reset);
1674                                 }
1675                         } else {
1676                                 if (exit_ss && (status & XD_EXIST))
1677                                         set_bit(XD_NR, &chip->need_reinit);
1678                         }
1679                 }
1680                 if (status & MS_INT) {
1681                         if (status & MS_EXIST) {
1682                                 set_bit(MS_NR, &chip->need_reset);
1683                         } else {
1684                                 set_bit(MS_NR, &chip->need_release);
1685                                 chip->ms_reset_counter = 0;
1686                                 chip->ms_show_cnt = 0;
1687                                 clear_bit(MS_NR, &chip->need_reset);
1688                         }
1689                 } else {
1690                         if (exit_ss && (status & MS_EXIST))
1691                                 set_bit(MS_NR, &chip->need_reinit);
1692                 }
1693         }
1694
1695 #ifdef SUPPORT_OCP
1696         chip->ocp_int = ocp_int & status;
1697 #endif
1698
1699         if (chip->sd_io && (chip->int_reg & DATA_DONE_INT))
1700                 chip->int_reg &= ~(u32)DATA_DONE_INT;
1701
1702         return STATUS_SUCCESS;
1703 }
1704
1705 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat)
1706 {
1707         int retval;
1708
1709         dev_dbg(rtsx_dev(chip), "%s, pm_stat = %d\n", __func__, pm_stat);
1710
1711         rtsx_set_stat(chip, RTSX_STAT_SUSPEND);
1712
1713         retval = rtsx_force_power_on(chip, SSC_PDCTL);
1714         if (retval != STATUS_SUCCESS)
1715                 return;
1716
1717         rtsx_release_cards(chip);
1718         rtsx_disable_bus_int(chip);
1719         turn_off_led(chip, LED_GPIO);
1720
1721 #ifdef HW_AUTO_SWITCH_SD_BUS
1722         if (chip->sd_io) {
1723                 chip->sdio_in_charge = 1;
1724                 if (CHECK_PID(chip, 0x5208)) {
1725                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
1726                         /* Enable sdio_bus_auto_switch */
1727                         rtsx_write_register(chip, 0xFE70, 0x80, 0x80);
1728                 } else if (CHECK_PID(chip, 0x5288)) {
1729                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
1730                         /* Enable sdio_bus_auto_switch */
1731                         rtsx_write_register(chip, 0xFE5A, 0x08, 0x08);
1732                 }
1733         }
1734 #endif
1735
1736         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
1737                 /* u_force_clkreq_0 */
1738                 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
1739         }
1740
1741         if (pm_stat == PM_S1) {
1742                 dev_dbg(rtsx_dev(chip), "Host enter S1\n");
1743                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
1744                                     HOST_ENTER_S1);
1745         } else if (pm_stat == PM_S3) {
1746                 if (chip->s3_pwr_off_delay > 0)
1747                         wait_timeout(chip->s3_pwr_off_delay);
1748
1749                 dev_dbg(rtsx_dev(chip), "Host enter S3\n");
1750                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
1751                                     HOST_ENTER_S3);
1752         }
1753
1754         if (chip->do_delink_before_power_down && chip->auto_delink_en)
1755                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2);
1756
1757         rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1758
1759         chip->cur_clk = 0;
1760         chip->cur_card = 0;
1761         chip->card_exist = 0;
1762 }
1763
1764 void rtsx_enable_aspm(struct rtsx_chip *chip)
1765 {
1766         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && !chip->aspm_enabled) {
1767                 dev_dbg(rtsx_dev(chip), "Try to enable ASPM\n");
1768                 chip->aspm_enabled = 1;
1769
1770                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1771                         rtsx_write_phy_register(chip, 0x07, 0);
1772                 if (CHECK_PID(chip, 0x5208)) {
1773                         rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3,
1774                                             0x30 | chip->aspm_level[0]);
1775                 } else {
1776                         rtsx_write_config_byte(chip, LCTLR,
1777                                                chip->aspm_l0s_l1_en);
1778                 }
1779
1780                 if (CHK_SDIO_EXIST(chip)) {
1781                         u16 val = chip->aspm_l0s_l1_en | 0x0100;
1782
1783                         rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
1784                                           0xC0, 0xFFF, val);
1785                 }
1786         }
1787 }
1788
1789 void rtsx_disable_aspm(struct rtsx_chip *chip)
1790 {
1791         if (CHECK_PID(chip, 0x5208))
1792                 rtsx_monitor_aspm_config(chip);
1793
1794         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && chip->aspm_enabled) {
1795                 dev_dbg(rtsx_dev(chip), "Try to disable ASPM\n");
1796                 chip->aspm_enabled = 0;
1797
1798                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1799                         rtsx_write_phy_register(chip, 0x07, 0x0129);
1800                 if (CHECK_PID(chip, 0x5208))
1801                         rtsx_write_register(chip, ASPM_FORCE_CTL,
1802                                             0xF3, 0x30);
1803                 else
1804                         rtsx_write_config_byte(chip, LCTLR, 0x00);
1805
1806                 wait_timeout(1);
1807         }
1808 }
1809
1810 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
1811 {
1812         int retval;
1813         int i, j;
1814         u16 reg_addr;
1815         u8 *ptr;
1816
1817         if (!buf)
1818                 TRACE_RET(chip, STATUS_ERROR);
1819
1820         ptr = buf;
1821         reg_addr = PPBUF_BASE2;
1822         for (i = 0; i < buf_len/256; i++) {
1823                 rtsx_init_cmd(chip);
1824
1825                 for (j = 0; j < 256; j++)
1826                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
1827
1828                 retval = rtsx_send_cmd(chip, 0, 250);
1829                 if (retval < 0)
1830                         TRACE_RET(chip, STATUS_FAIL);
1831
1832                 memcpy(ptr, rtsx_get_cmd_data(chip), 256);
1833                 ptr += 256;
1834         }
1835
1836         if (buf_len%256) {
1837                 rtsx_init_cmd(chip);
1838
1839                 for (j = 0; j < buf_len%256; j++)
1840                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
1841
1842                 retval = rtsx_send_cmd(chip, 0, 250);
1843                 if (retval < 0)
1844                         TRACE_RET(chip, STATUS_FAIL);
1845         }
1846
1847         memcpy(ptr, rtsx_get_cmd_data(chip), buf_len%256);
1848
1849         return STATUS_SUCCESS;
1850 }
1851
1852 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
1853 {
1854         int retval;
1855         int i, j;
1856         u16 reg_addr;
1857         u8 *ptr;
1858
1859         if (!buf)
1860                 TRACE_RET(chip, STATUS_ERROR);
1861
1862         ptr = buf;
1863         reg_addr = PPBUF_BASE2;
1864         for (i = 0; i < buf_len/256; i++) {
1865                 rtsx_init_cmd(chip);
1866
1867                 for (j = 0; j < 256; j++) {
1868                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
1869                                      *ptr);
1870                         ptr++;
1871                 }
1872
1873                 retval = rtsx_send_cmd(chip, 0, 250);
1874                 if (retval < 0)
1875                         TRACE_RET(chip, STATUS_FAIL);
1876         }
1877
1878         if (buf_len%256) {
1879                 rtsx_init_cmd(chip);
1880
1881                 for (j = 0; j < buf_len%256; j++) {
1882                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
1883                                      *ptr);
1884                         ptr++;
1885                 }
1886
1887                 retval = rtsx_send_cmd(chip, 0, 250);
1888                 if (retval < 0)
1889                         TRACE_RET(chip, STATUS_FAIL);
1890         }
1891
1892         return STATUS_SUCCESS;
1893 }
1894
1895 int rtsx_check_chip_exist(struct rtsx_chip *chip)
1896 {
1897         if (rtsx_readl(chip, 0) == 0xFFFFFFFF)
1898                 TRACE_RET(chip, STATUS_FAIL);
1899
1900         return STATUS_SUCCESS;
1901 }
1902
1903 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl)
1904 {
1905         int retval;
1906         u8 mask = 0;
1907
1908         if (ctl & SSC_PDCTL)
1909                 mask |= SSC_POWER_DOWN;
1910
1911 #ifdef SUPPORT_OCP
1912         if (ctl & OC_PDCTL) {
1913                 mask |= SD_OC_POWER_DOWN;
1914                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
1915                         mask |= MS_OC_POWER_DOWN;
1916         }
1917 #endif
1918
1919         if (mask) {
1920                 retval = rtsx_write_register(chip, FPDCTL, mask, 0);
1921                 if (retval != STATUS_SUCCESS)
1922                         TRACE_RET(chip, STATUS_FAIL);
1923
1924                 if (CHECK_PID(chip, 0x5288))
1925                         wait_timeout(200);
1926         }
1927
1928         return STATUS_SUCCESS;
1929 }
1930
1931 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl)
1932 {
1933         int retval;
1934         u8 mask = 0, val = 0;
1935
1936         if (ctl & SSC_PDCTL)
1937                 mask |= SSC_POWER_DOWN;
1938
1939 #ifdef SUPPORT_OCP
1940         if (ctl & OC_PDCTL) {
1941                 mask |= SD_OC_POWER_DOWN;
1942                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
1943                         mask |= MS_OC_POWER_DOWN;
1944         }
1945 #endif
1946
1947         if (mask) {
1948                 val = mask;
1949                 retval = rtsx_write_register(chip, FPDCTL, mask, val);
1950                 if (retval != STATUS_SUCCESS)
1951                         TRACE_RET(chip, STATUS_FAIL);
1952         }
1953
1954         return STATUS_SUCCESS;
1955 }