drivers/staging/rts5208/sd.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG (wei_wang@realsil.com.cn)
  20  *   Micky Ching (micky_ching@realsil.com.cn)
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26
  27 #include "rtsx.h"
  28 #include "rtsx_transport.h"
  29 #include "rtsx_scsi.h"
  30 #include "rtsx_card.h"
  31 #include "sd.h"
  32
  33 #define SD_MAX_RETRY_COUNT      3
  34
  35 static u16 REG_SD_CFG1;
  36 static u16 REG_SD_CFG2;
  37 static u16 REG_SD_CFG3;
  38 static u16 REG_SD_STAT1;
  39 static u16 REG_SD_STAT2;
  40 static u16 REG_SD_BUS_STAT;
  41 static u16 REG_SD_PAD_CTL;
  42 static u16 REG_SD_SAMPLE_POINT_CTL;
  43 static u16 REG_SD_PUSH_POINT_CTL;
  44 static u16 REG_SD_CMD0;
  45 static u16 REG_SD_CMD1;
  46 static u16 REG_SD_CMD2;
  47 static u16 REG_SD_CMD3;
  48 static u16 REG_SD_CMD4;
  49 static u16 REG_SD_CMD5;
  50 static u16 REG_SD_BYTE_CNT_L;
  51 static u16 REG_SD_BYTE_CNT_H;
  52 static u16 REG_SD_BLOCK_CNT_L;
  53 static u16 REG_SD_BLOCK_CNT_H;
  54 static u16 REG_SD_TRANSFER;
  55 static u16 REG_SD_VPCLK0_CTL;
  56 static u16 REG_SD_VPCLK1_CTL;
  57 static u16 REG_SD_DCMPS0_CTL;
  58 static u16 REG_SD_DCMPS1_CTL;
  59
  60 static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code)
  61 {
  62         struct sd_info *sd_card = &(chip->sd_card);
  63
  64         sd_card->err_code |= err_code;
  65 }
  66
  67 static inline void sd_clr_err_code(struct rtsx_chip *chip)
  68 {
  69         struct sd_info *sd_card = &(chip->sd_card);
  70
  71         sd_card->err_code = 0;
  72 }
  73
  74 static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code)
  75 {
  76         struct sd_info *sd_card = &(chip->sd_card);
  77
  78         return sd_card->err_code & err_code;
  79 }
  80
  81 static void sd_init_reg_addr(struct rtsx_chip *chip)
  82 {
  83         REG_SD_CFG1 = 0xFD31;
  84         REG_SD_CFG2 = 0xFD33;
  85         REG_SD_CFG3 = 0xFD3E;
  86         REG_SD_STAT1 = 0xFD30;
  87         REG_SD_STAT2 = 0;
  88         REG_SD_BUS_STAT = 0;
  89         REG_SD_PAD_CTL = 0;
  90         REG_SD_SAMPLE_POINT_CTL = 0;
  91         REG_SD_PUSH_POINT_CTL = 0;
  92         REG_SD_CMD0 = 0xFD34;
  93         REG_SD_CMD1 = 0xFD35;
  94         REG_SD_CMD2 = 0xFD36;
  95         REG_SD_CMD3 = 0xFD37;
  96         REG_SD_CMD4 = 0xFD38;
  97         REG_SD_CMD5 = 0xFD5A;
  98         REG_SD_BYTE_CNT_L = 0xFD39;
  99         REG_SD_BYTE_CNT_H = 0xFD3A;
 100         REG_SD_BLOCK_CNT_L = 0xFD3B;
 101         REG_SD_BLOCK_CNT_H = 0xFD3C;
 102         REG_SD_TRANSFER = 0xFD32;
 103         REG_SD_VPCLK0_CTL = 0;
 104         REG_SD_VPCLK1_CTL = 0;
 105         REG_SD_DCMPS0_CTL = 0;
 106         REG_SD_DCMPS1_CTL = 0;
 107 }
 108
 109 static int sd_check_data0_status(struct rtsx_chip *chip)
 110 {
 111         u8 stat;
 112
 113         RTSX_READ_REG(chip, REG_SD_STAT1, &stat);
 114
 115         if (!(stat & SD_DAT0_STATUS)) {
 116                 sd_set_err_code(chip, SD_BUSY);
 117                 TRACE_RET(chip, STATUS_FAIL);
 118         }
 119
 120         return STATUS_SUCCESS;
 121 }
 122
 123 static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
 124                 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
 125 {
 126         struct sd_info *sd_card = &(chip->sd_card);
 127         int retval;
 128         int timeout = 100;
 129         u16 reg_addr;
 130         u8 *ptr;
 131         int stat_idx = 0;
 132         int rty_cnt = 0;
 133
 134         sd_clr_err_code(chip);
 135
 136         dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg);
 137
 138         if (rsp_type == SD_RSP_TYPE_R1b)
 139                 timeout = 3000;
 140
 141 RTY_SEND_CMD:
 142
 143         rtsx_init_cmd(chip);
 144
 145         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
 146         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
 147         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
 148         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
 149         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
 150
 151         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
 152         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
 153                         0x01, PINGPONG_BUFFER);
 154         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
 155                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
 156         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
 157                 SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END | SD_STAT_IDLE);
 158
 159         if (rsp_type == SD_RSP_TYPE_R2) {
 160                 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
 161                      reg_addr++)
 162                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
 163
 164                 stat_idx = 16;
 165         } else if (rsp_type != SD_RSP_TYPE_R0) {
 166                 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
 167                      reg_addr++)
 168                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
 169
 170                 stat_idx = 5;
 171         }
 172
 173         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
 174
 175         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
 176         if (retval < 0) {
 177                 u8 val;
 178
 179                 rtsx_read_register(chip, REG_SD_STAT1, &val);
 180                 dev_dbg(rtsx_dev(chip), "SD_STAT1: 0x%x\n", val);
 181
 182                 rtsx_read_register(chip, REG_SD_CFG3, &val);
 183                 dev_dbg(rtsx_dev(chip), "SD_CFG3: 0x%x\n", val);
 184
 185                 if (retval == -ETIMEDOUT) {
 186                         if (rsp_type & SD_WAIT_BUSY_END) {
 187                                 retval = sd_check_data0_status(chip);
 188                                 if (retval != STATUS_SUCCESS) {
 189                                         rtsx_clear_sd_error(chip);
 190                                         TRACE_RET(chip, retval);
 191                                 }
 192                         } else {
 193                                 sd_set_err_code(chip, SD_TO_ERR);
 194                         }
 195                         retval = STATUS_TIMEDOUT;
 196                 } else {
 197                         retval = STATUS_FAIL;
 198                 }
 199                 rtsx_clear_sd_error(chip);
 200
 201                 TRACE_RET(chip, retval);
 202         }
 203
 204         if (rsp_type == SD_RSP_TYPE_R0)
 205                 return STATUS_SUCCESS;
 206
 207         ptr = rtsx_get_cmd_data(chip) + 1;
 208
 209         if ((ptr[0] & 0xC0) != 0) {
 210                 sd_set_err_code(chip, SD_STS_ERR);
 211                 TRACE_RET(chip, STATUS_FAIL);
 212         }
 213
 214         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 215                 if (ptr[stat_idx] & SD_CRC7_ERR) {
 216                         if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
 217                                 sd_set_err_code(chip, SD_CRC_ERR);
 218                                 TRACE_RET(chip, STATUS_FAIL);
 219                         }
 220                         if (rty_cnt < SD_MAX_RETRY_COUNT) {
 221                                 wait_timeout(20);
 222                                 rty_cnt++;
 223                                 goto RTY_SEND_CMD;
 224                         } else {
 225                                 sd_set_err_code(chip, SD_CRC_ERR);
 226                                 TRACE_RET(chip, STATUS_FAIL);
 227                         }
 228                 }
 229         }
 230
 231         if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) {
 232                 if ((cmd_idx != SEND_RELATIVE_ADDR) &&
 233                         (cmd_idx != SEND_IF_COND)) {
 234                         if (cmd_idx != STOP_TRANSMISSION) {
 235                                 if (ptr[1] & 0x80)
 236                                         TRACE_RET(chip, STATUS_FAIL);
 237                         }
 238 #ifdef SUPPORT_SD_LOCK
 239                         if (ptr[1] & 0x7D)
 240 #else
 241                         if (ptr[1] & 0x7F)
 242 #endif
 243                         {
 244                                 dev_dbg(rtsx_dev(chip), "ptr[1]: 0x%02x\n",
 245                                         ptr[1]);
 246                                 TRACE_RET(chip, STATUS_FAIL);
 247                         }
 248                         if (ptr[2] & 0xFF) {
 249                                 dev_dbg(rtsx_dev(chip), "ptr[2]: 0x%02x\n",
 250                                         ptr[2]);
 251                                 TRACE_RET(chip, STATUS_FAIL);
 252                         }
 253                         if (ptr[3] & 0x80) {
 254                                 dev_dbg(rtsx_dev(chip), "ptr[3]: 0x%02x\n",
 255                                         ptr[3]);
 256                                 TRACE_RET(chip, STATUS_FAIL);
 257                         }
 258                         if (ptr[3] & 0x01)
 259                                 sd_card->sd_data_buf_ready = 1;
 260                         else
 261                                 sd_card->sd_data_buf_ready = 0;
 262                 }
 263         }
 264
 265         if (rsp && rsp_len)
 266                 memcpy(rsp, ptr, rsp_len);
 267
 268         return STATUS_SUCCESS;
 269 }
 270
 271 static int sd_read_data(struct rtsx_chip *chip,
 272                         u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt,
 273                         u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len,
 274                         int timeout)
 275 {
 276         struct sd_info *sd_card = &(chip->sd_card);
 277         int retval;
 278         int i;
 279
 280         sd_clr_err_code(chip);
 281
 282         if (!buf)
 283                 buf_len = 0;
 284
 285         if (buf_len > 512)
 286                 TRACE_RET(chip, STATUS_FAIL);
 287
 288         rtsx_init_cmd(chip);
 289
 290         if (cmd_len) {
 291                 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40);
 292                 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++)
 293                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i,
 294                                      0xFF, cmd[i]);
 295         }
 296         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
 297                 (u8)byte_cnt);
 298         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
 299                 (u8)(byte_cnt >> 8));
 300         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
 301                 (u8)blk_cnt);
 302         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
 303                 (u8)(blk_cnt >> 8));
 304
 305         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
 306
 307         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
 308                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END|
 309                 SD_CHECK_CRC7 | SD_RSP_LEN_6);
 310         if (trans_mode != SD_TM_AUTO_TUNING)
 311                 rtsx_add_cmd(chip, WRITE_REG_CMD,
 312                         CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
 313
 314         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
 315                 trans_mode | SD_TRANSFER_START);
 316         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
 317                 SD_TRANSFER_END);
 318
 319         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
 320         if (retval < 0) {
 321                 if (retval == -ETIMEDOUT) {
 322                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
 323                                             SD_RSP_TYPE_R1, NULL, 0);
 324                 }
 325
 326                 TRACE_RET(chip, STATUS_FAIL);
 327         }
 328
 329         if (buf && buf_len) {
 330                 retval = rtsx_read_ppbuf(chip, buf, buf_len);
 331                 if (retval != STATUS_SUCCESS)
 332                         TRACE_RET(chip, STATUS_FAIL);
 333         }
 334
 335         return STATUS_SUCCESS;
 336 }
 337
 338 static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode,
 339                 u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt, u8 bus_width,
 340                 u8 *buf, int buf_len, int timeout)
 341 {
 342         struct sd_info *sd_card = &(chip->sd_card);
 343         int retval;
 344         int i;
 345
 346         sd_clr_err_code(chip);
 347
 348         if (!buf)
 349                 buf_len = 0;
 350
 351         if (buf_len > 512) {
 352                 /* This function can't write data more than one page */
 353                 TRACE_RET(chip, STATUS_FAIL);
 354         }
 355
 356         if (buf && buf_len) {
 357                 retval = rtsx_write_ppbuf(chip, buf, buf_len);
 358                 if (retval != STATUS_SUCCESS)
 359                         TRACE_RET(chip, STATUS_FAIL);
 360         }
 361
 362         rtsx_init_cmd(chip);
 363
 364         if (cmd_len) {
 365                 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40);
 366                 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
 367                         rtsx_add_cmd(chip, WRITE_REG_CMD,
 368                                      REG_SD_CMD0 + i, 0xFF, cmd[i]);
 369                 }
 370         }
 371         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
 372                 (u8)byte_cnt);
 373         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
 374                 (u8)(byte_cnt >> 8));
 375         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
 376                 (u8)blk_cnt);
 377         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
 378                 (u8)(blk_cnt >> 8));
 379
 380         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
 381
 382         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
 383                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
 384                 SD_CHECK_CRC7 | SD_RSP_LEN_6);
 385
 386         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
 387                 trans_mode | SD_TRANSFER_START);
 388         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
 389                 SD_TRANSFER_END);
 390
 391         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
 392         if (retval < 0) {
 393                 if (retval == -ETIMEDOUT) {
 394                         sd_send_cmd_get_rsp(chip, SEND_STATUS,
 395                                 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
 396                 }
 397
 398                 TRACE_RET(chip, STATUS_FAIL);
 399         }
 400
 401         return STATUS_SUCCESS;
 402 }
 403
 404 static int sd_check_csd(struct rtsx_chip *chip, char check_wp)
 405 {
 406         struct sd_info *sd_card = &(chip->sd_card);
 407         int retval;
 408         int i;
 409         u8 csd_ver, trans_speed;
 410         u8 rsp[16];
 411
 412         for (i = 0; i < 6; i++) {
 413                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
 414                         sd_set_err_code(chip, SD_NO_CARD);
 415                         TRACE_RET(chip, STATUS_FAIL);
 416                 }
 417
 418                 retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr,
 419                                         SD_RSP_TYPE_R2, rsp, 16);
 420                 if (retval == STATUS_SUCCESS)
 421                         break;
 422         }
 423
 424         if (i == 6)
 425                 TRACE_RET(chip, STATUS_FAIL);
 426
 427         memcpy(sd_card->raw_csd, rsp + 1, 15);
 428
 429         dev_dbg(rtsx_dev(chip), "CSD Response:\n");
 430         RTSX_DUMP(sd_card->raw_csd, 16);
 431
 432         csd_ver = (rsp[1] & 0xc0) >> 6;
 433         dev_dbg(rtsx_dev(chip), "csd_ver = %d\n", csd_ver);
 434
 435         trans_speed = rsp[4];
 436         if ((trans_speed & 0x07) == 0x02) {
 437                 if ((trans_speed & 0xf8) >= 0x30) {
 438                         if (chip->asic_code)
 439                                 sd_card->sd_clock = 47;
 440                         else
 441                                 sd_card->sd_clock = CLK_50;
 442
 443                 } else if ((trans_speed & 0xf8) == 0x28) {
 444                         if (chip->asic_code)
 445                                 sd_card->sd_clock = 39;
 446                         else
 447                                 sd_card->sd_clock = CLK_40;
 448
 449                 } else if ((trans_speed & 0xf8) == 0x20) {
 450                         if (chip->asic_code)
 451                                 sd_card->sd_clock = 29;
 452                         else
 453                                 sd_card->sd_clock = CLK_30;
 454
 455                 } else if ((trans_speed & 0xf8) >= 0x10) {
 456                         if (chip->asic_code)
 457                                 sd_card->sd_clock = 23;
 458                         else
 459                                 sd_card->sd_clock = CLK_20;
 460
 461                 } else if ((trans_speed & 0x08) >= 0x08) {
 462                         if (chip->asic_code)
 463                                 sd_card->sd_clock = 19;
 464                         else
 465                                 sd_card->sd_clock = CLK_20;
 466                 } else {
 467                         TRACE_RET(chip, STATUS_FAIL);
 468                 }
 469         } else {
 470                 TRACE_RET(chip, STATUS_FAIL);
 471         }
 472
 473         if (CHK_MMC_SECTOR_MODE(sd_card)) {
 474                 sd_card->capacity = 0;
 475         } else {
 476                 if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) {
 477                         u8 blk_size, c_size_mult;
 478                         u16 c_size;
 479                         blk_size = rsp[6] & 0x0F;
 480                         c_size =  ((u16)(rsp[7] & 0x03) << 10)
 481                                         + ((u16)rsp[8] << 2)
 482                                         + ((u16)(rsp[9] & 0xC0) >> 6);
 483                         c_size_mult = (u8)((rsp[10] & 0x03) << 1);
 484                         c_size_mult += (rsp[11] & 0x80) >> 7;
 485                         sd_card->capacity = (((u32)(c_size + 1)) *
 486                                         (1 << (c_size_mult + 2)))
 487                                 << (blk_size - 9);
 488                 } else {
 489                         u32 total_sector = 0;
 490                         total_sector = (((u32)rsp[8] & 0x3f) << 16) |
 491                                 ((u32)rsp[9] << 8) | (u32)rsp[10];
 492                         sd_card->capacity = (total_sector + 1) << 10;
 493                 }
 494         }
 495
 496         if (check_wp) {
 497                 if (rsp[15] & 0x30)
 498                         chip->card_wp |= SD_CARD;
 499
 500                 dev_dbg(rtsx_dev(chip), "CSD WP Status: 0x%x\n", rsp[15]);
 501         }
 502
 503         return STATUS_SUCCESS;
 504 }
 505
 506 static int sd_set_sample_push_timing(struct rtsx_chip *chip)
 507 {
 508         struct sd_info *sd_card = &(chip->sd_card);
 509
 510         u8 val = 0;
 511
 512         if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY)
 513                 val |= 0x10;
 514
 515         if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
 516                 if (chip->asic_code) {
 517                         if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
 518                                 if (val & 0x10)
 519                                         val |= 0x04;
 520                                 else
 521                                         val |= 0x08;
 522                         }
 523                 } else {
 524                         if (val & 0x10)
 525                                 val |= 0x04;
 526                         else
 527                                 val |= 0x08;
 528                 }
 529         } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) ==
 530                 SD_SAMPLE_POINT_DELAY) {
 531                 if (val & 0x10)
 532                         val |= 0x04;
 533                 else
 534                         val |= 0x08;
 535         }
 536
 537         RTSX_WRITE_REG(chip, REG_SD_CFG1, 0x1C, val);
 538
 539         return STATUS_SUCCESS;
 540 }
 541
 542 static void sd_choose_proper_clock(struct rtsx_chip *chip)
 543 {
 544         struct sd_info *sd_card = &(chip->sd_card);
 545
 546         if (CHK_SD_SDR104(sd_card)) {
 547                 if (chip->asic_code)
 548                         sd_card->sd_clock = chip->asic_sd_sdr104_clk;
 549                 else
 550                         sd_card->sd_clock = chip->fpga_sd_sdr104_clk;
 551
 552         } else if (CHK_SD_DDR50(sd_card)) {
 553                 if (chip->asic_code)
 554                         sd_card->sd_clock = chip->asic_sd_ddr50_clk;
 555                 else
 556                         sd_card->sd_clock = chip->fpga_sd_ddr50_clk;
 557
 558         } else if (CHK_SD_SDR50(sd_card)) {
 559                 if (chip->asic_code)
 560                         sd_card->sd_clock = chip->asic_sd_sdr50_clk;
 561                 else
 562                         sd_card->sd_clock = chip->fpga_sd_sdr50_clk;
 563
 564         } else if (CHK_SD_HS(sd_card)) {
 565                 if (chip->asic_code)
 566                         sd_card->sd_clock = chip->asic_sd_hs_clk;
 567                 else
 568                         sd_card->sd_clock = chip->fpga_sd_hs_clk;
 569
 570         } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
 571                 if (chip->asic_code)
 572                         sd_card->sd_clock = chip->asic_mmc_52m_clk;
 573                 else
 574                         sd_card->sd_clock = chip->fpga_mmc_52m_clk;
 575
 576         } else if (CHK_MMC_26M(sd_card)) {
 577                 if (chip->asic_code)
 578                         sd_card->sd_clock = 48;
 579                 else
 580                         sd_card->sd_clock = CLK_50;
 581         }
 582 }
 583
 584 static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div)
 585 {
 586         u8 mask = 0, val = 0;
 587
 588         mask = 0x60;
 589         if (clk_div == SD_CLK_DIVIDE_0)
 590                 val = 0x00;
 591         else if (clk_div == SD_CLK_DIVIDE_128)
 592                 val = 0x40;
 593         else if (clk_div == SD_CLK_DIVIDE_256)
 594                 val = 0x20;
 595
 596         RTSX_WRITE_REG(chip, REG_SD_CFG1, mask, val);
 597
 598         return STATUS_SUCCESS;
 599 }
 600
 601 static int sd_set_init_para(struct rtsx_chip *chip)
 602 {
 603         struct sd_info *sd_card = &(chip->sd_card);
 604         int retval;
 605
 606         retval = sd_set_sample_push_timing(chip);
 607         if (retval != STATUS_SUCCESS)
 608                 TRACE_RET(chip, STATUS_FAIL);
 609
 610         sd_choose_proper_clock(chip);
 611
 612         retval = switch_clock(chip, sd_card->sd_clock);
 613         if (retval != STATUS_SUCCESS)
 614                 TRACE_RET(chip, STATUS_FAIL);
 615
 616         return STATUS_SUCCESS;
 617 }
 618
 619 int sd_select_card(struct rtsx_chip *chip, int select)
 620 {
 621         struct sd_info *sd_card = &(chip->sd_card);
 622         int retval;
 623         u8 cmd_idx, cmd_type;
 624         u32 addr;
 625
 626         if (select) {
 627                 cmd_idx = SELECT_CARD;
 628                 cmd_type = SD_RSP_TYPE_R1;
 629                 addr = sd_card->sd_addr;
 630         } else {
 631                 cmd_idx = DESELECT_CARD;
 632                 cmd_type = SD_RSP_TYPE_R0;
 633                 addr = 0;
 634         }
 635
 636         retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
 637         if (retval != STATUS_SUCCESS)
 638                 TRACE_RET(chip, STATUS_FAIL);
 639
 640         return STATUS_SUCCESS;
 641 }
 642
 643 #ifdef SUPPORT_SD_LOCK
 644 static int sd_update_lock_status(struct rtsx_chip *chip)
 645 {
 646         struct sd_info *sd_card = &(chip->sd_card);
 647         int retval;
 648         u8 rsp[5];
 649
 650         retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
 651                                 SD_RSP_TYPE_R1, rsp, 5);
 652         if (retval != STATUS_SUCCESS)
 653                 TRACE_RET(chip, STATUS_FAIL);
 654
 655         if (rsp[1] & 0x02)
 656                 sd_card->sd_lock_status |= SD_LOCKED;
 657         else
 658                 sd_card->sd_lock_status &= ~SD_LOCKED;
 659
 660         dev_dbg(rtsx_dev(chip), "sd_card->sd_lock_status = 0x%x\n",
 661                 sd_card->sd_lock_status);
 662
 663         if (rsp[1] & 0x01)
 664                 TRACE_RET(chip, STATUS_FAIL);
 665
 666         return STATUS_SUCCESS;
 667 }
 668 #endif
 669
 670 static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state,
 671                                 u8 data_ready, int polling_cnt)
 672 {
 673         struct sd_info *sd_card = &(chip->sd_card);
 674         int retval, i;
 675         u8 rsp[5];
 676
 677         for (i = 0; i < polling_cnt; i++) {
 678                 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
 679                                         sd_card->sd_addr, SD_RSP_TYPE_R1, rsp,
 680                                         5);
 681                 if (retval != STATUS_SUCCESS)
 682                         TRACE_RET(chip, STATUS_FAIL);
 683
 684                 if (((rsp[3] & 0x1E) == state) &&
 685                         ((rsp[3] & 0x01) == data_ready))
 686                         return STATUS_SUCCESS;
 687         }
 688
 689         TRACE_RET(chip, STATUS_FAIL);
 690 }
 691
 692 static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage)
 693 {
 694         int retval;
 695
 696         if (voltage == SD_IO_3V3) {
 697                 if (chip->asic_code) {
 698                         retval = rtsx_write_phy_register(chip, 0x08,
 699                                                         0x4FC0 |
 700                                                         chip->phy_voltage);
 701                         if (retval != STATUS_SUCCESS)
 702                                 TRACE_RET(chip, STATUS_FAIL);
 703                 } else {
 704                         RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, 0);
 705                 }
 706         } else if (voltage == SD_IO_1V8) {
 707                 if (chip->asic_code) {
 708                         retval = rtsx_write_phy_register(chip, 0x08,
 709                                                         0x4C40 |
 710                                                         chip->phy_voltage);
 711                         if (retval != STATUS_SUCCESS)
 712                                 TRACE_RET(chip, STATUS_FAIL);
 713                 } else {
 714                         RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8,
 715                                 SD_IO_USING_1V8);
 716                 }
 717         } else {
 718                 TRACE_RET(chip, STATUS_FAIL);
 719         }
 720
 721         return STATUS_SUCCESS;
 722 }
 723
 724 static int sd_voltage_switch(struct rtsx_chip *chip)
 725 {
 726         int retval;
 727         u8 stat;
 728
 729         RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
 730                 SD_CLK_TOGGLE_EN);
 731
 732         retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1,
 733                                 NULL, 0);
 734         if (retval != STATUS_SUCCESS)
 735                 TRACE_RET(chip, STATUS_FAIL);
 736
 737         udelay(chip->sd_voltage_switch_delay);
 738
 739         RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
 740         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 741                                 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
 742                 TRACE_RET(chip, STATUS_FAIL);
 743         }
 744
 745         RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_FORCE_STOP);
 746         retval = sd_change_bank_voltage(chip, SD_IO_1V8);
 747         if (retval != STATUS_SUCCESS)
 748                 TRACE_RET(chip, STATUS_FAIL);
 749
 750         wait_timeout(50);
 751
 752         RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
 753         wait_timeout(10);
 754
 755         RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
 756         if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 757                                 SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
 758                         (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 759                                 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
 760                 dev_dbg(rtsx_dev(chip), "SD_BUS_STAT: 0x%x\n", stat);
 761                 rtsx_write_register(chip, SD_BUS_STAT,
 762                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 763                 rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0);
 764                 TRACE_RET(chip, STATUS_FAIL);
 765         }
 766
 767         RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
 768                 0);
 769
 770         return STATUS_SUCCESS;
 771 }
 772
 773 static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir)
 774 {
 775         if (tune_dir == TUNE_RX) {
 776                 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_RX);
 777                 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RX);
 778         } else {
 779                 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_TX);
 780                 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_TX);
 781         }
 782
 783         return STATUS_SUCCESS;
 784 }
 785
 786 static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
 787 {
 788         struct sd_info *sd_card = &(chip->sd_card);
 789         u16 SD_VP_CTL, SD_DCMPS_CTL;
 790         u8 val;
 791         int retval;
 792         int ddr_rx = 0;
 793
 794         dev_dbg(rtsx_dev(chip), "sd_change_phase (sample_point = %d, tune_dir = %d)\n",
 795                 sample_point, tune_dir);
 796
 797         if (tune_dir == TUNE_RX) {
 798                 SD_VP_CTL = SD_VPRX_CTL;
 799                 SD_DCMPS_CTL = SD_DCMPS_RX_CTL;
 800                 if (CHK_SD_DDR50(sd_card))
 801                         ddr_rx = 1;
 802         } else {
 803                 SD_VP_CTL = SD_VPTX_CTL;
 804                 SD_DCMPS_CTL = SD_DCMPS_TX_CTL;
 805         }
 806
 807         if (chip->asic_code) {
 808                 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 809                 RTSX_WRITE_REG(chip, SD_VP_CTL, 0x1F, sample_point);
 810                 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
 811                 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET,
 812                         PHASE_NOT_RESET);
 813                 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
 814         } else {
 815 #ifdef CONFIG_RTS5208_DEBUG
 816                 rtsx_read_register(chip, SD_VP_CTL, &val);
 817                 dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
 818                 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
 819                 dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
 820 #endif
 821
 822                 if (ddr_rx) {
 823                         RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE,
 824                                 PHASE_CHANGE);
 825                         udelay(50);
 826                         RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
 827                                 PHASE_CHANGE | PHASE_NOT_RESET | sample_point);
 828                 } else {
 829                         RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 830                         udelay(50);
 831                         RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
 832                                         PHASE_NOT_RESET | sample_point);
 833                 }
 834                 udelay(100);
 835
 836                 rtsx_init_cmd(chip);
 837                 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE,
 838                         DCMPS_CHANGE);
 839                 rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL,
 840                         DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
 841                 retval = rtsx_send_cmd(chip, SD_CARD, 100);
 842                 if (retval != STATUS_SUCCESS)
 843                         TRACE_GOTO(chip, Fail);
 844
 845                 val = *rtsx_get_cmd_data(chip);
 846                 if (val & DCMPS_ERROR)
 847                         TRACE_GOTO(chip, Fail);
 848
 849                 if ((val & DCMPS_CURRENT_PHASE) != sample_point)
 850                         TRACE_GOTO(chip, Fail);
 851
 852                 RTSX_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
 853                 if (ddr_rx)
 854                         RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, 0);
 855                 else
 856                         RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
 857
 858                 udelay(50);
 859         }
 860
 861         RTSX_WRITE_REG(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
 862
 863         return STATUS_SUCCESS;
 864
 865 Fail:
 866 #ifdef CONFIG_RTS5208_DEBUG
 867         rtsx_read_register(chip, SD_VP_CTL, &val);
 868         dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
 869         rtsx_read_register(chip, SD_DCMPS_CTL, &val);
 870         dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
 871 #endif
 872         rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
 873         rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0);
 874         wait_timeout(10);
 875         sd_reset_dcm(chip, tune_dir);
 876         return STATUS_FAIL;
 877 }
 878
 879 static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width)
 880 {
 881         struct sd_info *sd_card = &(chip->sd_card);
 882         int retval;
 883         u8 cmd[5], buf[8];
 884
 885         retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
 886                                 SD_RSP_TYPE_R1, NULL, 0);
 887         if (retval != STATUS_SUCCESS)
 888                 TRACE_RET(chip, STATUS_FAIL);
 889
 890         cmd[0] = 0x40 | SEND_SCR;
 891         cmd[1] = 0;
 892         cmd[2] = 0;
 893         cmd[3] = 0;
 894         cmd[4] = 0;
 895
 896         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width,
 897                         buf, 8, 250);
 898         if (retval != STATUS_SUCCESS) {
 899                 rtsx_clear_sd_error(chip);
 900                 TRACE_RET(chip, STATUS_FAIL);
 901         }
 902
 903         memcpy(sd_card->raw_scr, buf, 8);
 904
 905         if ((buf[0] & 0x0F) == 0)
 906                 TRACE_RET(chip, STATUS_FAIL);
 907
 908         return STATUS_SUCCESS;
 909 }
 910
 911 static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group,
 912                                 u8 func_to_switch, u8 *buf, int buf_len)
 913 {
 914         u8 support_mask = 0, query_switch = 0, switch_busy = 0;
 915         int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
 916
 917         if (func_group == SD_FUNC_GROUP_1) {
 918                 support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
 919                 query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
 920                 check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
 921
 922                 switch (func_to_switch) {
 923                 case HS_SUPPORT:
 924                         support_mask = HS_SUPPORT_MASK;
 925                         query_switch = HS_QUERY_SWITCH_OK;
 926                         switch_busy = HS_SWITCH_BUSY;
 927                         break;
 928
 929                 case SDR50_SUPPORT:
 930                         support_mask = SDR50_SUPPORT_MASK;
 931                         query_switch = SDR50_QUERY_SWITCH_OK;
 932                         switch_busy = SDR50_SWITCH_BUSY;
 933                         break;
 934
 935                 case SDR104_SUPPORT:
 936                         support_mask = SDR104_SUPPORT_MASK;
 937                         query_switch = SDR104_QUERY_SWITCH_OK;
 938                         switch_busy = SDR104_SWITCH_BUSY;
 939                         break;
 940
 941                 case DDR50_SUPPORT:
 942                         support_mask = DDR50_SUPPORT_MASK;
 943                         query_switch = DDR50_QUERY_SWITCH_OK;
 944                         switch_busy = DDR50_SWITCH_BUSY;
 945                         break;
 946
 947                 default:
 948                         TRACE_RET(chip, STATUS_FAIL);
 949                 }
 950         } else if (func_group == SD_FUNC_GROUP_3) {
 951                 support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
 952                 query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
 953                 check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
 954
 955                 switch (func_to_switch) {
 956                 case DRIVING_TYPE_A:
 957                         support_mask = DRIVING_TYPE_A_MASK;
 958                         query_switch = TYPE_A_QUERY_SWITCH_OK;
 959                         switch_busy = TYPE_A_SWITCH_BUSY;
 960                         break;
 961
 962                 case DRIVING_TYPE_C:
 963                         support_mask = DRIVING_TYPE_C_MASK;
 964                         query_switch = TYPE_C_QUERY_SWITCH_OK;
 965                         switch_busy = TYPE_C_SWITCH_BUSY;
 966                         break;
 967
 968                 case DRIVING_TYPE_D:
 969                         support_mask = DRIVING_TYPE_D_MASK;
 970                         query_switch = TYPE_D_QUERY_SWITCH_OK;
 971                         switch_busy = TYPE_D_SWITCH_BUSY;
 972                         break;
 973
 974                 default:
 975                         TRACE_RET(chip, STATUS_FAIL);
 976                 }
 977         } else if (func_group == SD_FUNC_GROUP_4) {
 978                 support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
 979                 query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
 980                 check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
 981
 982                 switch (func_to_switch) {
 983                 case CURRENT_LIMIT_400:
 984                         support_mask = CURRENT_LIMIT_400_MASK;
 985                         query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
 986                         switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
 987                         break;
 988
 989                 case CURRENT_LIMIT_600:
 990                         support_mask = CURRENT_LIMIT_600_MASK;
 991                         query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
 992                         switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
 993                         break;
 994
 995                 case CURRENT_LIMIT_800:
 996                         support_mask = CURRENT_LIMIT_800_MASK;
 997                         query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
 998                         switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
 999                         break;
1000
1001                 default:
1002                         TRACE_RET(chip, STATUS_FAIL);
1003                 }
1004         } else {
1005                 TRACE_RET(chip, STATUS_FAIL);
1006         }
1007
1008         if (func_group == SD_FUNC_GROUP_1) {
1009                 if (!(buf[support_offset] & support_mask) ||
1010                         ((buf[query_switch_offset] & 0x0F) != query_switch)) {
1011                         TRACE_RET(chip, STATUS_FAIL);
1012                 }
1013         }
1014
1015         /* Check 'Busy Status' */
1016         if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) &&
1017                     ((buf[check_busy_offset] & switch_busy) == switch_busy)) {
1018                 TRACE_RET(chip, STATUS_FAIL);
1019         }
1020
1021         return STATUS_SUCCESS;
1022 }
1023
1024 static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode,
1025                 u8 func_group, u8 func_to_switch, u8 bus_width)
1026 {
1027         struct sd_info *sd_card = &(chip->sd_card);
1028         int retval;
1029         u8 cmd[5], buf[64];
1030
1031         dev_dbg(rtsx_dev(chip), "sd_check_switch_mode (mode = %d, func_group = %d, func_to_switch = %d)\n",
1032                 mode, func_group, func_to_switch);
1033
1034         cmd[0] = 0x40 | SWITCH;
1035         cmd[1] = mode;
1036
1037         if (func_group == SD_FUNC_GROUP_1) {
1038                 cmd[2] = 0xFF;
1039                 cmd[3] = 0xFF;
1040                 cmd[4] = 0xF0 + func_to_switch;
1041         } else if (func_group == SD_FUNC_GROUP_3) {
1042                 cmd[2] = 0xFF;
1043                 cmd[3] = 0xF0 + func_to_switch;
1044                 cmd[4] = 0xFF;
1045         } else if (func_group == SD_FUNC_GROUP_4) {
1046                 cmd[2] = 0xFF;
1047                 cmd[3] = 0x0F + (func_to_switch << 4);
1048                 cmd[4] = 0xFF;
1049         } else {
1050                 cmd[1] = SD_CHECK_MODE;
1051                 cmd[2] = 0xFF;
1052                 cmd[3] = 0xFF;
1053                 cmd[4] = 0xFF;
1054         }
1055
1056         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width,
1057                         buf, 64, 250);
1058         if (retval != STATUS_SUCCESS) {
1059                 rtsx_clear_sd_error(chip);
1060                 TRACE_RET(chip, STATUS_FAIL);
1061         }
1062
1063         RTSX_DUMP(buf, 64);
1064
1065         if (func_group == NO_ARGUMENT) {
1066                 sd_card->func_group1_mask = buf[0x0D];
1067                 sd_card->func_group2_mask = buf[0x0B];
1068                 sd_card->func_group3_mask = buf[0x09];
1069                 sd_card->func_group4_mask = buf[0x07];
1070
1071                 dev_dbg(rtsx_dev(chip), "func_group1_mask = 0x%02x\n",
1072                         buf[0x0D]);
1073                 dev_dbg(rtsx_dev(chip), "func_group2_mask = 0x%02x\n",
1074                         buf[0x0B]);
1075                 dev_dbg(rtsx_dev(chip), "func_group3_mask = 0x%02x\n",
1076                         buf[0x09]);
1077                 dev_dbg(rtsx_dev(chip), "func_group4_mask = 0x%02x\n",
1078                         buf[0x07]);
1079         } else {
1080                 /* Maximum current consumption, check whether current is
1081                  * acceptable; bit[511:496] = 0x0000 means some error happened.
1082                  */
1083                 u16 cc = ((u16)buf[0] << 8) | buf[1];
1084                 dev_dbg(rtsx_dev(chip), "Maximum current consumption: %dmA\n",
1085                         cc);
1086                 if ((cc == 0) || (cc > 800))
1087                         TRACE_RET(chip, STATUS_FAIL);
1088
1089                 retval = sd_query_switch_result(chip, func_group,
1090                                                 func_to_switch, buf, 64);
1091                 if (retval != STATUS_SUCCESS)
1092                         TRACE_RET(chip, STATUS_FAIL);
1093
1094                 if ((cc > 400) || (func_to_switch > CURRENT_LIMIT_400)) {
1095                         RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK,
1096                                 chip->sd_800mA_ocp_thd);
1097                         RTSX_WRITE_REG(chip, CARD_PWR_CTL, PMOS_STRG_MASK,
1098                                 PMOS_STRG_800mA);
1099                 }
1100         }
1101
1102         return STATUS_SUCCESS;
1103 }
1104
1105 static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch)
1106 {
1107         if (func_group == SD_FUNC_GROUP_1) {
1108                 if (func_to_switch > HS_SUPPORT)
1109                         func_to_switch--;
1110
1111         } else if (func_group == SD_FUNC_GROUP_4) {
1112                 if (func_to_switch > CURRENT_LIMIT_200)
1113                         func_to_switch--;
1114         }
1115
1116         return func_to_switch;
1117 }
1118
1119 static int sd_check_switch(struct rtsx_chip *chip,
1120                 u8 func_group, u8 func_to_switch, u8 bus_width)
1121 {
1122         int retval;
1123         int i;
1124         int switch_good = 0;
1125
1126         for (i = 0; i < 3; i++) {
1127                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1128                         sd_set_err_code(chip, SD_NO_CARD);
1129                         TRACE_RET(chip, STATUS_FAIL);
1130                 }
1131
1132                 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group,
1133                                 func_to_switch, bus_width);
1134                 if (retval == STATUS_SUCCESS) {
1135                         u8 stat;
1136
1137                         retval = sd_check_switch_mode(chip, SD_SWITCH_MODE,
1138                                         func_group, func_to_switch, bus_width);
1139                         if (retval == STATUS_SUCCESS) {
1140                                 switch_good = 1;
1141                                 break;
1142                         }
1143
1144                         RTSX_READ_REG(chip, SD_STAT1, &stat);
1145                         if (stat & SD_CRC16_ERR) {
1146                                 dev_dbg(rtsx_dev(chip), "SD CRC16 error when switching mode\n");
1147                                 TRACE_RET(chip, STATUS_FAIL);
1148                         }
1149                 }
1150
1151                 func_to_switch = downgrade_switch_mode(func_group,
1152                                                 func_to_switch);
1153
1154                 wait_timeout(20);
1155         }
1156
1157         if (!switch_good)
1158                 TRACE_RET(chip, STATUS_FAIL);
1159
1160         return STATUS_SUCCESS;
1161 }
1162
1163 static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width)
1164 {
1165         struct sd_info *sd_card = &(chip->sd_card);
1166         int retval;
1167         int i;
1168         u8 func_to_switch = 0;
1169
1170         /* Get supported functions */
1171         retval = sd_check_switch_mode(chip, SD_CHECK_MODE,
1172                         NO_ARGUMENT, NO_ARGUMENT, bus_width);
1173         if (retval != STATUS_SUCCESS)
1174                 TRACE_RET(chip, STATUS_FAIL);
1175
1176         sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail);
1177
1178         /* Function Group 1: Access Mode */
1179         for (i = 0; i < 4; i++) {
1180                 switch ((u8)(chip->sd_speed_prior >> (i*8))) {
1181                 case SDR104_SUPPORT:
1182                         if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK)
1183                                         && chip->sdr104_en) {
1184                                 func_to_switch = SDR104_SUPPORT;
1185                         }
1186                         break;
1187
1188                 case DDR50_SUPPORT:
1189                         if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK)
1190                                         && chip->ddr50_en) {
1191                                 func_to_switch = DDR50_SUPPORT;
1192                         }
1193                         break;
1194
1195                 case SDR50_SUPPORT:
1196                         if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK)
1197                                         && chip->sdr50_en) {
1198                                 func_to_switch = SDR50_SUPPORT;
1199                         }
1200                         break;
1201
1202                 case HS_SUPPORT:
1203                         if (sd_card->func_group1_mask & HS_SUPPORT_MASK)
1204                                 func_to_switch = HS_SUPPORT;
1205
1206                         break;
1207
1208                 default:
1209                         continue;
1210                 }
1211
1212
1213                 if (func_to_switch)
1214                         break;
1215
1216         }
1217         dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_1: func_to_switch = 0x%02x",
1218                 func_to_switch);
1219
1220 #ifdef SUPPORT_SD_LOCK
1221         if ((sd_card->sd_lock_status & SD_SDR_RST)
1222                         && (DDR50_SUPPORT == func_to_switch)
1223                         && (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) {
1224                 func_to_switch = SDR50_SUPPORT;
1225                 dev_dbg(rtsx_dev(chip), "Using SDR50 instead of DDR50 for SD Lock\n");
1226         }
1227 #endif
1228
1229         if (func_to_switch) {
1230                 retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch,
1231                                         bus_width);
1232                 if (retval != STATUS_SUCCESS) {
1233                         if (func_to_switch == SDR104_SUPPORT) {
1234                                 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK;
1235                         } else if (func_to_switch == DDR50_SUPPORT) {
1236                                 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
1237                                         DDR50_SUPPORT_MASK;
1238                         } else if (func_to_switch == SDR50_SUPPORT) {
1239                                 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
1240                                         DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
1241                         }
1242                         TRACE_RET(chip, STATUS_FAIL);
1243                 }
1244
1245                 if (func_to_switch == SDR104_SUPPORT)
1246                         SET_SD_SDR104(sd_card);
1247                 else if (func_to_switch == DDR50_SUPPORT)
1248                         SET_SD_DDR50(sd_card);
1249                 else if (func_to_switch == SDR50_SUPPORT)
1250                         SET_SD_SDR50(sd_card);
1251                 else
1252                         SET_SD_HS(sd_card);
1253         }
1254
1255         if (CHK_SD_DDR50(sd_card)) {
1256                 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0x04);
1257                 retval = sd_set_sample_push_timing(chip);
1258                 if (retval != STATUS_SUCCESS)
1259                         TRACE_RET(chip, STATUS_FAIL);
1260         }
1261
1262         if (!func_to_switch || (func_to_switch == HS_SUPPORT)) {
1263                 /* Do not try to switch current limit if the card doesn't
1264                  * support UHS mode or we don't want it to support UHS mode
1265                  */
1266                 return STATUS_SUCCESS;
1267         }
1268
1269         /* Function Group 4: Current Limit */
1270         func_to_switch = 0xFF;
1271
1272         for (i = 0; i < 4; i++) {
1273                 switch ((u8)(chip->sd_current_prior >> (i*8))) {
1274                 case CURRENT_LIMIT_800:
1275                         if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK)
1276                                 func_to_switch = CURRENT_LIMIT_800;
1277
1278                         break;
1279
1280                 case CURRENT_LIMIT_600:
1281                         if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK)
1282                                 func_to_switch = CURRENT_LIMIT_600;
1283
1284                         break;
1285
1286                 case CURRENT_LIMIT_400:
1287                         if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK)
1288                                 func_to_switch = CURRENT_LIMIT_400;
1289
1290                         break;
1291
1292                 case CURRENT_LIMIT_200:
1293                         if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK)
1294                                 func_to_switch = CURRENT_LIMIT_200;
1295
1296                         break;
1297
1298                 default:
1299                         continue;
1300                 }
1301
1302                 if (func_to_switch != 0xFF)
1303                         break;
1304         }
1305
1306         dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_4: func_to_switch = 0x%02x",
1307                 func_to_switch);
1308
1309         if (func_to_switch <= CURRENT_LIMIT_800) {
1310                 retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch,
1311                                         bus_width);
1312                 if (retval != STATUS_SUCCESS) {
1313                         if (sd_check_err_code(chip, SD_NO_CARD))
1314                                 TRACE_RET(chip, STATUS_FAIL);
1315                 }
1316                 dev_dbg(rtsx_dev(chip), "Switch current limit finished! (%d)\n",
1317                         retval);
1318         }
1319
1320         if (CHK_SD_DDR50(sd_card))
1321                 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0);
1322
1323         return STATUS_SUCCESS;
1324 }
1325
1326 static int sd_wait_data_idle(struct rtsx_chip *chip)
1327 {
1328         int retval = STATUS_TIMEDOUT;
1329         int i;
1330         u8 val = 0;
1331
1332         for (i = 0; i < 100; i++) {
1333                 RTSX_READ_REG(chip, SD_DATA_STATE, &val);
1334                 if (val & SD_DATA_IDLE) {
1335                         retval = STATUS_SUCCESS;
1336                         break;
1337                 }
1338                 udelay(100);
1339         }
1340         dev_dbg(rtsx_dev(chip), "SD_DATA_STATE: 0x%02x\n", val);
1341
1342         return retval;
1343 }
1344
1345 static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1346 {
1347         int retval;
1348         u8 cmd[5];
1349
1350         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1351         if (retval != STATUS_SUCCESS)
1352                 TRACE_RET(chip, STATUS_FAIL);
1353
1354         cmd[0] = 0x40 | SEND_TUNING_PATTERN;
1355         cmd[1] = 0;
1356         cmd[2] = 0;
1357         cmd[3] = 0;
1358         cmd[4] = 0;
1359
1360         retval = sd_read_data(chip, SD_TM_AUTO_TUNING,
1361                         cmd, 5, 0x40, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1362         if (retval != STATUS_SUCCESS) {
1363                 (void)sd_wait_data_idle(chip);
1364
1365                 rtsx_clear_sd_error(chip);
1366                 TRACE_RET(chip, STATUS_FAIL);
1367         }
1368
1369         return STATUS_SUCCESS;
1370 }
1371
1372 static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1373 {
1374         struct sd_info *sd_card = &(chip->sd_card);
1375         int retval;
1376         u8 cmd[5];
1377
1378         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1379         if (retval != STATUS_SUCCESS)
1380                 TRACE_RET(chip, STATUS_FAIL);
1381
1382         dev_dbg(rtsx_dev(chip), "sd ddr tuning rx\n");
1383
1384         retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
1385                                 SD_RSP_TYPE_R1, NULL, 0);
1386         if (retval != STATUS_SUCCESS)
1387                 TRACE_RET(chip, STATUS_FAIL);
1388
1389         cmd[0] = 0x40 | SD_STATUS;
1390         cmd[1] = 0;
1391         cmd[2] = 0;
1392         cmd[3] = 0;
1393         cmd[4] = 0;
1394
1395         retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1396                         cmd, 5, 64, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1397         if (retval != STATUS_SUCCESS) {
1398                 (void)sd_wait_data_idle(chip);
1399
1400                 rtsx_clear_sd_error(chip);
1401                 TRACE_RET(chip, STATUS_FAIL);
1402         }
1403
1404         return STATUS_SUCCESS;
1405 }
1406
1407 static int mmc_ddr_tunning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1408 {
1409         struct sd_info *sd_card = &(chip->sd_card);
1410         int retval;
1411         u8 cmd[5], bus_width;
1412
1413         if (CHK_MMC_8BIT(sd_card))
1414                 bus_width = SD_BUS_WIDTH_8;
1415         else if (CHK_MMC_4BIT(sd_card))
1416                 bus_width = SD_BUS_WIDTH_4;
1417         else
1418                 bus_width = SD_BUS_WIDTH_1;
1419
1420         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1421         if (retval != STATUS_SUCCESS)
1422                 TRACE_RET(chip, STATUS_FAIL);
1423
1424         dev_dbg(rtsx_dev(chip), "mmc ddr tuning rx\n");
1425
1426         cmd[0] = 0x40 | SEND_EXT_CSD;
1427         cmd[1] = 0;
1428         cmd[2] = 0;
1429         cmd[3] = 0;
1430         cmd[4] = 0;
1431
1432         retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1433                         cmd, 5, 0x200, 1, bus_width, NULL, 0, 100);
1434         if (retval != STATUS_SUCCESS) {
1435                 (void)sd_wait_data_idle(chip);
1436
1437                 rtsx_clear_sd_error(chip);
1438                 TRACE_RET(chip, STATUS_FAIL);
1439         }
1440
1441         return STATUS_SUCCESS;
1442 }
1443
1444 static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1445 {
1446         struct sd_info *sd_card = &(chip->sd_card);
1447         int retval;
1448
1449         retval = sd_change_phase(chip, sample_point, TUNE_TX);
1450         if (retval != STATUS_SUCCESS)
1451                 TRACE_RET(chip, STATUS_FAIL);
1452
1453         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1454                 SD_RSP_80CLK_TIMEOUT_EN);
1455
1456         retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1457                 SD_RSP_TYPE_R1, NULL, 0);
1458         if (retval != STATUS_SUCCESS) {
1459                 if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1460                         rtsx_write_register(chip, SD_CFG3,
1461                                         SD_RSP_80CLK_TIMEOUT_EN, 0);
1462                         TRACE_RET(chip, STATUS_FAIL);
1463                 }
1464         }
1465
1466         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1467
1468         return STATUS_SUCCESS;
1469 }
1470
1471 static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1472 {
1473         struct sd_info *sd_card = &(chip->sd_card);
1474         int retval;
1475         u8 cmd[5], bus_width;
1476
1477         retval = sd_change_phase(chip, sample_point, TUNE_TX);
1478         if (retval != STATUS_SUCCESS)
1479                 TRACE_RET(chip, STATUS_FAIL);
1480
1481         if (CHK_SD(sd_card)) {
1482                 bus_width = SD_BUS_WIDTH_4;
1483         } else {
1484                 if (CHK_MMC_8BIT(sd_card))
1485                         bus_width = SD_BUS_WIDTH_8;
1486                 else if (CHK_MMC_4BIT(sd_card))
1487                         bus_width = SD_BUS_WIDTH_4;
1488                 else
1489                         bus_width = SD_BUS_WIDTH_1;
1490         }
1491
1492         retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
1493         if (retval != STATUS_SUCCESS)
1494                 TRACE_RET(chip, STATUS_FAIL);
1495
1496         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1497                 SD_RSP_80CLK_TIMEOUT_EN);
1498
1499         cmd[0] = 0x40 | PROGRAM_CSD;
1500         cmd[1] = 0;
1501         cmd[2] = 0;
1502         cmd[3] = 0;
1503         cmd[4] = 0;
1504
1505         retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2,
1506                         cmd, 5, 16, 1, bus_width, sd_card->raw_csd, 16, 100);
1507         if (retval != STATUS_SUCCESS) {
1508                 rtsx_clear_sd_error(chip);
1509                 rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1510                 TRACE_RET(chip, STATUS_FAIL);
1511         }
1512
1513         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1514
1515         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1,
1516                         NULL, 0);
1517
1518         return STATUS_SUCCESS;
1519 }
1520
1521 static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map,
1522                                 u8 tune_dir)
1523 {
1524         struct sd_info *sd_card = &(chip->sd_card);
1525         struct timing_phase_path path[MAX_PHASE + 1];
1526         int i, j, cont_path_cnt;
1527         int new_block, max_len, final_path_idx;
1528         u8 final_phase = 0xFF;
1529
1530         if (phase_map == 0xFFFFFFFF) {
1531                 if (tune_dir == TUNE_RX)
1532                         final_phase = (u8)chip->sd_default_rx_phase;
1533                 else
1534                         final_phase = (u8)chip->sd_default_tx_phase;
1535
1536                 goto Search_Finish;
1537         }
1538
1539         cont_path_cnt = 0;
1540         new_block = 1;
1541         j = 0;
1542         for (i = 0; i < MAX_PHASE + 1; i++) {
1543                 if (phase_map & (1 << i)) {
1544                         if (new_block) {
1545                                 new_block = 0;
1546                                 j = cont_path_cnt++;
1547                                 path[j].start = i;
1548                                 path[j].end = i;
1549                         } else {
1550                                 path[j].end = i;
1551                         }
1552                 } else {
1553                         new_block = 1;
1554                         if (cont_path_cnt) {
1555                                 int idx = cont_path_cnt - 1;
1556                                 path[idx].len = path[idx].end -
1557                                         path[idx].start + 1;
1558                                 path[idx].mid = path[idx].start +
1559                                         path[idx].len / 2;
1560                         }
1561                 }
1562         }
1563
1564         if (cont_path_cnt == 0) {
1565                 dev_dbg(rtsx_dev(chip), "No continuous phase path\n");
1566                 goto Search_Finish;
1567         } else {
1568                 int idx = cont_path_cnt - 1;
1569                 path[idx].len = path[idx].end - path[idx].start + 1;
1570                 path[idx].mid = path[idx].start + path[idx].len / 2;
1571         }
1572
1573         if ((path[0].start == 0) &&
1574                 (path[cont_path_cnt - 1].end == MAX_PHASE)) {
1575                 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1576                 path[0].len += path[cont_path_cnt - 1].len;
1577                 path[0].mid = path[0].start + path[0].len / 2;
1578                 if (path[0].mid < 0)
1579                         path[0].mid += MAX_PHASE + 1;
1580
1581                 cont_path_cnt--;
1582         }
1583
1584         max_len = 0;
1585         final_phase = 0;
1586         final_path_idx = 0;
1587         for (i = 0; i < cont_path_cnt; i++) {
1588                 if (path[i].len > max_len) {
1589                         max_len = path[i].len;
1590                         final_phase = (u8)path[i].mid;
1591                         final_path_idx = i;
1592                 }
1593
1594                 dev_dbg(rtsx_dev(chip), "path[%d].start = %d\n",
1595                         i, path[i].start);
1596                 dev_dbg(rtsx_dev(chip), "path[%d].end = %d\n", i, path[i].end);
1597                 dev_dbg(rtsx_dev(chip), "path[%d].len = %d\n", i, path[i].len);
1598                 dev_dbg(rtsx_dev(chip), "path[%d].mid = %d\n", i, path[i].mid);
1599                 dev_dbg(rtsx_dev(chip), "\n");
1600         }
1601
1602         if (tune_dir == TUNE_TX) {
1603                 if (CHK_SD_SDR104(sd_card)) {
1604                         if (max_len > 15) {
1605                                 int temp_mid = (max_len - 16) / 2;
1606                                 int temp_final_phase =
1607                                         path[final_path_idx].end -
1608                                         (max_len - (6 + temp_mid));
1609
1610                                 if (temp_final_phase < 0)
1611                                         final_phase = (u8)(temp_final_phase +
1612                                                         MAX_PHASE + 1);
1613                                 else
1614                                         final_phase = (u8)temp_final_phase;
1615                         }
1616                 } else if (CHK_SD_SDR50(sd_card)) {
1617                         if (max_len > 12) {
1618                                 int temp_mid = (max_len - 13) / 2;
1619                                 int temp_final_phase =
1620                                         path[final_path_idx].end -
1621                                         (max_len - (3 + temp_mid));
1622
1623                                 if (temp_final_phase < 0)
1624                                         final_phase = (u8)(temp_final_phase +
1625                                                         MAX_PHASE + 1);
1626                                 else
1627                                         final_phase = (u8)temp_final_phase;
1628                         }
1629                 }
1630         }
1631
1632 Search_Finish:
1633         dev_dbg(rtsx_dev(chip), "Final chosen phase: %d\n", final_phase);
1634         return final_phase;
1635 }
1636
1637 static int sd_tuning_rx(struct rtsx_chip *chip)
1638 {
1639         struct sd_info *sd_card = &(chip->sd_card);
1640         int retval;
1641         int i, j;
1642         u32 raw_phase_map[3], phase_map;
1643         u8 final_phase;
1644         int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1645
1646         if (CHK_SD(sd_card)) {
1647                 if (CHK_SD_DDR50(sd_card))
1648                         tuning_cmd = sd_ddr_tuning_rx_cmd;
1649                 else
1650                         tuning_cmd = sd_sdr_tuning_rx_cmd;
1651
1652         } else {
1653                 if (CHK_MMC_DDR52(sd_card))
1654                         tuning_cmd = mmc_ddr_tunning_rx_cmd;
1655                 else
1656                         TRACE_RET(chip, STATUS_FAIL);
1657         }
1658
1659         for (i = 0; i < 3; i++) {
1660                 raw_phase_map[i] = 0;
1661                 for (j = MAX_PHASE; j >= 0; j--) {
1662                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1663                                 sd_set_err_code(chip, SD_NO_CARD);
1664                                 TRACE_RET(chip, STATUS_FAIL);
1665                         }
1666
1667                         retval = tuning_cmd(chip, (u8)j);
1668                         if (retval == STATUS_SUCCESS)
1669                                 raw_phase_map[i] |= 1 << j;
1670                 }
1671         }
1672
1673         phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1674         for (i = 0; i < 3; i++)
1675                 dev_dbg(rtsx_dev(chip), "RX raw_phase_map[%d] = 0x%08x\n",
1676                         i, raw_phase_map[i]);
1677
1678         dev_dbg(rtsx_dev(chip), "RX phase_map = 0x%08x\n", phase_map);
1679
1680         final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX);
1681         if (final_phase == 0xFF)
1682                 TRACE_RET(chip, STATUS_FAIL);
1683
1684         retval = sd_change_phase(chip, final_phase, TUNE_RX);
1685         if (retval != STATUS_SUCCESS)
1686                 TRACE_RET(chip, STATUS_FAIL);
1687
1688         return STATUS_SUCCESS;
1689 }
1690
1691 static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip)
1692 {
1693         struct sd_info *sd_card = &(chip->sd_card);
1694         int retval;
1695         int i;
1696         u32 phase_map;
1697         u8 final_phase;
1698
1699         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1700                 SD_RSP_80CLK_TIMEOUT_EN);
1701
1702         phase_map = 0;
1703         for (i = MAX_PHASE; i >= 0; i--) {
1704                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1705                         sd_set_err_code(chip, SD_NO_CARD);
1706                         rtsx_write_register(chip, SD_CFG3,
1707                                                 SD_RSP_80CLK_TIMEOUT_EN, 0);
1708                         TRACE_RET(chip, STATUS_FAIL);
1709                 }
1710
1711                 retval = sd_change_phase(chip, (u8)i, TUNE_TX);
1712                 if (retval != STATUS_SUCCESS)
1713                         continue;
1714
1715                 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
1716                                         sd_card->sd_addr, SD_RSP_TYPE_R1, NULL,
1717                                         0);
1718                 if ((retval == STATUS_SUCCESS) ||
1719                         !sd_check_err_code(chip, SD_RSP_TIMEOUT))
1720                         phase_map |= 1 << i;
1721         }
1722
1723         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1724
1725         dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase_map = 0x%08x\n",
1726                 phase_map);
1727
1728         final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1729         if (final_phase == 0xFF)
1730                 TRACE_RET(chip, STATUS_FAIL);
1731
1732         retval = sd_change_phase(chip, final_phase, TUNE_TX);
1733         if (retval != STATUS_SUCCESS)
1734                 TRACE_RET(chip, STATUS_FAIL);
1735
1736         dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase: %d\n",
1737                 (int)final_phase);
1738
1739         return STATUS_SUCCESS;
1740 }
1741
1742 static int sd_tuning_tx(struct rtsx_chip *chip)
1743 {
1744         struct sd_info *sd_card = &(chip->sd_card);
1745         int retval;
1746         int i, j;
1747         u32 raw_phase_map[3], phase_map;
1748         u8 final_phase;
1749         int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1750
1751         if (CHK_SD(sd_card)) {
1752                 if (CHK_SD_DDR50(sd_card))
1753                         tuning_cmd = sd_ddr_tuning_tx_cmd;
1754                 else
1755                         tuning_cmd = sd_sdr_tuning_tx_cmd;
1756
1757         } else {
1758                 if (CHK_MMC_DDR52(sd_card))
1759                         tuning_cmd = sd_ddr_tuning_tx_cmd;
1760                 else
1761                         TRACE_RET(chip, STATUS_FAIL);
1762         }
1763
1764         for (i = 0; i < 3; i++) {
1765                 raw_phase_map[i] = 0;
1766                 for (j = MAX_PHASE; j >= 0; j--) {
1767                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1768                                 sd_set_err_code(chip, SD_NO_CARD);
1769                                 rtsx_write_register(chip, SD_CFG3,
1770                                                     SD_RSP_80CLK_TIMEOUT_EN, 0);
1771                                 TRACE_RET(chip, STATUS_FAIL);
1772                         }
1773
1774                         retval = tuning_cmd(chip, (u8)j);
1775                         if (retval == STATUS_SUCCESS)
1776                                 raw_phase_map[i] |= 1 << j;
1777                 }
1778         }
1779
1780         phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1781         for (i = 0; i < 3; i++)
1782                 dev_dbg(rtsx_dev(chip), "TX raw_phase_map[%d] = 0x%08x\n",
1783                         i, raw_phase_map[i]);
1784
1785         dev_dbg(rtsx_dev(chip), "TX phase_map = 0x%08x\n", phase_map);
1786
1787         final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1788         if (final_phase == 0xFF)
1789                 TRACE_RET(chip, STATUS_FAIL);
1790
1791         retval = sd_change_phase(chip, final_phase, TUNE_TX);
1792         if (retval != STATUS_SUCCESS)
1793                 TRACE_RET(chip, STATUS_FAIL);
1794
1795         return STATUS_SUCCESS;
1796 }
1797
1798 static int sd_sdr_tuning(struct rtsx_chip *chip)
1799 {
1800         int retval;
1801
1802         retval = sd_tuning_tx(chip);
1803         if (retval != STATUS_SUCCESS)
1804                 TRACE_RET(chip, STATUS_FAIL);
1805
1806         retval = sd_tuning_rx(chip);
1807         if (retval != STATUS_SUCCESS)
1808                 TRACE_RET(chip, STATUS_FAIL);
1809
1810         return STATUS_SUCCESS;
1811 }
1812
1813 static int sd_ddr_tuning(struct rtsx_chip *chip)
1814 {
1815         int retval;
1816
1817         if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1818                 retval = sd_ddr_pre_tuning_tx(chip);
1819                 if (retval != STATUS_SUCCESS)
1820                         TRACE_RET(chip, STATUS_FAIL);
1821         } else {
1822                 retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase,
1823                                         TUNE_TX);
1824                 if (retval != STATUS_SUCCESS)
1825                         TRACE_RET(chip, STATUS_FAIL);
1826         }
1827
1828         retval = sd_tuning_rx(chip);
1829         if (retval != STATUS_SUCCESS)
1830                 TRACE_RET(chip, STATUS_FAIL);
1831
1832         if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1833                 retval = sd_tuning_tx(chip);
1834                 if (retval != STATUS_SUCCESS)
1835                         TRACE_RET(chip, STATUS_FAIL);
1836         }
1837
1838         return STATUS_SUCCESS;
1839 }
1840
1841 static int mmc_ddr_tuning(struct rtsx_chip *chip)
1842 {
1843         int retval;
1844
1845         if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1846                 retval = sd_ddr_pre_tuning_tx(chip);
1847                 if (retval != STATUS_SUCCESS)
1848                         TRACE_RET(chip, STATUS_FAIL);
1849         } else {
1850                 retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase,
1851                                         TUNE_TX);
1852                 if (retval != STATUS_SUCCESS)
1853                         TRACE_RET(chip, STATUS_FAIL);
1854         }
1855
1856         retval = sd_tuning_rx(chip);
1857         if (retval != STATUS_SUCCESS)
1858                 TRACE_RET(chip, STATUS_FAIL);
1859
1860         if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1861                 retval = sd_tuning_tx(chip);
1862                 if (retval != STATUS_SUCCESS)
1863                         TRACE_RET(chip, STATUS_FAIL);
1864         }
1865
1866         return STATUS_SUCCESS;
1867 }
1868
1869 int sd_switch_clock(struct rtsx_chip *chip)
1870 {
1871         struct sd_info *sd_card = &(chip->sd_card);
1872         int retval;
1873         int re_tuning = 0;
1874
1875         retval = select_card(chip, SD_CARD);
1876         if (retval != STATUS_SUCCESS)
1877                 TRACE_RET(chip, STATUS_FAIL);
1878
1879         retval = switch_clock(chip, sd_card->sd_clock);
1880         if (retval != STATUS_SUCCESS)
1881                 TRACE_RET(chip, STATUS_FAIL);
1882
1883         if (re_tuning) {
1884                 if (CHK_SD(sd_card)) {
1885                         if (CHK_SD_DDR50(sd_card))
1886                                 retval = sd_ddr_tuning(chip);
1887                         else
1888                                 retval = sd_sdr_tuning(chip);
1889                 } else {
1890                         if (CHK_MMC_DDR52(sd_card))
1891                                 retval = mmc_ddr_tuning(chip);
1892                 }
1893
1894                 if (retval != STATUS_SUCCESS)
1895                         TRACE_RET(chip, STATUS_FAIL);
1896         }
1897
1898         return STATUS_SUCCESS;
1899 }
1900
1901 static int sd_prepare_reset(struct rtsx_chip *chip)
1902 {
1903         struct sd_info *sd_card = &(chip->sd_card);
1904         int retval;
1905
1906         if (chip->asic_code)
1907                 sd_card->sd_clock = 29;
1908         else
1909                 sd_card->sd_clock = CLK_30;
1910
1911         sd_card->sd_type = 0;
1912         sd_card->seq_mode = 0;
1913         sd_card->sd_data_buf_ready = 0;
1914         sd_card->capacity = 0;
1915
1916 #ifdef SUPPORT_SD_LOCK
1917         sd_card->sd_lock_status = 0;
1918         sd_card->sd_erase_status = 0;
1919 #endif
1920
1921         chip->capacity[chip->card2lun[SD_CARD]] = 0;
1922         chip->sd_io = 0;
1923
1924         retval = sd_set_init_para(chip);
1925         if (retval != STATUS_SUCCESS)
1926                 TRACE_RET(chip, retval);
1927
1928         RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF, 0x40);
1929
1930         RTSX_WRITE_REG(chip, CARD_STOP, SD_STOP | SD_CLR_ERR,
1931                 SD_STOP | SD_CLR_ERR);
1932
1933         retval = select_card(chip, SD_CARD);
1934         if (retval != STATUS_SUCCESS)
1935                 TRACE_RET(chip, STATUS_FAIL);
1936
1937         return STATUS_SUCCESS;
1938 }
1939
1940 static int sd_pull_ctl_disable(struct rtsx_chip *chip)
1941 {
1942         if (CHECK_PID(chip, 0x5208)) {
1943                 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
1944                         XD_D3_PD | SD_D7_PD | SD_CLK_PD | SD_D5_PD);
1945                 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
1946                         SD_D6_PD | SD_D0_PD | SD_D1_PD | XD_D5_PD);
1947                 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
1948                         SD_D4_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
1949                 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
1950                         XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
1951                 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
1952                         MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
1953                 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
1954         } else if (CHECK_PID(chip, 0x5288)) {
1955                 if (CHECK_BARO_PKG(chip, QFN)) {
1956                         RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
1957                         RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
1958                         RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
1959                         RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
1960                 }
1961         }
1962
1963         return STATUS_SUCCESS;
1964 }
1965
1966 int sd_pull_ctl_enable(struct rtsx_chip *chip)
1967 {
1968         int retval;
1969
1970         rtsx_init_cmd(chip);
1971
1972         if (CHECK_PID(chip, 0x5208)) {
1973                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
1974                         XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU);
1975                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
1976                         SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD);
1977                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
1978                         SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
1979                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
1980                         XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD);
1981                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
1982                         MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
1983                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
1984                         MS_D5_PD | MS_D4_PD);
1985         } else if (CHECK_PID(chip, 0x5288)) {
1986                 if (CHECK_BARO_PKG(chip, QFN)) {
1987                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
1988                                 0xA8);
1989                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
1990                                 0x5A);
1991                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
1992                                 0x95);
1993                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
1994                                 0xAA);
1995                 }
1996         }
1997
1998         retval = rtsx_send_cmd(chip, SD_CARD, 100);
1999         if (retval < 0)
2000                 TRACE_RET(chip, STATUS_FAIL);
2001
2002         return STATUS_SUCCESS;
2003 }
2004
2005 static int sd_init_power(struct rtsx_chip *chip)
2006 {
2007         int retval;
2008
2009         retval = sd_power_off_card3v3(chip);
2010         if (retval != STATUS_SUCCESS)
2011                 TRACE_RET(chip, STATUS_FAIL);
2012
2013         if (!chip->ft2_fast_mode)
2014                 wait_timeout(250);
2015
2016         retval = enable_card_clock(chip, SD_CARD);
2017         if (retval != STATUS_SUCCESS)
2018                 TRACE_RET(chip, STATUS_FAIL);
2019
2020         if (chip->asic_code) {
2021                 retval = sd_pull_ctl_enable(chip);
2022                 if (retval != STATUS_SUCCESS)
2023                         TRACE_RET(chip, STATUS_FAIL);
2024         } else {
2025                 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_SD_PULL_CTL_BIT | 0x20,
2026                         0);
2027         }
2028
2029         if (!chip->ft2_fast_mode) {
2030                 retval = card_power_on(chip, SD_CARD);
2031                 if (retval != STATUS_SUCCESS)
2032                         TRACE_RET(chip, STATUS_FAIL);
2033
2034                 wait_timeout(260);
2035
2036 #ifdef SUPPORT_OCP
2037                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
2038                         dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
2039                                 chip->ocp_stat);
2040                         TRACE_RET(chip, STATUS_FAIL);
2041                 }
2042 #endif
2043         }
2044
2045         RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
2046
2047         return STATUS_SUCCESS;
2048 }
2049
2050 static int sd_dummy_clock(struct rtsx_chip *chip)
2051 {
2052         RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0x01);
2053         wait_timeout(5);
2054         RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0);
2055
2056         return STATUS_SUCCESS;
2057 }
2058
2059 static int sd_read_lba0(struct rtsx_chip *chip)
2060 {
2061         struct sd_info *sd_card = &(chip->sd_card);
2062         int retval;
2063         u8 cmd[5], bus_width;
2064
2065         cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2066         cmd[1] = 0;
2067         cmd[2] = 0;
2068         cmd[3] = 0;
2069         cmd[4] = 0;
2070
2071         if (CHK_SD(sd_card)) {
2072                 bus_width = SD_BUS_WIDTH_4;
2073         } else {
2074                 if (CHK_MMC_8BIT(sd_card))
2075                         bus_width = SD_BUS_WIDTH_8;
2076                 else if (CHK_MMC_4BIT(sd_card))
2077                         bus_width = SD_BUS_WIDTH_4;
2078                 else
2079                         bus_width = SD_BUS_WIDTH_1;
2080         }
2081
2082         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd,
2083                 5, 512, 1, bus_width, NULL, 0, 100);
2084         if (retval != STATUS_SUCCESS) {
2085                 rtsx_clear_sd_error(chip);
2086                 TRACE_RET(chip, STATUS_FAIL);
2087         }
2088
2089         return STATUS_SUCCESS;
2090 }
2091
2092 static int sd_check_wp_state(struct rtsx_chip *chip)
2093 {
2094         struct sd_info *sd_card = &(chip->sd_card);
2095         int retval;
2096         u32 val;
2097         u16 sd_card_type;
2098         u8 cmd[5], buf[64];
2099
2100         retval = sd_send_cmd_get_rsp(chip, APP_CMD,
2101                         sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2102         if (retval != STATUS_SUCCESS)
2103                 TRACE_RET(chip, STATUS_FAIL);
2104
2105         cmd[0] = 0x40 | SD_STATUS;
2106         cmd[1] = 0;
2107         cmd[2] = 0;
2108         cmd[3] = 0;
2109         cmd[4] = 0;
2110
2111         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1,
2112                         SD_BUS_WIDTH_4, buf, 64, 250);
2113         if (retval != STATUS_SUCCESS) {
2114                 rtsx_clear_sd_error(chip);
2115
2116                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2117                                 SD_RSP_TYPE_R1, NULL, 0);
2118                 TRACE_RET(chip, STATUS_FAIL);
2119         }
2120
2121         dev_dbg(rtsx_dev(chip), "ACMD13:\n");
2122         RTSX_DUMP(buf, 64);
2123
2124         sd_card_type = ((u16)buf[2] << 8) | buf[3];
2125         dev_dbg(rtsx_dev(chip), "sd_card_type = 0x%04x\n", sd_card_type);
2126         if ((sd_card_type == 0x0001) || (sd_card_type == 0x0002)) {
2127                 /* ROM card or OTP */
2128                 chip->card_wp |= SD_CARD;
2129         }
2130
2131         /* Check SD Machanical Write-Protect Switch */
2132         val = rtsx_readl(chip, RTSX_BIPR);
2133         if (val & SD_WRITE_PROTECT)
2134                 chip->card_wp |= SD_CARD;
2135
2136         return STATUS_SUCCESS;
2137 }
2138
2139 static int reset_sd(struct rtsx_chip *chip)
2140 {
2141         struct sd_info *sd_card = &(chip->sd_card);
2142         int retval, i = 0, j = 0, k = 0, hi_cap_flow = 0;
2143         int sd_dont_switch = 0;
2144         int support_1v8 = 0;
2145         int try_sdio = 1;
2146         u8 rsp[16];
2147         u8 switch_bus_width;
2148         u32 voltage = 0;
2149         int sd20_mode = 0;
2150
2151         SET_SD(sd_card);
2152
2153 Switch_Fail:
2154
2155         i = 0;
2156         j = 0;
2157         k = 0;
2158         hi_cap_flow = 0;
2159
2160 #ifdef SUPPORT_SD_LOCK
2161         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2162                 goto SD_UNLOCK_ENTRY;
2163 #endif
2164
2165         retval = sd_prepare_reset(chip);
2166         if (retval != STATUS_SUCCESS)
2167                 TRACE_RET(chip, STATUS_FAIL);
2168
2169         retval = sd_dummy_clock(chip);
2170         if (retval != STATUS_SUCCESS)
2171                 TRACE_RET(chip, STATUS_FAIL);
2172
2173         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) {
2174                 int rty_cnt = 0;
2175
2176                 for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) {
2177                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2178                                 sd_set_err_code(chip, SD_NO_CARD);
2179                                 TRACE_RET(chip, STATUS_FAIL);
2180                         }
2181
2182                         retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0,
2183                                                 SD_RSP_TYPE_R4, rsp, 5);
2184                         if (retval == STATUS_SUCCESS) {
2185                                 int func_num = (rsp[1] >> 4) & 0x07;
2186                                 if (func_num) {
2187                                         dev_dbg(rtsx_dev(chip), "SD_IO card (Function number: %d)!\n",
2188                                                 func_num);
2189                                         chip->sd_io = 1;
2190                                         TRACE_RET(chip, STATUS_FAIL);
2191                                 }
2192
2193                                 break;
2194                         }
2195
2196                         sd_init_power(chip);
2197
2198                         sd_dummy_clock(chip);
2199                 }
2200
2201                 dev_dbg(rtsx_dev(chip), "Normal card!\n");
2202         }
2203
2204         /* Start Initialization Process of SD Card */
2205 RTY_SD_RST:
2206         retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
2207                                 NULL, 0);
2208         if (retval != STATUS_SUCCESS)
2209                 TRACE_RET(chip, STATUS_FAIL);
2210
2211         wait_timeout(20);
2212
2213         retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA,
2214                                 SD_RSP_TYPE_R7, rsp, 5);
2215         if (retval == STATUS_SUCCESS) {
2216                 if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) {
2217                         hi_cap_flow = 1;
2218                         voltage = SUPPORT_VOLTAGE | 0x40000000;
2219                 }
2220         }
2221
2222         if (!hi_cap_flow) {
2223                 voltage = SUPPORT_VOLTAGE;
2224
2225                 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0,
2226                                         SD_RSP_TYPE_R0, NULL, 0);
2227                 if (retval != STATUS_SUCCESS)
2228                         TRACE_RET(chip, STATUS_FAIL);
2229
2230                 wait_timeout(20);
2231         }
2232
2233         do {
2234                 retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1,
2235                                         NULL, 0);
2236                 if (retval != STATUS_SUCCESS) {
2237                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2238                                 sd_set_err_code(chip, SD_NO_CARD);
2239                                 TRACE_RET(chip, STATUS_FAIL);
2240                         }
2241
2242                         j++;
2243                         if (j < 3)
2244                                 goto RTY_SD_RST;
2245                         else
2246                                 TRACE_RET(chip, STATUS_FAIL);
2247                 }
2248
2249                 retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage,
2250                                         SD_RSP_TYPE_R3, rsp, 5);
2251                 if (retval != STATUS_SUCCESS) {
2252                         k++;
2253                         if (k < 3)
2254                                 goto RTY_SD_RST;
2255                         else
2256                                 TRACE_RET(chip, STATUS_FAIL);
2257                 }
2258
2259                 i++;
2260                 wait_timeout(20);
2261         } while (!(rsp[1] & 0x80) && (i < 255));
2262
2263         if (i == 255)
2264                 TRACE_RET(chip, STATUS_FAIL);
2265
2266         if (hi_cap_flow) {
2267                 if (rsp[1] & 0x40)
2268                         SET_SD_HCXC(sd_card);
2269                 else
2270                         CLR_SD_HCXC(sd_card);
2271
2272                 support_1v8 = 0;
2273         } else {
2274                 CLR_SD_HCXC(sd_card);
2275                 support_1v8 = 0;
2276         }
2277         dev_dbg(rtsx_dev(chip), "support_1v8 = %d\n", support_1v8);
2278
2279         if (support_1v8) {
2280                 retval = sd_voltage_switch(chip);
2281                 if (retval != STATUS_SUCCESS)
2282                         TRACE_RET(chip, STATUS_FAIL);
2283         }
2284
2285         retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2,
2286                                 NULL, 0);
2287         if (retval != STATUS_SUCCESS)
2288                 TRACE_RET(chip, STATUS_FAIL);
2289
2290         for (i = 0; i < 3; i++) {
2291                 retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0,
2292                                         SD_RSP_TYPE_R6, rsp, 5);
2293                 if (retval != STATUS_SUCCESS)
2294                         TRACE_RET(chip, STATUS_FAIL);
2295
2296                 sd_card->sd_addr = (u32)rsp[1] << 24;
2297                 sd_card->sd_addr += (u32)rsp[2] << 16;
2298
2299                 if (sd_card->sd_addr)
2300                         break;
2301         }
2302
2303         retval = sd_check_csd(chip, 1);
2304         if (retval != STATUS_SUCCESS)
2305                 TRACE_RET(chip, STATUS_FAIL);
2306
2307         retval = sd_select_card(chip, 1);
2308         if (retval != STATUS_SUCCESS)
2309                 TRACE_RET(chip, STATUS_FAIL);
2310
2311 #ifdef SUPPORT_SD_LOCK
2312 SD_UNLOCK_ENTRY:
2313         retval = sd_update_lock_status(chip);
2314         if (retval != STATUS_SUCCESS)
2315                 TRACE_RET(chip, STATUS_FAIL);
2316
2317         if (sd_card->sd_lock_status & SD_LOCKED) {
2318                 sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST);
2319                 return STATUS_SUCCESS;
2320         } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) {
2321                 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
2322         }
2323 #endif
2324
2325         retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2326                                 SD_RSP_TYPE_R1, NULL, 0);
2327         if (retval != STATUS_SUCCESS)
2328                 TRACE_RET(chip, STATUS_FAIL);
2329
2330         retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0,
2331                                 SD_RSP_TYPE_R1, NULL, 0);
2332         if (retval != STATUS_SUCCESS)
2333                 TRACE_RET(chip, STATUS_FAIL);
2334
2335         if (support_1v8) {
2336                 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2337                                         SD_RSP_TYPE_R1, NULL, 0);
2338                 if (retval != STATUS_SUCCESS)
2339                         TRACE_RET(chip, STATUS_FAIL);
2340
2341                 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,
2342                                         SD_RSP_TYPE_R1, NULL, 0);
2343                 if (retval != STATUS_SUCCESS)
2344                         TRACE_RET(chip, STATUS_FAIL);
2345
2346                 switch_bus_width = SD_BUS_WIDTH_4;
2347         } else {
2348                 switch_bus_width = SD_BUS_WIDTH_1;
2349         }
2350
2351         retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1,
2352                                 NULL, 0);
2353         if (retval != STATUS_SUCCESS)
2354                 TRACE_RET(chip, STATUS_FAIL);
2355
2356         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2357         if (retval != STATUS_SUCCESS)
2358                 TRACE_RET(chip, STATUS_FAIL);
2359
2360         if (!(sd_card->raw_csd[4] & 0x40))
2361                 sd_dont_switch = 1;
2362
2363         if (!sd_dont_switch) {
2364                 if (sd20_mode) {
2365                         /* Set sd_switch_fail here, because we needn't
2366                          * switch to UHS mode
2367                          */
2368                         sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
2369                                 DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
2370                 }
2371
2372                 /* Check the card whether follow SD1.1 spec or higher */
2373                 retval = sd_check_spec(chip, switch_bus_width);
2374                 if (retval == STATUS_SUCCESS) {
2375                         retval = sd_switch_function(chip, switch_bus_width);
2376                         if (retval != STATUS_SUCCESS) {
2377                                 sd_init_power(chip);
2378                                 sd_dont_switch = 1;
2379                                 try_sdio = 0;
2380
2381                                 goto Switch_Fail;
2382                         }
2383                 } else {
2384                         if (support_1v8) {
2385                                 sd_init_power(chip);
2386                                 sd_dont_switch = 1;
2387                                 try_sdio = 0;
2388
2389                                 goto Switch_Fail;
2390                         }
2391                 }
2392         }
2393
2394         if (!support_1v8) {
2395                 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2396                                         SD_RSP_TYPE_R1, NULL, 0);
2397                 if (retval != STATUS_SUCCESS)
2398                         TRACE_RET(chip, STATUS_FAIL);
2399
2400                 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,
2401                                         SD_RSP_TYPE_R1, NULL, 0);
2402                 if (retval != STATUS_SUCCESS)
2403                         TRACE_RET(chip, STATUS_FAIL);
2404         }
2405
2406 #ifdef SUPPORT_SD_LOCK
2407         sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2408 #endif
2409
2410         if (!sd20_mode && CHK_SD30_SPEED(sd_card)) {
2411                 int read_lba0 = 1;
2412
2413                 RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07,
2414                         chip->sd30_drive_sel_1v8);
2415
2416                 retval = sd_set_init_para(chip);
2417                 if (retval != STATUS_SUCCESS)
2418                         TRACE_RET(chip, STATUS_FAIL);
2419
2420                 if (CHK_SD_DDR50(sd_card))
2421                         retval = sd_ddr_tuning(chip);
2422                 else
2423                         retval = sd_sdr_tuning(chip);
2424
2425                 if (retval != STATUS_SUCCESS) {
2426                         if (sd20_mode) {
2427                                 TRACE_RET(chip, STATUS_FAIL);
2428                         } else {
2429                                 retval = sd_init_power(chip);
2430                                 if (retval != STATUS_SUCCESS)
2431                                         TRACE_RET(chip, STATUS_FAIL);
2432
2433                                 try_sdio = 0;
2434                                 sd20_mode = 1;
2435                                 goto Switch_Fail;
2436                         }
2437                 }
2438
2439                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2440                                 SD_RSP_TYPE_R1, NULL, 0);
2441
2442                 if (CHK_SD_DDR50(sd_card)) {
2443                         retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
2444                         if (retval != STATUS_SUCCESS)
2445                                 read_lba0 = 0;
2446                 }
2447
2448                 if (read_lba0) {
2449                         retval = sd_read_lba0(chip);
2450                         if (retval != STATUS_SUCCESS) {
2451                                 if (sd20_mode) {
2452                                         TRACE_RET(chip, STATUS_FAIL);
2453                                 } else {
2454                                         retval = sd_init_power(chip);
2455                                         if (retval != STATUS_SUCCESS)
2456                                                 TRACE_RET(chip, STATUS_FAIL);
2457
2458                                         try_sdio = 0;
2459                                         sd20_mode = 1;
2460                                         goto Switch_Fail;
2461                                 }
2462                         }
2463                 }
2464         }
2465
2466         retval = sd_check_wp_state(chip);
2467         if (retval != STATUS_SUCCESS)
2468                 TRACE_RET(chip, STATUS_FAIL);
2469
2470         chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2471
2472 #ifdef SUPPORT_SD_LOCK
2473         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2474                 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02);
2475                 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00);
2476         }
2477 #endif
2478
2479         return STATUS_SUCCESS;
2480 }
2481
2482
2483 static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width)
2484 {
2485         struct sd_info *sd_card = &(chip->sd_card);
2486         int retval;
2487         u8 buf[8] = {0}, bus_width, *ptr;
2488         u16 byte_cnt;
2489         int len;
2490
2491         retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL,
2492                                 0);
2493         if (retval != STATUS_SUCCESS)
2494                 TRACE_RET(chip, SWITCH_FAIL);
2495
2496         if (width == MMC_8BIT_BUS) {
2497                 buf[0] = 0x55;
2498                 buf[1] = 0xAA;
2499                 len = 8;
2500                 byte_cnt = 8;
2501                 bus_width = SD_BUS_WIDTH_8;
2502         } else {
2503                 buf[0] = 0x5A;
2504                 len = 4;
2505                 byte_cnt = 4;
2506                 bus_width = SD_BUS_WIDTH_4;
2507         }
2508
2509         retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0x02);
2510         if (retval != STATUS_SUCCESS)
2511                 TRACE_RET(chip, SWITCH_ERR);
2512
2513         retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3,
2514                         NULL, 0, byte_cnt, 1, bus_width, buf, len, 100);
2515         if (retval != STATUS_SUCCESS) {
2516                 rtsx_clear_sd_error(chip);
2517                 rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2518                 TRACE_RET(chip, SWITCH_ERR);
2519         }
2520
2521         retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2522         if (retval != STATUS_SUCCESS)
2523                 TRACE_RET(chip, SWITCH_ERR);
2524
2525         dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", BUSTEST_R);
2526
2527         rtsx_init_cmd(chip);
2528
2529         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R);
2530
2531         if (width == MMC_8BIT_BUS)
2532                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L,
2533                         0xFF, 0x08);
2534         else
2535                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L,
2536                         0xFF, 0x04);
2537
2538         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2539         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2540
2541         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2542                 SD_CALCULATE_CRC7 | SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END|
2543                 SD_CHECK_CRC7 | SD_RSP_LEN_6);
2544         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
2545                 PINGPONG_BUFFER);
2546         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
2547                 SD_TM_NORMAL_READ | SD_TRANSFER_START);
2548         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
2549                 SD_TRANSFER_END);
2550
2551         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0);
2552         if (width == MMC_8BIT_BUS)
2553                 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0);
2554
2555         retval = rtsx_send_cmd(chip, SD_CARD, 100);
2556         if (retval < 0) {
2557                 rtsx_clear_sd_error(chip);
2558                 TRACE_RET(chip, SWITCH_ERR);
2559         }
2560
2561         ptr = rtsx_get_cmd_data(chip) + 1;
2562
2563         if (width == MMC_8BIT_BUS) {
2564                 dev_dbg(rtsx_dev(chip), "BUSTEST_R [8bits]: 0x%02x 0x%02x\n",
2565                         ptr[0], ptr[1]);
2566                 if ((ptr[0] == 0xAA) && (ptr[1] == 0x55)) {
2567                         u8 rsp[5];
2568                         u32 arg;
2569
2570                         if (CHK_MMC_DDR52(sd_card))
2571                                 arg = 0x03B70600;
2572                         else
2573                                 arg = 0x03B70200;
2574
2575                         retval = sd_send_cmd_get_rsp(chip, SWITCH, arg,
2576                                                 SD_RSP_TYPE_R1b, rsp, 5);
2577                         if ((retval == STATUS_SUCCESS) &&
2578                                 !(rsp[4] & MMC_SWITCH_ERR))
2579                                 return SWITCH_SUCCESS;
2580                 }
2581         } else {
2582                 dev_dbg(rtsx_dev(chip), "BUSTEST_R [4bits]: 0x%02x\n", ptr[0]);
2583                 if (ptr[0] == 0xA5) {
2584                         u8 rsp[5];
2585                         u32 arg;
2586
2587                         if (CHK_MMC_DDR52(sd_card))
2588                                 arg = 0x03B70500;
2589                         else
2590                                 arg = 0x03B70100;
2591
2592                         retval = sd_send_cmd_get_rsp(chip, SWITCH, arg,
2593                                                 SD_RSP_TYPE_R1b, rsp, 5);
2594                         if ((retval == STATUS_SUCCESS) &&
2595                                 !(rsp[4] & MMC_SWITCH_ERR))
2596                                 return SWITCH_SUCCESS;
2597                 }
2598         }
2599
2600         TRACE_RET(chip, SWITCH_FAIL);
2601 }
2602
2603
2604 static int mmc_switch_timing_bus(struct rtsx_chip *chip, int switch_ddr)
2605 {
2606         struct sd_info *sd_card = &(chip->sd_card);
2607         int retval;
2608         u8 *ptr, card_type, card_type_mask = 0;
2609
2610         CLR_MMC_HS(sd_card);
2611
2612         dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", SEND_EXT_CSD);
2613
2614         rtsx_init_cmd(chip);
2615
2616         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
2617                 0x40 | SEND_EXT_CSD);
2618         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0);
2619         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0);
2620         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0);
2621         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0);
2622
2623         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0);
2624         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2);
2625         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2626         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2627
2628         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2629                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END|
2630                 SD_CHECK_CRC7 | SD_RSP_LEN_6);
2631         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
2632                 PINGPONG_BUFFER);
2633         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
2634                 SD_TM_NORMAL_READ | SD_TRANSFER_START);
2635         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
2636                 SD_TRANSFER_END);
2637
2638         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0);
2639         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0);
2640         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0);
2641         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0);
2642         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0);
2643
2644         retval = rtsx_send_cmd(chip, SD_CARD, 1000);
2645         if (retval < 0) {
2646                 if (retval == -ETIMEDOUT) {
2647                         rtsx_clear_sd_error(chip);
2648                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2649                                         SD_RSP_TYPE_R1, NULL, 0);
2650                 }
2651                 TRACE_RET(chip, STATUS_FAIL);
2652         }
2653
2654         ptr = rtsx_get_cmd_data(chip);
2655         if (ptr[0] & SD_TRANSFER_ERR) {
2656                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2657                                 SD_RSP_TYPE_R1, NULL, 0);
2658                 TRACE_RET(chip, STATUS_FAIL);
2659         }
2660
2661         if (CHK_MMC_SECTOR_MODE(sd_card)) {
2662                 sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) |
2663                         ((u32)ptr[3] << 8) | ((u32)ptr[2]);
2664         }
2665
2666         card_type_mask = 0x03;
2667         card_type = ptr[1] & card_type_mask;
2668         if (card_type) {
2669                 u8 rsp[5];
2670
2671                 if (card_type & 0x04) {
2672                         if (switch_ddr)
2673                                 SET_MMC_DDR52(sd_card);
2674                         else
2675                                 SET_MMC_52M(sd_card);
2676                 } else if (card_type & 0x02) {
2677                         SET_MMC_52M(sd_card);
2678                 } else {
2679                         SET_MMC_26M(sd_card);
2680                 }
2681
2682                 retval = sd_send_cmd_get_rsp(chip, SWITCH,
2683                                 0x03B90100, SD_RSP_TYPE_R1b, rsp, 5);
2684                 if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR))
2685                         CLR_MMC_HS(sd_card);
2686         }
2687
2688         sd_choose_proper_clock(chip);
2689         retval = switch_clock(chip, sd_card->sd_clock);
2690         if (retval != STATUS_SUCCESS)
2691                 TRACE_RET(chip, STATUS_FAIL);
2692
2693         /* Test Bus Procedure */
2694         retval = mmc_test_switch_bus(chip, MMC_8BIT_BUS);
2695         if (retval == SWITCH_SUCCESS) {
2696                 SET_MMC_8BIT(sd_card);
2697                 chip->card_bus_width[chip->card2lun[SD_CARD]] = 8;
2698 #ifdef SUPPORT_SD_LOCK
2699                 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2700 #endif
2701         } else if (retval == SWITCH_FAIL) {
2702                 retval = mmc_test_switch_bus(chip, MMC_4BIT_BUS);
2703                 if (retval == SWITCH_SUCCESS) {
2704                         SET_MMC_4BIT(sd_card);
2705                         chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2706 #ifdef SUPPORT_SD_LOCK
2707                         sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2708 #endif
2709                 } else if (retval == SWITCH_FAIL) {
2710                         CLR_MMC_8BIT(sd_card);
2711                         CLR_MMC_4BIT(sd_card);
2712                 } else {
2713                         TRACE_RET(chip, STATUS_FAIL);
2714                 }
2715         } else {
2716                 TRACE_RET(chip, STATUS_FAIL);
2717         }
2718
2719         return STATUS_SUCCESS;
2720 }
2721
2722
2723 static int reset_mmc(struct rtsx_chip *chip)
2724 {
2725         struct sd_info *sd_card = &(chip->sd_card);
2726         int retval, i = 0, j = 0, k = 0;
2727         int switch_ddr = 1;
2728         u8 rsp[16];
2729         u8 spec_ver = 0;
2730         u32 temp;
2731
2732 #ifdef SUPPORT_SD_LOCK
2733         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2734                 goto MMC_UNLOCK_ENTRY;
2735 #endif
2736
2737 Switch_Fail:
2738         retval = sd_prepare_reset(chip);
2739         if (retval != STATUS_SUCCESS)
2740                 TRACE_RET(chip, retval);
2741
2742         SET_MMC(sd_card);
2743
2744 RTY_MMC_RST:
2745         retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
2746                                 NULL, 0);
2747         if (retval != STATUS_SUCCESS)
2748                 TRACE_RET(chip, STATUS_FAIL);
2749
2750         do {
2751                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2752                         sd_set_err_code(chip, SD_NO_CARD);
2753                         TRACE_RET(chip, STATUS_FAIL);
2754                 }
2755
2756                 retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND,
2757                                         (SUPPORT_VOLTAGE | 0x40000000),
2758                                         SD_RSP_TYPE_R3, rsp, 5);
2759                 if (retval != STATUS_SUCCESS) {
2760                         if (sd_check_err_code(chip, SD_BUSY) ||
2761                                 sd_check_err_code(chip, SD_TO_ERR)) {
2762                                 k++;
2763                                 if (k < 20) {
2764                                         sd_clr_err_code(chip);
2765                                         goto RTY_MMC_RST;
2766                                 } else {
2767                                         TRACE_RET(chip, STATUS_FAIL);
2768                                 }
2769                         } else {
2770                                 j++;
2771                                 if (j < 100) {
2772                                         sd_clr_err_code(chip);
2773                                         goto RTY_MMC_RST;
2774                                 } else {
2775                                         TRACE_RET(chip, STATUS_FAIL);
2776                                 }
2777                         }
2778                 }
2779
2780                 wait_timeout(20);
2781                 i++;
2782         } while (!(rsp[1] & 0x80) && (i < 255));
2783
2784         if (i == 255)
2785                 TRACE_RET(chip, STATUS_FAIL);
2786
2787         if ((rsp[1] & 0x60) == 0x40)
2788                 SET_MMC_SECTOR_MODE(sd_card);
2789         else
2790                 CLR_MMC_SECTOR_MODE(sd_card);
2791
2792         retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2,
2793                                 NULL, 0);
2794         if (retval != STATUS_SUCCESS)
2795                 TRACE_RET(chip, STATUS_FAIL);
2796
2797         sd_card->sd_addr = 0x00100000;
2798         retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr,
2799                                 SD_RSP_TYPE_R6, rsp, 5);
2800         if (retval != STATUS_SUCCESS)
2801                 TRACE_RET(chip, STATUS_FAIL);
2802
2803         retval = sd_check_csd(chip, 1);
2804         if (retval != STATUS_SUCCESS)
2805                 TRACE_RET(chip, STATUS_FAIL);
2806
2807         spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2;
2808
2809         retval = sd_select_card(chip, 1);
2810         if (retval != STATUS_SUCCESS)
2811                 TRACE_RET(chip, STATUS_FAIL);
2812
2813         retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1,
2814                                 NULL, 0);
2815         if (retval != STATUS_SUCCESS)
2816                 TRACE_RET(chip, STATUS_FAIL);
2817
2818 #ifdef SUPPORT_SD_LOCK
2819 MMC_UNLOCK_ENTRY:
2820         retval = sd_update_lock_status(chip);
2821         if (retval != STATUS_SUCCESS)
2822                 TRACE_RET(chip, STATUS_FAIL);
2823 #endif
2824
2825         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2826         if (retval != STATUS_SUCCESS)
2827                 TRACE_RET(chip, STATUS_FAIL);
2828
2829         chip->card_bus_width[chip->card2lun[SD_CARD]] = 1;
2830
2831         if (!sd_card->mmc_dont_switch_bus) {
2832                 if (spec_ver == 4) {
2833                         /* MMC 4.x Cards */
2834                         retval = mmc_switch_timing_bus(chip, switch_ddr);
2835                         if (retval != STATUS_SUCCESS) {
2836                                 retval = sd_init_power(chip);
2837                                 if (retval != STATUS_SUCCESS)
2838                                         TRACE_RET(chip, STATUS_FAIL);
2839                                 sd_card->mmc_dont_switch_bus = 1;
2840                                 TRACE_GOTO(chip, Switch_Fail);
2841                         }
2842                 }
2843
2844                 if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0))
2845                         TRACE_RET(chip, STATUS_FAIL);
2846
2847                 if (switch_ddr && CHK_MMC_DDR52(sd_card)) {
2848                         retval = sd_set_init_para(chip);
2849                         if (retval != STATUS_SUCCESS)
2850                                 TRACE_RET(chip, STATUS_FAIL);
2851
2852                         retval = mmc_ddr_tuning(chip);
2853                         if (retval != STATUS_SUCCESS) {
2854                                 retval = sd_init_power(chip);
2855                                 if (retval != STATUS_SUCCESS)
2856                                         TRACE_RET(chip, STATUS_FAIL);
2857
2858                                 switch_ddr = 0;
2859                                 TRACE_GOTO(chip, Switch_Fail);
2860                         }
2861
2862                         retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
2863                         if (retval == STATUS_SUCCESS) {
2864                                 retval = sd_read_lba0(chip);
2865                                 if (retval != STATUS_SUCCESS) {
2866                                         retval = sd_init_power(chip);
2867                                         if (retval != STATUS_SUCCESS)
2868                                                 TRACE_RET(chip, STATUS_FAIL);
2869
2870                                         switch_ddr = 0;
2871                                         TRACE_GOTO(chip, Switch_Fail);
2872                                 }
2873                         }
2874                 }
2875         }
2876
2877 #ifdef SUPPORT_SD_LOCK
2878         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2879                 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02);
2880                 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00);
2881         }
2882 #endif
2883
2884         temp = rtsx_readl(chip, RTSX_BIPR);
2885         if (temp & SD_WRITE_PROTECT)
2886                 chip->card_wp |= SD_CARD;
2887
2888         return STATUS_SUCCESS;
2889 }
2890
2891 int reset_sd_card(struct rtsx_chip *chip)
2892 {
2893         struct sd_info *sd_card = &(chip->sd_card);
2894         int retval;
2895
2896         sd_init_reg_addr(chip);
2897
2898         memset(sd_card, 0, sizeof(struct sd_info));
2899         chip->capacity[chip->card2lun[SD_CARD]] = 0;
2900
2901         retval = enable_card_clock(chip, SD_CARD);
2902         if (retval != STATUS_SUCCESS)
2903                 TRACE_RET(chip, STATUS_FAIL);
2904
2905         if (chip->ignore_sd && CHK_SDIO_EXIST(chip) &&
2906                 !CHK_SDIO_IGNORED(chip)) {
2907                 if (chip->asic_code) {
2908                         retval = sd_pull_ctl_enable(chip);
2909                         if (retval != STATUS_SUCCESS)
2910                                 TRACE_RET(chip, STATUS_FAIL);
2911                 } else {
2912                         retval = rtsx_write_register(chip, FPGA_PULL_CTL,
2913                                                 FPGA_SD_PULL_CTL_BIT | 0x20, 0);
2914                         if (retval != STATUS_SUCCESS)
2915                                 TRACE_RET(chip, STATUS_FAIL);
2916                 }
2917                 retval = card_share_mode(chip, SD_CARD);
2918                 if (retval != STATUS_SUCCESS)
2919                         TRACE_RET(chip, STATUS_FAIL);
2920
2921                 chip->sd_io = 1;
2922                 TRACE_RET(chip, STATUS_FAIL);
2923         }
2924
2925         retval = sd_init_power(chip);
2926         if (retval != STATUS_SUCCESS)
2927                 TRACE_RET(chip, STATUS_FAIL);
2928
2929         if (chip->sd_ctl & RESET_MMC_FIRST) {
2930                 retval = reset_mmc(chip);
2931                 if (retval != STATUS_SUCCESS) {
2932                         if (sd_check_err_code(chip, SD_NO_CARD))
2933                                 TRACE_RET(chip, STATUS_FAIL);
2934
2935                         retval = reset_sd(chip);
2936                         if (retval != STATUS_SUCCESS)
2937                                 TRACE_RET(chip, STATUS_FAIL);
2938                 }
2939         } else {
2940                 retval = reset_sd(chip);
2941                 if (retval != STATUS_SUCCESS) {
2942                         if (sd_check_err_code(chip, SD_NO_CARD))
2943                                 TRACE_RET(chip, STATUS_FAIL);
2944
2945                         if (chip->sd_io) {
2946                                 TRACE_RET(chip, STATUS_FAIL);
2947                         } else {
2948                                 retval = reset_mmc(chip);
2949                                 if (retval != STATUS_SUCCESS)
2950                                         TRACE_RET(chip, STATUS_FAIL);
2951                         }
2952                 }
2953         }
2954
2955         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2956         if (retval != STATUS_SUCCESS)
2957                 TRACE_RET(chip, STATUS_FAIL);
2958
2959         RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
2960         RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
2961
2962         chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
2963
2964         retval = sd_set_init_para(chip);
2965         if (retval != STATUS_SUCCESS)
2966                 TRACE_RET(chip, STATUS_FAIL);
2967
2968         dev_dbg(rtsx_dev(chip), "sd_card->sd_type = 0x%x\n", sd_card->sd_type);
2969
2970         return STATUS_SUCCESS;
2971 }
2972
2973 static int reset_mmc_only(struct rtsx_chip *chip)
2974 {
2975         struct sd_info *sd_card = &(chip->sd_card);
2976         int retval;
2977
2978         sd_card->sd_type = 0;
2979         sd_card->seq_mode = 0;
2980         sd_card->sd_data_buf_ready = 0;
2981         sd_card->capacity = 0;
2982         sd_card->sd_switch_fail = 0;
2983
2984 #ifdef SUPPORT_SD_LOCK
2985         sd_card->sd_lock_status = 0;
2986         sd_card->sd_erase_status = 0;
2987 #endif
2988
2989         chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0;
2990
2991         retval = enable_card_clock(chip, SD_CARD);
2992         if (retval != STATUS_SUCCESS)
2993                 TRACE_RET(chip, STATUS_FAIL);
2994
2995         retval = sd_init_power(chip);
2996         if (retval != STATUS_SUCCESS)
2997                 TRACE_RET(chip, STATUS_FAIL);
2998
2999         retval = reset_mmc(chip);
3000         if (retval != STATUS_SUCCESS)
3001                 TRACE_RET(chip, STATUS_FAIL);
3002
3003         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3004         if (retval != STATUS_SUCCESS)
3005                 TRACE_RET(chip, STATUS_FAIL);
3006
3007         RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3008         RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3009
3010         chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3011
3012         retval = sd_set_init_para(chip);
3013         if (retval != STATUS_SUCCESS)
3014                 TRACE_RET(chip, STATUS_FAIL);
3015
3016         dev_dbg(rtsx_dev(chip), "In reset_mmc_only, sd_card->sd_type = 0x%x\n",
3017                 sd_card->sd_type);
3018
3019         return STATUS_SUCCESS;
3020 }
3021
3022 #define WAIT_DATA_READY_RTY_CNT         255
3023
3024 static int wait_data_buf_ready(struct rtsx_chip *chip)
3025 {
3026         struct sd_info *sd_card = &(chip->sd_card);
3027         int i, retval;
3028
3029         for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) {
3030                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3031                         sd_set_err_code(chip, SD_NO_CARD);
3032                         TRACE_RET(chip, STATUS_FAIL);
3033                 }
3034
3035                 sd_card->sd_data_buf_ready = 0;
3036
3037                 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
3038                                 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3039                 if (retval != STATUS_SUCCESS)
3040                         TRACE_RET(chip, STATUS_FAIL);
3041
3042                 if (sd_card->sd_data_buf_ready) {
3043                         return sd_send_cmd_get_rsp(chip, SEND_STATUS,
3044                                 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3045                 }
3046         }
3047
3048         sd_set_err_code(chip, SD_TO_ERR);
3049
3050         TRACE_RET(chip, STATUS_FAIL);
3051 }
3052
3053 void sd_stop_seq_mode(struct rtsx_chip *chip)
3054 {
3055         struct sd_info *sd_card = &(chip->sd_card);
3056         int retval;
3057
3058         if (sd_card->seq_mode) {
3059                 retval = sd_switch_clock(chip);
3060                 if (retval != STATUS_SUCCESS)
3061                         return;
3062
3063                 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3064                                 SD_RSP_TYPE_R1b, NULL, 0);
3065                 if (retval != STATUS_SUCCESS)
3066                         sd_set_err_code(chip, SD_STS_ERR);
3067
3068                 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3069                 if (retval != STATUS_SUCCESS)
3070                         sd_set_err_code(chip, SD_STS_ERR);
3071
3072                 sd_card->seq_mode = 0;
3073
3074                 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3075         }
3076 }
3077
3078 static inline int sd_auto_tune_clock(struct rtsx_chip *chip)
3079 {
3080         struct sd_info *sd_card = &(chip->sd_card);
3081         int retval;
3082
3083         if (chip->asic_code) {
3084                 if (sd_card->sd_clock > 30)
3085                         sd_card->sd_clock -= 20;
3086         } else {
3087                 switch (sd_card->sd_clock) {
3088                 case CLK_200:
3089                         sd_card->sd_clock = CLK_150;
3090                         break;
3091
3092                 case CLK_150:
3093                         sd_card->sd_clock = CLK_120;
3094                         break;
3095
3096                 case CLK_120:
3097                         sd_card->sd_clock = CLK_100;
3098                         break;
3099
3100                 case CLK_100:
3101                         sd_card->sd_clock = CLK_80;
3102                         break;
3103
3104                 case CLK_80:
3105                         sd_card->sd_clock = CLK_60;
3106                         break;
3107
3108                 case CLK_60:
3109                         sd_card->sd_clock = CLK_50;
3110                         break;
3111
3112                 default:
3113                         break;
3114                 }
3115         }
3116
3117         retval = sd_switch_clock(chip);
3118         if (retval != STATUS_SUCCESS)
3119                 TRACE_RET(chip, STATUS_FAIL);
3120
3121         return STATUS_SUCCESS;
3122 }
3123
3124 int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector,
3125         u16 sector_cnt)
3126 {
3127         struct sd_info *sd_card = &(chip->sd_card);
3128         u32 data_addr;
3129         u8 cfg2;
3130         int retval;
3131
3132         if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3133                 dev_dbg(rtsx_dev(chip), "sd_rw: Read %d %s from 0x%x\n",
3134                         sector_cnt, (sector_cnt > 1) ? "sectors" : "sector",
3135                         start_sector);
3136         } else {
3137                 dev_dbg(rtsx_dev(chip), "sd_rw: Write %d %s to 0x%x\n",
3138                         sector_cnt, (sector_cnt > 1) ? "sectors" : "sector",
3139                         start_sector);
3140         }
3141
3142         sd_card->cleanup_counter = 0;
3143
3144         if (!(chip->card_ready & SD_CARD)) {
3145                 sd_card->seq_mode = 0;
3146
3147                 retval = reset_sd_card(chip);
3148                 if (retval == STATUS_SUCCESS) {
3149                         chip->card_ready |= SD_CARD;
3150                         chip->card_fail &= ~SD_CARD;
3151                 } else {
3152                         chip->card_ready &= ~SD_CARD;
3153                         chip->card_fail |= SD_CARD;
3154                         chip->capacity[chip->card2lun[SD_CARD]] = 0;
3155                         chip->rw_need_retry = 1;
3156                         TRACE_RET(chip, STATUS_FAIL);
3157                 }
3158         }
3159
3160         if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card))
3161                 data_addr = start_sector << 9;
3162         else
3163                 data_addr = start_sector;
3164
3165         sd_clr_err_code(chip);
3166
3167         retval = sd_switch_clock(chip);
3168         if (retval != STATUS_SUCCESS) {
3169                 sd_set_err_code(chip, SD_IO_ERR);
3170                 TRACE_GOTO(chip, RW_FAIL);
3171         }
3172
3173         if (sd_card->seq_mode &&
3174                 ((sd_card->pre_dir != srb->sc_data_direction) ||
3175                         ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) !=
3176                                 start_sector))) {
3177                 if ((sd_card->pre_sec_cnt < 0x80)
3178                                 && (sd_card->pre_dir == DMA_FROM_DEVICE)
3179                                 && !CHK_SD30_SPEED(sd_card)
3180                                 && !CHK_SD_HS(sd_card)
3181                                 && !CHK_MMC_HS(sd_card)) {
3182                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3183                                         SD_RSP_TYPE_R1, NULL, 0);
3184                 }
3185
3186                 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
3187                                 0, SD_RSP_TYPE_R1b, NULL, 0);
3188                 if (retval != STATUS_SUCCESS) {
3189                         chip->rw_need_retry = 1;
3190                         sd_set_err_code(chip, SD_STS_ERR);
3191                         TRACE_GOTO(chip, RW_FAIL);
3192                 }
3193
3194                 sd_card->seq_mode = 0;
3195
3196                 retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3197                 if (retval != STATUS_SUCCESS) {
3198                         sd_set_err_code(chip, SD_IO_ERR);
3199                         TRACE_GOTO(chip, RW_FAIL);
3200                 }
3201
3202                 if ((sd_card->pre_sec_cnt < 0x80)
3203                                 && !CHK_SD30_SPEED(sd_card)
3204                                 && !CHK_SD_HS(sd_card)
3205                                 && !CHK_MMC_HS(sd_card)) {
3206                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3207                                         SD_RSP_TYPE_R1, NULL, 0);
3208                 }
3209         }
3210
3211         rtsx_init_cmd(chip);
3212
3213         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
3214         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
3215         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
3216                 (u8)sector_cnt);
3217         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
3218                 (u8)(sector_cnt >> 8));
3219
3220         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3221
3222         if (CHK_MMC_8BIT(sd_card))
3223                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3224                         0x03, SD_BUS_WIDTH_8);
3225         else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card))
3226                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3227                         0x03, SD_BUS_WIDTH_4);
3228         else
3229                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3230                         0x03, SD_BUS_WIDTH_1);
3231
3232         if (sd_card->seq_mode) {
3233                 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16|
3234                         SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 |
3235                         SD_RSP_LEN_0;
3236                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3237
3238                 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512,
3239                                 DMA_512);
3240
3241                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3242                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3243                                      SD_TM_AUTO_READ_3 | SD_TRANSFER_START);
3244                 } else {
3245                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3246                                      SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3247                 }
3248
3249                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3250                         SD_TRANSFER_END, SD_TRANSFER_END);
3251
3252                 rtsx_send_cmd_no_wait(chip);
3253         } else {
3254                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3255                         dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n",
3256                                 READ_MULTIPLE_BLOCK);
3257                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3258                                      0x40 | READ_MULTIPLE_BLOCK);
3259                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF,
3260                                 (u8)(data_addr >> 24));
3261                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF,
3262                                 (u8)(data_addr >> 16));
3263                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF,
3264                                 (u8)(data_addr >> 8));
3265                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF,
3266                                 (u8)data_addr);
3267
3268                         cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3269                                 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 |
3270                                 SD_RSP_LEN_6;
3271                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3272                                 cfg2);
3273
3274                         trans_dma_enable(srb->sc_data_direction, chip,
3275                                         sector_cnt * 512, DMA_512);
3276
3277                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3278                                      SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3279                         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3280                                      SD_TRANSFER_END, SD_TRANSFER_END);
3281
3282                         rtsx_send_cmd_no_wait(chip);
3283                 } else {
3284                         retval = rtsx_send_cmd(chip, SD_CARD, 50);
3285                         if (retval < 0) {
3286                                 rtsx_clear_sd_error(chip);
3287
3288                                 chip->rw_need_retry = 1;
3289                                 sd_set_err_code(chip, SD_TO_ERR);
3290                                 TRACE_GOTO(chip, RW_FAIL);
3291                         }
3292
3293                         retval = wait_data_buf_ready(chip);
3294                         if (retval != STATUS_SUCCESS) {
3295                                 chip->rw_need_retry = 1;
3296                                 sd_set_err_code(chip, SD_TO_ERR);
3297                                 TRACE_GOTO(chip, RW_FAIL);
3298                         }
3299
3300                         retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK,
3301                                         data_addr, SD_RSP_TYPE_R1, NULL, 0);
3302                         if (retval != STATUS_SUCCESS) {
3303                                 chip->rw_need_retry = 1;
3304                                 TRACE_GOTO(chip, RW_FAIL);
3305                         }
3306
3307                         rtsx_init_cmd(chip);
3308
3309                         cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3310                                 SD_NO_WAIT_BUSY_END |
3311                                 SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3312                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3313                                 cfg2);
3314
3315                         trans_dma_enable(srb->sc_data_direction, chip,
3316                                         sector_cnt * 512, DMA_512);
3317
3318                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3319                                      SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3320                         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3321                                      SD_TRANSFER_END, SD_TRANSFER_END);
3322
3323                         rtsx_send_cmd_no_wait(chip);
3324                 }
3325
3326                 sd_card->seq_mode = 1;
3327         }
3328
3329         retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
3330                                 scsi_bufflen(srb), scsi_sg_count(srb),
3331                                 srb->sc_data_direction, chip->sd_timeout);
3332         if (retval < 0) {
3333                 u8 stat = 0;
3334                 int err;
3335
3336                 sd_card->seq_mode = 0;
3337
3338                 if (retval == -ETIMEDOUT)
3339                         err = STATUS_TIMEDOUT;
3340                 else
3341                         err = STATUS_FAIL;
3342
3343                 rtsx_read_register(chip, REG_SD_STAT1, &stat);
3344                 rtsx_clear_sd_error(chip);
3345                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3346                         chip->rw_need_retry = 0;
3347                         dev_dbg(rtsx_dev(chip), "No card exist, exit sd_rw\n");
3348                         TRACE_RET(chip, STATUS_FAIL);
3349                 }
3350
3351                 chip->rw_need_retry = 1;
3352
3353                 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3354                                         SD_RSP_TYPE_R1b, NULL, 0);
3355                 if (retval != STATUS_SUCCESS) {
3356                         sd_set_err_code(chip, SD_STS_ERR);
3357                         TRACE_GOTO(chip, RW_FAIL);
3358                 }
3359
3360                 if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) {
3361                         dev_dbg(rtsx_dev(chip), "SD CRC error, tune clock!\n");
3362                         sd_set_err_code(chip, SD_CRC_ERR);
3363                         TRACE_GOTO(chip, RW_FAIL);
3364                 }
3365
3366                 if (err == STATUS_TIMEDOUT) {
3367                         sd_set_err_code(chip, SD_TO_ERR);
3368                         TRACE_GOTO(chip, RW_FAIL);
3369                 }
3370
3371                 TRACE_RET(chip, err);
3372         }
3373
3374         sd_card->pre_sec_addr = start_sector;
3375         sd_card->pre_sec_cnt = sector_cnt;
3376         sd_card->pre_dir = srb->sc_data_direction;
3377
3378         return STATUS_SUCCESS;
3379
3380 RW_FAIL:
3381         sd_card->seq_mode = 0;
3382
3383         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3384                 chip->rw_need_retry = 0;
3385                 dev_dbg(rtsx_dev(chip), "No card exist, exit sd_rw\n");
3386                 TRACE_RET(chip, STATUS_FAIL);
3387         }
3388
3389         if (sd_check_err_code(chip, SD_CRC_ERR)) {
3390                 if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) {
3391                         sd_card->mmc_dont_switch_bus = 1;
3392                         reset_mmc_only(chip);
3393                         sd_card->mmc_dont_switch_bus = 0;
3394                 } else {
3395                         sd_card->need_retune = 1;
3396                         sd_auto_tune_clock(chip);
3397                 }
3398         } else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) {
3399                 retval = reset_sd_card(chip);
3400                 if (retval != STATUS_SUCCESS) {
3401                         chip->card_ready &= ~SD_CARD;
3402                         chip->card_fail |= SD_CARD;
3403                         chip->capacity[chip->card2lun[SD_CARD]] = 0;
3404                 }
3405         }
3406
3407         TRACE_RET(chip, STATUS_FAIL);
3408 }
3409
3410 #ifdef SUPPORT_CPRM
3411 int soft_reset_sd_card(struct rtsx_chip *chip)
3412 {
3413         return reset_sd(chip);
3414 }
3415
3416 int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
3417                 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, int special_check)
3418 {
3419         int retval;
3420         int timeout = 100;
3421         u16 reg_addr;
3422         u8 *ptr;
3423         int stat_idx = 0;
3424         int rty_cnt = 0;
3425
3426         dev_dbg(rtsx_dev(chip), "EXT SD/MMC CMD %d\n", cmd_idx);
3427
3428         if (rsp_type == SD_RSP_TYPE_R1b)
3429                 timeout = 3000;
3430
3431 RTY_SEND_CMD:
3432
3433         rtsx_init_cmd(chip);
3434
3435         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
3436         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
3437         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
3438         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
3439         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
3440
3441         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
3442         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3443                         0x01, PINGPONG_BUFFER);
3444         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
3445                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
3446         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
3447                 SD_TRANSFER_END);
3448
3449         if (rsp_type == SD_RSP_TYPE_R2) {
3450                 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
3451                      reg_addr++)
3452                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3453
3454                 stat_idx = 17;
3455         } else if (rsp_type != SD_RSP_TYPE_R0) {
3456                 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
3457                      reg_addr++)
3458                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3459
3460                 stat_idx = 6;
3461         }
3462         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0);
3463
3464         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
3465
3466         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
3467         if (retval < 0) {
3468                 if (retval == -ETIMEDOUT) {
3469                         rtsx_clear_sd_error(chip);
3470
3471                         if (rsp_type & SD_WAIT_BUSY_END) {
3472                                 retval = sd_check_data0_status(chip);
3473                                 if (retval != STATUS_SUCCESS)
3474                                         TRACE_RET(chip, retval);
3475                         } else {
3476                                 sd_set_err_code(chip, SD_TO_ERR);
3477                         }
3478                 }
3479                 TRACE_RET(chip, STATUS_FAIL);
3480         }
3481
3482         if (rsp_type == SD_RSP_TYPE_R0)
3483                 return STATUS_SUCCESS;
3484
3485         ptr = rtsx_get_cmd_data(chip) + 1;
3486
3487         if ((ptr[0] & 0xC0) != 0) {
3488                 sd_set_err_code(chip, SD_STS_ERR);
3489                 TRACE_RET(chip, STATUS_FAIL);
3490         }
3491
3492         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
3493                 if (ptr[stat_idx] & SD_CRC7_ERR) {
3494                         if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
3495                                 sd_set_err_code(chip, SD_CRC_ERR);
3496                                 TRACE_RET(chip, STATUS_FAIL);
3497                         }
3498                         if (rty_cnt < SD_MAX_RETRY_COUNT) {
3499                                 wait_timeout(20);
3500                                 rty_cnt++;
3501                                 goto RTY_SEND_CMD;
3502                         } else {
3503                                 sd_set_err_code(chip, SD_CRC_ERR);
3504                                 TRACE_RET(chip, STATUS_FAIL);
3505                         }
3506                 }
3507         }
3508
3509         if ((cmd_idx == SELECT_CARD) || (cmd_idx == APP_CMD) ||
3510                 (cmd_idx == SEND_STATUS) || (cmd_idx == STOP_TRANSMISSION)) {
3511                 if ((cmd_idx != STOP_TRANSMISSION) && (special_check == 0)) {
3512                         if (ptr[1] & 0x80)
3513                                 TRACE_RET(chip, STATUS_FAIL);
3514                 }
3515 #ifdef SUPPORT_SD_LOCK
3516                 if (ptr[1] & 0x7D)
3517 #else
3518                 if (ptr[1] & 0x7F)
3519 #endif
3520                 {
3521                         TRACE_RET(chip, STATUS_FAIL);
3522                 }
3523                 if (ptr[2] & 0xF8)
3524                         TRACE_RET(chip, STATUS_FAIL);
3525
3526                 if (cmd_idx == SELECT_CARD) {
3527                         if (rsp_type == SD_RSP_TYPE_R2) {
3528                                 if ((ptr[3] & 0x1E) != 0x04)
3529                                         TRACE_RET(chip, STATUS_FAIL);
3530
3531                         } else if (rsp_type == SD_RSP_TYPE_R0) {
3532                                 if ((ptr[3] & 0x1E) != 0x03)
3533                                         TRACE_RET(chip, STATUS_FAIL);
3534                         }
3535                 }
3536         }
3537
3538         if (rsp && rsp_len)
3539                 memcpy(rsp, ptr, rsp_len);
3540
3541         return STATUS_SUCCESS;
3542 }
3543
3544 int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type)
3545 {
3546         int retval, rsp_len;
3547         u16 reg_addr;
3548
3549         if (rsp_type == SD_RSP_TYPE_R0)
3550                 return STATUS_SUCCESS;
3551
3552         rtsx_init_cmd(chip);
3553
3554         if (rsp_type == SD_RSP_TYPE_R2) {
3555                 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
3556                      reg_addr++)
3557                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3558
3559                 rsp_len = 17;
3560         } else if (rsp_type != SD_RSP_TYPE_R0) {
3561                 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
3562                      reg_addr++)
3563                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3564
3565                 rsp_len = 6;
3566         }
3567         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0);
3568
3569         retval = rtsx_send_cmd(chip, SD_CARD, 100);
3570         if (retval != STATUS_SUCCESS)
3571                 TRACE_RET(chip, STATUS_FAIL);
3572
3573         if (rsp) {
3574                 int min_len = (rsp_len < len) ? rsp_len : len;
3575
3576                 memcpy(rsp, rtsx_get_cmd_data(chip), min_len);
3577
3578                 dev_dbg(rtsx_dev(chip), "min_len = %d\n", min_len);
3579                 dev_dbg(rtsx_dev(chip), "Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n",
3580                         rsp[0], rsp[1], rsp[2], rsp[3]);
3581         }
3582
3583         return STATUS_SUCCESS;
3584 }
3585
3586 int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3587 {
3588         struct sd_info *sd_card = &(chip->sd_card);
3589         unsigned int lun = SCSI_LUN(srb);
3590         int len;
3591         u8 buf[18] = {
3592                 0x00,
3593                 0x00,
3594                 0x00,
3595                 0x0E,
3596                 0x00,
3597                 0x00,
3598                 0x00,
3599                 0x00,
3600                 0x53,
3601                 0x44,
3602                 0x20,
3603                 0x43,
3604                 0x61,
3605                 0x72,
3606                 0x64,
3607                 0x00,
3608                 0x00,
3609                 0x00,
3610         };
3611
3612         sd_card->pre_cmd_err = 0;
3613
3614         if (!(CHK_BIT(chip->lun_mc, lun))) {
3615                 SET_BIT(chip->lun_mc, lun);
3616                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3617                 TRACE_RET(chip, TRANSPORT_FAILED);
3618         }
3619
3620         if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) ||
3621                 (0x20 != srb->cmnd[4]) || (0x43 != srb->cmnd[5]) ||
3622                 (0x61 != srb->cmnd[6]) || (0x72 != srb->cmnd[7]) ||
3623                 (0x64 != srb->cmnd[8])) {
3624                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3625                 TRACE_RET(chip, TRANSPORT_FAILED);
3626         }
3627
3628         switch (srb->cmnd[1] & 0x0F) {
3629         case 0:
3630                 sd_card->sd_pass_thru_en = 0;
3631                 break;
3632
3633         case 1:
3634                 sd_card->sd_pass_thru_en = 1;
3635                 break;
3636
3637         default:
3638                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3639                 TRACE_RET(chip, TRANSPORT_FAILED);
3640         }
3641
3642         buf[5] = (1 == CHK_SD(sd_card)) ?  0x01 : 0x02;
3643         if (chip->card_wp & SD_CARD)
3644                 buf[5] |= 0x80;
3645
3646         buf[6] = (u8)(sd_card->sd_addr >> 16);
3647         buf[7] = (u8)(sd_card->sd_addr >> 24);
3648
3649         buf[15] = chip->max_lun;
3650
3651         len = min_t(int, 18, scsi_bufflen(srb));
3652         rtsx_stor_set_xfer_buf(buf, len, srb);
3653
3654         return TRANSPORT_GOOD;
3655 }
3656
3657 static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type,
3658                         int *rsp_len)
3659 {
3660         if (!rsp_type || !rsp_len)
3661                 return STATUS_FAIL;
3662
3663         switch (srb->cmnd[10]) {
3664         case 0x03:
3665                 *rsp_type = SD_RSP_TYPE_R0;
3666                 *rsp_len = 0;
3667                 break;
3668
3669         case 0x04:
3670                 *rsp_type = SD_RSP_TYPE_R1;
3671                 *rsp_len = 6;
3672                 break;
3673
3674         case 0x05:
3675                 *rsp_type = SD_RSP_TYPE_R1b;
3676                 *rsp_len = 6;
3677                 break;
3678
3679         case 0x06:
3680                 *rsp_type = SD_RSP_TYPE_R2;
3681                 *rsp_len = 17;
3682                 break;
3683
3684         case 0x07:
3685                 *rsp_type = SD_RSP_TYPE_R3;
3686                 *rsp_len = 6;
3687                 break;
3688
3689         default:
3690                 return STATUS_FAIL;
3691         }
3692
3693         return STATUS_SUCCESS;
3694 }
3695
3696 int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3697 {
3698         struct sd_info *sd_card = &(chip->sd_card);
3699         unsigned int lun = SCSI_LUN(srb);
3700         int retval, rsp_len;
3701         u8 cmd_idx, rsp_type;
3702         u8 standby = 0, acmd = 0;
3703         u32 arg;
3704
3705         if (!sd_card->sd_pass_thru_en) {
3706                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3707                 TRACE_RET(chip, TRANSPORT_FAILED);
3708         }
3709
3710         retval = sd_switch_clock(chip);
3711         if (retval != STATUS_SUCCESS)
3712                 TRACE_RET(chip, TRANSPORT_FAILED);
3713
3714         if (sd_card->pre_cmd_err) {
3715                 sd_card->pre_cmd_err = 0;
3716                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3717                 TRACE_RET(chip, TRANSPORT_FAILED);
3718         }
3719
3720         cmd_idx = srb->cmnd[2] & 0x3F;
3721         if (srb->cmnd[1] & 0x02)
3722                 standby = 1;
3723
3724         if (srb->cmnd[1] & 0x01)
3725                 acmd = 1;
3726
3727         arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
3728                 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
3729
3730         retval = get_rsp_type(srb, &rsp_type, &rsp_len);
3731         if (retval != STATUS_SUCCESS) {
3732                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3733                 TRACE_RET(chip, TRANSPORT_FAILED);
3734         }
3735         sd_card->last_rsp_type = rsp_type;
3736
3737         retval = sd_switch_clock(chip);
3738         if (retval != STATUS_SUCCESS)
3739                 TRACE_RET(chip, TRANSPORT_FAILED);
3740
3741 #ifdef SUPPORT_SD_LOCK
3742         if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
3743                 if (CHK_MMC_8BIT(sd_card)) {
3744                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
3745                                                 SD_BUS_WIDTH_8);
3746                         if (retval != STATUS_SUCCESS)
3747                                 TRACE_RET(chip, TRANSPORT_FAILED);
3748
3749                 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
3750                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
3751                                                 SD_BUS_WIDTH_4);
3752                         if (retval != STATUS_SUCCESS)
3753                                 TRACE_RET(chip, TRANSPORT_FAILED);
3754                 }
3755         }
3756 #else
3757         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3758         if (retval != STATUS_SUCCESS)
3759                 TRACE_RET(chip, TRANSPORT_FAILED);
3760 #endif
3761
3762         if (standby) {
3763                 retval = sd_select_card(chip, 0);
3764                 if (retval != STATUS_SUCCESS)
3765                         TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3766         }
3767
3768         if (acmd) {
3769                 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
3770                                                 sd_card->sd_addr,
3771                                                 SD_RSP_TYPE_R1, NULL, 0, 0);
3772                 if (retval != STATUS_SUCCESS)
3773                         TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3774         }
3775
3776         retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
3777                         sd_card->rsp, rsp_len, 0);
3778         if (retval != STATUS_SUCCESS)
3779                 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3780
3781         if (standby) {
3782                 retval = sd_select_card(chip, 1);
3783                 if (retval != STATUS_SUCCESS)
3784                         TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3785         }
3786
3787 #ifdef SUPPORT_SD_LOCK
3788         retval = sd_update_lock_status(chip);
3789         if (retval != STATUS_SUCCESS)
3790                 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3791 #endif
3792
3793         scsi_set_resid(srb, 0);
3794         return TRANSPORT_GOOD;
3795
3796 SD_Execute_Cmd_Failed:
3797         sd_card->pre_cmd_err = 1;
3798         set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
3799         release_sd_card(chip);
3800         do_reset_sd_card(chip);
3801         if (!(chip->card_ready & SD_CARD))
3802                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3803
3804         TRACE_RET(chip, TRANSPORT_FAILED);
3805 }
3806
3807 int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3808 {
3809         struct sd_info *sd_card = &(chip->sd_card);
3810         unsigned int lun = SCSI_LUN(srb);
3811         int retval, rsp_len, i;
3812         int cmd13_checkbit = 0, read_err = 0;
3813         u8 cmd_idx, rsp_type, bus_width;
3814         u8 send_cmd12 = 0, standby = 0, acmd = 0;
3815         u32 data_len;
3816
3817         if (!sd_card->sd_pass_thru_en) {
3818                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3819                 TRACE_RET(chip, TRANSPORT_FAILED);
3820         }
3821
3822         if (sd_card->pre_cmd_err) {
3823                 sd_card->pre_cmd_err = 0;
3824                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3825                 TRACE_RET(chip, TRANSPORT_FAILED);
3826         }
3827
3828         retval = sd_switch_clock(chip);
3829         if (retval != STATUS_SUCCESS)
3830                 TRACE_RET(chip, TRANSPORT_FAILED);
3831
3832         cmd_idx = srb->cmnd[2] & 0x3F;
3833         if (srb->cmnd[1] & 0x04)
3834                 send_cmd12 = 1;
3835
3836         if (srb->cmnd[1] & 0x02)
3837                 standby = 1;
3838
3839         if (srb->cmnd[1] & 0x01)
3840                 acmd = 1;
3841
3842         data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8]
3843                                                 << 8) | srb->cmnd[9];
3844
3845         retval = get_rsp_type(srb, &rsp_type, &rsp_len);
3846         if (retval != STATUS_SUCCESS) {
3847                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3848                 TRACE_RET(chip, TRANSPORT_FAILED);
3849         }
3850         sd_card->last_rsp_type = rsp_type;
3851
3852         retval = sd_switch_clock(chip);
3853         if (retval != STATUS_SUCCESS)
3854                 TRACE_RET(chip, TRANSPORT_FAILED);
3855
3856 #ifdef SUPPORT_SD_LOCK
3857         if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
3858                 if (CHK_MMC_8BIT(sd_card))
3859                         bus_width = SD_BUS_WIDTH_8;
3860                 else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card))
3861                         bus_width = SD_BUS_WIDTH_4;
3862                 else
3863                         bus_width = SD_BUS_WIDTH_1;
3864         } else {
3865                 bus_width = SD_BUS_WIDTH_4;
3866         }
3867         dev_dbg(rtsx_dev(chip), "bus_width = %d\n", bus_width);
3868 #else
3869         bus_width = SD_BUS_WIDTH_4;
3870 #endif
3871
3872         if (data_len < 512) {
3873                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
3874                                 SD_RSP_TYPE_R1, NULL, 0, 0);
3875                 if (retval != STATUS_SUCCESS)
3876                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3877         }
3878
3879         if (standby) {
3880                 retval = sd_select_card(chip, 0);
3881                 if (retval != STATUS_SUCCESS)
3882                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3883         }
3884
3885         if (acmd) {
3886                 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
3887                                                 sd_card->sd_addr,
3888                                                 SD_RSP_TYPE_R1, NULL, 0, 0);
3889                 if (retval != STATUS_SUCCESS)
3890                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3891         }
3892
3893         if (data_len <= 512) {
3894                 int min_len;
3895                 u8 *buf;
3896                 u16 byte_cnt, blk_cnt;
3897                 u8 cmd[5];
3898
3899                 byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9];
3900                 blk_cnt = 1;
3901
3902                 cmd[0] = 0x40 | cmd_idx;
3903                 cmd[1] = srb->cmnd[3];
3904                 cmd[2] = srb->cmnd[4];
3905                 cmd[3] = srb->cmnd[5];
3906                 cmd[4] = srb->cmnd[6];
3907
3908                 buf = kmalloc(data_len, GFP_KERNEL);
3909                 if (buf == NULL)
3910                         TRACE_RET(chip, TRANSPORT_ERROR);
3911
3912                 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt,
3913                                        blk_cnt, bus_width, buf, data_len, 2000);
3914                 if (retval != STATUS_SUCCESS) {
3915                         read_err = 1;
3916                         kfree(buf);
3917                         rtsx_clear_sd_error(chip);
3918                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3919                 }
3920
3921                 min_len = min(data_len, scsi_bufflen(srb));
3922                 rtsx_stor_set_xfer_buf(buf, min_len, srb);
3923
3924                 kfree(buf);
3925         } else if (!(data_len & 0x1FF)) {
3926                 rtsx_init_cmd(chip);
3927
3928                 trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512);
3929
3930                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
3931                         0x02);
3932                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
3933                         0x00);
3934                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
3935                                 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
3936                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
3937                                 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
3938
3939                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3940                         0x40 | cmd_idx);
3941                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF,
3942                         srb->cmnd[3]);
3943                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF,
3944                         srb->cmnd[4]);
3945                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF,
3946                         srb->cmnd[5]);
3947                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF,
3948                         srb->cmnd[6]);
3949
3950                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
3951                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
3952
3953                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
3954                              0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3955                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3956                         SD_TRANSFER_END, SD_TRANSFER_END);
3957
3958                 rtsx_send_cmd_no_wait(chip);
3959
3960                 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
3961                                         scsi_bufflen(srb), scsi_sg_count(srb),
3962                                         DMA_FROM_DEVICE, 10000);
3963                 if (retval < 0) {
3964                         read_err = 1;
3965                         rtsx_clear_sd_error(chip);
3966                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3967                 }
3968
3969         } else {
3970                 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3971         }
3972
3973         retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type);
3974         if (retval != STATUS_SUCCESS)
3975                 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3976
3977         if (standby) {
3978                 retval = sd_select_card(chip, 1);
3979                 if (retval != STATUS_SUCCESS)
3980                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3981         }
3982
3983         if (send_cmd12) {
3984                 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
3985                                 0, SD_RSP_TYPE_R1b, NULL, 0, 0);
3986                 if (retval != STATUS_SUCCESS)
3987                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3988         }
3989
3990         if (data_len < 512) {
3991                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
3992                                 SD_RSP_TYPE_R1, NULL, 0, 0);
3993                 if (retval != STATUS_SUCCESS)
3994                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3995
3996                 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
3997                 if (retval != STATUS_SUCCESS)
3998                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3999
4000                 retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4001                 if (retval != STATUS_SUCCESS)
4002                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4003         }
4004
4005         if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
4006                 cmd13_checkbit = 1;
4007
4008         for (i = 0; i < 3; i++) {
4009                 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS,
4010                                                 sd_card->sd_addr,
4011                                                 SD_RSP_TYPE_R1, NULL, 0,
4012                                                 cmd13_checkbit);
4013                 if (retval == STATUS_SUCCESS)
4014                         break;
4015         }
4016         if (retval != STATUS_SUCCESS)
4017                 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4018
4019         scsi_set_resid(srb, 0);
4020         return TRANSPORT_GOOD;
4021
4022 SD_Execute_Read_Cmd_Failed:
4023         sd_card->pre_cmd_err = 1;
4024         set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4025         if (read_err)
4026                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4027
4028         release_sd_card(chip);
4029         do_reset_sd_card(chip);
4030         if (!(chip->card_ready & SD_CARD))
4031                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4032
4033         TRACE_RET(chip, TRANSPORT_FAILED);
4034 }
4035
4036 int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4037 {
4038         struct sd_info *sd_card = &(chip->sd_card);
4039         unsigned int lun = SCSI_LUN(srb);
4040         int retval, rsp_len, i;
4041         int cmd13_checkbit = 0, write_err = 0;
4042         u8 cmd_idx, rsp_type;
4043         u8 send_cmd12 = 0, standby = 0, acmd = 0;
4044         u32 data_len, arg;
4045 #ifdef SUPPORT_SD_LOCK
4046         int lock_cmd_fail = 0;
4047         u8 sd_lock_state = 0;
4048         u8 lock_cmd_type = 0;
4049 #endif
4050
4051         if (!sd_card->sd_pass_thru_en) {
4052                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4053                 TRACE_RET(chip, TRANSPORT_FAILED);
4054         }
4055
4056         if (sd_card->pre_cmd_err) {
4057                 sd_card->pre_cmd_err = 0;
4058                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4059                 TRACE_RET(chip, TRANSPORT_FAILED);
4060         }
4061
4062         retval = sd_switch_clock(chip);
4063         if (retval != STATUS_SUCCESS)
4064                 TRACE_RET(chip, TRANSPORT_FAILED);
4065
4066         cmd_idx = srb->cmnd[2] & 0x3F;
4067         if (srb->cmnd[1] & 0x04)
4068                 send_cmd12 = 1;
4069
4070         if (srb->cmnd[1] & 0x02)
4071                 standby = 1;
4072
4073         if (srb->cmnd[1] & 0x01)
4074                 acmd = 1;
4075
4076         data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8]
4077                                                 << 8) | srb->cmnd[9];
4078         arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
4079                 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
4080
4081 #ifdef SUPPORT_SD_LOCK
4082         if (cmd_idx == LOCK_UNLOCK) {
4083                 sd_lock_state = sd_card->sd_lock_status;
4084                 sd_lock_state &= SD_LOCKED;
4085         }
4086 #endif
4087
4088         retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4089         if (retval != STATUS_SUCCESS) {
4090                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4091                 TRACE_RET(chip, TRANSPORT_FAILED);
4092         }
4093         sd_card->last_rsp_type = rsp_type;
4094
4095         retval = sd_switch_clock(chip);
4096         if (retval != STATUS_SUCCESS)
4097                 TRACE_RET(chip, TRANSPORT_FAILED);
4098
4099 #ifdef SUPPORT_SD_LOCK
4100         if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4101                 if (CHK_MMC_8BIT(sd_card)) {
4102                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4103                                                 SD_BUS_WIDTH_8);
4104                         if (retval != STATUS_SUCCESS)
4105                                 TRACE_RET(chip, TRANSPORT_FAILED);
4106
4107                 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4108                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4109                                                 SD_BUS_WIDTH_4);
4110                         if (retval != STATUS_SUCCESS)
4111                                 TRACE_RET(chip, TRANSPORT_FAILED);
4112                 }
4113         }
4114 #else
4115         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4116         if (retval != STATUS_SUCCESS)
4117                 TRACE_RET(chip, TRANSPORT_FAILED);
4118 #endif
4119
4120         if (data_len < 512) {
4121                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4122                                 SD_RSP_TYPE_R1, NULL, 0, 0);
4123                 if (retval != STATUS_SUCCESS)
4124                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4125         }
4126
4127         if (standby) {
4128                 retval = sd_select_card(chip, 0);
4129                 if (retval != STATUS_SUCCESS)
4130                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4131         }
4132
4133         if (acmd) {
4134                 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
4135                                                 sd_card->sd_addr,
4136                                                 SD_RSP_TYPE_R1, NULL, 0, 0);
4137                 if (retval != STATUS_SUCCESS)
4138                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4139         }
4140
4141         retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
4142                         sd_card->rsp, rsp_len, 0);
4143         if (retval != STATUS_SUCCESS)
4144                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4145
4146         if (data_len <= 512) {
4147                 u16 i;
4148                 u8 *buf;
4149
4150                 buf = kmalloc(data_len, GFP_KERNEL);
4151                 if (buf == NULL)
4152                         TRACE_RET(chip, TRANSPORT_ERROR);
4153
4154                 rtsx_stor_get_xfer_buf(buf, data_len, srb);
4155
4156 #ifdef SUPPORT_SD_LOCK
4157                 if (cmd_idx == LOCK_UNLOCK)
4158                         lock_cmd_type = buf[0] & 0x0F;
4159 #endif
4160
4161                 if (data_len > 256) {
4162                         rtsx_init_cmd(chip);
4163                         for (i = 0; i < 256; i++) {
4164                                 rtsx_add_cmd(chip, WRITE_REG_CMD,
4165                                                 PPBUF_BASE2 + i, 0xFF, buf[i]);
4166                         }
4167                         retval = rtsx_send_cmd(chip, 0, 250);
4168                         if (retval != STATUS_SUCCESS) {
4169                                 kfree(buf);
4170                                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4171                         }
4172
4173                         rtsx_init_cmd(chip);
4174                         for (i = 256; i < data_len; i++) {
4175                                 rtsx_add_cmd(chip, WRITE_REG_CMD,
4176                                                 PPBUF_BASE2 + i, 0xFF, buf[i]);
4177                         }
4178                         retval = rtsx_send_cmd(chip, 0, 250);
4179                         if (retval != STATUS_SUCCESS) {
4180                                 kfree(buf);
4181                                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4182                         }
4183                 } else {
4184                         rtsx_init_cmd(chip);
4185                         for (i = 0; i < data_len; i++) {
4186                                 rtsx_add_cmd(chip, WRITE_REG_CMD,
4187                                                 PPBUF_BASE2 + i, 0xFF, buf[i]);
4188                         }
4189                         retval = rtsx_send_cmd(chip, 0, 250);
4190                         if (retval != STATUS_SUCCESS) {
4191                                 kfree(buf);
4192                                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4193                         }
4194                 }
4195
4196                 kfree(buf);
4197
4198                 rtsx_init_cmd(chip);
4199
4200                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4201                         srb->cmnd[8] & 0x03);
4202                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4203                         srb->cmnd[9]);
4204                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
4205                         0x00);
4206                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
4207                         0x01);
4208                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
4209                         PINGPONG_BUFFER);
4210
4211                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4212                              SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4213                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4214                         SD_TRANSFER_END, SD_TRANSFER_END);
4215
4216                 retval = rtsx_send_cmd(chip, SD_CARD, 250);
4217         } else if (!(data_len & 0x1FF)) {
4218                 rtsx_init_cmd(chip);
4219
4220                 trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512);
4221
4222                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4223                         0x02);
4224                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4225                         0x00);
4226                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4227                                 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4228                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4229                                 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4230
4231                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4232                         SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4233                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4234                         SD_TRANSFER_END, SD_TRANSFER_END);
4235
4236                 rtsx_send_cmd_no_wait(chip);
4237
4238                 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
4239                                         scsi_bufflen(srb), scsi_sg_count(srb),
4240                                         DMA_TO_DEVICE, 10000);
4241
4242         } else {
4243                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4244         }
4245
4246         if (retval < 0) {
4247                 write_err = 1;
4248                 rtsx_clear_sd_error(chip);
4249                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4250         }
4251
4252 #ifdef SUPPORT_SD_LOCK
4253         if (cmd_idx == LOCK_UNLOCK) {
4254                 if (lock_cmd_type == SD_ERASE) {
4255                         sd_card->sd_erase_status = SD_UNDER_ERASING;
4256                         scsi_set_resid(srb, 0);
4257                         return TRANSPORT_GOOD;
4258                 }
4259
4260                 rtsx_init_cmd(chip);
4261                 rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02);
4262
4263                 rtsx_send_cmd(chip, SD_CARD, 250);
4264
4265                 retval = sd_update_lock_status(chip);
4266                 if (retval != STATUS_SUCCESS) {
4267                         dev_dbg(rtsx_dev(chip), "Lock command fail!\n");
4268                         lock_cmd_fail = 1;
4269                 }
4270         }
4271 #endif /* SUPPORT_SD_LOCK */
4272
4273         if (standby) {
4274                 retval = sd_select_card(chip, 1);
4275                 if (retval != STATUS_SUCCESS)
4276                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4277         }
4278
4279         if (send_cmd12) {
4280                 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
4281                                 0, SD_RSP_TYPE_R1b, NULL, 0, 0);
4282                 if (retval != STATUS_SUCCESS)
4283                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4284         }
4285
4286         if (data_len < 512) {
4287                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4288                                 SD_RSP_TYPE_R1, NULL, 0, 0);
4289                 if (retval != STATUS_SUCCESS)
4290                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4291
4292                 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4293                 if (retval != STATUS_SUCCESS)
4294                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4295
4296                 rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4297                 if (retval != STATUS_SUCCESS)
4298                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4299         }
4300
4301         if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
4302                 cmd13_checkbit = 1;
4303
4304         for (i = 0; i < 3; i++) {
4305                 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS,
4306                                                 sd_card->sd_addr,
4307                                                 SD_RSP_TYPE_R1, NULL, 0,
4308                                                 cmd13_checkbit);
4309                 if (retval == STATUS_SUCCESS)
4310                         break;
4311         }
4312         if (retval != STATUS_SUCCESS)
4313                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4314
4315 #ifdef SUPPORT_SD_LOCK
4316         if (cmd_idx == LOCK_UNLOCK) {
4317                 if (!lock_cmd_fail) {
4318                         dev_dbg(rtsx_dev(chip), "lock_cmd_type = 0x%x\n",
4319                                 lock_cmd_type);
4320                         if (lock_cmd_type & SD_CLR_PWD)
4321                                 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
4322
4323                         if (lock_cmd_type & SD_SET_PWD)
4324                                 sd_card->sd_lock_status |= SD_PWD_EXIST;
4325                 }
4326
4327                 dev_dbg(rtsx_dev(chip), "sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n",
4328                         sd_lock_state, sd_card->sd_lock_status);
4329                 if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) {
4330                         sd_card->sd_lock_notify = 1;
4331                         if (sd_lock_state) {
4332                                 if (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) {
4333                                         sd_card->sd_lock_status |= (
4334                                                 SD_UNLOCK_POW_ON | SD_SDR_RST);
4335                                         if (CHK_SD(sd_card)) {
4336                                                 retval = reset_sd(chip);
4337                                                 if (retval != STATUS_SUCCESS) {
4338                                                         sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4339                                                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4340                                                 }
4341                                         }
4342
4343                                         sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4344                                 }
4345                         }
4346                 }
4347         }
4348
4349         if (lock_cmd_fail) {
4350                 scsi_set_resid(srb, 0);
4351                 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4352                 TRACE_RET(chip, TRANSPORT_FAILED);
4353         }
4354 #endif  /* SUPPORT_SD_LOCK */
4355
4356         scsi_set_resid(srb, 0);
4357         return TRANSPORT_GOOD;
4358
4359 SD_Execute_Write_Cmd_Failed:
4360         sd_card->pre_cmd_err = 1;
4361         set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4362         if (write_err)
4363                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
4364
4365         release_sd_card(chip);
4366         do_reset_sd_card(chip);
4367         if (!(chip->card_ready & SD_CARD))
4368                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4369
4370         TRACE_RET(chip, TRANSPORT_FAILED);
4371 }
4372
4373 int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4374 {
4375         struct sd_info *sd_card = &(chip->sd_card);
4376         unsigned int lun = SCSI_LUN(srb);
4377         int count;
4378         u16 data_len;
4379
4380         if (!sd_card->sd_pass_thru_en) {
4381                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4382                 TRACE_RET(chip, TRANSPORT_FAILED);
4383         }
4384
4385         if (sd_card->pre_cmd_err) {
4386                 sd_card->pre_cmd_err = 0;
4387                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4388                 TRACE_RET(chip, TRANSPORT_FAILED);
4389         }
4390
4391         data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8];
4392
4393         if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) {
4394                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4395                 TRACE_RET(chip, TRANSPORT_FAILED);
4396         } else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) {
4397                 count = (data_len < 17) ? data_len : 17;
4398         } else {
4399                 count = (data_len < 6) ? data_len : 6;
4400         }
4401         rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb);
4402
4403         dev_dbg(rtsx_dev(chip), "Response length: %d\n", data_len);
4404         dev_dbg(rtsx_dev(chip), "Response: 0x%x 0x%x 0x%x 0x%x\n",
4405                 sd_card->rsp[0], sd_card->rsp[1],
4406                 sd_card->rsp[2], sd_card->rsp[3]);
4407
4408         scsi_set_resid(srb, 0);
4409         return TRANSPORT_GOOD;
4410 }
4411
4412 int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4413 {
4414         struct sd_info *sd_card = &(chip->sd_card);
4415         unsigned int lun = SCSI_LUN(srb);
4416         int retval;
4417
4418         if (!sd_card->sd_pass_thru_en) {
4419                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4420                 TRACE_RET(chip, TRANSPORT_FAILED);
4421         }
4422
4423         if (sd_card->pre_cmd_err) {
4424                 sd_card->pre_cmd_err = 0;
4425                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4426                 TRACE_RET(chip, TRANSPORT_FAILED);
4427         }
4428
4429         if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) ||
4430                 (0x20 != srb->cmnd[4]) || (0x43 != srb->cmnd[5]) ||
4431                 (0x61 != srb->cmnd[6]) || (0x72 != srb->cmnd[7]) ||
4432                 (0x64 != srb->cmnd[8])) {
4433                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4434                 TRACE_RET(chip, TRANSPORT_FAILED);
4435         }
4436
4437         switch (srb->cmnd[1] & 0x0F) {
4438         case 0:
4439 #ifdef SUPPORT_SD_LOCK
4440                 if (0x64 == srb->cmnd[9])
4441                         sd_card->sd_lock_status |= SD_SDR_RST;
4442 #endif
4443                 retval = reset_sd_card(chip);
4444                 if (retval != STATUS_SUCCESS) {
4445 #ifdef SUPPORT_SD_LOCK
4446                         sd_card->sd_lock_status &= ~SD_SDR_RST;
4447 #endif
4448                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4449                         sd_card->pre_cmd_err = 1;
4450                         TRACE_RET(chip, TRANSPORT_FAILED);
4451                 }
4452 #ifdef SUPPORT_SD_LOCK
4453                 sd_card->sd_lock_status &= ~SD_SDR_RST;
4454 #endif
4455                 break;
4456
4457         case 1:
4458                 retval = soft_reset_sd_card(chip);
4459                 if (retval != STATUS_SUCCESS) {
4460                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4461                         sd_card->pre_cmd_err = 1;
4462                         TRACE_RET(chip, TRANSPORT_FAILED);
4463                 }
4464                 break;
4465
4466         default:
4467                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4468                 TRACE_RET(chip, TRANSPORT_FAILED);
4469         }
4470
4471         scsi_set_resid(srb, 0);
4472         return TRANSPORT_GOOD;
4473 }
4474 #endif
4475
4476 void sd_cleanup_work(struct rtsx_chip *chip)
4477 {
4478         struct sd_info *sd_card = &(chip->sd_card);
4479
4480         if (sd_card->seq_mode) {
4481                 dev_dbg(rtsx_dev(chip), "SD: stop transmission\n");
4482                 sd_stop_seq_mode(chip);
4483                 sd_card->cleanup_counter = 0;
4484         }
4485 }
4486
4487 int sd_power_off_card3v3(struct rtsx_chip *chip)
4488 {
4489         int retval;
4490
4491         retval = disable_card_clock(chip, SD_CARD);
4492         if (retval != STATUS_SUCCESS)
4493                 TRACE_RET(chip, STATUS_FAIL);
4494
4495         RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, 0);
4496
4497         if (!chip->ft2_fast_mode) {
4498                 retval = card_power_off(chip, SD_CARD);
4499                 if (retval != STATUS_SUCCESS)
4500                         TRACE_RET(chip, STATUS_FAIL);
4501
4502                 wait_timeout(50);
4503         }
4504
4505         if (chip->asic_code) {
4506                 retval = sd_pull_ctl_disable(chip);
4507                 if (retval != STATUS_SUCCESS)
4508                         TRACE_RET(chip, STATUS_FAIL);
4509         } else {
4510                 RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
4511                         FPGA_SD_PULL_CTL_BIT | 0x20, FPGA_SD_PULL_CTL_BIT);
4512         }
4513
4514         return STATUS_SUCCESS;
4515 }
4516
4517 int release_sd_card(struct rtsx_chip *chip)
4518 {
4519         struct sd_info *sd_card = &(chip->sd_card);
4520         int retval;
4521
4522         chip->card_ready &= ~SD_CARD;
4523         chip->card_fail &= ~SD_CARD;
4524         chip->card_wp &= ~SD_CARD;
4525
4526         chip->sd_io = 0;
4527         chip->sd_int = 0;
4528
4529 #ifdef SUPPORT_SD_LOCK
4530         sd_card->sd_lock_status = 0;
4531         sd_card->sd_erase_status = 0;
4532 #endif
4533
4534         memset(sd_card->raw_csd, 0, 16);
4535         memset(sd_card->raw_scr, 0, 8);
4536
4537         retval = sd_power_off_card3v3(chip);
4538         if (retval != STATUS_SUCCESS)
4539                 TRACE_RET(chip, STATUS_FAIL);
4540
4541         return STATUS_SUCCESS;
4542 }