drivers/staging/rts_pstor/sd.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   wwang (wei_wang@realsil.com.cn)
  20  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26
  27 #include "rtsx.h"
  28 #include "rtsx_transport.h"
  29 #include "rtsx_scsi.h"
  30 #include "rtsx_card.h"
  31 #include "sd.h"
  32
  33 #define SD_MAX_RETRY_COUNT      3
  34
  35 static u16 REG_SD_CFG1;
  36 static u16 REG_SD_CFG2;
  37 static u16 REG_SD_CFG3;
  38 static u16 REG_SD_STAT1;
  39 static u16 REG_SD_STAT2;
  40 static u16 REG_SD_BUS_STAT;
  41 static u16 REG_SD_PAD_CTL;
  42 static u16 REG_SD_SAMPLE_POINT_CTL;
  43 static u16 REG_SD_PUSH_POINT_CTL;
  44 static u16 REG_SD_CMD0;
  45 static u16 REG_SD_CMD1;
  46 static u16 REG_SD_CMD2;
  47 static u16 REG_SD_CMD3;
  48 static u16 REG_SD_CMD4;
  49 static u16 REG_SD_CMD5;
  50 static u16 REG_SD_BYTE_CNT_L;
  51 static u16 REG_SD_BYTE_CNT_H;
  52 static u16 REG_SD_BLOCK_CNT_L;
  53 static u16 REG_SD_BLOCK_CNT_H;
  54 static u16 REG_SD_TRANSFER;
  55 static u16 REG_SD_VPCLK0_CTL;
  56 static u16 REG_SD_VPCLK1_CTL;
  57 static u16 REG_SD_DCMPS0_CTL;
  58 static u16 REG_SD_DCMPS1_CTL;
  59
  60 static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code)
  61 {
  62         struct sd_info *sd_card = &(chip->sd_card);
  63
  64         sd_card->err_code |= err_code;
  65 }
  66
  67 static inline void sd_clr_err_code(struct rtsx_chip *chip)
  68 {
  69         struct sd_info *sd_card = &(chip->sd_card);
  70
  71         sd_card->err_code = 0;
  72 }
  73
  74 static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code)
  75 {
  76         struct sd_info *sd_card = &(chip->sd_card);
  77
  78         return sd_card->err_code & err_code;
  79 }
  80
  81 static void sd_init_reg_addr(struct rtsx_chip *chip)
  82 {
  83         if (CHECK_PID(chip, 0x5209)) {
  84                 REG_SD_CFG1 = SD_CFG1;
  85                 REG_SD_CFG2 = SD_CFG2;
  86                 REG_SD_CFG3 = SD_CFG3;
  87                 REG_SD_STAT1 = SD_STAT1;
  88                 REG_SD_STAT2 = SD_STAT2;
  89                 REG_SD_BUS_STAT = SD_BUS_STAT;
  90                 REG_SD_PAD_CTL = SD_PAD_CTL;
  91                 REG_SD_SAMPLE_POINT_CTL = SD_SAMPLE_POINT_CTL;
  92                 REG_SD_PUSH_POINT_CTL = SD_PUSH_POINT_CTL;
  93                 REG_SD_CMD0 = SD_CMD0;
  94                 REG_SD_CMD1 = SD_CMD1;
  95                 REG_SD_CMD2 = SD_CMD2;
  96                 REG_SD_CMD3 = SD_CMD3;
  97                 REG_SD_CMD4 = SD_CMD4;
  98                 REG_SD_CMD5 = SD_CMD5;
  99                 REG_SD_BYTE_CNT_L = SD_BYTE_CNT_L;
 100                 REG_SD_BYTE_CNT_H = SD_BYTE_CNT_H;
 101                 REG_SD_BLOCK_CNT_L = SD_BLOCK_CNT_L;
 102                 REG_SD_BLOCK_CNT_H = SD_BLOCK_CNT_H;
 103                 REG_SD_TRANSFER = SD_TRANSFER;
 104                 REG_SD_VPCLK0_CTL = SD_VPCLK0_CTL;
 105                 REG_SD_VPCLK1_CTL = SD_VPCLK1_CTL;
 106                 REG_SD_DCMPS0_CTL = SD_DCMPS0_CTL;
 107                 REG_SD_DCMPS1_CTL = SD_DCMPS1_CTL;
 108         } else {
 109                 REG_SD_CFG1 = 0xFD31;
 110                 REG_SD_CFG2 = 0xFD33;
 111                 REG_SD_CFG3 = 0xFD3E;
 112                 REG_SD_STAT1 = 0xFD30;
 113                 REG_SD_STAT2 = 0;
 114                 REG_SD_BUS_STAT = 0;
 115                 REG_SD_PAD_CTL = 0;
 116                 REG_SD_SAMPLE_POINT_CTL = 0;
 117                 REG_SD_PUSH_POINT_CTL = 0;
 118                 REG_SD_CMD0 = 0xFD34;
 119                 REG_SD_CMD1 = 0xFD35;
 120                 REG_SD_CMD2 = 0xFD36;
 121                 REG_SD_CMD3 = 0xFD37;
 122                 REG_SD_CMD4 = 0xFD38;
 123                 REG_SD_CMD5 = 0xFD5A;
 124                 REG_SD_BYTE_CNT_L = 0xFD39;
 125                 REG_SD_BYTE_CNT_H = 0xFD3A;
 126                 REG_SD_BLOCK_CNT_L = 0xFD3B;
 127                 REG_SD_BLOCK_CNT_H = 0xFD3C;
 128                 REG_SD_TRANSFER = 0xFD32;
 129                 REG_SD_VPCLK0_CTL = 0;
 130                 REG_SD_VPCLK1_CTL = 0;
 131                 REG_SD_DCMPS0_CTL = 0;
 132                 REG_SD_DCMPS1_CTL = 0;
 133         }
 134 }
 135
 136 static int sd_check_data0_status(struct rtsx_chip *chip)
 137 {
 138         u8 stat;
 139
 140         if (CHECK_PID(chip, 0x5209))
 141                 RTSX_READ_REG(chip, REG_SD_BUS_STAT, &stat);
 142         else
 143                 RTSX_READ_REG(chip, REG_SD_STAT1, &stat);
 144
 145         if (!(stat & SD_DAT0_STATUS)) {
 146                 sd_set_err_code(chip, SD_BUSY);
 147                 TRACE_RET(chip, STATUS_FAIL);
 148         }
 149
 150         return STATUS_SUCCESS;
 151 }
 152
 153 static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
 154                 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
 155 {
 156         struct sd_info *sd_card = &(chip->sd_card);
 157         int retval;
 158         int timeout = 100;
 159         u16 reg_addr;
 160         u8 *ptr;
 161         int stat_idx = 0;
 162         int rty_cnt = 0;
 163
 164         sd_clr_err_code(chip);
 165
 166         RTSX_DEBUGP("SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg);
 167
 168         if (rsp_type == SD_RSP_TYPE_R1b)
 169                 timeout = 3000;
 170
 171 RTY_SEND_CMD:
 172
 173         rtsx_init_cmd(chip);
 174
 175         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
 176         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
 177         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
 178         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
 179         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
 180
 181         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
 182         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
 183                         0x01, PINGPONG_BUFFER);
 184         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
 185                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
 186         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
 187                      SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END | SD_STAT_IDLE);
 188
 189         if (rsp_type == SD_RSP_TYPE_R2) {
 190                 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++)
 191                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
 192
 193                 stat_idx = 16;
 194         } else if (rsp_type != SD_RSP_TYPE_R0) {
 195                 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++)
 196                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
 197
 198                 stat_idx = 5;
 199         }
 200
 201         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
 202
 203         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
 204         if (retval < 0) {
 205                 u8 val;
 206
 207                 rtsx_read_register(chip, REG_SD_STAT1, &val);
 208                 RTSX_DEBUGP("SD_STAT1: 0x%x\n", val);
 209
 210                 if (CHECK_PID(chip, 0x5209)) {
 211                         rtsx_read_register(chip, REG_SD_STAT2, &val);
 212                         RTSX_DEBUGP("SD_STAT2: 0x%x\n", val);
 213
 214                         if (val & SD_RSP_80CLK_TIMEOUT) {
 215                                 rtsx_clear_sd_error(chip);
 216                                 sd_set_err_code(chip, SD_RSP_TIMEOUT);
 217                                 TRACE_RET(chip, STATUS_FAIL);
 218                         }
 219
 220                         rtsx_read_register(chip, REG_SD_BUS_STAT, &val);
 221                         RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", val);
 222                 } else {
 223                         rtsx_read_register(chip, REG_SD_CFG3, &val);
 224                         RTSX_DEBUGP("SD_CFG3: 0x%x\n", val);
 225                 }
 226
 227                 if (retval == -ETIMEDOUT) {
 228                         if (rsp_type & SD_WAIT_BUSY_END) {
 229                                 retval = sd_check_data0_status(chip);
 230                                 if (retval != STATUS_SUCCESS) {
 231                                         rtsx_clear_sd_error(chip);
 232                                         TRACE_RET(chip, retval);
 233                                 }
 234                         } else {
 235                                 sd_set_err_code(chip, SD_TO_ERR);
 236                         }
 237                         retval = STATUS_TIMEDOUT;
 238                 } else {
 239                         retval = STATUS_FAIL;
 240                 }
 241                 rtsx_clear_sd_error(chip);
 242
 243                 TRACE_RET(chip, retval);
 244         }
 245
 246         if (rsp_type == SD_RSP_TYPE_R0)
 247                 return STATUS_SUCCESS;
 248
 249         ptr = rtsx_get_cmd_data(chip) + 1;
 250
 251         if ((ptr[0] & 0xC0) != 0) {
 252                 sd_set_err_code(chip, SD_STS_ERR);
 253                 TRACE_RET(chip, STATUS_FAIL);
 254         }
 255
 256         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 257                 if (ptr[stat_idx] & SD_CRC7_ERR) {
 258                         if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
 259                                 sd_set_err_code(chip, SD_CRC_ERR);
 260                                 TRACE_RET(chip, STATUS_FAIL);
 261                         }
 262                         if (rty_cnt < SD_MAX_RETRY_COUNT) {
 263                                 wait_timeout(20);
 264                                 rty_cnt++;
 265                                 goto RTY_SEND_CMD;
 266                         } else {
 267                                 sd_set_err_code(chip, SD_CRC_ERR);
 268                                 TRACE_RET(chip, STATUS_FAIL);
 269                         }
 270                 }
 271         }
 272
 273         if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) {
 274                 if ((cmd_idx != SEND_RELATIVE_ADDR) && (cmd_idx != SEND_IF_COND)) {
 275                         if (cmd_idx != STOP_TRANSMISSION) {
 276                                 if (ptr[1] & 0x80)
 277                                         TRACE_RET(chip, STATUS_FAIL);
 278                         }
 279 #ifdef SUPPORT_SD_LOCK
 280                         if (ptr[1] & 0x7D)
 281 #else
 282                         if (ptr[1] & 0x7F)
 283 #endif
 284                         {
 285                                 RTSX_DEBUGP("ptr[1]: 0x%02x\n", ptr[1]);
 286                                 TRACE_RET(chip, STATUS_FAIL);
 287                         }
 288                         if (ptr[2] & 0xFF) {
 289                                 RTSX_DEBUGP("ptr[2]: 0x%02x\n", ptr[2]);
 290                                 TRACE_RET(chip, STATUS_FAIL);
 291                         }
 292                         if (ptr[3] & 0x80) {
 293                                 RTSX_DEBUGP("ptr[3]: 0x%02x\n", ptr[3]);
 294                                 TRACE_RET(chip, STATUS_FAIL);
 295                         }
 296                         if (ptr[3] & 0x01)
 297                                 sd_card->sd_data_buf_ready = 1;
 298                         else
 299                                 sd_card->sd_data_buf_ready = 0;
 300                 }
 301         }
 302
 303         if (rsp && rsp_len)
 304                 memcpy(rsp, ptr, rsp_len);
 305
 306         return STATUS_SUCCESS;
 307 }
 308
 309 static int sd_read_data(struct rtsx_chip *chip,
 310                         u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt,
 311                         u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len,
 312                         int timeout)
 313 {
 314         struct sd_info *sd_card = &(chip->sd_card);
 315         int retval;
 316         int i;
 317
 318         sd_clr_err_code(chip);
 319
 320         if (!buf)
 321                 buf_len = 0;
 322
 323         if (buf_len > 512)
 324                 TRACE_RET(chip, STATUS_FAIL);
 325
 326         rtsx_init_cmd(chip);
 327
 328         if (cmd_len) {
 329                 RTSX_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
 330                 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++)
 331                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i, 0xFF, cmd[i]);
 332         }
 333         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
 334         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8));
 335         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)blk_cnt);
 336         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(blk_cnt >> 8));
 337
 338         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
 339
 340         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
 341                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
 342                         SD_CHECK_CRC7 | SD_RSP_LEN_6);
 343         if (trans_mode != SD_TM_AUTO_TUNING)
 344                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
 345
 346         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START);
 347         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
 348
 349         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
 350         if (retval < 0) {
 351                 if (retval == -ETIMEDOUT) {
 352                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
 353                                             SD_RSP_TYPE_R1, NULL, 0);
 354                 }
 355
 356                 TRACE_RET(chip, STATUS_FAIL);
 357         }
 358
 359         if (buf && buf_len) {
 360                 retval = rtsx_read_ppbuf(chip, buf, buf_len);
 361                 if (retval != STATUS_SUCCESS)
 362                         TRACE_RET(chip, STATUS_FAIL);
 363         }
 364
 365         return STATUS_SUCCESS;
 366 }
 367
 368 static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode,
 369                 u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt, u8 bus_width,
 370                 u8 *buf, int buf_len, int timeout)
 371 {
 372         struct sd_info *sd_card = &(chip->sd_card);
 373         int retval;
 374         int i;
 375
 376         sd_clr_err_code(chip);
 377
 378         if (!buf)
 379                 buf_len = 0;
 380
 381         if (buf_len > 512) {
 382                 /* This function can't write data more than one page */
 383                 TRACE_RET(chip, STATUS_FAIL);
 384         }
 385
 386         if (buf && buf_len) {
 387                 retval = rtsx_write_ppbuf(chip, buf, buf_len);
 388                 if (retval != STATUS_SUCCESS)
 389                         TRACE_RET(chip, STATUS_FAIL);
 390         }
 391
 392         rtsx_init_cmd(chip);
 393
 394         if (cmd_len) {
 395                 RTSX_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
 396                 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
 397                         rtsx_add_cmd(chip, WRITE_REG_CMD,
 398                                      REG_SD_CMD0 + i, 0xFF, cmd[i]);
 399                 }
 400         }
 401         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
 402         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8));
 403         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)blk_cnt);
 404         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(blk_cnt >> 8));
 405
 406         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
 407
 408         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
 409                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
 410                 SD_CHECK_CRC7 | SD_RSP_LEN_6);
 411
 412         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START);
 413         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
 414
 415         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
 416         if (retval < 0) {
 417                 if (retval == -ETIMEDOUT) {
 418                         sd_send_cmd_get_rsp(chip, SEND_STATUS,
 419                                 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
 420                 }
 421
 422                 TRACE_RET(chip, STATUS_FAIL);
 423         }
 424
 425         return STATUS_SUCCESS;
 426 }
 427
 428 static int sd_check_csd(struct rtsx_chip *chip, char check_wp)
 429 {
 430         struct sd_info *sd_card = &(chip->sd_card);
 431         int retval;
 432         int i;
 433         u8 csd_ver, trans_speed;
 434         u8 rsp[16];
 435
 436         for (i = 0; i < 6; i++) {
 437                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
 438                         sd_set_err_code(chip, SD_NO_CARD);
 439                         TRACE_RET(chip, STATUS_FAIL);
 440                 }
 441
 442                 retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr, SD_RSP_TYPE_R2, rsp, 16);
 443                 if (retval == STATUS_SUCCESS)
 444                         break;
 445         }
 446
 447         if (i == 6)
 448                 TRACE_RET(chip, STATUS_FAIL);
 449
 450         memcpy(sd_card->raw_csd, rsp + 1, 15);
 451
 452         if (CHECK_PID(chip, 0x5209))
 453                 RTSX_READ_REG(chip, REG_SD_CMD5, sd_card->raw_csd + 15);
 454
 455         RTSX_DEBUGP("CSD Response:\n");
 456         RTSX_DUMP(sd_card->raw_csd, 16);
 457
 458         csd_ver = (rsp[1] & 0xc0) >> 6;
 459         RTSX_DEBUGP("csd_ver = %d\n", csd_ver);
 460
 461         trans_speed = rsp[4];
 462         if ((trans_speed & 0x07) == 0x02) {
 463                 if ((trans_speed & 0xf8) >= 0x30) {
 464                         if (chip->asic_code)
 465                                 sd_card->sd_clock = 47;
 466                         else
 467                                 sd_card->sd_clock = CLK_50;
 468
 469                 } else if ((trans_speed & 0xf8) == 0x28) {
 470                         if (chip->asic_code)
 471                                 sd_card->sd_clock = 39;
 472                         else
 473                                 sd_card->sd_clock = CLK_40;
 474
 475                 } else if ((trans_speed & 0xf8) == 0x20) {
 476                         if (chip->asic_code)
 477                                 sd_card->sd_clock = 29;
 478                         else
 479                                 sd_card->sd_clock = CLK_30;
 480
 481                 } else if ((trans_speed & 0xf8) >= 0x10) {
 482                         if (chip->asic_code)
 483                                 sd_card->sd_clock = 23;
 484                         else
 485                                 sd_card->sd_clock = CLK_20;
 486
 487                 } else if ((trans_speed & 0x08) >= 0x08) {
 488                         if (chip->asic_code)
 489                                 sd_card->sd_clock = 19;
 490                         else
 491                                 sd_card->sd_clock = CLK_20;
 492                 } else {
 493                         TRACE_RET(chip, STATUS_FAIL);
 494                 }
 495         } else {
 496                 TRACE_RET(chip, STATUS_FAIL);
 497         }
 498
 499         if (CHK_MMC_SECTOR_MODE(sd_card)) {
 500                 sd_card->capacity = 0;
 501         } else {
 502                 if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) {
 503                         u8 blk_size, c_size_mult;
 504                         u16 c_size;
 505                         blk_size = rsp[6] & 0x0F;
 506                         c_size =  ((u16)(rsp[7] & 0x03) << 10)
 507                                         + ((u16)rsp[8] << 2)
 508                                         + ((u16)(rsp[9] & 0xC0) >> 6);
 509                         c_size_mult = (u8)((rsp[10] & 0x03) << 1);
 510                         c_size_mult += (rsp[11] & 0x80) >> 7;
 511                         sd_card->capacity = (((u32)(c_size + 1)) * (1 << (c_size_mult + 2))) << (blk_size - 9);
 512                 } else {
 513                         u32 total_sector = 0;
 514                         total_sector = (((u32)rsp[8] & 0x3f) << 16) |
 515                                 ((u32)rsp[9] << 8) | (u32)rsp[10];
 516                         sd_card->capacity = (total_sector + 1) << 10;
 517                 }
 518         }
 519
 520         if (check_wp) {
 521                 if (rsp[15] & 0x30)
 522                         chip->card_wp |= SD_CARD;
 523
 524                 RTSX_DEBUGP("CSD WP Status: 0x%x\n", rsp[15]);
 525         }
 526
 527         return STATUS_SUCCESS;
 528 }
 529
 530 static int sd_set_sample_push_timing(struct rtsx_chip *chip)
 531 {
 532         struct sd_info *sd_card = &(chip->sd_card);
 533
 534         if (CHECK_PID(chip, 0x5209)) {
 535                 if (CHK_SD_SDR104(sd_card) || CHK_SD_SDR50(sd_card)) {
 536                         RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST,
 537                                         SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
 538                         RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
 539                         RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
 540                                         CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 541                         RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
 542                 } else if (CHK_SD_DDR50(sd_card) || CHK_MMC_DDR52(sd_card)) {
 543                         RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST,
 544                                         SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
 545                         RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
 546                         RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
 547                                         CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 548                         RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
 549                         RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, DDR_VAR_TX_CMD_DAT,
 550                                         DDR_VAR_TX_CMD_DAT);
 551                         RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
 552                                         DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
 553                 } else {
 554                         u8 val = 0;
 555
 556                         RTSX_WRITE_REG(chip, SD_CFG1, 0x0C, SD_20_MODE);
 557                         RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
 558                         RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
 559                                         CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
 560                         RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
 561
 562                         if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_AUTO)
 563                                 val = SD20_TX_NEG_EDGE;
 564                         else if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY)
 565                                 val = SD20_TX_14_AHEAD;
 566                         else
 567                                 val = SD20_TX_NEG_EDGE;
 568
 569                         RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, SD20_TX_SEL_MASK, val);
 570
 571                         if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
 572                                 if (chip->asic_code) {
 573                                         if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card))
 574                                                 val = SD20_RX_14_DELAY;
 575                                         else
 576                                                 val = SD20_RX_POS_EDGE;
 577                                 } else {
 578                                         val = SD20_RX_14_DELAY;
 579                                 }
 580                         } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_DELAY) {
 581                                 val = SD20_RX_14_DELAY;
 582                         } else {
 583                                 val = SD20_RX_POS_EDGE;
 584                         }
 585                         RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, SD20_RX_SEL_MASK, val);
 586                 }
 587         } else {
 588                 u8 val = 0;
 589
 590                 if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY)
 591                         val |= 0x10;
 592
 593                 if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
 594                         if (chip->asic_code) {
 595                                 if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
 596                                         if (val & 0x10)
 597                                                 val |= 0x04;
 598                                         else
 599                                                 val |= 0x08;
 600                                 }
 601                         } else {
 602                                 if (val & 0x10)
 603                                         val |= 0x04;
 604                                 else
 605                                         val |= 0x08;
 606                         }
 607                 } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_DELAY) {
 608                         if (val & 0x10)
 609                                 val |= 0x04;
 610                         else
 611                                 val |= 0x08;
 612                 }
 613
 614                 RTSX_WRITE_REG(chip, REG_SD_CFG1, 0x1C, val);
 615         }
 616
 617         return STATUS_SUCCESS;
 618 }
 619
 620 static void sd_choose_proper_clock(struct rtsx_chip *chip)
 621 {
 622         struct sd_info *sd_card = &(chip->sd_card);
 623
 624         if (CHK_SD_SDR104(sd_card)) {
 625                 if (chip->asic_code)
 626                         sd_card->sd_clock = chip->asic_sd_sdr104_clk;
 627                 else
 628                         sd_card->sd_clock = chip->fpga_sd_sdr104_clk;
 629
 630         } else if (CHK_SD_DDR50(sd_card)) {
 631                 if (chip->asic_code)
 632                         sd_card->sd_clock = chip->asic_sd_ddr50_clk;
 633                 else
 634                         sd_card->sd_clock = chip->fpga_sd_ddr50_clk;
 635
 636         } else if (CHK_SD_SDR50(sd_card)) {
 637                 if (chip->asic_code)
 638                         sd_card->sd_clock = chip->asic_sd_sdr50_clk;
 639                 else
 640                         sd_card->sd_clock = chip->fpga_sd_sdr50_clk;
 641
 642         } else if (CHK_SD_HS(sd_card)) {
 643                 if (chip->asic_code)
 644                         sd_card->sd_clock = chip->asic_sd_hs_clk;
 645                 else
 646                         sd_card->sd_clock = chip->fpga_sd_hs_clk;
 647
 648         } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
 649                 if (chip->asic_code)
 650                         sd_card->sd_clock = chip->asic_mmc_52m_clk;
 651                 else
 652                         sd_card->sd_clock = chip->fpga_mmc_52m_clk;
 653
 654         } else if (CHK_MMC_26M(sd_card)) {
 655                 if (chip->asic_code)
 656                         sd_card->sd_clock = 48;
 657                 else
 658                         sd_card->sd_clock = CLK_50;
 659         }
 660 }
 661
 662 static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div)
 663 {
 664         u8 mask = 0, val = 0;
 665
 666         if (CHECK_PID(chip, 0x5209)) {
 667                 mask = SD_CLK_DIVIDE_MASK;
 668                 val = clk_div;
 669         } else {
 670                 mask = 0x60;
 671                 if (clk_div == SD_CLK_DIVIDE_0)
 672                         val = 0x00;
 673                 else if (clk_div == SD_CLK_DIVIDE_128)
 674                         val = 0x40;
 675                 else if (clk_div == SD_CLK_DIVIDE_256)
 676                         val = 0x20;
 677         }
 678
 679         RTSX_WRITE_REG(chip, REG_SD_CFG1, mask, val);
 680
 681         return STATUS_SUCCESS;
 682 }
 683
 684 static int sd_set_init_para(struct rtsx_chip *chip)
 685 {
 686         struct sd_info *sd_card = &(chip->sd_card);
 687         int retval;
 688
 689         retval = sd_set_sample_push_timing(chip);
 690         if (retval != STATUS_SUCCESS)
 691                 TRACE_RET(chip, STATUS_FAIL);
 692
 693         sd_choose_proper_clock(chip);
 694
 695         retval = switch_clock(chip, sd_card->sd_clock);
 696         if (retval != STATUS_SUCCESS)
 697                 TRACE_RET(chip, STATUS_FAIL);
 698
 699         return STATUS_SUCCESS;
 700 }
 701
 702 int sd_select_card(struct rtsx_chip *chip, int select)
 703 {
 704         struct sd_info *sd_card = &(chip->sd_card);
 705         int retval;
 706         u8 cmd_idx, cmd_type;
 707         u32 addr;
 708
 709         if (select) {
 710                 cmd_idx = SELECT_CARD;
 711                 cmd_type = SD_RSP_TYPE_R1;
 712                 addr = sd_card->sd_addr;
 713         } else {
 714                 cmd_idx = DESELECT_CARD;
 715                 cmd_type = SD_RSP_TYPE_R0;
 716                 addr = 0;
 717         }
 718
 719         retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
 720         if (retval != STATUS_SUCCESS)
 721                 TRACE_RET(chip, STATUS_FAIL);
 722
 723         return STATUS_SUCCESS;
 724 }
 725
 726 #ifdef SUPPORT_SD_LOCK
 727 static int sd_update_lock_status(struct rtsx_chip *chip)
 728 {
 729         struct sd_info *sd_card = &(chip->sd_card);
 730         int retval;
 731         u8 rsp[5];
 732
 733         retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, 5);
 734         if (retval != STATUS_SUCCESS)
 735                 TRACE_RET(chip, STATUS_FAIL);
 736
 737         if (rsp[1] & 0x02)
 738                 sd_card->sd_lock_status |= SD_LOCKED;
 739         else
 740                 sd_card->sd_lock_status &= ~SD_LOCKED;
 741
 742         RTSX_DEBUGP("sd_card->sd_lock_status = 0x%x\n", sd_card->sd_lock_status);
 743
 744         if (rsp[1] & 0x01)
 745                 TRACE_RET(chip, STATUS_FAIL);
 746
 747         return STATUS_SUCCESS;
 748 }
 749 #endif
 750
 751 static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state, u8 data_ready, int polling_cnt)
 752 {
 753         struct sd_info *sd_card = &(chip->sd_card);
 754         int retval, i;
 755         u8 rsp[5];
 756
 757         for (i = 0; i < polling_cnt; i++) {
 758                 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
 759                                              sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, 5);
 760                 if (retval != STATUS_SUCCESS)
 761                         TRACE_RET(chip, STATUS_FAIL);
 762
 763                 if (((rsp[3] & 0x1E) == state) && ((rsp[3] & 0x01) == data_ready))
 764                         return STATUS_SUCCESS;
 765         }
 766
 767         TRACE_RET(chip, STATUS_FAIL);
 768 }
 769
 770 static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage)
 771 {
 772         int retval;
 773
 774         if (voltage == SD_IO_3V3) {
 775                 if (chip->asic_code) {
 776                         retval = rtsx_write_phy_register(chip, 0x08, 0x4FC0 | chip->phy_voltage);
 777                         if (retval != STATUS_SUCCESS) {
 778                                 TRACE_RET(chip, STATUS_FAIL);
 779                         }
 780                 } else {
 781                         RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, 0);
 782                 }
 783         } else if (voltage == SD_IO_1V8) {
 784                 if (chip->asic_code) {
 785                         retval = rtsx_write_phy_register(chip, 0x08, 0x4C40 | chip->phy_voltage);
 786                         if (retval != STATUS_SUCCESS) {
 787                                 TRACE_RET(chip, STATUS_FAIL);
 788                         }
 789                 } else {
 790                         RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, SD_IO_USING_1V8);
 791                 }
 792         } else {
 793                 TRACE_RET(chip, STATUS_FAIL);
 794         }
 795
 796         return STATUS_SUCCESS;
 797 }
 798
 799 static int sd_voltage_switch(struct rtsx_chip *chip)
 800 {
 801         int retval;
 802         u8 stat;
 803
 804         RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, SD_CLK_TOGGLE_EN);
 805
 806         retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1, NULL, 0);
 807         if (retval != STATUS_SUCCESS) {
 808                 TRACE_RET(chip, STATUS_FAIL);
 809         }
 810
 811         udelay(chip->sd_voltage_switch_delay);
 812
 813         RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
 814         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 815                                 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
 816                 TRACE_RET(chip, STATUS_FAIL);
 817         }
 818
 819         RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_FORCE_STOP);
 820         retval = sd_change_bank_voltage(chip, SD_IO_1V8);
 821         if (retval != STATUS_SUCCESS) {
 822                 TRACE_RET(chip, STATUS_FAIL);
 823         }
 824         wait_timeout(50);
 825
 826         RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
 827         wait_timeout(10);
 828
 829         RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
 830         if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 831                                 SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
 832                         (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
 833                                 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
 834                 RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", stat);
 835                 rtsx_write_register(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 836                 rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0);
 837                 TRACE_RET(chip, STATUS_FAIL);
 838         }
 839
 840         RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 841
 842         return STATUS_SUCCESS;
 843 }
 844
 845 static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir)
 846 {
 847         if (tune_dir == TUNE_RX) {
 848                 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_RX);
 849                 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RX);
 850         } else {
 851                 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_TX);
 852                 RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_TX);
 853         }
 854
 855         return STATUS_SUCCESS;
 856 }
 857
 858 static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
 859 {
 860         struct sd_info *sd_card = &(chip->sd_card);
 861         u16 SD_VP_CTL, SD_DCMPS_CTL;
 862         u8 val;
 863         int retval;
 864         int ddr_rx = 0;
 865
 866         RTSX_DEBUGP("sd_change_phase (sample_point = %d, tune_dir = %d)\n",
 867                                 sample_point, tune_dir);
 868
 869         if (tune_dir == TUNE_RX) {
 870                 SD_VP_CTL = SD_VPRX_CTL;
 871                 SD_DCMPS_CTL = SD_DCMPS_RX_CTL;
 872                 if (CHK_SD_DDR50(sd_card)) {
 873                         ddr_rx = 1;
 874                 }
 875         } else {
 876                 SD_VP_CTL = SD_VPTX_CTL;
 877                 SD_DCMPS_CTL = SD_DCMPS_TX_CTL;
 878         }
 879
 880         if (chip->asic_code) {
 881                 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 882                 RTSX_WRITE_REG(chip, SD_VP_CTL, 0x1F, sample_point);
 883                 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
 884                 RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET);
 885                 RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
 886         } else {
 887 #ifdef CONFIG_RTS_PSTOR_DEBUG
 888                 rtsx_read_register(chip, SD_VP_CTL, &val);
 889                 RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val);
 890                 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
 891                 RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
 892 #endif
 893
 894                 if (ddr_rx) {
 895                         RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, PHASE_CHANGE);
 896                         udelay(50);
 897                         RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
 898                                         PHASE_CHANGE | PHASE_NOT_RESET | sample_point);
 899                 } else {
 900                         RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 901                         udelay(50);
 902                         RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
 903                                         PHASE_NOT_RESET | sample_point);
 904                 }
 905                 udelay(100);
 906
 907                 rtsx_init_cmd(chip);
 908                 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE, DCMPS_CHANGE);
 909                 rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
 910                 retval = rtsx_send_cmd(chip, SD_CARD, 100);
 911                 if (retval != STATUS_SUCCESS) {
 912                         TRACE_GOTO(chip, Fail);
 913                 }
 914
 915                 val = *rtsx_get_cmd_data(chip);
 916                 if (val & DCMPS_ERROR) {
 917                         TRACE_GOTO(chip, Fail);
 918                 }
 919                 if ((val & DCMPS_CURRENT_PHASE) != sample_point) {
 920                         TRACE_GOTO(chip, Fail);
 921                 }
 922                 RTSX_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
 923                 if (ddr_rx) {
 924                         RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, 0);
 925                 } else {
 926                         RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
 927                 }
 928                 udelay(50);
 929         }
 930
 931         RTSX_WRITE_REG(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
 932
 933         return STATUS_SUCCESS;
 934
 935 Fail:
 936 #ifdef CONFIG_RTS_PSTOR_DEBUG
 937         rtsx_read_register(chip, SD_VP_CTL, &val);
 938         RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val);
 939         rtsx_read_register(chip, SD_DCMPS_CTL, &val);
 940         RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
 941 #endif
 942
 943         rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
 944         rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0);
 945         wait_timeout(10);
 946         sd_reset_dcm(chip, tune_dir);
 947         return STATUS_FAIL;
 948 }
 949
 950 static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width)
 951 {
 952         struct sd_info *sd_card = &(chip->sd_card);
 953         int retval;
 954         u8 cmd[5], buf[8];
 955
 956         retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
 957         if (retval != STATUS_SUCCESS) {
 958                 TRACE_RET(chip, STATUS_FAIL);
 959         }
 960
 961         cmd[0] = 0x40 | SEND_SCR;
 962         cmd[1] = 0;
 963         cmd[2] = 0;
 964         cmd[3] = 0;
 965         cmd[4] = 0;
 966
 967         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width, buf, 8, 250);
 968         if (retval != STATUS_SUCCESS) {
 969                 rtsx_clear_sd_error(chip);
 970                 TRACE_RET(chip, STATUS_FAIL);
 971         }
 972
 973         memcpy(sd_card->raw_scr, buf, 8);
 974
 975         if ((buf[0] & 0x0F) == 0) {
 976                 TRACE_RET(chip, STATUS_FAIL);
 977         }
 978
 979         return STATUS_SUCCESS;
 980 }
 981
 982 static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group, u8 func_to_switch,
 983                 u8 *buf, int buf_len)
 984 {
 985         u8 support_mask = 0, query_switch = 0, switch_busy = 0;
 986         int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
 987
 988         if (func_group == SD_FUNC_GROUP_1) {
 989                 support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
 990                 query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
 991                 check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
 992
 993                 switch (func_to_switch) {
 994                 case HS_SUPPORT:
 995                         support_mask = HS_SUPPORT_MASK;
 996                         query_switch = HS_QUERY_SWITCH_OK;
 997                         switch_busy = HS_SWITCH_BUSY;
 998                         break;
 999
1000                 case SDR50_SUPPORT:
1001                         support_mask = SDR50_SUPPORT_MASK;
1002                         query_switch = SDR50_QUERY_SWITCH_OK;
1003                         switch_busy = SDR50_SWITCH_BUSY;
1004                         break;
1005
1006                 case SDR104_SUPPORT:
1007                         support_mask = SDR104_SUPPORT_MASK;
1008                         query_switch = SDR104_QUERY_SWITCH_OK;
1009                         switch_busy = SDR104_SWITCH_BUSY;
1010                         break;
1011
1012                 case DDR50_SUPPORT:
1013                         support_mask = DDR50_SUPPORT_MASK;
1014                         query_switch = DDR50_QUERY_SWITCH_OK;
1015                         switch_busy = DDR50_SWITCH_BUSY;
1016                         break;
1017
1018                 default:
1019                         TRACE_RET(chip, STATUS_FAIL);
1020                 }
1021         } else if (func_group == SD_FUNC_GROUP_3) {
1022                 support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
1023                 query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
1024                 check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
1025
1026                 switch (func_to_switch) {
1027                 case DRIVING_TYPE_A:
1028                         support_mask = DRIVING_TYPE_A_MASK;
1029                         query_switch = TYPE_A_QUERY_SWITCH_OK;
1030                         switch_busy = TYPE_A_SWITCH_BUSY;
1031                         break;
1032
1033                 case DRIVING_TYPE_C:
1034                         support_mask = DRIVING_TYPE_C_MASK;
1035                         query_switch = TYPE_C_QUERY_SWITCH_OK;
1036                         switch_busy = TYPE_C_SWITCH_BUSY;
1037                         break;
1038
1039                 case DRIVING_TYPE_D:
1040                         support_mask = DRIVING_TYPE_D_MASK;
1041                         query_switch = TYPE_D_QUERY_SWITCH_OK;
1042                         switch_busy = TYPE_D_SWITCH_BUSY;
1043                         break;
1044
1045                 default:
1046                         TRACE_RET(chip, STATUS_FAIL);
1047                 }
1048         } else if (func_group == SD_FUNC_GROUP_4) {
1049                 support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
1050                 query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
1051                 check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
1052
1053                 switch (func_to_switch) {
1054                 case CURRENT_LIMIT_400:
1055                         support_mask = CURRENT_LIMIT_400_MASK;
1056                         query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
1057                         switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
1058                         break;
1059
1060                 case CURRENT_LIMIT_600:
1061                         support_mask = CURRENT_LIMIT_600_MASK;
1062                         query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
1063                         switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
1064                         break;
1065
1066                 case CURRENT_LIMIT_800:
1067                         support_mask = CURRENT_LIMIT_800_MASK;
1068                         query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
1069                         switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
1070                         break;
1071
1072                 default:
1073                         TRACE_RET(chip, STATUS_FAIL);
1074                 }
1075         } else {
1076                 TRACE_RET(chip, STATUS_FAIL);
1077         }
1078
1079         if (func_group == SD_FUNC_GROUP_1) {
1080                 if (!(buf[support_offset] & support_mask) ||
1081                                 ((buf[query_switch_offset] & 0x0F) != query_switch)) {
1082                         TRACE_RET(chip, STATUS_FAIL);
1083                 }
1084         }
1085
1086         /* Check 'Busy Status' */
1087         if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) &&
1088                     ((buf[check_busy_offset] & switch_busy) == switch_busy)) {
1089                 TRACE_RET(chip, STATUS_FAIL);
1090         }
1091
1092         return STATUS_SUCCESS;
1093 }
1094
1095 static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode,
1096                 u8 func_group, u8 func_to_switch, u8 bus_width)
1097 {
1098         struct sd_info *sd_card = &(chip->sd_card);
1099         int retval;
1100         u8 cmd[5], buf[64];
1101
1102         RTSX_DEBUGP("sd_check_switch_mode (mode = %d, func_group = %d, func_to_switch = %d)\n",
1103                         mode, func_group, func_to_switch);
1104
1105         cmd[0] = 0x40 | SWITCH;
1106         cmd[1] = mode;
1107
1108         if (func_group == SD_FUNC_GROUP_1) {
1109                 cmd[2] = 0xFF;
1110                 cmd[3] = 0xFF;
1111                 cmd[4] = 0xF0 + func_to_switch;
1112         } else if (func_group == SD_FUNC_GROUP_3) {
1113                 cmd[2] = 0xFF;
1114                 cmd[3] = 0xF0 + func_to_switch;
1115                 cmd[4] = 0xFF;
1116         } else if (func_group == SD_FUNC_GROUP_4) {
1117                 cmd[2] = 0xFF;
1118                 cmd[3] = 0x0F + (func_to_switch << 4);
1119                 cmd[4] = 0xFF;
1120         } else {
1121                 cmd[1] = SD_CHECK_MODE;
1122                 cmd[2] = 0xFF;
1123                 cmd[3] = 0xFF;
1124                 cmd[4] = 0xFF;
1125         }
1126
1127         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width, buf, 64, 250);
1128         if (retval != STATUS_SUCCESS) {
1129                 rtsx_clear_sd_error(chip);
1130                 TRACE_RET(chip, STATUS_FAIL);
1131         }
1132
1133         RTSX_DUMP(buf, 64);
1134
1135         if (func_group == NO_ARGUMENT) {
1136                 sd_card->func_group1_mask = buf[0x0D];
1137                 sd_card->func_group2_mask = buf[0x0B];
1138                 sd_card->func_group3_mask = buf[0x09];
1139                 sd_card->func_group4_mask = buf[0x07];
1140
1141                 RTSX_DEBUGP("func_group1_mask = 0x%02x\n", buf[0x0D]);
1142                 RTSX_DEBUGP("func_group2_mask = 0x%02x\n", buf[0x0B]);
1143                 RTSX_DEBUGP("func_group3_mask = 0x%02x\n", buf[0x09]);
1144                 RTSX_DEBUGP("func_group4_mask = 0x%02x\n", buf[0x07]);
1145         } else {
1146                 /* Maximum current consumption, check whether current is acceptable;
1147                  * bit[511:496] = 0x0000 means some error happened.
1148                  */
1149                 u16 cc = ((u16)buf[0] << 8) | buf[1];
1150                 RTSX_DEBUGP("Maximum current consumption: %dmA\n", cc);
1151                 if ((cc == 0) || (cc > 800)) {
1152                         TRACE_RET(chip, STATUS_FAIL);
1153                 }
1154                 retval = sd_query_switch_result(chip, func_group, func_to_switch, buf, 64);
1155                 if (retval != STATUS_SUCCESS) {
1156                         TRACE_RET(chip, STATUS_FAIL);
1157                 }
1158
1159                 if ((cc > 400) || (func_to_switch > CURRENT_LIMIT_400)) {
1160                         RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK, chip->sd_800mA_ocp_thd);
1161                         RTSX_WRITE_REG(chip, CARD_PWR_CTL, PMOS_STRG_MASK, PMOS_STRG_800mA);
1162                 }
1163         }
1164
1165         return STATUS_SUCCESS;
1166 }
1167
1168 static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch)
1169 {
1170         if (func_group == SD_FUNC_GROUP_1) {
1171                 if (func_to_switch > HS_SUPPORT) {
1172                         func_to_switch--;
1173                 }
1174         } else if (func_group == SD_FUNC_GROUP_4) {
1175                 if (func_to_switch > CURRENT_LIMIT_200) {
1176                         func_to_switch--;
1177                 }
1178         }
1179
1180         return func_to_switch;
1181 }
1182
1183 static int sd_check_switch(struct rtsx_chip *chip,
1184                 u8 func_group, u8 func_to_switch, u8 bus_width)
1185 {
1186         int retval;
1187         int i;
1188         int switch_good = 0;
1189
1190         for (i = 0; i < 3; i++) {
1191                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1192                         sd_set_err_code(chip, SD_NO_CARD);
1193                         TRACE_RET(chip, STATUS_FAIL);
1194                 }
1195
1196                 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group,
1197                                 func_to_switch, bus_width);
1198                 if (retval == STATUS_SUCCESS) {
1199                         u8 stat;
1200
1201                         retval = sd_check_switch_mode(chip, SD_SWITCH_MODE,
1202                                         func_group, func_to_switch, bus_width);
1203                         if (retval == STATUS_SUCCESS) {
1204                                 switch_good = 1;
1205                                 break;
1206                         }
1207
1208                         RTSX_READ_REG(chip, SD_STAT1, &stat);
1209                         if (stat & SD_CRC16_ERR) {
1210                                 RTSX_DEBUGP("SD CRC16 error when switching mode\n");
1211                                 TRACE_RET(chip, STATUS_FAIL);
1212                         }
1213                 }
1214
1215                 func_to_switch = downgrade_switch_mode(func_group, func_to_switch);
1216
1217                 wait_timeout(20);
1218         }
1219
1220         if (!switch_good) {
1221                 TRACE_RET(chip, STATUS_FAIL);
1222         }
1223
1224         return STATUS_SUCCESS;
1225 }
1226
1227 static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width)
1228 {
1229         struct sd_info *sd_card = &(chip->sd_card);
1230         int retval;
1231         int i;
1232         u8 func_to_switch = 0;
1233
1234         /* Get supported functions */
1235         retval = sd_check_switch_mode(chip, SD_CHECK_MODE,
1236                         NO_ARGUMENT, NO_ARGUMENT, bus_width);
1237         if (retval != STATUS_SUCCESS) {
1238                 TRACE_RET(chip, STATUS_FAIL);
1239         }
1240
1241         sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail);
1242
1243         /* Function Group 1: Access Mode */
1244         for (i = 0; i < 4; i++) {
1245                 switch ((u8)(chip->sd_speed_prior >> (i*8))) {
1246                 case SDR104_SUPPORT:
1247                         if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK)
1248                                         && chip->sdr104_en) {
1249                                 func_to_switch = SDR104_SUPPORT;
1250                         }
1251                         break;
1252
1253                 case DDR50_SUPPORT:
1254                         if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK)
1255                                         && chip->ddr50_en) {
1256                                 func_to_switch = DDR50_SUPPORT;
1257                         }
1258                         break;
1259
1260                 case SDR50_SUPPORT:
1261                         if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK)
1262                                         && chip->sdr50_en) {
1263                                 func_to_switch = SDR50_SUPPORT;
1264                         }
1265                         break;
1266
1267                 case HS_SUPPORT:
1268                         if (sd_card->func_group1_mask & HS_SUPPORT_MASK) {
1269                                 func_to_switch = HS_SUPPORT;
1270                         }
1271                         break;
1272
1273                 default:
1274                         continue;
1275                 }
1276
1277
1278                 if (func_to_switch) {
1279                         break;
1280                 }
1281         }
1282         RTSX_DEBUGP("SD_FUNC_GROUP_1: func_to_switch = 0x%02x", func_to_switch);
1283
1284 #ifdef SUPPORT_SD_LOCK
1285         if ((sd_card->sd_lock_status & SD_SDR_RST)
1286                         && (DDR50_SUPPORT == func_to_switch)
1287                         && (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) {
1288                 func_to_switch = SDR50_SUPPORT;
1289                 RTSX_DEBUGP("Using SDR50 instead of DDR50 for SD Lock\n");
1290         }
1291 #endif
1292
1293         if (func_to_switch) {
1294                 retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch, bus_width);
1295                 if (retval != STATUS_SUCCESS) {
1296                         if (func_to_switch == SDR104_SUPPORT) {
1297                                 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK;
1298                         } else if (func_to_switch == DDR50_SUPPORT) {
1299                                 sd_card->sd_switch_fail =
1300                                         SDR104_SUPPORT_MASK | DDR50_SUPPORT_MASK;
1301                         } else if (func_to_switch == SDR50_SUPPORT) {
1302                                 sd_card->sd_switch_fail =
1303                                         SDR104_SUPPORT_MASK | DDR50_SUPPORT_MASK |
1304                                         SDR50_SUPPORT_MASK;
1305                         }
1306                         TRACE_RET(chip, STATUS_FAIL);
1307                 }
1308
1309                 if (func_to_switch == SDR104_SUPPORT) {
1310                         SET_SD_SDR104(sd_card);
1311                 } else if (func_to_switch == DDR50_SUPPORT) {
1312                         SET_SD_DDR50(sd_card);
1313                 } else if (func_to_switch == SDR50_SUPPORT) {
1314                         SET_SD_SDR50(sd_card);
1315                 } else {
1316                         SET_SD_HS(sd_card);
1317                 }
1318         }
1319
1320         if (CHK_SD_DDR50(sd_card)) {
1321                 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0x04);
1322                 retval = sd_set_sample_push_timing(chip);
1323                 if (retval != STATUS_SUCCESS) {
1324                         TRACE_RET(chip, STATUS_FAIL);
1325                 }
1326         }
1327
1328         if (!func_to_switch || (func_to_switch == HS_SUPPORT)) {
1329                 /* Do not try to switch current limit if the card doesn't
1330                  * support UHS mode or we don't want it to support UHS mode
1331                  */
1332                 return STATUS_SUCCESS;
1333         }
1334
1335         /* Function Group 4: Current Limit */
1336         func_to_switch = 0xFF;
1337
1338         for (i = 0; i < 4; i++) {
1339                 switch ((u8)(chip->sd_current_prior >> (i*8))) {
1340                 case CURRENT_LIMIT_800:
1341                         if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK) {
1342                                 func_to_switch = CURRENT_LIMIT_800;
1343                         }
1344                         break;
1345
1346                 case CURRENT_LIMIT_600:
1347                         if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK) {
1348                                 func_to_switch = CURRENT_LIMIT_600;
1349                         }
1350                         break;
1351
1352                 case CURRENT_LIMIT_400:
1353                         if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK) {
1354                                 func_to_switch = CURRENT_LIMIT_400;
1355                         }
1356                         break;
1357
1358                 case CURRENT_LIMIT_200:
1359                         if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK) {
1360                                 func_to_switch = CURRENT_LIMIT_200;
1361                         }
1362                         break;
1363
1364                 default:
1365                         continue;
1366                 }
1367
1368                 if (func_to_switch != 0xFF) {
1369                         break;
1370                 }
1371         }
1372
1373         RTSX_DEBUGP("SD_FUNC_GROUP_4: func_to_switch = 0x%02x", func_to_switch);
1374
1375         if (func_to_switch <= CURRENT_LIMIT_800) {
1376                 retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch, bus_width);
1377                 if (retval != STATUS_SUCCESS) {
1378                         if (sd_check_err_code(chip, SD_NO_CARD)) {
1379                                 TRACE_RET(chip, STATUS_FAIL);
1380                         }
1381                 }
1382                 RTSX_DEBUGP("Switch current limit finished! (%d)\n", retval);
1383         }
1384
1385         if (CHK_SD_DDR50(sd_card)) {
1386                 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0);
1387         }
1388
1389         return STATUS_SUCCESS;
1390 }
1391
1392 static int sd_wait_data_idle(struct rtsx_chip *chip)
1393 {
1394         int retval = STATUS_TIMEDOUT;
1395         int i;
1396         u8 val = 0;
1397
1398         for (i = 0; i < 100; i++) {
1399                 RTSX_READ_REG(chip, SD_DATA_STATE, &val);
1400                 if (val & SD_DATA_IDLE) {
1401                         retval = STATUS_SUCCESS;
1402                         break;
1403                 }
1404                 udelay(100);
1405         }
1406         RTSX_DEBUGP("SD_DATA_STATE: 0x%02x\n", val);
1407
1408         return retval;
1409 }
1410
1411 static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1412 {
1413         int retval;
1414         u8 cmd[5];
1415
1416         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1417         if (retval != STATUS_SUCCESS) {
1418                 TRACE_RET(chip, STATUS_FAIL);
1419         }
1420
1421         cmd[0] = 0x40 | SEND_TUNING_PATTERN;
1422         cmd[1] = 0;
1423         cmd[2] = 0;
1424         cmd[3] = 0;
1425         cmd[4] = 0;
1426
1427         retval = sd_read_data(chip, SD_TM_AUTO_TUNING,
1428                         cmd, 5, 0x40, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1429         if (retval != STATUS_SUCCESS) {
1430                 (void)sd_wait_data_idle(chip);
1431
1432                 rtsx_clear_sd_error(chip);
1433                 TRACE_RET(chip, STATUS_FAIL);
1434         }
1435
1436         return STATUS_SUCCESS;
1437 }
1438
1439 static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1440 {
1441         struct sd_info *sd_card = &(chip->sd_card);
1442         int retval;
1443         u8 cmd[5];
1444
1445         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1446         if (retval != STATUS_SUCCESS) {
1447                 TRACE_RET(chip, STATUS_FAIL);
1448         }
1449
1450         RTSX_DEBUGP("sd ddr tuning rx\n");
1451
1452         retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
1453         if (retval != STATUS_SUCCESS) {
1454                 TRACE_RET(chip, STATUS_FAIL);
1455         }
1456
1457         cmd[0] = 0x40 | SD_STATUS;
1458         cmd[1] = 0;
1459         cmd[2] = 0;
1460         cmd[3] = 0;
1461         cmd[4] = 0;
1462
1463         retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1464                         cmd, 5, 64, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1465         if (retval != STATUS_SUCCESS) {
1466                 (void)sd_wait_data_idle(chip);
1467
1468                 rtsx_clear_sd_error(chip);
1469                 TRACE_RET(chip, STATUS_FAIL);
1470         }
1471
1472         return STATUS_SUCCESS;
1473 }
1474
1475 static int mmc_ddr_tunning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1476 {
1477         struct sd_info *sd_card = &(chip->sd_card);
1478         int retval;
1479         u8 cmd[5], bus_width;
1480
1481         if (CHK_MMC_8BIT(sd_card)) {
1482                 bus_width = SD_BUS_WIDTH_8;
1483         } else if (CHK_MMC_4BIT(sd_card)) {
1484                 bus_width = SD_BUS_WIDTH_4;
1485         } else {
1486                 bus_width = SD_BUS_WIDTH_1;
1487         }
1488
1489         retval = sd_change_phase(chip, sample_point, TUNE_RX);
1490         if (retval != STATUS_SUCCESS) {
1491                 TRACE_RET(chip, STATUS_FAIL);
1492         }
1493
1494         RTSX_DEBUGP("mmc ddr tuning rx\n");
1495
1496         cmd[0] = 0x40 | SEND_EXT_CSD;
1497         cmd[1] = 0;
1498         cmd[2] = 0;
1499         cmd[3] = 0;
1500         cmd[4] = 0;
1501
1502         retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1503                         cmd, 5, 0x200, 1, bus_width, NULL, 0, 100);
1504         if (retval != STATUS_SUCCESS) {
1505                 (void)sd_wait_data_idle(chip);
1506
1507                 rtsx_clear_sd_error(chip);
1508                 TRACE_RET(chip, STATUS_FAIL);
1509         }
1510
1511         return STATUS_SUCCESS;
1512 }
1513
1514 static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1515 {
1516         struct sd_info *sd_card = &(chip->sd_card);
1517         int retval;
1518
1519         retval = sd_change_phase(chip, sample_point, TUNE_TX);
1520         if (retval != STATUS_SUCCESS) {
1521                 TRACE_RET(chip, STATUS_FAIL);
1522         }
1523
1524         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN);
1525
1526         retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1527                 SD_RSP_TYPE_R1, NULL, 0);
1528         if (retval != STATUS_SUCCESS) {
1529                 if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1530                         rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1531                         TRACE_RET(chip, STATUS_FAIL);
1532                 }
1533         }
1534
1535         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1536
1537         return STATUS_SUCCESS;
1538 }
1539
1540 static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1541 {
1542         struct sd_info *sd_card = &(chip->sd_card);
1543         int retval;
1544         u8 cmd[5], bus_width;
1545
1546         retval = sd_change_phase(chip, sample_point, TUNE_TX);
1547         if (retval != STATUS_SUCCESS) {
1548                 TRACE_RET(chip, STATUS_FAIL);
1549         }
1550
1551         if (CHK_SD(sd_card)) {
1552                 bus_width = SD_BUS_WIDTH_4;
1553         } else {
1554                 if (CHK_MMC_8BIT(sd_card)) {
1555                         bus_width = SD_BUS_WIDTH_8;
1556                 } else if (CHK_MMC_4BIT(sd_card)) {
1557                         bus_width = SD_BUS_WIDTH_4;
1558                 } else {
1559                         bus_width = SD_BUS_WIDTH_1;
1560                 }
1561         }
1562
1563         retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
1564         if (retval != STATUS_SUCCESS) {
1565                 TRACE_RET(chip, STATUS_FAIL);
1566         }
1567
1568         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN);
1569
1570         cmd[0] = 0x40 | PROGRAM_CSD;
1571         cmd[1] = 0;
1572         cmd[2] = 0;
1573         cmd[3] = 0;
1574         cmd[4] = 0;
1575
1576         retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2,
1577                         cmd, 5, 16, 1, bus_width, sd_card->raw_csd, 16, 100);
1578         if (retval != STATUS_SUCCESS) {
1579                 rtsx_clear_sd_error(chip);
1580                 rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1581                 TRACE_RET(chip, STATUS_FAIL);
1582         }
1583
1584         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1585
1586         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
1587
1588         return STATUS_SUCCESS;
1589 }
1590
1591 static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map, u8 tune_dir)
1592 {
1593         struct sd_info *sd_card = &(chip->sd_card);
1594         struct timing_phase_path path[MAX_PHASE + 1];
1595         int i, j, cont_path_cnt;
1596         int new_block, max_len, final_path_idx;
1597         u8 final_phase = 0xFF;
1598
1599         if (phase_map == 0xFFFFFFFF) {
1600                 if (tune_dir == TUNE_RX) {
1601                         final_phase = (u8)chip->sd_default_rx_phase;
1602                 } else {
1603                         final_phase = (u8)chip->sd_default_tx_phase;
1604                 }
1605
1606                 goto Search_Finish;
1607         }
1608
1609         cont_path_cnt = 0;
1610         new_block = 1;
1611         j = 0;
1612         for (i = 0; i < MAX_PHASE + 1; i++) {
1613                 if (phase_map & (1 << i)) {
1614                         if (new_block) {
1615                                 new_block = 0;
1616                                 j = cont_path_cnt++;
1617                                 path[j].start = i;
1618                                 path[j].end = i;
1619                         } else {
1620                                 path[j].end = i;
1621                         }
1622                 } else {
1623                         new_block = 1;
1624                         if (cont_path_cnt) {
1625                                 int idx = cont_path_cnt - 1;
1626                                 path[idx].len = path[idx].end - path[idx].start + 1;
1627                                 path[idx].mid = path[idx].start + path[idx].len / 2;
1628                         }
1629                 }
1630         }
1631
1632         if (cont_path_cnt == 0) {
1633                 RTSX_DEBUGP("No continuous phase path\n");
1634                 goto Search_Finish;
1635         } else {
1636                 int idx = cont_path_cnt - 1;
1637                 path[idx].len = path[idx].end - path[idx].start + 1;
1638                 path[idx].mid = path[idx].start + path[idx].len / 2;
1639         }
1640
1641         if ((path[0].start == 0) && (path[cont_path_cnt - 1].end == MAX_PHASE)) {
1642                 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1643                 path[0].len += path[cont_path_cnt - 1].len;
1644                 path[0].mid = path[0].start + path[0].len / 2;
1645                 if (path[0].mid < 0) {
1646                         path[0].mid += MAX_PHASE + 1;
1647                 }
1648                 cont_path_cnt--;
1649         }
1650
1651         max_len = 0;
1652         final_phase = 0;
1653         final_path_idx = 0;
1654         for (i = 0; i < cont_path_cnt; i++) {
1655                 if (path[i].len > max_len) {
1656                         max_len = path[i].len;
1657                         final_phase = (u8)path[i].mid;
1658                         final_path_idx = i;
1659                 }
1660
1661                 RTSX_DEBUGP("path[%d].start = %d\n", i, path[i].start);
1662                 RTSX_DEBUGP("path[%d].end = %d\n", i, path[i].end);
1663                 RTSX_DEBUGP("path[%d].len = %d\n", i, path[i].len);
1664                 RTSX_DEBUGP("path[%d].mid = %d\n", i, path[i].mid);
1665                 RTSX_DEBUGP("\n");
1666         }
1667
1668         if (tune_dir == TUNE_TX) {
1669                 if (CHK_SD_SDR104(sd_card)) {
1670                         if (max_len > 15) {
1671                                 int temp_mid = (max_len - 16) / 2;
1672                                 int temp_final_phase =
1673                                         path[final_path_idx].end - (max_len - (6 + temp_mid));
1674
1675                                 if (temp_final_phase < 0) {
1676                                         final_phase = (u8)(temp_final_phase + MAX_PHASE + 1);
1677                                 } else {
1678                                         final_phase = (u8)temp_final_phase;
1679                                 }
1680                         }
1681                 } else if (CHK_SD_SDR50(sd_card)) {
1682                         if (max_len > 12) {
1683                                 int temp_mid = (max_len - 13) / 2;
1684                                 int temp_final_phase =
1685                                         path[final_path_idx].end - (max_len - (3 + temp_mid));
1686
1687                                 if (temp_final_phase < 0) {
1688                                         final_phase = (u8)(temp_final_phase + MAX_PHASE + 1);
1689                                 } else {
1690                                         final_phase = (u8)temp_final_phase;
1691                                 }
1692                         }
1693                 }
1694         }
1695
1696 Search_Finish:
1697         RTSX_DEBUGP("Final chosen phase: %d\n", final_phase);
1698         return final_phase;
1699 }
1700
1701 static int sd_tuning_rx(struct rtsx_chip *chip)
1702 {
1703         struct sd_info *sd_card = &(chip->sd_card);
1704         int retval;
1705         int i, j;
1706         u32 raw_phase_map[3], phase_map;
1707         u8 final_phase;
1708         int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1709
1710         if (CHK_SD(sd_card)) {
1711                 if (CHK_SD_DDR50(sd_card)) {
1712                         tuning_cmd = sd_ddr_tuning_rx_cmd;
1713                 } else {
1714                         tuning_cmd = sd_sdr_tuning_rx_cmd;
1715                 }
1716         } else {
1717                 if (CHK_MMC_DDR52(sd_card)) {
1718                         tuning_cmd = mmc_ddr_tunning_rx_cmd;
1719                 } else {
1720                         TRACE_RET(chip, STATUS_FAIL);
1721                 }
1722         }
1723
1724         for (i = 0; i < 3; i++) {
1725                 raw_phase_map[i] = 0;
1726                 for (j = MAX_PHASE; j >= 0; j--) {
1727                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1728                                 sd_set_err_code(chip, SD_NO_CARD);
1729                                 TRACE_RET(chip, STATUS_FAIL);
1730                         }
1731
1732                         retval = tuning_cmd(chip, (u8)j);
1733                         if (retval == STATUS_SUCCESS) {
1734                                 raw_phase_map[i] |= 1 << j;
1735                         }
1736                 }
1737         }
1738
1739         phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1740         for (i = 0; i < 3; i++) {
1741                 RTSX_DEBUGP("RX raw_phase_map[%d] = 0x%08x\n", i, raw_phase_map[i]);
1742         }
1743         RTSX_DEBUGP("RX phase_map = 0x%08x\n", phase_map);
1744
1745         final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX);
1746         if (final_phase == 0xFF) {
1747                 TRACE_RET(chip, STATUS_FAIL);
1748         }
1749
1750         retval = sd_change_phase(chip, final_phase, TUNE_RX);
1751         if (retval != STATUS_SUCCESS) {
1752                 TRACE_RET(chip, STATUS_FAIL);
1753         }
1754
1755         return STATUS_SUCCESS;
1756 }
1757
1758 static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip)
1759 {
1760         struct sd_info *sd_card = &(chip->sd_card);
1761         int retval;
1762         int i;
1763         u32 phase_map;
1764         u8 final_phase;
1765
1766         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN);
1767
1768         phase_map = 0;
1769         for (i = MAX_PHASE; i >= 0; i--) {
1770                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1771                         sd_set_err_code(chip, SD_NO_CARD);
1772                         rtsx_write_register(chip, SD_CFG3,
1773                                                 SD_RSP_80CLK_TIMEOUT_EN, 0);
1774                         TRACE_RET(chip, STATUS_FAIL);
1775                 }
1776
1777                 retval = sd_change_phase(chip, (u8)i, TUNE_TX);
1778                 if (retval != STATUS_SUCCESS) {
1779                         continue;
1780                 }
1781
1782                 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1783                                 SD_RSP_TYPE_R1, NULL, 0);
1784                 if ((retval == STATUS_SUCCESS) || !sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1785                         phase_map |= 1 << i;
1786                 }
1787         }
1788
1789         RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1790
1791         RTSX_DEBUGP("DDR TX pre tune phase_map = 0x%08x\n", phase_map);
1792
1793         final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1794         if (final_phase == 0xFF) {
1795                 TRACE_RET(chip, STATUS_FAIL);
1796         }
1797
1798         retval = sd_change_phase(chip, final_phase, TUNE_TX);
1799         if (retval != STATUS_SUCCESS) {
1800                 TRACE_RET(chip, STATUS_FAIL);
1801         }
1802
1803         RTSX_DEBUGP("DDR TX pre tune phase: %d\n", (int)final_phase);
1804
1805         return STATUS_SUCCESS;
1806 }
1807
1808 static int sd_tuning_tx(struct rtsx_chip *chip)
1809 {
1810         struct sd_info *sd_card = &(chip->sd_card);
1811         int retval;
1812         int i, j;
1813         u32 raw_phase_map[3], phase_map;
1814         u8 final_phase;
1815         int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1816
1817         if (CHK_SD(sd_card)) {
1818                 if (CHK_SD_DDR50(sd_card)) {
1819                         tuning_cmd = sd_ddr_tuning_tx_cmd;
1820                 } else {
1821                         tuning_cmd = sd_sdr_tuning_tx_cmd;
1822                 }
1823         } else {
1824                 if (CHK_MMC_DDR52(sd_card)) {
1825                         tuning_cmd = sd_ddr_tuning_tx_cmd;
1826                 } else {
1827                         TRACE_RET(chip, STATUS_FAIL);
1828                 }
1829         }
1830
1831         for (i = 0; i < 3; i++) {
1832                 raw_phase_map[i] = 0;
1833                 for (j = MAX_PHASE; j >= 0; j--) {
1834                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1835                                 sd_set_err_code(chip, SD_NO_CARD);
1836                                 rtsx_write_register(chip, SD_CFG3,
1837                                                     SD_RSP_80CLK_TIMEOUT_EN, 0);
1838                                 TRACE_RET(chip, STATUS_FAIL);
1839                         }
1840
1841                         retval = tuning_cmd(chip, (u8)j);
1842                         if (retval == STATUS_SUCCESS) {
1843                                 raw_phase_map[i] |= 1 << j;
1844                         }
1845                 }
1846         }
1847
1848         phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1849         for (i = 0; i < 3; i++) {
1850                 RTSX_DEBUGP("TX raw_phase_map[%d] = 0x%08x\n", i, raw_phase_map[i]);
1851         }
1852         RTSX_DEBUGP("TX phase_map = 0x%08x\n", phase_map);
1853
1854         final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1855         if (final_phase == 0xFF) {
1856                 TRACE_RET(chip, STATUS_FAIL);
1857         }
1858
1859         retval = sd_change_phase(chip, final_phase, TUNE_TX);
1860         if (retval != STATUS_SUCCESS) {
1861                 TRACE_RET(chip, STATUS_FAIL);
1862         }
1863
1864         return STATUS_SUCCESS;
1865 }
1866
1867 static int sd_sdr_tuning(struct rtsx_chip *chip)
1868 {
1869         int retval;
1870
1871         retval = sd_tuning_tx(chip);
1872         if (retval != STATUS_SUCCESS) {
1873                 TRACE_RET(chip, STATUS_FAIL);
1874         }
1875
1876         retval = sd_tuning_rx(chip);
1877         if (retval != STATUS_SUCCESS) {
1878                 TRACE_RET(chip, STATUS_FAIL);
1879         }
1880
1881         return STATUS_SUCCESS;
1882 }
1883
1884 static int sd_ddr_tuning(struct rtsx_chip *chip)
1885 {
1886         int retval;
1887
1888         if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1889                 retval = sd_ddr_pre_tuning_tx(chip);
1890                 if (retval != STATUS_SUCCESS) {
1891                         TRACE_RET(chip, STATUS_FAIL);
1892                 }
1893         } else {
1894                 retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase, TUNE_TX);
1895                 if (retval != STATUS_SUCCESS) {
1896                         TRACE_RET(chip, STATUS_FAIL);
1897                 }
1898         }
1899
1900         retval = sd_tuning_rx(chip);
1901         if (retval != STATUS_SUCCESS) {
1902                 TRACE_RET(chip, STATUS_FAIL);
1903         }
1904
1905         if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1906                 retval = sd_tuning_tx(chip);
1907                 if (retval != STATUS_SUCCESS) {
1908                         TRACE_RET(chip, STATUS_FAIL);
1909                 }
1910         }
1911
1912         return STATUS_SUCCESS;
1913 }
1914
1915 static int mmc_ddr_tuning(struct rtsx_chip *chip)
1916 {
1917         int retval;
1918
1919         if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1920                 retval = sd_ddr_pre_tuning_tx(chip);
1921                 if (retval != STATUS_SUCCESS) {
1922                         TRACE_RET(chip, STATUS_FAIL);
1923                 }
1924         } else {
1925                 retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase, TUNE_TX);
1926                 if (retval != STATUS_SUCCESS) {
1927                         TRACE_RET(chip, STATUS_FAIL);
1928                 }
1929         }
1930
1931         retval = sd_tuning_rx(chip);
1932         if (retval != STATUS_SUCCESS) {
1933                 TRACE_RET(chip, STATUS_FAIL);
1934         }
1935
1936         if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1937                 retval = sd_tuning_tx(chip);
1938                 if (retval != STATUS_SUCCESS) {
1939                         TRACE_RET(chip, STATUS_FAIL);
1940                 }
1941         }
1942
1943         return STATUS_SUCCESS;
1944 }
1945
1946 int sd_switch_clock(struct rtsx_chip *chip)
1947 {
1948         struct sd_info *sd_card = &(chip->sd_card);
1949         int retval;
1950         int re_tuning = 0;
1951
1952         retval = select_card(chip, SD_CARD);
1953         if (retval != STATUS_SUCCESS) {
1954                 TRACE_RET(chip, STATUS_FAIL);
1955         }
1956
1957         if (CHECK_PID(chip, 0x5209) &&
1958                         (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))) {
1959                 if (sd_card->need_retune && (sd_card->sd_clock != chip->cur_clk)) {
1960                         re_tuning = 1;
1961                         sd_card->need_retune = 0;
1962                 }
1963         }
1964
1965         retval = switch_clock(chip, sd_card->sd_clock);
1966         if (retval != STATUS_SUCCESS) {
1967                 TRACE_RET(chip, STATUS_FAIL);
1968         }
1969
1970         if (re_tuning) {
1971                 if (CHK_SD(sd_card)) {
1972                         if (CHK_SD_DDR50(sd_card)) {
1973                                 retval = sd_ddr_tuning(chip);
1974                         } else {
1975                                 retval = sd_sdr_tuning(chip);
1976                         }
1977                 } else {
1978                         if (CHK_MMC_DDR52(sd_card)) {
1979                                 retval = mmc_ddr_tuning(chip);
1980                         }
1981                 }
1982
1983                 if (retval != STATUS_SUCCESS) {
1984                         TRACE_RET(chip, STATUS_FAIL);
1985                 }
1986         }
1987
1988         return STATUS_SUCCESS;
1989 }
1990
1991 static int sd_prepare_reset(struct rtsx_chip *chip)
1992 {
1993         struct sd_info *sd_card = &(chip->sd_card);
1994         int retval;
1995
1996         if (chip->asic_code) {
1997                 sd_card->sd_clock = 29;
1998         } else {
1999                 sd_card->sd_clock = CLK_30;
2000         }
2001
2002         sd_card->sd_type = 0;
2003         sd_card->seq_mode = 0;
2004         sd_card->sd_data_buf_ready = 0;
2005         sd_card->capacity = 0;
2006
2007 #ifdef SUPPORT_SD_LOCK
2008         sd_card->sd_lock_status = 0;
2009         sd_card->sd_erase_status = 0;
2010 #endif
2011
2012         chip->capacity[chip->card2lun[SD_CARD]] = 0;
2013         chip->sd_io = 0;
2014
2015         retval = sd_set_init_para(chip);
2016         if (retval != STATUS_SUCCESS) {
2017                 TRACE_RET(chip, retval);
2018         }
2019
2020         if (CHECK_PID(chip, 0x5209)) {
2021                 RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF,
2022                         SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1);
2023                 RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, 0xFF, SD20_RX_POS_EDGE);
2024                 RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0xFF, 0);
2025         } else {
2026                 RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF, 0x40);
2027         }
2028
2029         RTSX_WRITE_REG(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
2030
2031         retval = select_card(chip, SD_CARD);
2032         if (retval != STATUS_SUCCESS) {
2033                 TRACE_RET(chip, STATUS_FAIL);
2034         }
2035
2036         return STATUS_SUCCESS;
2037 }
2038
2039 static int sd_pull_ctl_disable(struct rtsx_chip *chip)
2040 {
2041         if (CHECK_PID(chip, 0x5209)) {
2042                 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
2043                 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
2044                 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0xD5);
2045         } else if (CHECK_PID(chip, 0x5208)) {
2046                 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
2047                         XD_D3_PD | SD_D7_PD | SD_CLK_PD | SD_D5_PD);
2048                 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
2049                         SD_D6_PD | SD_D0_PD | SD_D1_PD | XD_D5_PD);
2050                 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
2051                         SD_D4_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
2052                 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
2053                         XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
2054                 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
2055                         MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
2056                 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
2057         } else if (CHECK_PID(chip, 0x5288)) {
2058                 if (CHECK_BARO_PKG(chip, QFN)) {
2059                         RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
2060                         RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
2061                         RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
2062                         RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
2063                 }
2064         }
2065
2066         return STATUS_SUCCESS;
2067 }
2068
2069 int sd_pull_ctl_enable(struct rtsx_chip *chip)
2070 {
2071         int retval;
2072
2073         rtsx_init_cmd(chip);
2074
2075         if (CHECK_PID(chip, 0x5209)) {
2076                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA);
2077                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0xAA);
2078                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xE9);
2079         } else if (CHECK_PID(chip, 0x5208)) {
2080                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
2081                         XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU);
2082                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
2083                         SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD);
2084                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
2085                         SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
2086                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
2087                         XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD);
2088                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
2089                         MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
2090                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
2091         } else if (CHECK_PID(chip, 0x5288)) {
2092                 if (CHECK_BARO_PKG(chip, QFN)) {
2093                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xA8);
2094                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x5A);
2095                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
2096                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0xAA);
2097                 }
2098         }
2099
2100         retval = rtsx_send_cmd(chip, SD_CARD, 100);
2101         if (retval < 0) {
2102                 TRACE_RET(chip, STATUS_FAIL);
2103         }
2104
2105         return STATUS_SUCCESS;
2106 }
2107
2108 static int sd_init_power(struct rtsx_chip *chip)
2109 {
2110         int retval;
2111
2112         if (CHECK_PID(chip, 0x5209)) {
2113                 RTSX_WRITE_REG(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_OFF);
2114         }
2115
2116         retval = sd_power_off_card3v3(chip);
2117         if (retval != STATUS_SUCCESS) {
2118                 TRACE_RET(chip, STATUS_FAIL);
2119         }
2120
2121         if (!chip->ft2_fast_mode) {
2122                 wait_timeout(250);
2123         }
2124
2125         retval = enable_card_clock(chip, SD_CARD);
2126         if (retval != STATUS_SUCCESS) {
2127                 TRACE_RET(chip, STATUS_FAIL);
2128         }
2129
2130         if (chip->asic_code) {
2131                 retval = sd_pull_ctl_enable(chip);
2132                 if (retval != STATUS_SUCCESS) {
2133                         TRACE_RET(chip, STATUS_FAIL);
2134                 }
2135         } else {
2136                 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_SD_PULL_CTL_BIT | 0x20, 0);
2137         }
2138
2139         if (chip->ft2_fast_mode) {
2140                 if (CHECK_PID(chip, 0x5209)) {
2141                         RTSX_WRITE_REG(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_ON);
2142                 }
2143         } else {
2144                 retval = card_power_on(chip, SD_CARD);
2145                 if (retval != STATUS_SUCCESS) {
2146                         TRACE_RET(chip, STATUS_FAIL);
2147                 }
2148                 wait_timeout(260);
2149
2150 #ifdef SUPPORT_OCP
2151                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
2152                         RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat);
2153                         TRACE_RET(chip, STATUS_FAIL);
2154                 }
2155 #endif
2156         }
2157
2158         RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
2159
2160         return STATUS_SUCCESS;
2161 }
2162
2163 static int sd_dummy_clock(struct rtsx_chip *chip)
2164 {
2165         if (CHECK_PID(chip, 0x5209)) {
2166                 RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
2167                 wait_timeout(5);
2168                 RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0x00);
2169         } else {
2170                 RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0x01);
2171                 wait_timeout(5);
2172                 RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0);
2173         }
2174
2175         return STATUS_SUCCESS;
2176 }
2177
2178 static int sd_read_lba0(struct rtsx_chip *chip)
2179 {
2180         struct sd_info *sd_card = &(chip->sd_card);
2181         int retval;
2182         u8 cmd[5], bus_width;
2183
2184         cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2185         cmd[1] = 0;
2186         cmd[2] = 0;
2187         cmd[3] = 0;
2188         cmd[4] = 0;
2189
2190         if (CHK_SD(sd_card)) {
2191                 bus_width = SD_BUS_WIDTH_4;
2192         } else {
2193                 if (CHK_MMC_8BIT(sd_card)) {
2194                         bus_width = SD_BUS_WIDTH_8;
2195                 } else if (CHK_MMC_4BIT(sd_card)) {
2196                         bus_width = SD_BUS_WIDTH_4;
2197                 } else {
2198                         bus_width = SD_BUS_WIDTH_1;
2199                 }
2200         }
2201
2202         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd,
2203                 5, 512, 1, bus_width, NULL, 0, 100);
2204         if (retval != STATUS_SUCCESS) {
2205                 rtsx_clear_sd_error(chip);
2206                 TRACE_RET(chip, STATUS_FAIL);
2207         }
2208
2209         return STATUS_SUCCESS;
2210 }
2211
2212 static int sd_check_wp_state(struct rtsx_chip *chip)
2213 {
2214         struct sd_info *sd_card = &(chip->sd_card);
2215         int retval;
2216         u32 val;
2217         u16 sd_card_type;
2218         u8 cmd[5], buf[64];
2219
2220         retval = sd_send_cmd_get_rsp(chip, APP_CMD,
2221                         sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2222         if (retval != STATUS_SUCCESS) {
2223                 TRACE_RET(chip, STATUS_FAIL);
2224         }
2225
2226         cmd[0] = 0x40 | SD_STATUS;
2227         cmd[1] = 0;
2228         cmd[2] = 0;
2229         cmd[3] = 0;
2230         cmd[4] = 0;
2231
2232         retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, SD_BUS_WIDTH_4, buf, 64, 250);
2233         if (retval != STATUS_SUCCESS) {
2234                 rtsx_clear_sd_error(chip);
2235
2236                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2237                 TRACE_RET(chip, STATUS_FAIL);
2238         }
2239
2240         RTSX_DEBUGP("ACMD13:\n");
2241         RTSX_DUMP(buf, 64);
2242
2243         sd_card_type = ((u16)buf[2] << 8) | buf[3];
2244         RTSX_DEBUGP("sd_card_type = 0x%04x\n", sd_card_type);
2245         if ((sd_card_type == 0x0001) || (sd_card_type == 0x0002)) {
2246                 /* ROM card or OTP */
2247                 chip->card_wp |= SD_CARD;
2248         }
2249
2250         /* Check SD Machanical Write-Protect Switch */
2251         val = rtsx_readl(chip, RTSX_BIPR);
2252         if (val & SD_WRITE_PROTECT) {
2253                 chip->card_wp |= SD_CARD;
2254         }
2255
2256         return STATUS_SUCCESS;
2257 }
2258
2259 static int reset_sd(struct rtsx_chip *chip)
2260 {
2261         struct sd_info *sd_card = &(chip->sd_card);
2262         int retval, i = 0, j = 0, k = 0, hi_cap_flow = 0;
2263         int sd_dont_switch = 0;
2264         int support_1v8 = 0;
2265         int try_sdio = 1;
2266         u8 rsp[16];
2267         u8 switch_bus_width;
2268         u32 voltage = 0;
2269         int sd20_mode = 0;
2270
2271         SET_SD(sd_card);
2272
2273 Switch_Fail:
2274
2275         i = 0;
2276         j = 0;
2277         k = 0;
2278         hi_cap_flow = 0;
2279
2280 #ifdef SUPPORT_SD_LOCK
2281         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2282                 goto SD_UNLOCK_ENTRY;
2283 #endif
2284
2285         retval = sd_prepare_reset(chip);
2286         if (retval != STATUS_SUCCESS) {
2287                 TRACE_RET(chip, STATUS_FAIL);
2288         }
2289
2290         retval = sd_dummy_clock(chip);
2291         if (retval != STATUS_SUCCESS) {
2292                 TRACE_RET(chip, STATUS_FAIL);
2293         }
2294
2295         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) {
2296                 int rty_cnt = 0;
2297
2298                 for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) {
2299                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2300                                 sd_set_err_code(chip, SD_NO_CARD);
2301                                 TRACE_RET(chip, STATUS_FAIL);
2302                         }
2303
2304                         retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0, SD_RSP_TYPE_R4, rsp, 5);
2305                         if (retval == STATUS_SUCCESS) {
2306                                 int func_num = (rsp[1] >> 4) & 0x07;
2307                                 if (func_num) {
2308                                         RTSX_DEBUGP("SD_IO card (Function number: %d)!\n", func_num);
2309                                         chip->sd_io = 1;
2310                                         TRACE_RET(chip, STATUS_FAIL);
2311                                 }
2312
2313                                 break;
2314                         }
2315
2316                         sd_init_power(chip);
2317
2318                         sd_dummy_clock(chip);
2319                 }
2320
2321                 RTSX_DEBUGP("Normal card!\n");
2322         }
2323
2324         /* Start Initialization Process of SD Card */
2325 RTY_SD_RST:
2326         retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0);
2327         if (retval != STATUS_SUCCESS) {
2328                TRACE_RET(chip, STATUS_FAIL);
2329         }
2330
2331         wait_timeout(20);
2332
2333         retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA, SD_RSP_TYPE_R7, rsp, 5);
2334         if (retval == STATUS_SUCCESS) {
2335                 if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) {
2336                         hi_cap_flow = 1;
2337                         if (CHECK_PID(chip, 0x5209)) {
2338                                 if (sd20_mode) {
2339                                         voltage = SUPPORT_VOLTAGE |
2340                                                 SUPPORT_HIGH_AND_EXTENDED_CAPACITY;
2341                                 } else {
2342                                         voltage = SUPPORT_VOLTAGE |
2343                                                 SUPPORT_HIGH_AND_EXTENDED_CAPACITY |
2344                                                 SUPPORT_MAX_POWER_PERMANCE | SUPPORT_1V8;
2345                                 }
2346                         } else {
2347                                 voltage = SUPPORT_VOLTAGE | 0x40000000;
2348                         }
2349                 }
2350         }
2351
2352         if (!hi_cap_flow) {
2353                 voltage = SUPPORT_VOLTAGE;
2354
2355                 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0);
2356                 if (retval != STATUS_SUCCESS) {
2357                        TRACE_RET(chip, STATUS_FAIL);
2358                 }
2359
2360                 wait_timeout(20);
2361         }
2362
2363         do {
2364                 retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1, NULL, 0);
2365                 if (retval != STATUS_SUCCESS) {
2366                         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2367                                 sd_set_err_code(chip, SD_NO_CARD);
2368                                 TRACE_RET(chip, STATUS_FAIL);
2369                         }
2370
2371                         j++;
2372                         if (j < 3) {
2373                                 goto RTY_SD_RST;
2374                         } else {
2375                                 TRACE_RET(chip, STATUS_FAIL);
2376                         }
2377                 }
2378
2379                 retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage, SD_RSP_TYPE_R3, rsp, 5);
2380                 if (retval != STATUS_SUCCESS) {
2381                         k++;
2382                         if (k < 3) {
2383                                 goto RTY_SD_RST;
2384                         } else {
2385                                 TRACE_RET(chip, STATUS_FAIL);
2386                         }
2387                 }
2388
2389                 i++;
2390                 wait_timeout(20);
2391         } while (!(rsp[1] & 0x80) && (i < 255));
2392
2393         if (i == 255) {
2394                 TRACE_RET(chip, STATUS_FAIL);
2395         }
2396
2397         if (hi_cap_flow) {
2398                 if (rsp[1] & 0x40) {
2399                         SET_SD_HCXC(sd_card);
2400                 } else {
2401                         CLR_SD_HCXC(sd_card);
2402                 }
2403                 if (CHECK_PID(chip, 0x5209) && CHK_SD_HCXC(sd_card) && !sd20_mode) {
2404                         support_1v8 = (rsp[1] & 0x01) ? 1 : 0;
2405                 } else {
2406                         support_1v8 = 0;
2407                 }
2408         } else {
2409                 CLR_SD_HCXC(sd_card);
2410                 support_1v8 = 0;
2411         }
2412         RTSX_DEBUGP("support_1v8 = %d\n", support_1v8);
2413
2414         if (support_1v8) {
2415                 retval = sd_voltage_switch(chip);
2416                 if (retval != STATUS_SUCCESS) {
2417                         TRACE_RET(chip, STATUS_FAIL);
2418                 }
2419         }
2420
2421         retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0);
2422         if (retval != STATUS_SUCCESS) {
2423                 TRACE_RET(chip, STATUS_FAIL);
2424         }
2425
2426         for (i = 0; i < 3; i++) {
2427                 retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0, SD_RSP_TYPE_R6, rsp, 5);
2428                 if (retval != STATUS_SUCCESS) {
2429                         TRACE_RET(chip, STATUS_FAIL);
2430                 }
2431
2432                 sd_card->sd_addr = (u32)rsp[1] << 24;
2433                 sd_card->sd_addr += (u32)rsp[2] << 16;
2434
2435                 if (sd_card->sd_addr) {
2436                         break;
2437                 }
2438         }
2439
2440         retval = sd_check_csd(chip, 1);
2441         if (retval != STATUS_SUCCESS) {
2442                 TRACE_RET(chip, STATUS_FAIL);
2443         }
2444
2445         retval = sd_select_card(chip, 1);
2446         if (retval != STATUS_SUCCESS) {
2447                 TRACE_RET(chip, STATUS_FAIL);
2448         }
2449
2450 #ifdef SUPPORT_SD_LOCK
2451 SD_UNLOCK_ENTRY:
2452         retval = sd_update_lock_status(chip);
2453         if (retval != STATUS_SUCCESS) {
2454                 TRACE_RET(chip, STATUS_FAIL);
2455         }
2456
2457         if (sd_card->sd_lock_status & SD_LOCKED) {
2458                 sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST);
2459                 return STATUS_SUCCESS;
2460         } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) {
2461                 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
2462         }
2463 #endif
2464
2465         retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2466         if (retval != STATUS_SUCCESS) {
2467                 TRACE_RET(chip, STATUS_FAIL);
2468         }
2469         retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0, SD_RSP_TYPE_R1, NULL, 0);
2470         if (retval != STATUS_SUCCESS) {
2471                 TRACE_RET(chip, STATUS_FAIL);
2472         }
2473
2474         if (support_1v8) {
2475                 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2476                 if (retval != STATUS_SUCCESS) {
2477                         TRACE_RET(chip, STATUS_FAIL);
2478                 }
2479                 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1, NULL, 0);
2480                 if (retval != STATUS_SUCCESS) {
2481                         TRACE_RET(chip, STATUS_FAIL);
2482                 }
2483
2484                 switch_bus_width = SD_BUS_WIDTH_4;
2485         } else {
2486                 switch_bus_width = SD_BUS_WIDTH_1;
2487         }
2488
2489         retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, NULL, 0);
2490         if (retval != STATUS_SUCCESS) {
2491                 TRACE_RET(chip, STATUS_FAIL);
2492         }
2493
2494         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2495         if (retval != STATUS_SUCCESS) {
2496                 TRACE_RET(chip, STATUS_FAIL);
2497         }
2498
2499         if (!(sd_card->raw_csd[4] & 0x40))
2500                 sd_dont_switch = 1;
2501
2502         if (!sd_dont_switch) {
2503                 if (sd20_mode) {
2504                         /* Set sd_switch_fail here, because we needn't
2505                          * switch to UHS mode
2506                          */
2507                         sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
2508                                 DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
2509                 }
2510
2511                 /* Check the card whether follow SD1.1 spec or higher */
2512                 retval = sd_check_spec(chip, switch_bus_width);
2513                 if (retval == STATUS_SUCCESS) {
2514                         retval = sd_switch_function(chip, switch_bus_width);
2515                         if (retval != STATUS_SUCCESS) {
2516                                 if (CHECK_PID(chip, 0x5209)) {
2517                                         sd_change_bank_voltage(chip, SD_IO_3V3);
2518                                 }
2519                                 sd_init_power(chip);
2520                                 sd_dont_switch = 1;
2521                                 try_sdio = 0;
2522
2523                                 goto Switch_Fail;
2524                         }
2525                 } else {
2526                         if (support_1v8) {
2527                                 if (CHECK_PID(chip, 0x5209)) {
2528                                         sd_change_bank_voltage(chip, SD_IO_3V3);
2529                                 }
2530                                 sd_init_power(chip);
2531                                 sd_dont_switch = 1;
2532                                 try_sdio = 0;
2533
2534                                 goto Switch_Fail;
2535                         }
2536                 }
2537         }
2538
2539         if (!support_1v8) {
2540                 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2541                 if (retval != STATUS_SUCCESS) {
2542                         TRACE_RET(chip, STATUS_FAIL);
2543                 }
2544                 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1, NULL, 0);
2545                 if (retval != STATUS_SUCCESS) {
2546                         TRACE_RET(chip, STATUS_FAIL);
2547                 }
2548         }
2549
2550 #ifdef SUPPORT_SD_LOCK
2551         sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2552 #endif
2553
2554         if (!sd20_mode && CHK_SD30_SPEED(sd_card)) {
2555                 int read_lba0 = 1;
2556
2557                 RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_1v8);
2558
2559                 retval = sd_set_init_para(chip);
2560                 if (retval != STATUS_SUCCESS) {
2561                         TRACE_RET(chip, STATUS_FAIL);
2562                 }
2563
2564                 if (CHK_SD_DDR50(sd_card)) {
2565                         retval = sd_ddr_tuning(chip);
2566                 } else {
2567                         retval = sd_sdr_tuning(chip);
2568                 }
2569
2570                 if (retval != STATUS_SUCCESS) {
2571                         if (sd20_mode) {
2572                                 TRACE_RET(chip, STATUS_FAIL);
2573                         } else {
2574                                 retval = sd_init_power(chip);
2575                                 if (retval != STATUS_SUCCESS) {
2576                                         TRACE_RET(chip, STATUS_FAIL);
2577                                 }
2578                                 try_sdio = 0;
2579                                 sd20_mode = 1;
2580                                 goto Switch_Fail;
2581                         }
2582                 }
2583
2584                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2585
2586                 if (CHK_SD_DDR50(sd_card)) {
2587                         retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
2588                         if (retval != STATUS_SUCCESS) {
2589                                 read_lba0 = 0;
2590                         }
2591                 }
2592
2593                 if (read_lba0) {
2594                         retval = sd_read_lba0(chip);
2595                         if (retval != STATUS_SUCCESS) {
2596                                 if (sd20_mode) {
2597                                         TRACE_RET(chip, STATUS_FAIL);
2598                                 } else {
2599                                         retval = sd_init_power(chip);
2600                                         if (retval != STATUS_SUCCESS) {
2601                                                 TRACE_RET(chip, STATUS_FAIL);
2602                                         }
2603                                         try_sdio = 0;
2604                                         sd20_mode = 1;
2605                                         goto Switch_Fail;
2606                                 }
2607                         }
2608                 }
2609         }
2610
2611         retval = sd_check_wp_state(chip);
2612         if (retval != STATUS_SUCCESS) {
2613                 TRACE_RET(chip, STATUS_FAIL);
2614         }
2615
2616         chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2617
2618 #ifdef SUPPORT_SD_LOCK
2619         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2620                 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02);
2621                 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00);
2622         }
2623 #endif
2624
2625         return STATUS_SUCCESS;
2626 }
2627
2628
2629 static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width)
2630 {
2631         struct sd_info *sd_card = &(chip->sd_card);
2632         int retval;
2633         u8 buf[8] = {0}, bus_width, *ptr;
2634         u16 byte_cnt;
2635         int len;
2636
2637         retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL, 0);
2638         if (retval != STATUS_SUCCESS) {
2639                 TRACE_RET(chip, SWITCH_FAIL);
2640         }
2641
2642         if (width == MMC_8BIT_BUS) {
2643                 buf[0] = 0x55;
2644                 buf[1] = 0xAA;
2645                 len = 8;
2646                 byte_cnt = 8;
2647                 bus_width = SD_BUS_WIDTH_8;
2648         } else {
2649                 buf[0] = 0x5A;
2650                 len = 4;
2651                 byte_cnt = 4;
2652                 bus_width = SD_BUS_WIDTH_4;
2653         }
2654
2655         if (!CHECK_PID(chip, 0x5209)) {
2656                 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0x02);
2657                 if (retval != STATUS_SUCCESS)
2658                         TRACE_RET(chip, SWITCH_ERR);
2659         }
2660
2661         retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3,
2662                         NULL, 0, byte_cnt, 1, bus_width, buf, len, 100);
2663         if (retval != STATUS_SUCCESS) {
2664                 if (CHECK_PID(chip, 0x5209)) {
2665                         u8 val1 = 0, val2 = 0;
2666                         rtsx_read_register(chip, REG_SD_STAT1, &val1);
2667                         rtsx_read_register(chip, REG_SD_STAT2, &val2);
2668                         rtsx_clear_sd_error(chip);
2669                         if ((val1 & 0xE0) || val2) {
2670                                 TRACE_RET(chip, SWITCH_ERR);
2671                         }
2672                 } else {
2673                         rtsx_clear_sd_error(chip);
2674                         rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2675                         TRACE_RET(chip, SWITCH_ERR);
2676                 }
2677         }
2678
2679         if (!CHECK_PID(chip, 0x5209)) {
2680                 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2681                 if (retval != STATUS_SUCCESS)
2682                         TRACE_RET(chip, SWITCH_ERR);
2683         }
2684
2685         RTSX_DEBUGP("SD/MMC CMD %d\n", BUSTEST_R);
2686
2687         rtsx_init_cmd(chip);
2688
2689         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R);
2690
2691         if (width == MMC_8BIT_BUS) {
2692                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x08);
2693         } else {
2694                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x04);
2695         }
2696
2697         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2698         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2699
2700         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2701                         SD_CALCULATE_CRC7 | SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2702                         SD_CHECK_CRC7 | SD_RSP_LEN_6);
2703         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
2704         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_NORMAL_READ | SD_TRANSFER_START);
2705         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
2706
2707         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0);
2708         if (width == MMC_8BIT_BUS) {
2709                 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0);
2710         }
2711
2712         retval = rtsx_send_cmd(chip, SD_CARD, 100);
2713         if (retval < 0) {
2714                 rtsx_clear_sd_error(chip);
2715                 TRACE_RET(chip, SWITCH_ERR);
2716         }
2717
2718         ptr = rtsx_get_cmd_data(chip) + 1;
2719
2720         if (width == MMC_8BIT_BUS) {
2721                 RTSX_DEBUGP("BUSTEST_R [8bits]: 0x%02x 0x%02x\n", ptr[0], ptr[1]);
2722                 if ((ptr[0] == 0xAA) && (ptr[1] == 0x55)) {
2723                         u8 rsp[5];
2724                         u32 arg;
2725
2726                         if (CHK_MMC_DDR52(sd_card)) {
2727                                 arg = 0x03B70600;
2728                         } else {
2729                                 arg = 0x03B70200;
2730                         }
2731                         retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, SD_RSP_TYPE_R1b, rsp, 5);
2732                         if ((retval == STATUS_SUCCESS) && !(rsp[4] & MMC_SWITCH_ERR)) {
2733                                 return SWITCH_SUCCESS;
2734                         }
2735                 }
2736         } else {
2737                 RTSX_DEBUGP("BUSTEST_R [4bits]: 0x%02x\n", ptr[0]);
2738                 if (ptr[0] == 0xA5) {
2739                         u8 rsp[5];
2740                         u32 arg;
2741
2742                         if (CHK_MMC_DDR52(sd_card)) {
2743                                 arg = 0x03B70500;
2744                         } else {
2745                                 arg = 0x03B70100;
2746                         }
2747                         retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, SD_RSP_TYPE_R1b, rsp, 5);
2748                         if ((retval == STATUS_SUCCESS) && !(rsp[4] & MMC_SWITCH_ERR)) {
2749                                 return SWITCH_SUCCESS;
2750                         }
2751                 }
2752         }
2753
2754         TRACE_RET(chip, SWITCH_FAIL);
2755 }
2756
2757
2758 static int mmc_switch_timing_bus(struct rtsx_chip *chip, int switch_ddr)
2759 {
2760         struct sd_info *sd_card = &(chip->sd_card);
2761         int retval;
2762         u8 *ptr, card_type, card_type_mask = 0;
2763
2764         CLR_MMC_HS(sd_card);
2765
2766         RTSX_DEBUGP("SD/MMC CMD %d\n", SEND_EXT_CSD);
2767
2768         rtsx_init_cmd(chip);
2769
2770         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | SEND_EXT_CSD);
2771         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0);
2772         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0);
2773         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0);
2774         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0);
2775
2776         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0);
2777         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2);
2778         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2779         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2780
2781         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2782                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2783                         SD_CHECK_CRC7 | SD_RSP_LEN_6);
2784         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
2785         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_NORMAL_READ | SD_TRANSFER_START);
2786         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
2787
2788         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0);
2789         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0);
2790         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0);
2791         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0);
2792         rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0);
2793
2794         retval = rtsx_send_cmd(chip, SD_CARD, 1000);
2795         if (retval < 0) {
2796                 if (retval == -ETIMEDOUT) {
2797                         rtsx_clear_sd_error(chip);
2798                         sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2799                                         SD_RSP_TYPE_R1, NULL, 0);
2800                 }
2801                 TRACE_RET(chip, STATUS_FAIL);
2802         }
2803
2804         ptr = rtsx_get_cmd_data(chip);
2805         if (ptr[0] & SD_TRANSFER_ERR) {
2806                 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2807                 TRACE_RET(chip, STATUS_FAIL);
2808         }
2809
2810         if (CHK_MMC_SECTOR_MODE(sd_card)) {
2811                 sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) |
2812                         ((u32)ptr[3] << 8) | ((u32)ptr[2]);
2813         }
2814
2815         if (CHECK_PID(chip, 0x5209)) {
2816 #ifdef SUPPORT_SD_LOCK
2817                 if (!(sd_card->sd_lock_status & SD_SDR_RST) &&
2818                                 (chip->sd_ctl & SUPPORT_MMC_DDR_MODE)) {
2819                         card_type_mask = 0x07;
2820                 } else {
2821                         card_type_mask = 0x03;
2822                 }
2823 #else
2824                 if (chip->sd_ctl & SUPPORT_MMC_DDR_MODE) {
2825                         card_type_mask = 0x07;
2826                 } else {
2827                         card_type_mask = 0x03;
2828                 }
2829 #endif
2830         } else {
2831                 card_type_mask = 0x03;
2832         }
2833         card_type = ptr[1] & card_type_mask;
2834         if (card_type) {
2835                 u8 rsp[5];
2836
2837                 if (card_type & 0x04) {
2838                         if (switch_ddr) {
2839                                 SET_MMC_DDR52(sd_card);
2840                         } else {
2841                                 SET_MMC_52M(sd_card);
2842                         }
2843                 } else if (card_type & 0x02) {
2844                         SET_MMC_52M(sd_card);
2845                 } else {
2846                         SET_MMC_26M(sd_card);
2847                 }
2848
2849                 retval = sd_send_cmd_get_rsp(chip, SWITCH,
2850                                 0x03B90100, SD_RSP_TYPE_R1b, rsp, 5);
2851                 if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR)) {
2852                         CLR_MMC_HS(sd_card);
2853                 }
2854         }
2855
2856         sd_choose_proper_clock(chip);
2857         retval = switch_clock(chip, sd_card->sd_clock);
2858         if (retval != STATUS_SUCCESS) {
2859                 TRACE_RET(chip, STATUS_FAIL);
2860         }
2861
2862         /* Test Bus Procedure */
2863         retval = mmc_test_switch_bus(chip, MMC_8BIT_BUS);
2864         if (retval == SWITCH_SUCCESS) {
2865                 SET_MMC_8BIT(sd_card);
2866                 chip->card_bus_width[chip->card2lun[SD_CARD]] = 8;
2867 #ifdef SUPPORT_SD_LOCK
2868                 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2869 #endif
2870         } else if (retval == SWITCH_FAIL) {
2871                 retval = mmc_test_switch_bus(chip, MMC_4BIT_BUS);
2872                 if (retval == SWITCH_SUCCESS) {
2873                         SET_MMC_4BIT(sd_card);
2874                         chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2875 #ifdef SUPPORT_SD_LOCK
2876                         sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2877 #endif
2878                 } else if (retval == SWITCH_FAIL) {
2879                         CLR_MMC_8BIT(sd_card);
2880                         CLR_MMC_4BIT(sd_card);
2881                 } else {
2882                         TRACE_RET(chip, STATUS_FAIL);
2883                 }
2884         } else {
2885                 TRACE_RET(chip, STATUS_FAIL);
2886         }
2887
2888         return STATUS_SUCCESS;
2889 }
2890
2891
2892 static int reset_mmc(struct rtsx_chip *chip)
2893 {
2894         struct sd_info *sd_card = &(chip->sd_card);
2895         int retval, i = 0, j = 0, k = 0;
2896         int switch_ddr = 1;
2897         u8 rsp[16];
2898         u8 spec_ver = 0;
2899         u32 temp;
2900
2901 #ifdef SUPPORT_SD_LOCK
2902         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2903                 goto MMC_UNLOCK_ENTRY;
2904 #endif
2905
2906 Switch_Fail:
2907         retval = sd_prepare_reset(chip);
2908         if (retval != STATUS_SUCCESS) {
2909                 TRACE_RET(chip, retval);
2910         }
2911
2912         SET_MMC(sd_card);
2913
2914 RTY_MMC_RST:
2915         retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0);
2916         if (retval != STATUS_SUCCESS) {
2917                TRACE_RET(chip, STATUS_FAIL);
2918         }
2919
2920         do {
2921                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2922                         sd_set_err_code(chip, SD_NO_CARD);
2923                         TRACE_RET(chip, STATUS_FAIL);
2924                 }
2925
2926                 retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND,
2927                                 (SUPPORT_VOLTAGE|0x40000000), SD_RSP_TYPE_R3, rsp, 5);
2928                 if (retval != STATUS_SUCCESS) {
2929                         if (sd_check_err_code(chip, SD_BUSY) || sd_check_err_code(chip, SD_TO_ERR)) {
2930                                 k++;
2931                                 if (k < 20) {
2932                                         sd_clr_err_code(chip);
2933                                         goto RTY_MMC_RST;
2934                                 } else {
2935                                         TRACE_RET(chip, STATUS_FAIL);
2936                                 }
2937                         } else {
2938                                 j++;
2939                                 if (j < 100) {
2940                                         sd_clr_err_code(chip);
2941                                         goto RTY_MMC_RST;
2942                                 } else {
2943                                         TRACE_RET(chip, STATUS_FAIL);
2944                                 }
2945                         }
2946                 }
2947
2948                 wait_timeout(20);
2949                 i++;
2950         } while (!(rsp[1] & 0x80) && (i < 255));
2951
2952         if (i == 255) {
2953                 TRACE_RET(chip, STATUS_FAIL);
2954         }
2955
2956         if ((rsp[1] & 0x60) == 0x40) {
2957                 SET_MMC_SECTOR_MODE(sd_card);
2958         } else {
2959                 CLR_MMC_SECTOR_MODE(sd_card);
2960         }
2961
2962         retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0);
2963         if (retval != STATUS_SUCCESS) {
2964                 TRACE_RET(chip, STATUS_FAIL);
2965         }
2966
2967         sd_card->sd_addr = 0x00100000;
2968         retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr, SD_RSP_TYPE_R6, rsp, 5);
2969         if (retval != STATUS_SUCCESS) {
2970                 TRACE_RET(chip, STATUS_FAIL);
2971         }
2972
2973         retval = sd_check_csd(chip, 1);
2974         if (retval != STATUS_SUCCESS) {
2975                 TRACE_RET(chip, STATUS_FAIL);
2976         }
2977
2978         spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2;
2979
2980         retval = sd_select_card(chip, 1);
2981         if (retval != STATUS_SUCCESS) {
2982                 TRACE_RET(chip, STATUS_FAIL);
2983         }
2984
2985         retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, NULL, 0);
2986         if (retval != STATUS_SUCCESS) {
2987                 TRACE_RET(chip, STATUS_FAIL);
2988         }
2989
2990 #ifdef SUPPORT_SD_LOCK
2991 MMC_UNLOCK_ENTRY:
2992         retval = sd_update_lock_status(chip);
2993         if (retval != STATUS_SUCCESS) {
2994                 TRACE_RET(chip, STATUS_FAIL);
2995         }
2996 #endif
2997
2998         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2999         if (retval != STATUS_SUCCESS) {
3000                 TRACE_RET(chip, STATUS_FAIL);
3001         }
3002
3003         chip->card_bus_width[chip->card2lun[SD_CARD]] = 1;
3004
3005         if (!sd_card->mmc_dont_switch_bus) {
3006                 if (spec_ver == 4) {
3007                         /* MMC 4.x Cards */
3008                         retval = mmc_switch_timing_bus(chip, switch_ddr);
3009                         if (retval != STATUS_SUCCESS) {
3010                                 retval = sd_init_power(chip);
3011                                 if (retval != STATUS_SUCCESS)
3012                                         TRACE_RET(chip, STATUS_FAIL);
3013                                 sd_card->mmc_dont_switch_bus = 1;
3014                                 TRACE_GOTO(chip, Switch_Fail);
3015                         }
3016                 }
3017
3018                 if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0)) {
3019                         TRACE_RET(chip, STATUS_FAIL);
3020                 }
3021
3022                 if (switch_ddr && CHK_MMC_DDR52(sd_card)) {
3023                         retval = sd_set_init_para(chip);
3024                         if (retval != STATUS_SUCCESS) {
3025                                 TRACE_RET(chip, STATUS_FAIL);
3026                         }
3027
3028                         retval = mmc_ddr_tuning(chip);
3029                         if (retval != STATUS_SUCCESS) {
3030                                 retval = sd_init_power(chip);
3031                                 if (retval != STATUS_SUCCESS) {
3032                                         TRACE_RET(chip, STATUS_FAIL);
3033                                 }
3034                                 switch_ddr = 0;
3035                                 TRACE_GOTO(chip, Switch_Fail);
3036                         }
3037
3038                         retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3039                         if (retval == STATUS_SUCCESS) {
3040                                 retval = sd_read_lba0(chip);
3041                                 if (retval != STATUS_SUCCESS) {
3042                                         retval = sd_init_power(chip);
3043                                         if (retval != STATUS_SUCCESS) {
3044                                                 TRACE_RET(chip, STATUS_FAIL);
3045                                         }
3046                                         switch_ddr = 0;
3047                                         TRACE_GOTO(chip, Switch_Fail);
3048                                 }
3049                         }
3050                 }
3051         }
3052
3053 #ifdef SUPPORT_SD_LOCK
3054         if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
3055                 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02);
3056                 RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00);
3057         }
3058 #endif
3059
3060         temp = rtsx_readl(chip, RTSX_BIPR);
3061         if (temp & SD_WRITE_PROTECT) {
3062                 chip->card_wp |= SD_CARD;
3063         }
3064
3065         return STATUS_SUCCESS;
3066 }
3067
3068 int reset_sd_card(struct rtsx_chip *chip)
3069 {
3070         struct sd_info *sd_card = &(chip->sd_card);
3071         int retval;
3072
3073         sd_init_reg_addr(chip);
3074
3075         memset(sd_card, 0, sizeof(struct sd_info));
3076         chip->capacity[chip->card2lun[SD_CARD]] = 0;
3077
3078         retval = enable_card_clock(chip, SD_CARD);
3079         if (retval != STATUS_SUCCESS) {
3080                 TRACE_RET(chip, STATUS_FAIL);
3081         }
3082
3083         if (chip->ignore_sd && CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
3084                 if (chip->asic_code) {
3085                         retval = sd_pull_ctl_enable(chip);
3086                         if (retval != STATUS_SUCCESS) {
3087                                 TRACE_RET(chip, STATUS_FAIL);
3088                         }
3089                 } else {
3090                         retval = rtsx_write_register(chip, FPGA_PULL_CTL,
3091                                                      FPGA_SD_PULL_CTL_BIT | 0x20, 0);
3092                         if (retval != STATUS_SUCCESS) {
3093                                 TRACE_RET(chip, STATUS_FAIL);
3094                         }
3095                 }
3096                 retval = card_share_mode(chip, SD_CARD);
3097                 if (retval != STATUS_SUCCESS) {
3098                         TRACE_RET(chip, STATUS_FAIL);
3099                 }
3100
3101                 chip->sd_io = 1;
3102                 TRACE_RET(chip, STATUS_FAIL);
3103         }
3104
3105         retval = sd_init_power(chip);
3106         if (retval != STATUS_SUCCESS) {
3107                 TRACE_RET(chip, STATUS_FAIL);
3108         }
3109
3110         if (chip->sd_ctl & RESET_MMC_FIRST) {
3111                 retval = reset_mmc(chip);
3112                 if (retval != STATUS_SUCCESS) {
3113                         if (sd_check_err_code(chip, SD_NO_CARD))
3114                                 TRACE_RET(chip, STATUS_FAIL);
3115
3116                         retval = reset_sd(chip);
3117                         if (retval != STATUS_SUCCESS) {
3118                                 if (CHECK_PID(chip, 0x5209))
3119                                         sd_change_bank_voltage(chip, SD_IO_3V3);
3120
3121                                 TRACE_RET(chip, STATUS_FAIL);
3122                         }
3123                 }
3124         } else {
3125                 retval = reset_sd(chip);
3126                 if (retval != STATUS_SUCCESS) {
3127                         if (sd_check_err_code(chip, SD_NO_CARD))
3128                                 TRACE_RET(chip, STATUS_FAIL);
3129
3130                         if (CHECK_PID(chip, 0x5209)) {
3131                                 retval = sd_change_bank_voltage(chip, SD_IO_3V3);
3132                                 if (retval != STATUS_SUCCESS)
3133                                         TRACE_RET(chip, STATUS_FAIL);
3134                         }
3135
3136                         if (chip->sd_io) {
3137                                 TRACE_RET(chip, STATUS_FAIL);
3138                         } else {
3139                                 retval = reset_mmc(chip);
3140                                 if (retval != STATUS_SUCCESS)
3141                                         TRACE_RET(chip, STATUS_FAIL);
3142                         }
3143                 }
3144         }
3145
3146         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3147         if (retval != STATUS_SUCCESS) {
3148                 TRACE_RET(chip, STATUS_FAIL);
3149         }
3150         RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3151         RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3152
3153         chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3154
3155         retval = sd_set_init_para(chip);
3156         if (retval != STATUS_SUCCESS) {
3157                 TRACE_RET(chip, STATUS_FAIL);
3158         }
3159
3160         RTSX_DEBUGP("sd_card->sd_type = 0x%x\n", sd_card->sd_type);
3161
3162         return STATUS_SUCCESS;
3163 }
3164
3165 static int reset_mmc_only(struct rtsx_chip *chip)
3166 {
3167         struct sd_info *sd_card = &(chip->sd_card);
3168         int retval;
3169
3170         sd_card->sd_type = 0;
3171         sd_card->seq_mode = 0;
3172         sd_card->sd_data_buf_ready = 0;
3173         sd_card->capacity = 0;
3174         sd_card->sd_switch_fail = 0;
3175
3176 #ifdef SUPPORT_SD_LOCK
3177         sd_card->sd_lock_status = 0;
3178         sd_card->sd_erase_status = 0;
3179 #endif
3180
3181         chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0;
3182
3183         retval = enable_card_clock(chip, SD_CARD);
3184         if (retval != STATUS_SUCCESS) {
3185                 TRACE_RET(chip, STATUS_FAIL);
3186         }
3187
3188         retval = sd_init_power(chip);
3189         if (retval != STATUS_SUCCESS) {
3190                 TRACE_RET(chip, STATUS_FAIL);
3191         }
3192
3193         retval = reset_mmc(chip);
3194         if (retval != STATUS_SUCCESS) {
3195                 TRACE_RET(chip, STATUS_FAIL);
3196         }
3197
3198         retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3199         if (retval != STATUS_SUCCESS) {
3200                 TRACE_RET(chip, STATUS_FAIL);
3201         }
3202         RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3203         RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3204
3205         chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3206
3207         retval = sd_set_init_para(chip);
3208         if (retval != STATUS_SUCCESS) {
3209                 TRACE_RET(chip, STATUS_FAIL);
3210         }
3211
3212         RTSX_DEBUGP("In reset_mmc_only, sd_card->sd_type = 0x%x\n", sd_card->sd_type);
3213
3214         return STATUS_SUCCESS;
3215 }
3216
3217 #define WAIT_DATA_READY_RTY_CNT         255
3218
3219 static int wait_data_buf_ready(struct rtsx_chip *chip)
3220 {
3221         struct sd_info *sd_card = &(chip->sd_card);
3222         int i, retval;
3223
3224         for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) {
3225                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3226                         sd_set_err_code(chip, SD_NO_CARD);
3227                         TRACE_RET(chip, STATUS_FAIL);
3228                 }
3229
3230                 sd_card->sd_data_buf_ready = 0;
3231
3232                 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
3233                                 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3234                 if (retval != STATUS_SUCCESS) {
3235                         TRACE_RET(chip, STATUS_FAIL);
3236                 }
3237
3238                 if (sd_card->sd_data_buf_ready) {
3239                         return sd_send_cmd_get_rsp(chip, SEND_STATUS,
3240                                 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3241                 }
3242         }
3243
3244         sd_set_err_code(chip, SD_TO_ERR);
3245
3246         TRACE_RET(chip, STATUS_FAIL);
3247 }
3248
3249 void sd_stop_seq_mode(struct rtsx_chip *chip)
3250 {
3251         struct sd_info *sd_card = &(chip->sd_card);
3252         int retval;
3253
3254         if (sd_card->seq_mode) {
3255                 retval = sd_switch_clock(chip);
3256                 if (retval != STATUS_SUCCESS) {
3257                         return;
3258                 }
3259
3260                 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3261                                 SD_RSP_TYPE_R1b, NULL, 0);
3262                 if (retval != STATUS_SUCCESS) {
3263                         sd_set_err_code(chip, SD_STS_ERR);
3264                 }
3265                 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3266                 if (retval != STATUS_SUCCESS) {
3267                         sd_set_err_code(chip, SD_STS_ERR);
3268                 }
3269                 sd_card->seq_mode = 0;
3270
3271                 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3272         }
3273 }
3274
3275 static inline int sd_auto_tune_clock(struct rtsx_chip *chip)
3276 {
3277         struct sd_info *sd_card = &(chip->sd_card);
3278         int retval;
3279
3280         if (chip->asic_code) {
3281                 if (sd_card->sd_clock > 30) {
3282                         sd_card->sd_clock -= 20;
3283                 }
3284         } else {
3285                 switch (sd_card->sd_clock) {
3286                 case CLK_200:
3287                         sd_card->sd_clock = CLK_150;
3288                         break;
3289
3290                 case CLK_150:
3291                         sd_card->sd_clock = CLK_120;
3292                         break;
3293
3294                 case CLK_120:
3295                         sd_card->sd_clock = CLK_100;
3296                         break;
3297
3298                 case CLK_100:
3299                         sd_card->sd_clock = CLK_80;
3300                         break;
3301
3302                 case CLK_80:
3303                         sd_card->sd_clock = CLK_60;
3304                         break;
3305
3306                 case CLK_60:
3307                         sd_card->sd_clock = CLK_50;
3308                         break;
3309
3310                 default:
3311                         break;
3312                 }
3313         }
3314
3315         retval = sd_switch_clock(chip);
3316         if (retval != STATUS_SUCCESS) {
3317                 TRACE_RET(chip, STATUS_FAIL);
3318         }
3319
3320         return STATUS_SUCCESS;
3321 }
3322
3323 int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt)
3324 {
3325         struct sd_info *sd_card = &(chip->sd_card);
3326         u32 data_addr;
3327         u8 cfg2;
3328         int retval;
3329
3330         if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3331                 RTSX_DEBUGP("sd_rw: Read %d %s from 0x%x\n", sector_cnt,
3332                              (sector_cnt > 1) ? "sectors" : "sector", start_sector);
3333         } else {
3334                 RTSX_DEBUGP("sd_rw: Write %d %s to 0x%x\n", sector_cnt,
3335                              (sector_cnt > 1) ? "sectors" : "sector", start_sector);
3336         }
3337
3338         sd_card->cleanup_counter = 0;
3339
3340         if (!(chip->card_ready & SD_CARD)) {
3341                 sd_card->seq_mode = 0;
3342
3343                 retval = reset_sd_card(chip);
3344                 if (retval == STATUS_SUCCESS) {
3345                         chip->card_ready |= SD_CARD;
3346                         chip->card_fail &= ~SD_CARD;
3347                 } else {
3348                         chip->card_ready &= ~SD_CARD;
3349                         chip->card_fail |= SD_CARD;
3350                         chip->capacity[chip->card2lun[SD_CARD]] = 0;
3351                         chip->rw_need_retry = 1;
3352                         TRACE_RET(chip, STATUS_FAIL);
3353                 }
3354         }
3355
3356         if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card)) {
3357                 data_addr = start_sector << 9;
3358         } else {
3359                 data_addr = start_sector;
3360         }
3361
3362         sd_clr_err_code(chip);
3363
3364         retval = sd_switch_clock(chip);
3365         if (retval != STATUS_SUCCESS) {
3366                 sd_set_err_code(chip, SD_IO_ERR);
3367                 TRACE_GOTO(chip, RW_FAIL);
3368         }
3369
3370         if (sd_card->seq_mode && ((sd_card->pre_dir != srb->sc_data_direction)
3371                         || ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) != start_sector))) {
3372                 if ((sd_card->pre_sec_cnt < 0x80)
3373                                 && (sd_card->pre_dir == DMA_FROM_DEVICE)
3374                                 && !CHK_SD30_SPEED(sd_card)
3375                                 && !CHK_SD_HS(sd_card)
3376                                 && !CHK_MMC_HS(sd_card)) {
3377                         sd_send_cmd_get_rsp(chip, SEND_STATUS,
3378                                         sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3379                 }
3380
3381                 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
3382                                 0, SD_RSP_TYPE_R1b, NULL, 0);
3383                 if (retval != STATUS_SUCCESS) {
3384                         chip->rw_need_retry = 1;
3385                         sd_set_err_code(chip, SD_STS_ERR);
3386                         TRACE_GOTO(chip, RW_FAIL);
3387                 }
3388
3389                 sd_card->seq_mode = 0;
3390
3391                 retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3392                 if (retval != STATUS_SUCCESS) {
3393                         sd_set_err_code(chip, SD_IO_ERR);
3394                         TRACE_GOTO(chip, RW_FAIL);
3395                 }
3396
3397                 if ((sd_card->pre_sec_cnt < 0x80)
3398                                 && !CHK_SD30_SPEED(sd_card)
3399                                 && !CHK_SD_HS(sd_card)
3400                                 && !CHK_MMC_HS(sd_card)) {
3401                         sd_send_cmd_get_rsp(chip, SEND_STATUS,
3402                                         sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3403                 }
3404         }
3405
3406         rtsx_init_cmd(chip);
3407
3408         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
3409         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
3410         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)sector_cnt);
3411         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(sector_cnt >> 8));
3412
3413         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3414
3415         if (CHK_MMC_8BIT(sd_card)) {
3416                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8);
3417         } else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card)) {
3418                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3419         } else {
3420                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_1);
3421         }
3422
3423         if (sd_card->seq_mode) {
3424                 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3425                                 SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3426                 if (CHECK_PID(chip, 0x5209)) {
3427                         if (!CHK_SD30_SPEED(sd_card)) {
3428                                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
3429                         }
3430                 }
3431                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3432
3433                 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512);
3434
3435                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3436                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3437                                      SD_TM_AUTO_READ_3 | SD_TRANSFER_START);
3438                 } else {
3439                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3440                                      SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3441                 }
3442
3443                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
3444
3445                 rtsx_send_cmd_no_wait(chip);
3446         } else {
3447                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3448                         RTSX_DEBUGP("SD/MMC CMD %d\n", READ_MULTIPLE_BLOCK);
3449                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3450                                      0x40 | READ_MULTIPLE_BLOCK);
3451                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(data_addr >> 24));
3452                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(data_addr >> 16));
3453                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(data_addr >> 8));
3454                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)data_addr);
3455
3456                         cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3457                                         SD_CHECK_CRC7 | SD_RSP_LEN_6;
3458                         if (CHECK_PID(chip, 0x5209)) {
3459                                 if (!CHK_SD30_SPEED(sd_card)) {
3460                                         cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
3461                                 }
3462                         }
3463                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3464
3465                         trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512);
3466
3467                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3468                                      SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3469                         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3470                                      SD_TRANSFER_END, SD_TRANSFER_END);
3471
3472                         rtsx_send_cmd_no_wait(chip);
3473                 } else {
3474                         retval = rtsx_send_cmd(chip, SD_CARD, 50);
3475                         if (retval < 0) {
3476                                 rtsx_clear_sd_error(chip);
3477
3478                                 chip->rw_need_retry = 1;
3479                                 sd_set_err_code(chip, SD_TO_ERR);
3480                                 TRACE_GOTO(chip, RW_FAIL);
3481                         }
3482
3483                         retval = wait_data_buf_ready(chip);
3484                         if (retval != STATUS_SUCCESS) {
3485                                 chip->rw_need_retry = 1;
3486                                 sd_set_err_code(chip, SD_TO_ERR);
3487                                 TRACE_GOTO(chip, RW_FAIL);
3488                         }
3489
3490                         retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK,
3491                                         data_addr, SD_RSP_TYPE_R1, NULL, 0);
3492                         if (retval != STATUS_SUCCESS) {
3493                                 chip->rw_need_retry = 1;
3494                                 TRACE_GOTO(chip, RW_FAIL);
3495                         }
3496
3497                         rtsx_init_cmd(chip);
3498
3499                         cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3500                                         SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3501                         if (CHECK_PID(chip, 0x5209)) {
3502                                 if (!CHK_SD30_SPEED(sd_card)) {
3503                                         cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
3504                                 }
3505                         }
3506                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3507
3508                         trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512);
3509
3510                         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3511                                      SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3512                         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3513                                      SD_TRANSFER_END, SD_TRANSFER_END);
3514
3515                         rtsx_send_cmd_no_wait(chip);
3516                 }
3517
3518                 sd_card->seq_mode = 1;
3519         }
3520
3521         retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb),
3522                         scsi_sg_count(srb), srb->sc_data_direction, chip->sd_timeout);
3523         if (retval < 0) {
3524                 u8 stat = 0;
3525                 int err;
3526
3527                 sd_card->seq_mode = 0;
3528
3529                 if (retval == -ETIMEDOUT) {
3530                         err = STATUS_TIMEDOUT;
3531                 } else {
3532                         err = STATUS_FAIL;
3533                 }
3534
3535                 rtsx_read_register(chip, REG_SD_STAT1, &stat);
3536                 rtsx_clear_sd_error(chip);
3537                 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3538                         chip->rw_need_retry = 0;
3539                         RTSX_DEBUGP("No card exist, exit sd_rw\n");
3540                         TRACE_RET(chip, STATUS_FAIL);
3541                 }
3542
3543                 chip->rw_need_retry = 1;
3544
3545                 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, SD_RSP_TYPE_R1b, NULL, 0);
3546                 if (retval != STATUS_SUCCESS) {
3547                         sd_set_err_code(chip, SD_STS_ERR);
3548                         TRACE_GOTO(chip, RW_FAIL);
3549                 }
3550
3551                 if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) {
3552                         RTSX_DEBUGP("SD CRC error, tune clock!\n");
3553                         sd_set_err_code(chip, SD_CRC_ERR);
3554                         TRACE_GOTO(chip, RW_FAIL);
3555                 }
3556
3557                 if (err == STATUS_TIMEDOUT) {
3558                         sd_set_err_code(chip, SD_TO_ERR);
3559                         TRACE_GOTO(chip, RW_FAIL);
3560                 }
3561
3562                 TRACE_RET(chip, err);
3563         }
3564
3565         sd_card->pre_sec_addr = start_sector;
3566         sd_card->pre_sec_cnt = sector_cnt;
3567         sd_card->pre_dir = srb->sc_data_direction;
3568
3569         return STATUS_SUCCESS;
3570
3571 RW_FAIL:
3572         sd_card->seq_mode = 0;
3573
3574         if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3575                 chip->rw_need_retry = 0;
3576                 RTSX_DEBUGP("No card exist, exit sd_rw\n");
3577                 TRACE_RET(chip, STATUS_FAIL);
3578         }
3579
3580         if (sd_check_err_code(chip, SD_CRC_ERR)) {
3581                 if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) {
3582                         sd_card->mmc_dont_switch_bus = 1;
3583                         reset_mmc_only(chip);
3584                         sd_card->mmc_dont_switch_bus = 0;
3585                 } else {
3586                         sd_card->need_retune = 1;
3587                         sd_auto_tune_clock(chip);
3588                 }
3589         } else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) {
3590                 retval = reset_sd_card(chip);
3591                 if (retval != STATUS_SUCCESS) {
3592                         chip->card_ready &= ~SD_CARD;
3593                         chip->card_fail |= SD_CARD;
3594                         chip->capacity[chip->card2lun[SD_CARD]] = 0;
3595                 }
3596         }
3597
3598         TRACE_RET(chip, STATUS_FAIL);
3599 }
3600
3601 #ifdef SUPPORT_CPRM
3602 int soft_reset_sd_card(struct rtsx_chip *chip)
3603 {
3604         return reset_sd(chip);
3605 }
3606
3607 int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
3608                 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, int special_check)
3609 {
3610         int retval;
3611         int timeout = 100;
3612         u16 reg_addr;
3613         u8 *ptr;
3614         int stat_idx = 0;
3615         int rty_cnt = 0;
3616
3617         RTSX_DEBUGP("EXT SD/MMC CMD %d\n", cmd_idx);
3618
3619         if (rsp_type == SD_RSP_TYPE_R1b) {
3620                 timeout = 3000;
3621         }
3622
3623 RTY_SEND_CMD:
3624
3625         rtsx_init_cmd(chip);
3626
3627         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
3628         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
3629         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
3630         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
3631         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
3632
3633         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
3634         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3635                         0x01, PINGPONG_BUFFER);
3636         rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
3637                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
3638         rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
3639
3640         if (rsp_type == SD_RSP_TYPE_R2) {
3641                 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) {
3642                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3643                 }
3644                 stat_idx = 17;
3645         } else if (rsp_type != SD_RSP_TYPE_R0) {
3646                 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++) {
3647                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3648                 }
3649                 stat_idx = 6;
3650         }
3651         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0);
3652
3653         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
3654
3655         retval = rtsx_send_cmd(chip, SD_CARD, timeout);
3656         if (retval < 0) {
3657                 if (retval == -ETIMEDOUT) {
3658                         rtsx_clear_sd_error(chip);
3659
3660                         if (rsp_type & SD_WAIT_BUSY_END) {
3661                                 retval = sd_check_data0_status(chip);
3662                                 if (retval != STATUS_SUCCESS) {
3663                                         TRACE_RET(chip, retval);
3664                                 }
3665                         } else {
3666                                 sd_set_err_code(chip, SD_TO_ERR);
3667                         }
3668                 }
3669                 TRACE_RET(chip, STATUS_FAIL);
3670         }
3671
3672         if (rsp_type == SD_RSP_TYPE_R0) {
3673                 return STATUS_SUCCESS;
3674         }
3675
3676         ptr = rtsx_get_cmd_data(chip) + 1;
3677
3678         if ((ptr[0] & 0xC0) != 0) {
3679                 sd_set_err_code(chip, SD_STS_ERR);
3680                 TRACE_RET(chip, STATUS_FAIL);
3681         }
3682
3683         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
3684                 if (ptr[stat_idx] & SD_CRC7_ERR) {
3685                         if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
3686                                 sd_set_err_code(chip, SD_CRC_ERR);
3687                                 TRACE_RET(chip, STATUS_FAIL);
3688                         }
3689                         if (rty_cnt < SD_MAX_RETRY_COUNT) {
3690                                 wait_timeout(20);
3691                                 rty_cnt++;
3692                                 goto RTY_SEND_CMD;
3693                         } else {
3694                                 sd_set_err_code(chip, SD_CRC_ERR);
3695                                 TRACE_RET(chip, STATUS_FAIL);
3696                         }
3697                 }
3698         }
3699
3700         if ((cmd_idx == SELECT_CARD) || (cmd_idx == APP_CMD) ||
3701                         (cmd_idx == SEND_STATUS) || (cmd_idx == STOP_TRANSMISSION)) {
3702                 if ((cmd_idx != STOP_TRANSMISSION) && (special_check == 0)) {
3703                         if (ptr[1] & 0x80) {
3704                                 TRACE_RET(chip, STATUS_FAIL);
3705                         }
3706                 }
3707 #ifdef SUPPORT_SD_LOCK
3708                 if (ptr[1] & 0x7D)
3709 #else
3710                 if (ptr[1] & 0x7F)
3711 #endif
3712                 {
3713                         TRACE_RET(chip, STATUS_FAIL);
3714                 }
3715                 if (ptr[2] & 0xF8) {
3716                         TRACE_RET(chip, STATUS_FAIL);
3717                 }
3718
3719                 if (cmd_idx == SELECT_CARD) {
3720                         if (rsp_type == SD_RSP_TYPE_R2) {
3721                                 if ((ptr[3] & 0x1E) != 0x04) {
3722                                         TRACE_RET(chip, STATUS_FAIL);
3723                                 }
3724                         } else if (rsp_type == SD_RSP_TYPE_R0) {
3725                                 if ((ptr[3] & 0x1E) != 0x03) {
3726                                         TRACE_RET(chip, STATUS_FAIL);
3727                                 }
3728                         }
3729                 }
3730         }
3731
3732         if (rsp && rsp_len) {
3733                 memcpy(rsp, ptr, rsp_len);
3734         }
3735
3736         return STATUS_SUCCESS;
3737 }
3738
3739 int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type)
3740 {
3741         int retval, rsp_len;
3742         u16 reg_addr;
3743
3744         if (rsp_type == SD_RSP_TYPE_R0) {
3745                 return STATUS_SUCCESS;
3746         }
3747
3748         rtsx_init_cmd(chip);
3749
3750         if (rsp_type == SD_RSP_TYPE_R2) {
3751                 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++) {
3752                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3753                 }
3754                 rsp_len = 17;
3755         } else if (rsp_type != SD_RSP_TYPE_R0) {
3756                 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++) {
3757                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3758                 }
3759                 rsp_len = 6;
3760         }
3761         rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0);
3762
3763         retval = rtsx_send_cmd(chip, SD_CARD, 100);
3764         if (retval != STATUS_SUCCESS) {
3765                 TRACE_RET(chip, STATUS_FAIL);
3766         }
3767
3768         if (rsp) {
3769                 int min_len = (rsp_len < len) ? rsp_len : len;
3770
3771                 memcpy(rsp, rtsx_get_cmd_data(chip), min_len);
3772
3773                 RTSX_DEBUGP("min_len = %d\n", min_len);
3774                 RTSX_DEBUGP("Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n",
3775                         rsp[0], rsp[1], rsp[2], rsp[3]);
3776         }
3777
3778         return STATUS_SUCCESS;
3779 }
3780
3781 int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3782 {
3783         struct sd_info *sd_card = &(chip->sd_card);
3784         unsigned int lun = SCSI_LUN(srb);
3785         int len;
3786         u8 buf[18] = {
3787                 0x00,
3788                 0x00,
3789                 0x00,
3790                 0x0E,
3791                 0x00,
3792                 0x00,
3793                 0x00,
3794                 0x00,
3795                 0x53,
3796                 0x44,
3797                 0x20,
3798                 0x43,
3799                 0x61,
3800                 0x72,
3801                 0x64,
3802                 0x00,
3803                 0x00,
3804                 0x00,
3805         };
3806
3807         sd_card->pre_cmd_err = 0;
3808
3809         if (!(CHK_BIT(chip->lun_mc, lun))) {
3810                 SET_BIT(chip->lun_mc, lun);
3811                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3812                 TRACE_RET(chip, TRANSPORT_FAILED);
3813         }
3814
3815         if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) || (0x20 != srb->cmnd[4]) ||
3816                         (0x43 != srb->cmnd[5]) || (0x61 != srb->cmnd[6]) ||
3817                         (0x72 != srb->cmnd[7]) || (0x64 != srb->cmnd[8])) {
3818                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3819                 TRACE_RET(chip, TRANSPORT_FAILED);
3820         }
3821
3822         switch (srb->cmnd[1] & 0x0F) {
3823         case 0:
3824                 sd_card->sd_pass_thru_en = 0;
3825                 break;
3826
3827         case 1:
3828                 sd_card->sd_pass_thru_en = 1;
3829                 break;
3830
3831         default:
3832                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3833                 TRACE_RET(chip, TRANSPORT_FAILED);
3834         }
3835
3836         buf[5] = (1 == CHK_SD(sd_card)) ?  0x01 : 0x02;
3837         if (chip->card_wp & SD_CARD) {
3838                 buf[5] |= 0x80;
3839         }
3840
3841         buf[6] = (u8)(sd_card->sd_addr >> 16);
3842         buf[7] = (u8)(sd_card->sd_addr >> 24);
3843
3844         buf[15] = chip->max_lun;
3845
3846         len = min(18, (int)scsi_bufflen(srb));
3847         rtsx_stor_set_xfer_buf(buf, len, srb);
3848
3849         return TRANSPORT_GOOD;
3850 }
3851
3852 static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type, int *rsp_len)
3853 {
3854         if (!rsp_type || !rsp_len) {
3855                 return STATUS_FAIL;
3856         }
3857
3858         switch (srb->cmnd[10]) {
3859         case 0x03:
3860                 *rsp_type = SD_RSP_TYPE_R0;
3861                 *rsp_len = 0;
3862                 break;
3863
3864         case 0x04:
3865                 *rsp_type = SD_RSP_TYPE_R1;
3866                 *rsp_len = 6;
3867                 break;
3868
3869         case 0x05:
3870                 *rsp_type = SD_RSP_TYPE_R1b;
3871                 *rsp_len = 6;
3872                 break;
3873
3874         case 0x06:
3875                 *rsp_type = SD_RSP_TYPE_R2;
3876                 *rsp_len = 17;
3877                 break;
3878
3879         case 0x07:
3880                 *rsp_type = SD_RSP_TYPE_R3;
3881                 *rsp_len = 6;
3882                 break;
3883
3884         default:
3885                 return STATUS_FAIL;
3886         }
3887
3888         return STATUS_SUCCESS;
3889 }
3890
3891 int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3892 {
3893         struct sd_info *sd_card = &(chip->sd_card);
3894         unsigned int lun = SCSI_LUN(srb);
3895         int retval, rsp_len;
3896         u8 cmd_idx, rsp_type;
3897         u8 standby = 0, acmd = 0;
3898         u32 arg;
3899
3900         if (!sd_card->sd_pass_thru_en) {
3901                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3902                 TRACE_RET(chip, TRANSPORT_FAILED);
3903         }
3904
3905         retval = sd_switch_clock(chip);
3906         if (retval != STATUS_SUCCESS) {
3907                 TRACE_RET(chip, TRANSPORT_FAILED);
3908         }
3909
3910         if (sd_card->pre_cmd_err) {
3911                 sd_card->pre_cmd_err = 0;
3912                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3913                 TRACE_RET(chip, TRANSPORT_FAILED);
3914         }
3915
3916         cmd_idx = srb->cmnd[2] & 0x3F;
3917         if (srb->cmnd[1] & 0x02) {
3918                 standby = 1;
3919         }
3920         if (srb->cmnd[1] & 0x01) {
3921                 acmd = 1;
3922         }
3923
3924         arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
3925                 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
3926
3927         retval = get_rsp_type(srb, &rsp_type, &rsp_len);
3928         if (retval != STATUS_SUCCESS) {
3929                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3930                 TRACE_RET(chip, TRANSPORT_FAILED);
3931         }
3932         sd_card->last_rsp_type = rsp_type;
3933
3934         retval = sd_switch_clock(chip);
3935         if (retval != STATUS_SUCCESS) {
3936                 TRACE_RET(chip, TRANSPORT_FAILED);
3937         }
3938
3939 #ifdef SUPPORT_SD_LOCK
3940         if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
3941                 if (CHK_MMC_8BIT(sd_card)) {
3942                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8);
3943                         if (retval != STATUS_SUCCESS) {
3944                                 TRACE_RET(chip, TRANSPORT_FAILED);
3945                         }
3946                 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
3947                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3948                         if (retval != STATUS_SUCCESS) {
3949                                 TRACE_RET(chip, TRANSPORT_FAILED);
3950                         }
3951                 }
3952         }
3953 #else
3954         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3955         if (retval != STATUS_SUCCESS) {
3956                 TRACE_RET(chip, TRANSPORT_FAILED);
3957         }
3958 #endif
3959
3960         if (standby) {
3961                 retval = sd_select_card(chip, 0);
3962                 if (retval != STATUS_SUCCESS) {
3963                         TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3964                 }
3965         }
3966
3967         if (acmd) {
3968                 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
3969                                 SD_RSP_TYPE_R1, NULL, 0, 0);
3970                 if (retval != STATUS_SUCCESS) {
3971                         TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3972                 }
3973         }
3974
3975         retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
3976                         sd_card->rsp, rsp_len, 0);
3977         if (retval != STATUS_SUCCESS) {
3978                 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3979         }
3980
3981         if (standby) {
3982                 retval = sd_select_card(chip, 1);
3983                 if (retval != STATUS_SUCCESS) {
3984                         TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3985                 }
3986         }
3987
3988 #ifdef SUPPORT_SD_LOCK
3989         retval = sd_update_lock_status(chip);
3990         if (retval != STATUS_SUCCESS) {
3991                 TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3992         }
3993 #endif
3994
3995         scsi_set_resid(srb, 0);
3996         return TRANSPORT_GOOD;
3997
3998 SD_Execute_Cmd_Failed:
3999         sd_card->pre_cmd_err = 1;
4000         set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4001         release_sd_card(chip);
4002         do_reset_sd_card(chip);
4003         if (!(chip->card_ready & SD_CARD)) {
4004                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4005         }
4006
4007         TRACE_RET(chip, TRANSPORT_FAILED);
4008 }
4009
4010 int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4011 {
4012         struct sd_info *sd_card = &(chip->sd_card);
4013         unsigned int lun = SCSI_LUN(srb);
4014         int retval, rsp_len, i;
4015         int cmd13_checkbit = 0, read_err = 0;
4016         u8 cmd_idx, rsp_type, bus_width;
4017         u8 send_cmd12 = 0, standby = 0, acmd = 0;
4018         u32 data_len;
4019
4020         if (!sd_card->sd_pass_thru_en) {
4021                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4022                 TRACE_RET(chip, TRANSPORT_FAILED);
4023         }
4024
4025         if (sd_card->pre_cmd_err) {
4026                 sd_card->pre_cmd_err = 0;
4027                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4028                 TRACE_RET(chip, TRANSPORT_FAILED);
4029         }
4030
4031         retval = sd_switch_clock(chip);
4032         if (retval != STATUS_SUCCESS) {
4033                 TRACE_RET(chip, TRANSPORT_FAILED);
4034         }
4035
4036         cmd_idx = srb->cmnd[2] & 0x3F;
4037         if (srb->cmnd[1] & 0x04) {
4038                 send_cmd12 = 1;
4039         }
4040         if (srb->cmnd[1] & 0x02) {
4041                 standby = 1;
4042         }
4043         if (srb->cmnd[1] & 0x01) {
4044                 acmd = 1;
4045         }
4046
4047         data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] << 8) | srb->cmnd[9];
4048
4049         retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4050         if (retval != STATUS_SUCCESS) {
4051                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4052                 TRACE_RET(chip, TRANSPORT_FAILED);
4053         }
4054         sd_card->last_rsp_type = rsp_type;
4055
4056         retval = sd_switch_clock(chip);
4057         if (retval != STATUS_SUCCESS) {
4058                 TRACE_RET(chip, TRANSPORT_FAILED);
4059         }
4060
4061 #ifdef SUPPORT_SD_LOCK
4062         if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4063                 if (CHK_MMC_8BIT(sd_card)) {
4064                         bus_width = SD_BUS_WIDTH_8;
4065                 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4066                         bus_width = SD_BUS_WIDTH_4;
4067                 } else {
4068                         bus_width = SD_BUS_WIDTH_1;
4069                 }
4070         } else {
4071                 bus_width = SD_BUS_WIDTH_4;
4072         }
4073         RTSX_DEBUGP("bus_width = %d\n", bus_width);
4074 #else
4075         bus_width = SD_BUS_WIDTH_4;
4076 #endif
4077
4078         if (data_len < 512) {
4079                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4080                                 SD_RSP_TYPE_R1, NULL, 0, 0);
4081                 if (retval != STATUS_SUCCESS) {
4082                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4083                 }
4084         }
4085
4086         if (standby) {
4087                 retval = sd_select_card(chip, 0);
4088                 if (retval != STATUS_SUCCESS) {
4089                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4090                 }
4091         }
4092
4093         if (acmd) {
4094                 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
4095                                 SD_RSP_TYPE_R1, NULL, 0, 0);
4096                 if (retval != STATUS_SUCCESS) {
4097                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4098                 }
4099         }
4100
4101         if (data_len <= 512) {
4102                 int min_len;
4103                 u8 *buf;
4104                 u16 byte_cnt, blk_cnt;
4105                 u8 cmd[5];
4106
4107                 byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9];
4108                 blk_cnt = 1;
4109
4110                 cmd[0] = 0x40 | cmd_idx;
4111                 cmd[1] = srb->cmnd[3];
4112                 cmd[2] = srb->cmnd[4];
4113                 cmd[3] = srb->cmnd[5];
4114                 cmd[4] = srb->cmnd[6];
4115
4116                 buf = kmalloc(data_len, GFP_KERNEL);
4117                 if (buf == NULL) {
4118                         TRACE_RET(chip, TRANSPORT_ERROR);
4119                 }
4120
4121                 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt,
4122                                        blk_cnt, bus_width, buf, data_len, 2000);
4123                 if (retval != STATUS_SUCCESS) {
4124                         read_err = 1;
4125                         kfree(buf);
4126                         rtsx_clear_sd_error(chip);
4127                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4128                 }
4129
4130                 min_len = min(data_len, scsi_bufflen(srb));
4131                 rtsx_stor_set_xfer_buf(buf, min_len, srb);
4132
4133                 kfree(buf);
4134         } else if (!(data_len & 0x1FF)) {
4135                 rtsx_init_cmd(chip);
4136
4137                 trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512);
4138
4139                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
4140                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
4141                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4142                                 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4143                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4144                                 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4145
4146                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
4147                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, srb->cmnd[3]);
4148                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, srb->cmnd[4]);
4149                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, srb->cmnd[5]);
4150                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, srb->cmnd[6]);
4151
4152                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
4153                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
4154
4155                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
4156                              0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
4157                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
4158
4159                 rtsx_send_cmd_no_wait(chip);
4160
4161                 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb),
4162                         scsi_sg_count(srb), DMA_FROM_DEVICE, 10000);
4163                 if (retval < 0) {
4164                         read_err = 1;
4165                         rtsx_clear_sd_error(chip);
4166                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4167                 }
4168
4169         } else {
4170                 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4171         }
4172
4173         retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type);
4174         if (retval != STATUS_SUCCESS) {
4175                 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4176         }
4177
4178         if (standby) {
4179                 retval = sd_select_card(chip, 1);
4180                 if (retval != STATUS_SUCCESS) {
4181                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4182                 }
4183         }
4184
4185         if (send_cmd12) {
4186                 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
4187                                 0, SD_RSP_TYPE_R1b, NULL, 0, 0);
4188                 if (retval != STATUS_SUCCESS) {
4189                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4190                 }
4191         }
4192
4193         if (data_len < 512) {
4194                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4195                                 SD_RSP_TYPE_R1, NULL, 0, 0);
4196                 if (retval != STATUS_SUCCESS) {
4197                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4198                 }
4199
4200                 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4201                 if (retval != STATUS_SUCCESS) {
4202                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4203                 }
4204                 retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4205                 if (retval != STATUS_SUCCESS) {
4206                         TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4207                 }
4208         }
4209
4210         if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) {
4211                 cmd13_checkbit = 1;
4212         }
4213
4214         for (i = 0; i < 3; i++) {
4215                 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
4216                         SD_RSP_TYPE_R1, NULL, 0, cmd13_checkbit);
4217                 if (retval == STATUS_SUCCESS) {
4218                         break;
4219                 }
4220         }
4221         if (retval != STATUS_SUCCESS) {
4222                 TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4223         }
4224
4225         scsi_set_resid(srb, 0);
4226         return TRANSPORT_GOOD;
4227
4228 SD_Execute_Read_Cmd_Failed:
4229         sd_card->pre_cmd_err = 1;
4230         set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4231         if (read_err) {
4232                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4233         }
4234         release_sd_card(chip);
4235         do_reset_sd_card(chip);
4236         if (!(chip->card_ready & SD_CARD)) {
4237                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4238         }
4239
4240         TRACE_RET(chip, TRANSPORT_FAILED);
4241 }
4242
4243 int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4244 {
4245         struct sd_info *sd_card = &(chip->sd_card);
4246         unsigned int lun = SCSI_LUN(srb);
4247         int retval, rsp_len, i;
4248         int cmd13_checkbit = 0, write_err = 0;
4249         u8 cmd_idx, rsp_type;
4250         u8 send_cmd12 = 0, standby = 0, acmd = 0;
4251         u32 data_len, arg;
4252 #ifdef SUPPORT_SD_LOCK
4253         int lock_cmd_fail = 0;
4254         u8 sd_lock_state = 0;
4255         u8 lock_cmd_type = 0;
4256 #endif
4257
4258         if (!sd_card->sd_pass_thru_en) {
4259                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4260                 TRACE_RET(chip, TRANSPORT_FAILED);
4261         }
4262
4263         if (sd_card->pre_cmd_err) {
4264                 sd_card->pre_cmd_err = 0;
4265                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4266                 TRACE_RET(chip, TRANSPORT_FAILED);
4267         }
4268
4269         retval = sd_switch_clock(chip);
4270         if (retval != STATUS_SUCCESS) {
4271                 TRACE_RET(chip, TRANSPORT_FAILED);
4272         }
4273
4274         cmd_idx = srb->cmnd[2] & 0x3F;
4275         if (srb->cmnd[1] & 0x04) {
4276                 send_cmd12 = 1;
4277         }
4278         if (srb->cmnd[1] & 0x02) {
4279                 standby = 1;
4280         }
4281         if (srb->cmnd[1] & 0x01) {
4282                 acmd = 1;
4283         }
4284
4285         data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] << 8) | srb->cmnd[9];
4286         arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
4287                 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
4288
4289 #ifdef SUPPORT_SD_LOCK
4290         if (cmd_idx == LOCK_UNLOCK) {
4291                 sd_lock_state = sd_card->sd_lock_status;
4292                 sd_lock_state &= SD_LOCKED;
4293         }
4294 #endif
4295
4296         retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4297         if (retval != STATUS_SUCCESS) {
4298                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4299                 TRACE_RET(chip, TRANSPORT_FAILED);
4300         }
4301         sd_card->last_rsp_type = rsp_type;
4302
4303         retval = sd_switch_clock(chip);
4304         if (retval != STATUS_SUCCESS) {
4305                 TRACE_RET(chip, TRANSPORT_FAILED);
4306         }
4307
4308 #ifdef SUPPORT_SD_LOCK
4309         if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4310                 if (CHK_MMC_8BIT(sd_card)) {
4311                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8);
4312                         if (retval != STATUS_SUCCESS) {
4313                                 TRACE_RET(chip, TRANSPORT_FAILED);
4314                         }
4315                 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4316                         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4317                         if (retval != STATUS_SUCCESS) {
4318                                 TRACE_RET(chip, TRANSPORT_FAILED);
4319                         }
4320                 }
4321         }
4322 #else
4323         retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4324         if (retval != STATUS_SUCCESS) {
4325                 TRACE_RET(chip, TRANSPORT_FAILED);
4326         }
4327 #endif
4328
4329         if (data_len < 512) {
4330                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4331                                 SD_RSP_TYPE_R1, NULL, 0, 0);
4332                 if (retval != STATUS_SUCCESS) {
4333                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4334                 }
4335         }
4336
4337         if (standby) {
4338                 retval = sd_select_card(chip, 0);
4339                 if (retval != STATUS_SUCCESS) {
4340                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4341                 }
4342         }
4343
4344         if (acmd) {
4345                 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
4346                                 SD_RSP_TYPE_R1, NULL, 0, 0);
4347                 if (retval != STATUS_SUCCESS) {
4348                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4349                 }
4350         }
4351
4352         retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
4353                         sd_card->rsp, rsp_len, 0);
4354         if (retval != STATUS_SUCCESS) {
4355                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4356         }
4357
4358         if (data_len <= 512) {
4359                 u16 i;
4360                 u8 *buf;
4361
4362                 buf = kmalloc(data_len, GFP_KERNEL);
4363                 if (buf == NULL) {
4364                         TRACE_RET(chip, TRANSPORT_ERROR);
4365                 }
4366
4367                 rtsx_stor_get_xfer_buf(buf, data_len, srb);
4368
4369 #ifdef SUPPORT_SD_LOCK
4370                 if (cmd_idx == LOCK_UNLOCK) {
4371                         lock_cmd_type = buf[0] & 0x0F;
4372                 }
4373 #endif
4374
4375                 if (data_len > 256) {
4376                         rtsx_init_cmd(chip);
4377                         for (i = 0; i < 256; i++) {
4378                                 rtsx_add_cmd(chip, WRITE_REG_CMD,
4379                                                 PPBUF_BASE2 + i, 0xFF, buf[i]);
4380                         }
4381                         retval = rtsx_send_cmd(chip, 0, 250);
4382                         if (retval != STATUS_SUCCESS) {
4383                                 kfree(buf);
4384                                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4385                         }
4386
4387                         rtsx_init_cmd(chip);
4388                         for (i = 256; i < data_len; i++) {
4389                                 rtsx_add_cmd(chip, WRITE_REG_CMD,
4390                                                 PPBUF_BASE2 + i, 0xFF, buf[i]);
4391                         }
4392                         retval = rtsx_send_cmd(chip, 0, 250);
4393                         if (retval != STATUS_SUCCESS) {
4394                                 kfree(buf);
4395                                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4396                         }
4397                 } else {
4398                         rtsx_init_cmd(chip);
4399                         for (i = 0; i < data_len; i++) {
4400                                 rtsx_add_cmd(chip, WRITE_REG_CMD,
4401                                                 PPBUF_BASE2 + i, 0xFF, buf[i]);
4402                         }
4403                         retval = rtsx_send_cmd(chip, 0, 250);
4404                         if (retval != STATUS_SUCCESS) {
4405                                 kfree(buf);
4406                                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4407                         }
4408                 }
4409
4410                 kfree(buf);
4411
4412                 rtsx_init_cmd(chip);
4413
4414                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, srb->cmnd[8] & 0x03);
4415                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, srb->cmnd[9]);
4416                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0x00);
4417                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 0x01);
4418                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
4419
4420                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4421                              SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4422                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
4423
4424                 retval = rtsx_send_cmd(chip, SD_CARD, 250);
4425         } else if (!(data_len & 0x1FF)) {
4426                 rtsx_init_cmd(chip);
4427
4428                 trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512);
4429
4430                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
4431                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
4432                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4433                                 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4434                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4435                                 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4436
4437                 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4438                 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
4439
4440                 rtsx_send_cmd_no_wait(chip);
4441
4442                 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb),
4443                         scsi_sg_count(srb), DMA_TO_DEVICE, 10000);
4444
4445         } else {
4446                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4447         }
4448
4449         if (retval < 0) {
4450                 write_err = 1;
4451                 rtsx_clear_sd_error(chip);
4452                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4453         }
4454
4455 #ifdef SUPPORT_SD_LOCK
4456         if (cmd_idx == LOCK_UNLOCK) {
4457                 if (lock_cmd_type == SD_ERASE) {
4458                         sd_card->sd_erase_status = SD_UNDER_ERASING;
4459                         scsi_set_resid(srb, 0);
4460                         return TRANSPORT_GOOD;
4461                 }
4462
4463                 rtsx_init_cmd(chip);
4464                 if (CHECK_PID(chip, 0x5209)) {
4465                         rtsx_add_cmd(chip, CHECK_REG_CMD, SD_BUS_STAT, SD_DAT0_STATUS, SD_DAT0_STATUS);
4466                 } else {
4467                         rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02);
4468                 }
4469                 rtsx_send_cmd(chip, SD_CARD, 250);
4470
4471                 retval = sd_update_lock_status(chip);
4472                 if (retval != STATUS_SUCCESS) {
4473                         RTSX_DEBUGP("Lock command fail!\n");
4474                         lock_cmd_fail = 1;
4475                 }
4476         }
4477 #endif /* SUPPORT_SD_LOCK */
4478
4479         if (standby) {
4480                 retval = sd_select_card(chip, 1);
4481                 if (retval != STATUS_SUCCESS) {
4482                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4483                 }
4484         }
4485
4486         if (send_cmd12) {
4487                 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
4488                                 0, SD_RSP_TYPE_R1b, NULL, 0, 0);
4489                 if (retval != STATUS_SUCCESS) {
4490                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4491                 }
4492         }
4493
4494         if (data_len < 512) {
4495                 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4496                                 SD_RSP_TYPE_R1, NULL, 0, 0);
4497                 if (retval != STATUS_SUCCESS) {
4498                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4499                 }
4500
4501                 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4502                 if (retval != STATUS_SUCCESS) {
4503                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4504                 }
4505                 rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4506                 if (retval != STATUS_SUCCESS) {
4507                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4508                 }
4509         }
4510
4511         if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) {
4512                 cmd13_checkbit = 1;
4513         }
4514
4515         for (i = 0; i < 3; i++) {
4516                 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
4517                         SD_RSP_TYPE_R1, NULL, 0, cmd13_checkbit);
4518                 if (retval == STATUS_SUCCESS) {
4519                         break;
4520                 }
4521         }
4522         if (retval != STATUS_SUCCESS) {
4523                 TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4524         }
4525
4526 #ifdef SUPPORT_SD_LOCK
4527         if (cmd_idx == LOCK_UNLOCK) {
4528                 if (!lock_cmd_fail) {
4529                         RTSX_DEBUGP("lock_cmd_type = 0x%x\n", lock_cmd_type);
4530                         if (lock_cmd_type & SD_CLR_PWD) {
4531                                 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
4532                         }
4533                         if (lock_cmd_type & SD_SET_PWD) {
4534                                 sd_card->sd_lock_status |= SD_PWD_EXIST;
4535                         }
4536                 }
4537
4538                 RTSX_DEBUGP("sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n",
4539                              sd_lock_state, sd_card->sd_lock_status);
4540                 if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) {
4541                         sd_card->sd_lock_notify = 1;
4542                         if (sd_lock_state) {
4543                                 if (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) {
4544                                         sd_card->sd_lock_status |= (SD_UNLOCK_POW_ON | SD_SDR_RST);
4545                                         if (CHK_SD(sd_card)) {
4546                                                 retval = reset_sd(chip);
4547                                                 if (retval != STATUS_SUCCESS) {
4548                                                         sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4549                                                         TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4550                                                 }
4551                                         }
4552
4553                                         sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4554                                 }
4555                         }
4556                 }
4557         }
4558
4559         if (lock_cmd_fail) {
4560                 scsi_set_resid(srb, 0);
4561                 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4562                 TRACE_RET(chip, TRANSPORT_FAILED);
4563         }
4564 #endif  /* SUPPORT_SD_LOCK */
4565
4566         scsi_set_resid(srb, 0);
4567         return TRANSPORT_GOOD;
4568
4569 SD_Execute_Write_Cmd_Failed:
4570         sd_card->pre_cmd_err = 1;
4571         set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4572         if (write_err) {
4573                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
4574         }
4575         release_sd_card(chip);
4576         do_reset_sd_card(chip);
4577         if (!(chip->card_ready & SD_CARD)) {
4578                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4579         }
4580
4581         TRACE_RET(chip, TRANSPORT_FAILED);
4582 }
4583
4584 int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4585 {
4586         struct sd_info *sd_card = &(chip->sd_card);
4587         unsigned int lun = SCSI_LUN(srb);
4588         int count;
4589         u16 data_len;
4590
4591         if (!sd_card->sd_pass_thru_en) {
4592                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4593                 TRACE_RET(chip, TRANSPORT_FAILED);
4594         }
4595
4596         if (sd_card->pre_cmd_err) {
4597                 sd_card->pre_cmd_err = 0;
4598                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4599                 TRACE_RET(chip, TRANSPORT_FAILED);
4600         }
4601
4602         data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8];
4603
4604         if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) {
4605                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4606                 TRACE_RET(chip, TRANSPORT_FAILED);
4607         } else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) {
4608                 count = (data_len < 17) ? data_len : 17;
4609         } else {
4610                 count = (data_len < 6) ? data_len : 6;
4611         }
4612         rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb);
4613
4614         RTSX_DEBUGP("Response length: %d\n", data_len);
4615         RTSX_DEBUGP("Response: 0x%x 0x%x 0x%x 0x%x\n",
4616                 sd_card->rsp[0], sd_card->rsp[1], sd_card->rsp[2], sd_card->rsp[3]);
4617
4618         scsi_set_resid(srb, 0);
4619         return TRANSPORT_GOOD;
4620 }
4621
4622 int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4623 {
4624         struct sd_info *sd_card = &(chip->sd_card);
4625         unsigned int lun = SCSI_LUN(srb);
4626         int retval;
4627
4628         if (!sd_card->sd_pass_thru_en) {
4629                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4630                 TRACE_RET(chip, TRANSPORT_FAILED);
4631         }
4632
4633         if (sd_card->pre_cmd_err) {
4634                 sd_card->pre_cmd_err = 0;
4635                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4636                 TRACE_RET(chip, TRANSPORT_FAILED);
4637         }
4638
4639         if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) || (0x20 != srb->cmnd[4]) ||
4640                         (0x43 != srb->cmnd[5]) || (0x61 != srb->cmnd[6]) ||
4641                         (0x72 != srb->cmnd[7]) || (0x64 != srb->cmnd[8])) {
4642                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4643                 TRACE_RET(chip, TRANSPORT_FAILED);
4644         }
4645
4646         switch (srb->cmnd[1] & 0x0F) {
4647         case 0:
4648 #ifdef SUPPORT_SD_LOCK
4649                 if (0x64 == srb->cmnd[9]) {
4650                         sd_card->sd_lock_status |= SD_SDR_RST;
4651                 }
4652 #endif
4653                 retval = reset_sd_card(chip);
4654                 if (retval != STATUS_SUCCESS) {
4655 #ifdef SUPPORT_SD_LOCK
4656                         sd_card->sd_lock_status &= ~SD_SDR_RST;
4657 #endif
4658                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4659                         sd_card->pre_cmd_err = 1;
4660                         TRACE_RET(chip, TRANSPORT_FAILED);
4661                 }
4662 #ifdef SUPPORT_SD_LOCK
4663                 sd_card->sd_lock_status &= ~SD_SDR_RST;
4664 #endif
4665                 break;
4666
4667         case 1:
4668                 retval = soft_reset_sd_card(chip);
4669                 if (retval != STATUS_SUCCESS) {
4670                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4671                         sd_card->pre_cmd_err = 1;
4672                         TRACE_RET(chip, TRANSPORT_FAILED);
4673                 }
4674                 break;
4675
4676         default:
4677                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4678                 TRACE_RET(chip, TRANSPORT_FAILED);
4679         }
4680
4681         scsi_set_resid(srb, 0);
4682         return TRANSPORT_GOOD;
4683 }
4684 #endif
4685
4686 void sd_cleanup_work(struct rtsx_chip *chip)
4687 {
4688         struct sd_info *sd_card = &(chip->sd_card);
4689
4690         if (sd_card->seq_mode) {
4691                 RTSX_DEBUGP("SD: stop transmission\n");
4692                 sd_stop_seq_mode(chip);
4693                 sd_card->cleanup_counter = 0;
4694         }
4695 }
4696
4697 int sd_power_off_card3v3(struct rtsx_chip *chip)
4698 {
4699         int retval;
4700
4701         retval = disable_card_clock(chip, SD_CARD);
4702         if (retval != STATUS_SUCCESS) {
4703                 TRACE_RET(chip, STATUS_FAIL);
4704         }
4705
4706         RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, 0);
4707
4708         if (!chip->ft2_fast_mode) {
4709                 retval = card_power_off(chip, SD_CARD);
4710                 if (retval != STATUS_SUCCESS) {
4711                         TRACE_RET(chip, STATUS_FAIL);
4712                 }
4713
4714                 wait_timeout(50);
4715         }
4716
4717         if (chip->asic_code) {
4718                 retval = sd_pull_ctl_disable(chip);
4719                 if (retval != STATUS_SUCCESS) {
4720                         TRACE_RET(chip, STATUS_FAIL);
4721                 }
4722         } else {
4723                 RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
4724                         FPGA_SD_PULL_CTL_BIT | 0x20, FPGA_SD_PULL_CTL_BIT);
4725         }
4726
4727         return STATUS_SUCCESS;
4728 }
4729
4730 int release_sd_card(struct rtsx_chip *chip)
4731 {
4732         struct sd_info *sd_card = &(chip->sd_card);
4733         int retval;
4734
4735         RTSX_DEBUGP("release_sd_card\n");
4736
4737         chip->card_ready &= ~SD_CARD;
4738         chip->card_fail &= ~SD_CARD;
4739         chip->card_wp &= ~SD_CARD;
4740
4741         chip->sd_io = 0;
4742         chip->sd_int = 0;
4743
4744 #ifdef SUPPORT_SD_LOCK
4745         sd_card->sd_lock_status = 0;
4746         sd_card->sd_erase_status = 0;
4747 #endif
4748
4749         memset(sd_card->raw_csd, 0, 16);
4750         memset(sd_card->raw_scr, 0, 8);
4751
4752         retval = sd_power_off_card3v3(chip);
4753         if (retval != STATUS_SUCCESS) {
4754                 TRACE_RET(chip, STATUS_FAIL);
4755         }
4756
4757         if (CHECK_PID(chip, 0x5209)) {
4758                 retval = sd_change_bank_voltage(chip, SD_IO_3V3);
4759                 if (retval != STATUS_SUCCESS) {
4760                         TRACE_RET(chip, STATUS_FAIL);
4761                 }
4762
4763                 if (CHK_SD30_SPEED(sd_card)) {
4764                         RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_3v3);
4765                 }
4766
4767                 RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK, chip->sd_400mA_ocp_thd);
4768         }
4769
4770         return STATUS_SUCCESS;
4771 }