1 /**************************************************************************
3 * Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above
13 * copyright notice, this list of conditions and the following
14 * disclaimer in the documentation and/or other materials provided
15 * with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
18 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
27 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * The views and conclusions contained in the software and documentation
31 * are those of the authors and should not be interpreted as representing
32 * official policies, either expressed or implied, of Alacritech, Inc.
34 **************************************************************************/
39 * This header file contains definitions that are common to our hardware.
44 #define PCI_VENDOR_ID_ALACRITECH 0x139A
45 #define SLIC_1GB_DEVICE_ID 0x0005
46 #define SLIC_2GB_DEVICE_ID 0x0007 /* Oasis Device ID */
48 #define SLIC_1GB_CICADA_SUBSYS_ID 0x0008
50 #define SLIC_NBR_MACS 4
52 #define SLIC_RCVBUF_SIZE 2048
53 #define SLIC_RCVBUF_HEADSIZE 34
54 #define SLIC_RCVBUF_TAILSIZE 0
55 #define SLIC_RCVBUF_DATASIZE (SLIC_RCVBUF_SIZE - \
56 (SLIC_RCVBUF_HEADSIZE + \
57 SLIC_RCVBUF_TAILSIZE))
59 #define VGBSTAT_XPERR 0x40000000
60 #define VGBSTAT_XERRSHFT 25
61 #define VGBSTAT_XCSERR 0x23
62 #define VGBSTAT_XUFLOW 0x22
63 #define VGBSTAT_XHLEN 0x20
64 #define VGBSTAT_NETERR 0x01000000
65 #define VGBSTAT_NERRSHFT 16
66 #define VGBSTAT_NERRMSK 0x1ff
67 #define VGBSTAT_NCSERR 0x103
68 #define VGBSTAT_NUFLOW 0x102
69 #define VGBSTAT_NHLEN 0x100
70 #define VGBSTAT_LNKERR 0x00000080
71 #define VGBSTAT_LERRMSK 0xff
72 #define VGBSTAT_LDEARLY 0x86
73 #define VGBSTAT_LBOFLO 0x85
74 #define VGBSTAT_LCODERR 0x84
75 #define VGBSTAT_LDBLNBL 0x83
76 #define VGBSTAT_LCRCERR 0x82
77 #define VGBSTAT_LOFLO 0x81
78 #define VGBSTAT_LUFLO 0x80
79 #define IRHDDR_FLEN_MSK 0x0000ffff
80 #define IRHDDR_SVALID 0x80000000
81 #define IRHDDR_ERR 0x10000000
82 #define VRHSTAT_802OE 0x80000000
83 #define VRHSTAT_TPOFLO 0x10000000
84 #define VRHSTATB_802UE 0x80000000
85 #define VRHSTATB_RCVE 0x40000000
86 #define VRHSTATB_BUFF 0x20000000
87 #define VRHSTATB_CARRE 0x08000000
88 #define VRHSTATB_LONGE 0x02000000
89 #define VRHSTATB_PREA 0x01000000
90 #define VRHSTATB_CRC 0x00800000
91 #define VRHSTATB_DRBL 0x00400000
92 #define VRHSTATB_CODE 0x00200000
93 #define VRHSTATB_TPCSUM 0x00100000
94 #define VRHSTATB_TPHLEN 0x00080000
95 #define VRHSTATB_IPCSUM 0x00040000
96 #define VRHSTATB_IPLERR 0x00020000
97 #define VRHSTATB_IPHERR 0x00010000
98 #define SLIC_MAX64_BCNT 23
99 #define SLIC_MAX32_BCNT 26
100 #define IHCMD_XMT_REQ 0x01
101 #define IHFLG_IFSHFT 2
102 #define SLIC_RSPBUF_SIZE 32
104 #define SLIC_RESET_MAGIC 0xDEAD
105 #define ICR_INT_OFF 0
107 #define ICR_INT_MASK 2
109 #define ISR_ERR 0x80000000
110 #define ISR_RCV 0x40000000
111 #define ISR_CMD 0x20000000
112 #define ISR_IO 0x60000000
113 #define ISR_UPC 0x10000000
114 #define ISR_LEVENT 0x08000000
115 #define ISR_RMISS 0x02000000
116 #define ISR_UPCERR 0x01000000
117 #define ISR_XDROP 0x00800000
118 #define ISR_UPCBSY 0x00020000
119 #define ISR_EVMSK 0xffff0000
120 #define ISR_PINGMASK 0x00700000
121 #define ISR_PINGDSMASK 0x00710000
122 #define ISR_UPCMASK 0x11000000
123 #define SLIC_WCS_START 0x80000000
124 #define SLIC_WCS_COMPARE 0x40000000
125 #define SLIC_RCVWCS_BEGIN 0x40000000
126 #define SLIC_RCVWCS_FINISH 0x80000000
127 #define SLIC_PM_MAXPATTERNS 6
128 #define SLIC_PM_PATTERNSIZE 128
129 #define SLIC_PMCAPS_WAKEONLAN 0x00000001
130 #define MIICR_REG_PCR 0x00000000
131 #define MIICR_REG_4 0x00040000
132 #define MIICR_REG_9 0x00090000
133 #define MIICR_REG_16 0x00100000
134 #define PCR_RESET 0x8000
135 #define PCR_POWERDOWN 0x0800
136 #define PCR_SPEED_100 0x2000
137 #define PCR_SPEED_1000 0x0040
138 #define PCR_AUTONEG 0x1000
139 #define PCR_AUTONEG_RST 0x0200
140 #define PCR_DUPLEX_FULL 0x0100
141 #define PSR_LINKUP 0x0004
143 #define PAR_ADV100FD 0x0100
144 #define PAR_ADV100HD 0x0080
145 #define PAR_ADV10FD 0x0040
146 #define PAR_ADV10HD 0x0020
147 #define PAR_ASYMPAUSE 0x0C00
148 #define PAR_802_3 0x0001
150 #define PAR_ADV1000XFD 0x0020
151 #define PAR_ADV1000XHD 0x0040
152 #define PAR_ASYMPAUSE_FIBER 0x0180
154 #define PGC_ADV1000FD 0x0200
155 #define PGC_ADV1000HD 0x0100
156 #define SEEQ_LINKFAIL 0x4000
157 #define SEEQ_SPEED 0x0080
158 #define SEEQ_DUPLEX 0x0040
159 #define TDK_DUPLEX 0x0800
160 #define TDK_SPEED 0x0400
161 #define MRV_REG16_XOVERON 0x0068
162 #define MRV_REG16_XOVEROFF 0x0008
163 #define MRV_SPEED_1000 0x8000
164 #define MRV_SPEED_100 0x4000
165 #define MRV_SPEED_10 0x0000
166 #define MRV_FULLDUPLEX 0x2000
167 #define MRV_LINKUP 0x0400
169 #define GIG_LINKUP 0x0001
170 #define GIG_FULLDUPLEX 0x0002
171 #define GIG_SPEED_MASK 0x000C
172 #define GIG_SPEED_1000 0x0008
173 #define GIG_SPEED_100 0x0004
174 #define GIG_SPEED_10 0x0000
176 #define MCR_RESET 0x80000000
177 #define MCR_CRCEN 0x40000000
178 #define MCR_FULLD 0x10000000
179 #define MCR_PAD 0x02000000
180 #define MCR_RETRYLATE 0x01000000
181 #define MCR_BOL_SHIFT 21
182 #define MCR_IPG1_SHIFT 14
183 #define MCR_IPG2_SHIFT 7
184 #define MCR_IPG3_SHIFT 0
185 #define GMCR_RESET 0x80000000
186 #define GMCR_GBIT 0x20000000
187 #define GMCR_FULLD 0x10000000
188 #define GMCR_GAPBB_SHIFT 14
189 #define GMCR_GAPR1_SHIFT 7
190 #define GMCR_GAPR2_SHIFT 0
191 #define GMCR_GAPBB_1000 0x60
192 #define GMCR_GAPR1_1000 0x2C
193 #define GMCR_GAPR2_1000 0x40
194 #define GMCR_GAPBB_100 0x70
195 #define GMCR_GAPR1_100 0x2C
196 #define GMCR_GAPR2_100 0x40
197 #define XCR_RESET 0x80000000
198 #define XCR_XMTEN 0x40000000
199 #define XCR_PAUSEEN 0x20000000
200 #define XCR_LOADRNG 0x10000000
201 #define RCR_RESET 0x80000000
202 #define RCR_RCVEN 0x40000000
203 #define RCR_RCVALL 0x20000000
204 #define RCR_RCVBAD 0x10000000
205 #define RCR_CTLEN 0x08000000
206 #define RCR_ADDRAEN 0x02000000
207 #define GXCR_RESET 0x80000000
208 #define GXCR_XMTEN 0x40000000
209 #define GXCR_PAUSEEN 0x20000000
210 #define GRCR_RESET 0x80000000
211 #define GRCR_RCVEN 0x40000000
212 #define GRCR_RCVALL 0x20000000
213 #define GRCR_RCVBAD 0x10000000
214 #define GRCR_CTLEN 0x08000000
215 #define GRCR_ADDRAEN 0x02000000
216 #define GRCR_HASHSIZE_SHIFT 17
217 #define GRCR_HASHSIZE 14
219 #define SLIC_EEPROM_ID 0xA5A5
220 #define SLIC_SRAM_SIZE2GB (64 * 1024)
221 #define SLIC_SRAM_SIZE1GB (32 * 1024)
222 #define SLIC_HOSTID_DEFAULT 0xFFFF /* uninitialized hostid */
223 #define SLIC_NBR_MACS 4
235 u8 data[SLIC_RCVBUF_DATASIZE];
238 struct slic_hddr_wds {
257 #define frame_status14 u0.hdrs_14port.frame_status
258 #define frame_status_b14 u0.hdrs_14port.frame_status_b
259 #define frame_statusGB u0.hdrs_gbit.frame_status
261 struct slic_host64sg {
267 struct slic_host64_cmd {
279 struct slic_host64sg bufs[SLIC_MAX64_BCNT];
293 #define SLIC_REG_RESET 0x0000
294 /* Interrupt Control Register */
295 #define SLIC_REG_ICR 0x0008
296 /* Interrupt status pointer */
297 #define SLIC_REG_ISP 0x0010
298 /* Interrupt status */
299 #define SLIC_REG_ISR 0x0018
301 * Header buffer address reg
302 * 31-8 - phy addr of set of contiguous hdr buffers
303 * 7-0 - number of buffers passed
304 * Buffers are 256 bytes long on 256-byte boundaries.
306 #define SLIC_REG_HBAR 0x0020
308 * Data buffer handle & address reg
309 * 4 sets of registers; Buffers are 2K bytes long 2 per 4K page.
311 #define SLIC_REG_DBAR 0x0028
313 * Xmt Cmd buf addr regs.
314 * 1 per XMT interface
315 * 31-5 - phy addr of host command buffer
316 * 4-0 - length of cmd in multiples of 32 bytes
317 * Buffers are 32 bytes up to 512 bytes long
319 #define SLIC_REG_CBAR 0x0030
320 /* Write control store */
321 #define SLIC_REG_WCS 0x0034
323 * Response buffer address reg.
324 * 31-8 - phy addr of set of contiguous response buffers
325 * 7-0 - number of buffers passed
326 * Buffers are 32 bytes long on 32-byte boundaries.
328 #define SLIC_REG_RBAR 0x0038
329 /* Read statistics (UPR) */
330 #define SLIC_REG_RSTAT 0x0040
331 /* Read link status */
332 #define SLIC_REG_LSTAT 0x0048
333 /* Write Mac Config */
334 #define SLIC_REG_WMCFG 0x0050
335 /* Write phy register */
336 #define SLIC_REG_WPHY 0x0058
337 /* Rcv Cmd buf addr reg */
338 #define SLIC_REG_RCBAR 0x0060
339 /* Read SLIC Config*/
340 #define SLIC_REG_RCONFIG 0x0068
341 /* Interrupt aggregation time */
342 #define SLIC_REG_INTAGG 0x0070
343 /* Write XMIT config reg */
344 #define SLIC_REG_WXCFG 0x0078
345 /* Write RCV config reg */
346 #define SLIC_REG_WRCFG 0x0080
347 /* Write rcv addr a low */
348 #define SLIC_REG_WRADDRAL 0x0088
349 /* Write rcv addr a high */
350 #define SLIC_REG_WRADDRAH 0x0090
351 /* Write rcv addr b low */
352 #define SLIC_REG_WRADDRBL 0x0098
353 /* Write rcv addr b high */
354 #define SLIC_REG_WRADDRBH 0x00a0
355 /* Low bits of mcast mask */
356 #define SLIC_REG_MCASTLOW 0x00a8
357 /* High bits of mcast mask */
358 #define SLIC_REG_MCASTHIGH 0x00b0
360 #define SLIC_REG_PING 0x00b8
362 #define SLIC_REG_DUMP_CMD 0x00c0
363 /* Dump data pointer */
364 #define SLIC_REG_DUMP_DATA 0x00c8
365 /* Read card's pci_status register */
366 #define SLIC_REG_PCISTATUS 0x00d0
367 /* Write hostid field */
368 #define SLIC_REG_WRHOSTID 0x00d8
369 /* Put card in a low power state */
370 #define SLIC_REG_LOW_POWER 0x00e0
371 /* Force slic into quiescent state before soft reset */
372 #define SLIC_REG_QUIESCE 0x00e8
373 /* Reset interface queues */
374 #define SLIC_REG_RESET_IFACE 0x00f0
376 * Register is only written when it has changed.
377 * Bits 63-32 for host i/f addrs.
379 #define SLIC_REG_ADDR_UPPER 0x00f8
380 /* 64 bit Header buffer address reg */
381 #define SLIC_REG_HBAR64 0x0100
382 /* 64 bit Data buffer handle & address reg */
383 #define SLIC_REG_DBAR64 0x0108
384 /* 64 bit Xmt Cmd buf addr regs. */
385 #define SLIC_REG_CBAR64 0x0110
386 /* 64 bit Response buffer address reg.*/
387 #define SLIC_REG_RBAR64 0x0118
388 /* 64 bit Rcv Cmd buf addr reg*/
389 #define SLIC_REG_RCBAR64 0x0120
390 /* Read statistics (64 bit UPR) */
391 #define SLIC_REG_RSTAT64 0x0128
392 /* Download Gigabit RCV sequencer ucode */
393 #define SLIC_REG_RCV_WCS 0x0130
394 /* Write VlanId field */
395 #define SLIC_REG_WRVLANID 0x0138
396 /* Read Transformer info */
397 #define SLIC_REG_READ_XF_INFO 0x0140
398 /* Write Transformer info */
399 #define SLIC_REG_WRITE_XF_INFO 0x0148
400 /* Write card ticks per second */
401 #define SLIC_REG_TICKS_PER_SEC 0x0170
403 #define SLIC_REG_HOSTID 0x1554
418 struct inicpm_wakepattern {
420 u8 pattern[SLIC_PM_PATTERNSIZE];
421 u8 mask[SLIC_PM_PATTERNSIZE];
424 struct inicpm_state {
428 u32 wake_magicpacket;
429 u32 wake_framepattern;
430 struct inicpm_wakepattern wakepattern[SLIC_PM_MAXPATTERNS];
433 struct slicpm_packet_pattern {
442 enum slicpm_power_state {
443 slicpm_state_unspecified = 0,
451 struct slicpm_wakeup_capabilities {
452 enum slicpm_power_state min_magic_packet_wakeup;
453 enum slicpm_power_state min_pattern_wakeup;
454 enum slicpm_power_state min_link_change_wakeup;
457 struct slic_pnp_capabilities {
459 struct slicpm_wakeup_capabilities wakeup_capabilities;
462 struct slic_config_mac {
466 #define ATK_FRU_FORMAT 0x00
467 #define VENDOR1_FRU_FORMAT 0x01
468 #define VENDOR2_FRU_FORMAT 0x02
469 #define VENDOR3_FRU_FORMAT 0x03
470 #define VENDOR4_FRU_FORMAT 0x04
471 #define NO_FRU_FORMAT 0xFF
513 struct vendor1_fru vendor1_fru;
514 struct vendor2_fru vendor2_fru;
515 struct vendor3_fru vendor3_fru;
516 struct vendor4_fru vendor4_fru;
520 * SLIC EEPROM structure for Mojave
523 u16 Id; /* 00 EEPROM/FLASH Magic code 'A5A5'*/
524 u16 EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/
525 u16 FlashSize; /* 02 Flash size */
526 u16 EepromSize; /* 03 EEPROM Size */
527 u16 VendorId; /* 04 Vendor ID */
528 u16 DeviceId; /* 05 Device ID */
529 u8 RevisionId; /* 06 Revision ID */
530 u8 ClassCode[3]; /* 07 Class Code */
531 u8 DbgIntPin; /* 08 Debug Interrupt pin */
532 u8 NetIntPin0; /* Network Interrupt Pin */
533 u8 MinGrant; /* 09 Minimum grant */
534 u8 MaxLat; /* Maximum Latency */
535 u16 PciStatus; /* 10 PCI Status */
536 u16 SubSysVId; /* 11 Subsystem Vendor Id */
537 u16 SubSysId; /* 12 Subsystem ID */
538 u16 DbgDevId; /* 13 Debug Device Id */
539 u16 DramRomFn; /* 14 Dram/Rom function */
540 u16 DSize2Pci; /* 15 DRAM size to PCI (bytes * 64K) */
541 u16 RSize2Pci; /* 16 ROM extension size to PCI (bytes * 4k) */
542 u8 NetIntPin1; /* 17 Network Interface Pin 1
545 u8 NetIntPin2; /* Network Interface Pin 2 (simba/leone only)*/
547 u8 NetIntPin3; /* 18 Network Interface Pin 3 (simba only) */
548 u8 FreeTime; /* FreeTime setting (leone/mojave only) */
550 u8 TBIctl; /* 10-bit interface control (Mojave only) */
551 u16 DramSize; /* 19 DRAM size (bytes * 64k) */
554 /* Mac Interface Specific portions */
555 struct slic_config_mac MacInfo[SLIC_NBR_MACS];
556 } mac; /* MAC access for all boards */
558 /* use above struct for MAC access */
559 struct slic_config_mac pad[SLIC_NBR_MACS - 1];
560 u16 DeviceId2; /* Device ID for 2nd PCI function */
561 u8 IntPin2; /* Interrupt pin for 2nd PCI function */
562 u8 ClassCode2[3]; /* Class Code for 2nd PCI function */
563 } mojave; /* 2nd function access for gigabit board */
565 u16 CfgByte6; /* Config Byte 6 */
566 u16 PMECapab; /* Power Mgment capabilities */
567 u16 NwClkCtrls; /* NetworkClockControls */
568 u8 FruFormat; /* Alacritech FRU format type */
569 struct atk_fru AtkFru; /* Alacritech FRU information */
570 u8 OemFruFormat; /* optional OEM FRU format type */
571 union oemfru OemFru; /* optional OEM FRU information */
572 u8 Pad[4]; /* Pad to 128 bytes - includes 2 cksum bytes
573 * (if OEM FRU info exists) and two unusable
578 /* SLIC EEPROM structure for Oasis */
579 struct oslic_eeprom {
580 u16 Id; /* 00 EEPROM/FLASH Magic code 'A5A5' */
581 u16 EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/
582 u16 FlashConfig0; /* 02 Flash Config for SPI device 0 */
583 u16 FlashConfig1; /* 03 Flash Config for SPI device 1 */
584 u16 VendorId; /* 04 Vendor ID */
585 u16 DeviceId; /* 05 Device ID (function 0) */
586 u8 RevisionId; /* 06 Revision ID */
587 u8 ClassCode[3]; /* 07 Class Code for PCI function 0 */
588 u8 IntPin1; /* 08 Interrupt pin for PCI function 1*/
589 u8 ClassCode2[3]; /* 09 Class Code for PCI function 1 */
590 u8 IntPin2; /* 10 Interrupt pin for PCI function 2*/
591 u8 IntPin0; /* Interrupt pin for PCI function 0*/
592 u8 MinGrant; /* 11 Minimum grant */
593 u8 MaxLat; /* Maximum Latency */
594 u16 SubSysVId; /* 12 Subsystem Vendor Id */
595 u16 SubSysId; /* 13 Subsystem ID */
596 u16 FlashSize; /* 14 Flash size (bytes / 4K) */
597 u16 DSize2Pci; /* 15 DRAM size to PCI (bytes / 64K) */
598 u16 RSize2Pci; /* 16 Flash (ROM extension) size to PCI
601 u16 DeviceId1; /* 17 Device Id (function 1) */
602 u16 DeviceId2; /* 18 Device Id (function 2) */
603 u16 CfgByte6; /* 19 Device Status Config Bytes 6-7 */
604 u16 PMECapab; /* 20 Power Mgment capabilities */
605 u8 MSICapab; /* 21 MSI capabilities */
606 u8 ClockDivider; /* Clock divider */
607 u16 PciStatusLow; /* 22 PCI Status bits 15:0 */
608 u16 PciStatusHigh; /* 23 PCI Status bits 31:16 */
609 u16 DramConfigLow; /* 24 DRAM Configuration bits 15:0 */
610 u16 DramConfigHigh; /* 25 DRAM Configuration bits 31:16 */
611 u16 DramSize; /* 26 DRAM size (bytes / 64K) */
612 u16 GpioTbiCtl; /* 27 GPIO/TBI controls for functions 1/0 */
613 u16 EepromSize; /* 28 EEPROM Size */
614 struct slic_config_mac MacInfo[2]; /* 29 MAC addresses (2 ports) */
615 u8 FruFormat; /* 35 Alacritech FRU format type */
616 struct atk_fru AtkFru; /* Alacritech FRU information */
617 u8 OemFruFormat; /* optional OEM FRU format type */
618 union oemfru OemFru; /* optional OEM FRU information */
619 u8 Pad[4]; /* Pad to 128 bytes - includes 2 checksum bytes
620 * (if OEM FRU info exists) and two unusable
625 #define MAX_EECODE_SIZE sizeof(struct slic_eeprom)
626 #define MIN_EECODE_SIZE 0x62 /* code size without optional OEM FRU stuff */
629 * SLIC CONFIG structure
631 * This structure lives in the CARD structure and is valid for all board types.
632 * It is filled in from the appropriate EEPROM structure by
633 * SlicGetConfigData()
636 bool EepromValid; /* Valid EEPROM flag (checksum good?) */
637 u16 DramSize; /* DRAM size (bytes / 64K) */
638 struct slic_config_mac MacInfo[SLIC_NBR_MACS]; /* MAC addresses */
639 u8 FruFormat; /* Alacritech FRU format type */
640 struct atk_fru AtkFru; /* Alacritech FRU information */
641 u8 OemFruFormat; /* optional OEM FRU format type */
643 struct vendor1_fru vendor1_fru;
644 struct vendor2_fru vendor2_fru;
645 struct vendor3_fru vendor3_fru;
646 struct vendor4_fru vendor4_fru;