1 /**************************************************************************
3 * Copyright © 2000-2008 Alacritech, Inc. All rights reserved.
5 * $Id: sxg.h,v 1.3 2008/07/24 17:25:08 chris Exp $
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
22 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * The views and conclusions contained in the software and documentation
32 * are those of the authors and should not be interpreted as representing
33 * official policies, either expressed or implied, of Alacritech, Inc.
35 **************************************************************************/
40 * This is the base set of header definitions for the SXG driver.
42 #ifndef __SXG_DRIVER_H__
43 #define __SXG_DRIVER_H__
45 #define SLIC_DUMP_ENABLED 0
47 #define SXG_DRV_NAME "sxg" /* TBD: This might be removed eventually */
48 #define SXG_DRV_VERSION "1.0.1"
50 extern char sxg_driver_name[];
52 * struct sxg_stats - Probably move these to someplace where
53 * the slicstat (sxgstat?) program can get them.
57 u32 XmtNBL; /* Offload send NBL count */
58 u64 DumbXmtBytes; /* Dumbnic send bytes */
59 u64 SlowXmtBytes; /* Slowpath send bytes */
60 u64 FastXmtBytes; /* Fastpath send bytes */
61 u64 DumbXmtPkts; /* Dumbnic send packets */
62 u64 SlowXmtPkts; /* Slowpath send packets */
63 u64 FastXmtPkts; /* Fastpath send packets */
64 u64 DumbXmtUcastPkts; /* directed packets */
65 u64 DumbXmtMcastPkts; /* Multicast packets */
66 u64 DumbXmtBcastPkts; /* OID_GEN_BROADCAST_FRAMES_RCV */
67 u64 DumbXmtUcastBytes; /* OID_GEN_DIRECTED_BYTES_XMIT */
68 u64 DumbXmtMcastBytes; /* OID_GEN_MULTICAST_BYTES_XMIT */
69 u64 DumbXmtBcastBytes; /* OID_GEN_BROADCAST_BYTES_XMIT */
70 u64 XmtErrors; /* OID_GEN_XMIT_ERROR */
71 u64 XmtDiscards; /* OID_GEN_XMIT_DISCARDS */
72 u64 XmtOk; /* OID_GEN_XMIT_OK */
73 u64 XmtQLen; /* OID_GEN_TRANSMIT_QUEUE_LENGTH */
74 u64 XmtZeroFull; /* Transmit ring zero full */
76 u32 RcvNBL; /* Offload recieve NBL count */
77 u64 DumbRcvBytes; /* dumbnic recv bytes */
78 u64 DumbRcvUcastBytes; /* OID_GEN_DIRECTED_BYTES_RCV */
79 u64 DumbRcvMcastBytes; /* OID_GEN_MULTICAST_BYTES_RCV */
80 u64 DumbRcvBcastBytes; /* OID_GEN_BROADCAST_BYTES_RCV */
81 u64 SlowRcvBytes; /* Slowpath recv bytes */
82 u64 FastRcvBytes; /* Fastpath recv bytes */
83 u64 DumbRcvPkts; /* OID_GEN_DIRECTED_FRAMES_RCV */
84 u64 DumbRcvTcpPkts; /* See SxgCollectStats */
85 u64 DumbRcvUcastPkts; /* directed packets */
86 u64 DumbRcvMcastPkts; /* Multicast packets */
87 u64 DumbRcvBcastPkts; /* OID_GEN_BROADCAST_FRAMES_RCV */
88 u64 SlowRcvPkts; /* OID_GEN_DIRECTED_FRAMES_RCV */
89 u64 RcvErrors; /* OID_GEN_RCV_ERROR */
90 u64 RcvDiscards; /* OID_GEN_RCV_DISCARDS */
91 u64 RcvNoBuffer; /* OID_GEN_RCV_NO_BUFFER */
92 u64 PdqFull; /* Processed Data Queue Full */
93 u64 EventRingFull; /* Event ring full */
95 u64 MaxSends; /* Max sends outstanding */
96 u64 NoSglBuf; /* SGL buffer allocation failure */
97 u64 SglFail; /* NDIS SGL failure */
98 u64 SglAsync; /* NDIS SGL failure */
99 u64 NoMem; /* Memory allocation failure */
100 u64 NumInts; /* Interrupts */
101 u64 FalseInts; /* Interrupt with ISR == 0 */
102 u64 XmtDrops; /* No sahara DRAM buffer for xmt */
103 /* Sahara receive status */
104 u64 TransportCsum; /* SXG_RCV_STATUS_TRANSPORT_CSUM */
105 u64 TransportUflow; /* SXG_RCV_STATUS_TRANSPORT_UFLOW */
106 u64 TransportHdrLen; /* SXG_RCV_STATUS_TRANSPORT_HDRLEN */
107 u64 NetworkCsum; /* SXG_RCV_STATUS_NETWORK_CSUM: */
108 u64 NetworkUflow; /* SXG_RCV_STATUS_NETWORK_UFLOW: */
109 u64 NetworkHdrLen; /* SXG_RCV_STATUS_NETWORK_HDRLEN: */
110 u64 Parity; /* SXG_RCV_STATUS_PARITY */
111 u64 LinkParity; /* SXG_RCV_STATUS_LINK_PARITY: */
112 u64 LinkEarly; /* SXG_RCV_STATUS_LINK_EARLY: */
113 u64 LinkBufOflow; /* SXG_RCV_STATUS_LINK_BUFOFLOW: */
114 u64 LinkCode; /* SXG_RCV_STATUS_LINK_CODE: */
115 u64 LinkDribble; /* SXG_RCV_STATUS_LINK_DRIBBLE: */
116 u64 LinkCrc; /* SXG_RCV_STATUS_LINK_CRC: */
117 u64 LinkOflow; /* SXG_RCV_STATUS_LINK_OFLOW: */
118 u64 LinkUflow; /* SXG_RCV_STATUS_LINK_UFLOW: */
122 /* DUMB-NIC Send path definitions */
124 #define SXG_COMPLETE_DUMB_SEND(_pAdapt, _skb, _phys_addr, _size) { \
126 pci_unmap_single(_pAdapt->pcidev, _size, _phys_addr, PCI_DMA_TODEVICE); \
127 dev_kfree_skb_irq(_skb); \
130 #define SXG_DROP_DUMB_SEND(_pAdapt, _skb) { \
132 dev_kfree_skb(_skb); \
136 * Locate current receive header buffer location. Use this
137 * instead of RcvDataHdr->VirtualAddress since the data
138 * may have been offset by SXG_ADVANCE_MDL_OFFSET
140 #define SXG_RECEIVE_DATA_LOCATION(_RcvDataHdr) (_RcvDataHdr)->skb->data
142 /* Dumb-NIC receive processing */
143 /* Define an SXG_PACKET as an NDIS_PACKET */
144 #define PSXG_PACKET struct sk_buff *
145 /* Indications array size */
146 #define SXG_RCV_ARRAYSIZE 64
148 #define SXG_ALLOCATE_RCV_PACKET(_pAdapt, _RcvDataBufferHdr, BufferSize) {\
149 struct sk_buff * skb; \
150 skb = netdev_alloc_skb(_pAdapt->netdev, BufferSize); \
152 (_RcvDataBufferHdr)->skb = skb; \
154 _RcvDataBufferHdr->PhysicalAddress = pci_map_single(adapter->pcidev,\
155 _RcvDataBufferHdr->skb->data, BufferSize, PCI_DMA_FROMDEVICE); \
157 (_RcvDataBufferHdr)->skb = NULL; \
161 #define SXG_FREE_RCV_PACKET(_RcvDataBufferHdr) { \
162 if((_RcvDataBufferHdr)->skb) { \
163 dev_kfree_skb((_RcvDataBufferHdr)->skb); \
168 * Macro to add a NDIS_PACKET to an indication array
169 * If we fill up our array of packet pointers, then indicate this
170 * block up now and start on a new one.
172 #define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, \
174 (_IndicationList)[_NumPackets] = (_Packet); \
176 if((_NumPackets) == SXG_RCV_ARRAYSIZE) { \
177 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
178 (_NumPackets), 0, 0, 0); \
179 netif_rx((_IndicationList),(_NumPackets)); \
184 #define SXG_INDICATE_PACKETS(_pAdapt, _IndicationList, _NumPackets) { \
186 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
187 (_NumPackets), 0, 0, 0); \
188 netif_rx((_IndicationList),(_NumPackets)); \
193 #define SXG_REINIATIALIZE_PACKET(_Packet) \
194 {} /*_NdisReinitializePacket(_Packet)*/
195 /* this is not necessary with an skb */
197 /* Definitions to initialize Dumb-nic Receive NBLs */
198 #define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((struct sxg_rcv_nbl_reserved *)\
199 ((_Packet)->MiniportReservedEx))->RcvDataBufferHdr)
201 #define SXG_RCV_SET_CHECKSUM_INFO(_Packet, _Cpi) \
202 NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), \
203 TcpIpChecksumPacketInfo) = (PVOID)(_Cpi)
205 #define SXG_RCV_SET_TOEPLITZ(_Packet, _Toeplitz, _Type, _Function) { \
206 NDIS_PACKET_SET_HASH_VALUE((_Packet), (_Toeplitz)); \
207 NDIS_PACKET_SET_HASH_TYPE((_Packet), (_Type)); \
208 NDIS_PACKET_SET_HASH_FUNCTION((_Packet), (_Function)); \
211 #define SXG_RCV_SET_VLAN_INFO(_Packet, _VlanId, _Priority) { \
212 NDIS_PACKET_8021Q_INFO _Packet8021qInfo; \
213 _Packet8021qInfo.TagHeader.VlanId = (_VlanId); \
214 _Packet8021qInfo.TagHeader.UserPriority = (_Priority); \
215 NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), Ieee8021QNetBufferListInfo) = \
216 _Packet8021qInfo.Value; \
219 #define SXG_ADJUST_RCV_PACKET(_Packet, _RcvDataBufferHdr, _Event) { \
220 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbRcv", \
221 (_RcvDataBufferHdr), (_Packet), \
222 (_Event)->Status, 0); \
223 /* ASSERT((_Event)->Length <= (_RcvDataBufferHdr)->Size); */ \
224 skb_put(Packet, (_Event)->Length); \
228 * Macros to free a receive data buffer and receive data descriptor block
229 * NOTE - Lock must be held with RCV macros
231 #define SXG_GET_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
232 struct list_entry *_ple; \
234 if((_pAdapt)->FreeRcvBufferCount) { \
235 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeRcvBuffers))); \
236 _ple = RemoveHeadList(&(_pAdapt)->FreeRcvBuffers); \
237 (_Hdr) = container_of(_ple, struct sxg_rcv_data_buffer_hdr, \
239 (_pAdapt)->FreeRcvBufferCount--; \
240 ASSERT((_Hdr)->State == SXG_BUFFER_FREE); \
244 #define SXG_FREE_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
245 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RtnDHdr", \
246 (_Hdr), (_pAdapt)->FreeRcvBufferCount, \
247 (_Hdr)->State, 0/*(_Hdr)->VirtualAddress*/); \
248 /* SXG_RESTORE_MDL_OFFSET(_Hdr); */ \
249 (_pAdapt)->FreeRcvBufferCount++; \
250 ASSERT(((_pAdapt)->AllRcvBlockCount * SXG_RCV_DESCRIPTORS_PER_BLOCK) \
251 >= (_pAdapt)->FreeRcvBufferCount); \
252 ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
253 (_Hdr)->State = SXG_BUFFER_FREE; \
254 InsertTailList(&(_pAdapt)->FreeRcvBuffers, &((_Hdr)->FreeList)); \
257 #define SXG_FREE_RCV_DESCRIPTOR_BLOCK(_pAdapt, _Hdr) { \
258 ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
259 (_Hdr)->State = SXG_BUFFER_FREE; \
260 (_pAdapt)->FreeRcvBlockCount++; \
261 ASSERT((_pAdapt)->AllRcvBlockCount >= (_pAdapt)->FreeRcvBlockCount); \
262 InsertTailList(&(_pAdapt)->FreeRcvBlocks, &(_Hdr)->FreeList); \
266 #define SXG_FREE_SGL_BUFFER(_pAdapt, _Sgl, _NB, _irq) { \
268 spin_lock_irqsave(&(_pAdapt)->SglQLock, sgl_flags); \
270 spin_lock(&(_pAdapt)->SglQLock); \
271 (_pAdapt)->FreeSglBufferCount++; \
272 ASSERT((_pAdapt)->AllSglBufferCount >= (_pAdapt)->FreeSglBufferCount); \
273 ASSERT(!((_Sgl)->State & SXG_BUFFER_FREE)); \
274 (_Sgl)->State = SXG_BUFFER_FREE; \
275 InsertTailList(&(_pAdapt)->FreeSglBuffers, &(_Sgl)->FreeList); \
277 spin_unlock_irqrestore(&(_pAdapt)->SglQLock, sgl_flags); \
279 spin_unlock(&(_pAdapt)->SglQLock); \
283 * Get an SGL buffer from the free queue. The first part of this macro
284 * attempts to keep ahead of buffer depletion by allocating more when
285 * we hit a minimum threshold. Note that we don't grab the lock
286 * until after that. We're dealing with round numbers here, so we don't need to,
287 * and not grabbing it avoids a possible double-trip.
289 #define SXG_GET_SGL_BUFFER(_pAdapt, _Sgl, _irq) { \
290 struct list_entry *_ple; \
291 if ((_pAdapt->FreeSglBufferCount < SXG_MIN_SGL_BUFFERS) && \
292 (_pAdapt->AllSglBufferCount < SXG_MAX_SGL_BUFFERS) && \
293 (atomic_read(&_pAdapt->pending_allocations) == 0)) { \
294 sxg_allocate_buffer_memory(_pAdapt, \
295 (sizeof(struct sxg_scatter_gather) + SXG_SGL_BUF_SIZE),\
296 SXG_BUFFER_TYPE_SGL); \
300 spin_lock_irqsave(&(_pAdapt)->SglQLock, sgl_flags); \
302 spin_lock(&(_pAdapt)->SglQLock); \
303 if((_pAdapt)->FreeSglBufferCount) { \
304 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeSglBuffers))); \
305 _ple = RemoveHeadList(&(_pAdapt)->FreeSglBuffers); \
306 (_Sgl) = container_of(_ple, struct sxg_scatter_gather, \
308 (_pAdapt)->FreeSglBufferCount--; \
309 ASSERT((_Sgl)->State == SXG_BUFFER_FREE); \
310 (_Sgl)->State = SXG_BUFFER_BUSY; \
311 (_Sgl)->pSgl = NULL; \
314 spin_unlock_irqrestore(&(_pAdapt)->SglQLock, sgl_flags);\
316 spin_unlock(&(_pAdapt)->SglQLock); \
320 * struct sxg_multicast_address
321 * Linked list of multicast addresses.
323 struct sxg_multicast_address {
324 unsigned char Address[6];
325 struct sxg_multicast_address *Next;
329 * Structure to maintain chimney send and receive buffer queues.
330 * This structure maintains NET_BUFFER_LIST queues that are
331 * given to us via the Chimney MiniportTcpOffloadSend and
332 * MiniportTcpOffloadReceive routines. This structure DOES NOT
333 * manage our data buffer queue
335 struct sxg_buffer_queue {
336 u32 Type; /* Slow or fast - See below */
337 u32 Direction; /* Xmt or Rcv */
338 u32 Bytes; /* Byte count */
339 u32 * Head; /* Send queue head */
340 u32 * Tail; /* Send queue tail */
341 /* PNET_BUFFER_LIST NextNBL;*/ /* Short cut - next NBL */
342 /* PNET_BUFFER NextNB; */ /* Short cut - next NB */
345 #define SXG_SLOW_SEND_BUFFER 0
346 #define SXG_FAST_SEND_BUFFER 1
347 #define SXG_RECEIVE_BUFFER 2
349 #define SXG_INIT_BUFFER(_Buffer, _Type) { \
350 (_Buffer)->Type = (_Type); \
351 if((_Type) == SXG_RECEIVE_BUFFER) { \
352 (_Buffer)->Direction = 0; \
354 (_Buffer)->Direction = NDIS_SG_LIST_WRITE_TO_DEVICE; \
356 (_Buffer)->Bytes = 0; \
357 (_Buffer)->Head = NULL; \
358 (_Buffer)->Tail = NULL; \
362 #define SXG_RSS_CPU_COUNT(_pAdapt) \
363 ((_pAdapt)->RssEnabled ? NR_CPUS : 1)
365 /* DRIVER and ADAPTER structures */
368 * Adapter states - These states closely match the adapter states
369 * documented in the DDK (with a few exceptions).
372 SXG_STATE_INITIALIZING, /* Initializing */
373 SXG_STATE_BOOTDIAG, /* Boot-Diagnostic mode */
374 SXG_STATE_PAUSING, /* Pausing */
375 SXG_STATE_PAUSED, /* Paused */
376 SXG_STATE_RUNNING, /* Running */
377 SXG_STATE_RESETTING, /* Reset in progress */
378 SXG_STATE_SLEEP, /* Sleeping */
379 SXG_STATE_DIAG, /* Diagnostic mode */
380 SXG_STATE_HALTING, /* Halting */
381 SXG_STATE_HALTED, /* Down or not-initialized */
382 SXG_STATE_SHUTDOWN /* shutdown */
386 enum SXG_LINK_STATE {
391 /* Link initialization timeout in 100us units */
392 #define SXG_LINK_TIMEOUT 100000 /* 10 Seconds - REDUCE! */
395 /* Microcode file selection codes */
397 SXG_UCODE_SAHARA, /* Sahara ucode */
398 SXG_UCODE_SDIAGCPU, /* Sahara CPU diagnostic ucode */
399 SXG_UCODE_SDIAGSYS /* Sahara system diagnostic ucode */
403 #define SXG_DISABLE_ALL_INTERRUPTS(_padapt) sxg_disable_interrupt(_padapt)
404 #define SXG_ENABLE_ALL_INTERRUPTS(_padapt) sxg_enable_interrupt(_padapt)
406 /* This probably lives in a proto.h file. Move later */
407 #define SXG_MULTICAST_PACKET(_pether) ((_pether)->ether_dhost[0] & 0x01)
408 #define SXG_BROADCAST_PACKET(_pether) \
409 ((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) && \
410 (*(u16 *)&(_pether)->ether_dhost[4] == 0xFFFF))
413 #define SXG_ID DPFLTR_IHVNETWORK_ID
414 #define SXG_ERROR DPFLTR_ERROR_LEVEL
417 * struct sxg_driver structure -
419 * contains information about the sxg driver. There is only
420 * one of these, and it is defined as a global.
424 struct adapter_t *Adapters; /* Linked list of adapters */
425 ushort AdapterID; /* Maintain unique adapter ID */
428 #ifdef STATUS_SUCCESS
429 #undef STATUS_SUCCESS
432 /* TODO: We need to try and use NETDEV_TX_* before posting this out */
433 #define STATUS_SUCCESS 0
434 #define STATUS_PENDING 0
435 #define STATUS_FAILURE -1
436 #define STATUS_ERROR -2
437 #define STATUS_NOT_SUPPORTED -3
438 #define STATUS_BUFFER_TOO_SHORT -4
439 #define STATUS_RESOURCES -5
441 #define SLIC_MAX_CARDS 32
442 #define SLIC_MAX_PORTS 4 /* Max # of ports per card */
443 #if SLIC_DUMP_ENABLED
447 * This cannot be bigger than the max DMA size the card supports,
448 * given the current code structure in the host and ucode.
449 * Mojave supports 16K, Oasis supports 16K-1, so
450 * just set this at 15K, shouldnt make that much of a diff.
452 #define DUMP_BUF_SIZE 0x3C00
455 #define MIN(a, b) ((u32)(a) < (u32)(b) ? (a) : (b))
456 #define MAX(a, b) ((u32)(a) > (u32)(b) ? (a) : (b))
458 struct mcast_address {
459 unsigned char address[6];
460 struct mcast_address *next;
463 #define CARD_DOWN 0x00000000
464 #define CARD_UP 0x00000001
465 #define CARD_FAIL 0x00000002
466 #define CARD_DIAG 0x00000003
467 #define CARD_SLEEP 0x00000004
469 #define ADAPT_DOWN 0x00
470 #define ADAPT_UP 0x01
471 #define ADAPT_FAIL 0x02
472 #define ADAPT_RESET 0x03
473 #define ADAPT_SLEEP 0x04
475 #define ADAPT_FLAGS_BOOTTIME 0x0001
476 #define ADAPT_FLAGS_IS64BIT 0x0002
477 #define ADAPT_FLAGS_PENDINGLINKDOWN 0x0004
478 #define ADAPT_FLAGS_FIBERMEDIA 0x0008
479 #define ADAPT_FLAGS_LOCKS_ALLOCED 0x0010
480 #define ADAPT_FLAGS_INT_REGISTERED 0x0020
481 #define ADAPT_FLAGS_LOAD_TIMER_SET 0x0040
482 #define ADAPT_FLAGS_STATS_TIMER_SET 0x0080
483 #define ADAPT_FLAGS_RESET_TIMER_SET 0x0100
485 #define LINK_DOWN 0x00
486 #define LINK_CONFIG 0x01
489 #define LINK_10MB 0x00
490 #define LINK_100MB 0x01
491 #define LINK_AUTOSPEED 0x02
492 #define LINK_1000MB 0x03
493 #define LINK_10000MB 0x04
495 #define LINK_HALFD 0x00
496 #define LINK_FULLD 0x01
497 #define LINK_AUTOD 0x02
499 #define MAC_DIRECTED 0x00000001
500 #define MAC_BCAST 0x00000002
501 #define MAC_MCAST 0x00000004
502 #define MAC_PROMISC 0x00000008
503 #define MAC_LOOPBACK 0x00000010
504 #define MAC_ALLMCAST 0x00000020
506 #define SLIC_DUPLEX(x) ((x==LINK_FULLD) ? "FDX" : "HDX")
507 #define SLIC_SPEED(x) ((x==LINK_100MB) ? "100Mb" : \
508 ((x==LINK_1000MB) ? "1000Mb" : " 10Mb"))
509 #define SLIC_LINKSTATE(x) ((x==LINK_DOWN) ? "Down" : "Up ")
510 #define SLIC_ADAPTER_STATE(x) ((x==ADAPT_UP) ? "UP" : "Down")
511 #define SLIC_CARD_STATE(x) ((x==CARD_UP) ? "UP" : "Down")
514 struct ether_header {
515 unsigned char ether_dhost[6];
516 unsigned char ether_shost[6];
521 #define NUM_CFG_SPACES 2
522 #define NUM_CFG_REGS 64
525 struct adapter_t *adapter[SLIC_MAX_PORTS];
526 struct physcard *next;
527 unsigned int adapters_allocd;
530 struct sxgbase_driver {
531 spinlock_t driver_lock;
532 unsigned long flags; /* irqsave for spinlock */
535 u32 num_sxg_ports_active;
537 struct physcard *phys_card;
544 struct physcard *physcard;
545 unsigned int physport;
546 unsigned int slotnumber;
547 unsigned int functionnumber;
553 void __iomem * base_addr;
557 unsigned int activated;
559 unsigned int isp_initialized;
561 unsigned char linkstate;
563 unsigned char macaddr[6];
564 unsigned char currmacaddr[6];
566 ushort devflags_prev;
568 struct mcast_address *mcastaddrs;
569 struct timer_list pingtimer;
571 struct timer_list statstimer;
573 struct timer_list vpci_timer;
575 struct timer_list loadtimer;
582 u32 error_interrupts;
583 u32 error_rmiss_interrupts;
588 u32 linkevent_interrupts;
591 u32 false_interrupts;
600 u32 rcv_interrupt_yields;
602 struct net_device_stats stats;
603 u32 * MiniportHandle; /* Our miniport handle */
604 enum SXG_STATE State; /* Adapter state */
605 enum SXG_LINK_STATE LinkState; /* Link state */
606 u64 LinkSpeed; /* Link Speed */
607 u32 PowerState; /* NDIS power state */
608 struct adapter_t *Next; /* Linked list */
609 ushort AdapterID; /* 1..n */
610 struct net_device * netdev;
611 struct net_device * next_netdevice;
612 struct pci_dev *pcidev;
614 struct sxg_multicast_address *MulticastAddrs; /* Multicast list */
615 u64 MulticastMask; /* Multicast mask */
616 u32 *InterruptHandle; /* Register Interrupt handle */
617 u32 InterruptLevel; /* From Resource list */
618 u32 InterruptVector; /* From Resource list */
619 spinlock_t AdapterLock; /* Serialize access adapter routines */
620 spinlock_t Bit64RegLock; /* For writing 64-bit addresses */
621 struct sxg_hw_regs *HwRegs; /* Sahara HW Register Memory (BAR0/1) */
622 struct sxg_ucode_regs *UcodeRegs; /* Microcode Register Memory (BAR2/3) */
623 struct sxg_tcb_regs *TcbRegs; /* Same as Ucode regs - See sxghw.h */
624 ushort FrameSize; /* Maximum frame size */
625 u32 * DmaHandle; /* NDIS DMA handle */
626 u32 * PacketPoolHandle; /* Used with NDIS 5.2 only. Don't ifdef out */
627 u32 * BufferPoolHandle; /* Used with NDIS 5.2 only. Don't ifdef out */
628 u32 MacFilter; /* NDIS MAC Filter */
629 struct sxg_event_ring *EventRings; /* Host event rings. 1/CPU to 16 max */
630 dma_addr_t PEventRings; /* Physical address */
631 u32 NextEvent[SXG_MAX_RSS]; /* Current location in ring */
632 dma_addr_t PTcbBuffers; /* TCB Buffers - physical address */
633 dma_addr_t PTcbCompBuffers; /* TCB Composite Buffers - phys addr */
634 struct sxg_xmt_ring *XmtRings; /* Transmit rings */
635 dma_addr_t PXmtRings; /* Transmit rings - physical address */
636 struct sxg_ring_info XmtRingZeroInfo; /* Transmit ring 0 info */
638 spinlock_t XmtZeroLock; /* Transmit ring 0 lock */
639 u32 * XmtRingZeroIndex; /* Shared XMT ring 0 index */
640 dma_addr_t PXmtRingZeroIndex; /* Shared XMT ring 0 index - physical */
641 struct list_entry FreeProtocolHeaders;/* Free protocol headers */
642 u32 FreeProtoHdrCount; /* Count */
643 void * ProtocolHeaders; /* Block of protocol header */
644 dma_addr_t PProtocolHeaders; /* Block of protocol headers - phys */
646 struct sxg_rcv_ring *RcvRings; /* Receive rings */
647 dma_addr_t PRcvRings; /* Receive rings - physical address */
648 struct sxg_ucode_stats *ucode_stats; /* Ucode Stats */
649 /* Ucode Stats - physical address */
650 dma_addr_t pucode_stats;
652 struct sxg_ring_info RcvRingZeroInfo; /* Receive ring 0 info */
654 u32 * Isr; /* Interrupt status register */
655 dma_addr_t PIsr; /* ISR - physical address */
656 u32 IsrCopy[SXG_MAX_RSS]; /* Copy of ISR */
657 ushort InterruptsEnabled; /* Bitmask of enabled vectors */
658 unsigned char *IndirectionTable; /* RSS indirection table */
659 dma_addr_t PIndirectionTable; /* Physical address */
660 ushort RssTableSize; /* From NDIS_RECEIVE_SCALE_PARAMETERS */
661 ushort HashKeySize; /* From NDIS_RECEIVE_SCALE_PARAMETERS */
662 unsigned char HashSecretKey[40]; /* rss key */
664 /* Receive buffer queues */
665 spinlock_t RcvQLock; /* Receive Queue Lock */
666 struct list_entry FreeRcvBuffers; /* Free SXG_DATA_BUFFER queue */
667 struct list_entry FreeRcvBlocks; /* Free SXG_RCV_DESCRIPTOR_BLOCK Q */
668 struct list_entry AllRcvBlocks; /* All SXG_RCV_BLOCKs */
669 ushort FreeRcvBufferCount; /* Number of free rcv data buffers */
670 ushort FreeRcvBlockCount; /* # of free rcv descriptor blocks */
671 ushort AllRcvBlockCount; /* Number of total receive blocks */
672 ushort ReceiveBufferSize; /* SXG_RCV_DATA/JUMBO_BUFFER_SIZE only */
673 /* Converted this to a atomic variable
674 u32 AllocationsPending; */
675 atomic_t pending_allocations;
676 u32 AllocationsPending; /* Receive allocation pending */
677 u32 RcvBuffersOnCard; /* SXG_DATA_BUFFERS owned by card */
679 spinlock_t SglQLock; /* SGL Queue Lock */
680 struct list_entry FreeSglBuffers; /* Free struct sxg_scatter_gather */
681 struct list_entry AllSglBuffers; /* All struct sxg_scatter_gather */
682 ushort FreeSglBufferCount; /* Number of free SGL buffers */
683 ushort AllSglBufferCount; /* Number of total SGL buffers */
684 u32 CurrentTime; /* Tick count */
685 u32 FastpathConnections;/* # of fastpath connections */
686 /* Various single-bit flags: */
687 u32 BasicAllocations:1; /* Locks and listheads */
688 u32 IntRegistered:1; /* Interrupt registered */
689 u32 PingOutstanding:1; /* Ping outstanding to card */
690 u32 Dead:1; /* Card dead */
691 u32 DumpDriver:1; /* OID_SLIC_DRIVER_DUMP request */
692 u32 DumpCard:1; /* OID_SLIC_CARD_DUMP request */
693 u32 DumpCmdRunning:1; /* Dump command in progress */
694 u32 DebugRunning:1; /* AGDB debug in progress */
695 u32 JumboEnabled:1; /* Jumbo frames enabled */
696 u32 MsiEnabled:1; /* MSI interrupt enabled */
697 u32 RssEnabled:1; /* RSS Enabled */
698 u32 FailOnBadEeprom:1; /* Fail on Bad Eeprom */
699 u32 DiagStart:1; /* Init adapter for diagnostic start */
701 u32 PendingRcvCount; /* Outstanding rcv indications */
702 u32 PendingXmtCount; /* Outstanding send requests */
703 struct sxg_stats Stats; /* Statistics */
704 u32 ReassBufs; /* Number of reassembly buffers */
705 /* Card Crash Info */
706 ushort CrashLocation; /* Microcode crash location */
707 unsigned char CrashCpu; /* Sahara CPU ID */
709 /* PDIAG_CMD DiagCmds; */ /* List of free diagnostic commands */
710 /* PDIAG_BUFFER DiagBuffers; */ /* List of free diagnostic buffers */
711 /* PDIAG_REQ DiagReqQ; */ /* List of outstanding (asynchronous) diag requests */
712 /* u32 DiagCmdTimeout; */ /* Time out for diag cmds (seconds) XXXTODO - replace with SXG_PARAM var? */
713 /* unsigned char DiagDmaDesc[DMA_CPU_CTXS]; */ /* Free DMA descriptors bit field (32 CPU ctx * 8 DMA ctx) */
715 * Put preprocessor-conditional fields at the end so we don't
716 * have to recompile sxgdbg everytime we reconfigure the driver
718 #if defined(CONFIG_X86)
719 u32 AddrUpper; /* Upper 32 bits of 64-bit register */
721 /*#if SXG_FAILURE_DUMP */
722 /* NDIS_EVENT DumpThreadEvent; */ /* syncronize dump thread */
723 /* BOOLEAN DumpThreadRunning; */ /* termination flag */
724 /* PSXG_DUMP_CMD DumpBuffer; */ /* 68k - Cmd and Buffer */
725 /* dma_addr_t PDumpBuffer; */ /* Physical address */
726 /*#endif */ /* SXG_FAILURE_DUMP */
729 #if SLIC_DUMP_ENABLED
730 #define SLIC_DUMP_REQUESTED 1
731 #define SLIC_DUMP_IN_PROGRESS 2
732 #define SLIC_DUMP_DONE 3
735 * Microcode crash information structure. This
736 * structure is written out to the card's SRAM when the microcode panic's.
738 struct slic_crash_info {
743 #define CRASH_INFO_OFFSET 0x155C
747 #define UPDATE_STATS(largestat, newstat, oldstat) \
749 if ((newstat) < (oldstat)) \
750 (largestat) += ((newstat) + (0xFFFFFFFF - oldstat + 1)); \
752 (largestat) += ((newstat) - (oldstat)); \
755 #define UPDATE_STATS_GB(largestat, newstat, oldstat) \
757 (largestat) += ((newstat) - (oldstat)); \
760 #define ETHER_EQ_ADDR(_AddrA, _AddrB, _Result) \
763 if (*(u32 *)(_AddrA) != *(u32 *)(_AddrB)) \
765 if (*(u16 *)(&((_AddrA)[4])) != *(u16 *)(&((_AddrB)[4]))) \
769 #define ETHERMAXFRAME 1514
770 #define JUMBOMAXFRAME 9014
772 #if defined(CONFIG_X86_64) || defined(CONFIG_IA64)
773 #define SXG_GET_ADDR_LOW(_addr) (u32)((u64)(_addr) & 0x00000000FFFFFFFF)
774 #define SXG_GET_ADDR_HIGH(_addr) \
775 (u32)(((u64)(_addr) >> 32) & 0x00000000FFFFFFFF)
777 #define SXG_GET_ADDR_LOW(_addr) (u32)_addr
778 #define SXG_GET_ADDR_HIGH(_addr) (u32)0
782 #define DONT_FLUSH FALSE
784 #define SIOCSLICDUMPCARD (SIOCDEVPRIVATE+9)
785 #define SIOCSLICSETINTAGG (SIOCDEVPRIVATE+10)
786 #define SIOCSLICTRACEDUMP (SIOCDEVPRIVATE+11)
788 extern struct ethtool_ops sxg_nic_ethtool_ops;
789 #define SXG_COMPLETE_SLOW_SEND_LIMIT 128
790 #endif /* __SXG_DRIVER_H__ */