2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 * Purpose: MAC routines
29 * MACbIsRegBitsOn - Test if All test Bits On
30 * MACbIsRegBitsOff - Test if All test Bits Off
31 * MACbIsIntDisable - Test if MAC interrupt disable
32 * MACvSetShortRetryLimit - Set 802.11 Short Retry limit
33 * MACvSetLongRetryLimit - Set 802.11 Long Retry limit
34 * MACvSetLoopbackMode - Set MAC Loopback Mode
35 * MACvSaveContext - Save Context of MAC Registers
36 * MACvRestoreContext - Restore Context of MAC Registers
37 * MACbSoftwareReset - Software Reset MAC
38 * MACbSafeRxOff - Turn Off MAC Rx
39 * MACbSafeTxOff - Turn Off MAC Tx
40 * MACbSafeStop - Stop MAC function
41 * MACbShutdown - Shut down MAC
42 * MACvInitialize - Initialize MAC
43 * MACvSetCurrRxDescAddr - Set Rx Descriptors Address
44 * MACvSetCurrTx0DescAddr - Set Tx0 Descriptors Address
45 * MACvSetCurrTx1DescAddr - Set Tx1 Descriptors Address
46 * MACvTimer0MicroSDelay - Micro Second Delay Loop by MAC
49 * 08-22-2003 Kyle Hsu : Porting MAC functions from sim53
50 * 09-03-2003 Bryan YC Fan : Add MACvClearBusSusInd()&
51 * MACvEnableBusSusEn()
52 * 09-18-2003 Jerry Chen : Add MACvSetKeyEntry & MACvDisableKeyEntry
61 * Test if all test bits on
65 * io_base - Base Address for MAC
66 * byRegOfs - Offset of MAC Register
67 * byTestBits - Test bits
71 * Return Value: true if all test bits On; otherwise false
74 bool MACbIsRegBitsOn(struct vnt_private *priv, unsigned char byRegOfs,
75 unsigned char byTestBits)
77 void __iomem *io_base = priv->PortOffset;
79 return (ioread8(io_base + byRegOfs) & byTestBits) == byTestBits;
84 * Test if all test bits off
88 * io_base - Base Address for MAC
89 * byRegOfs - Offset of MAC Register
90 * byTestBits - Test bits
94 * Return Value: true if all test bits Off; otherwise false
97 bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs,
98 unsigned char byTestBits)
100 void __iomem *io_base = priv->PortOffset;
102 return !(ioread8(io_base + byRegOfs) & byTestBits);
107 * Test if MAC interrupt disable
111 * io_base - Base Address for MAC
115 * Return Value: true if interrupt is disable; otherwise false
118 bool MACbIsIntDisable(struct vnt_private *priv)
120 void __iomem *io_base = priv->PortOffset;
122 if (ioread32(io_base + MAC_REG_IMR))
130 * Set 802.11 Short Retry Limit
134 * io_base - Base Address for MAC
135 * byRetryLimit- Retry Limit
142 void MACvSetShortRetryLimit(struct vnt_private *priv,
143 unsigned char byRetryLimit)
145 void __iomem *io_base = priv->PortOffset;
147 iowrite8(byRetryLimit, io_base + MAC_REG_SRT);
153 * Set 802.11 Long Retry Limit
157 * io_base - Base Address for MAC
158 * byRetryLimit- Retry Limit
165 void MACvSetLongRetryLimit(struct vnt_private *priv,
166 unsigned char byRetryLimit)
168 void __iomem *io_base = priv->PortOffset;
170 iowrite8(byRetryLimit, io_base + MAC_REG_LRT);
175 * Set MAC Loopback mode
179 * io_base - Base Address for MAC
180 * byLoopbackMode - Loopback Mode
187 void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode)
189 void __iomem *io_base = priv->PortOffset;
191 byLoopbackMode <<= 6;
193 iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode,
194 io_base + MAC_REG_TEST);
199 * Save MAC registers to context buffer
203 * io_base - Base Address for MAC
205 * cxt_buf - Context buffer
210 void MACvSaveContext(struct vnt_private *priv, unsigned char *cxt_buf)
212 void __iomem *io_base = priv->PortOffset;
214 /* read page0 register */
215 memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0);
217 MACvSelectPage1(io_base);
219 /* read page1 register */
220 memcpy_fromio(cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, io_base,
221 MAC_MAX_CONTEXT_SIZE_PAGE1);
223 MACvSelectPage0(io_base);
228 * Restore MAC registers from context buffer
232 * io_base - Base Address for MAC
233 * cxt_buf - Context buffer
240 void MACvRestoreContext(struct vnt_private *priv, unsigned char *cxt_buf)
242 void __iomem *io_base = priv->PortOffset;
244 MACvSelectPage1(io_base);
246 memcpy_toio(io_base, cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0,
247 MAC_MAX_CONTEXT_SIZE_PAGE1);
249 MACvSelectPage0(io_base);
251 /* restore RCR,TCR,IMR... */
252 memcpy_toio(io_base + MAC_REG_RCR, cxt_buf + MAC_REG_RCR,
253 MAC_REG_ISR - MAC_REG_RCR);
255 /* restore MAC Config. */
256 memcpy_toio(io_base + MAC_REG_LRT, cxt_buf + MAC_REG_LRT,
257 MAC_REG_PAGE1SEL - MAC_REG_LRT);
259 iowrite8(*(cxt_buf + MAC_REG_CFG), io_base + MAC_REG_CFG);
261 /* restore PS Config. */
262 memcpy_toio(io_base + MAC_REG_PSCFG, cxt_buf + MAC_REG_PSCFG,
263 MAC_REG_BBREGCTL - MAC_REG_PSCFG);
265 /* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */
266 iowrite32(*(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0),
267 io_base + MAC_REG_TXDMAPTR0);
268 iowrite32(*(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR),
269 io_base + MAC_REG_AC0DMAPTR);
270 iowrite32(*(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR),
271 io_base + MAC_REG_BCNDMAPTR);
272 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0),
273 io_base + MAC_REG_RXDMAPTR0);
274 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1),
275 io_base + MAC_REG_RXDMAPTR1);
284 * io_base - Base Address for MAC
288 * Return Value: true if Reset Success; otherwise false
291 bool MACbSoftwareReset(struct vnt_private *priv)
293 void __iomem *io_base = priv->PortOffset;
296 /* turn on HOSTCR_SOFTRST, just write 0x01 to reset */
297 iowrite8(0x01, io_base + MAC_REG_HOSTCR);
299 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
300 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_SOFTRST))
303 if (ww == W_MAX_TIMEOUT)
310 * save some important register's value, then do reset, then restore
315 * io_base - Base Address for MAC
319 * Return Value: true if success; otherwise false
322 bool MACbSafeSoftwareReset(struct vnt_private *priv)
324 unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0+MAC_MAX_CONTEXT_SIZE_PAGE1];
328 * save some important register's value, then do
329 * reset, then restore register's value
331 /* save MAC context */
332 MACvSaveContext(priv, abyTmpRegData);
334 bRetVal = MACbSoftwareReset(priv);
335 /* restore MAC context, except CR0 */
336 MACvRestoreContext(priv, abyTmpRegData);
347 * io_base - Base Address for MAC
351 * Return Value: true if success; otherwise false
354 bool MACbSafeRxOff(struct vnt_private *priv)
356 void __iomem *io_base = priv->PortOffset;
359 /* turn off wow temp for turn off Rx safely */
361 /* Clear RX DMA0,1 */
362 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0);
363 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1);
364 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
365 if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
368 if (ww == W_MAX_TIMEOUT) {
369 pr_debug(" DBG_PORT80(0x10)\n");
372 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
373 if (!(ioread32(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
376 if (ww == W_MAX_TIMEOUT) {
377 pr_debug(" DBG_PORT80(0x11)\n");
381 /* try to safe shutdown RX */
382 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_RXON);
383 /* W_MAX_TIMEOUT is the timeout period */
384 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
385 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_RXONST))
388 if (ww == W_MAX_TIMEOUT) {
389 pr_debug(" DBG_PORT80(0x12)\n");
401 * io_base - Base Address for MAC
405 * Return Value: true if success; otherwise false
408 bool MACbSafeTxOff(struct vnt_private *priv)
410 void __iomem *io_base = priv->PortOffset;
415 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0);
417 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL);
419 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
420 if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
423 if (ww == W_MAX_TIMEOUT) {
424 pr_debug(" DBG_PORT80(0x20)\n");
427 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
428 if (!(ioread32(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
431 if (ww == W_MAX_TIMEOUT) {
432 pr_debug(" DBG_PORT80(0x21)\n");
436 /* try to safe shutdown TX */
437 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_TXON);
439 /* W_MAX_TIMEOUT is the timeout period */
440 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
441 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_TXONST))
444 if (ww == W_MAX_TIMEOUT) {
445 pr_debug(" DBG_PORT80(0x24)\n");
457 * io_base - Base Address for MAC
461 * Return Value: true if success; otherwise false
464 bool MACbSafeStop(struct vnt_private *priv)
466 void __iomem *io_base = priv->PortOffset;
468 MACvRegBitsOff(io_base, MAC_REG_TCR, TCR_AUTOBCNTX);
470 if (!MACbSafeRxOff(priv)) {
471 pr_debug(" MACbSafeRxOff == false)\n");
472 MACbSafeSoftwareReset(priv);
475 if (!MACbSafeTxOff(priv)) {
476 pr_debug(" MACbSafeTxOff == false)\n");
477 MACbSafeSoftwareReset(priv);
481 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_MACEN);
492 * io_base - Base Address for MAC
496 * Return Value: true if success; otherwise false
499 bool MACbShutdown(struct vnt_private *priv)
501 void __iomem *io_base = priv->PortOffset;
502 /* disable MAC IMR */
503 MACvIntDisable(io_base);
504 MACvSetLoopbackMode(priv, MAC_LB_INTERNAL);
505 /* stop the adapter */
506 if (!MACbSafeStop(priv)) {
507 MACvSetLoopbackMode(priv, MAC_LB_NONE);
510 MACvSetLoopbackMode(priv, MAC_LB_NONE);
520 * io_base - Base Address for MAC
527 void MACvInitialize(struct vnt_private *priv)
529 void __iomem *io_base = priv->PortOffset;
530 /* clear sticky bits */
531 MACvClearStckDS(io_base);
532 /* disable force PME-enable */
533 iowrite8(PME_OVR, io_base + MAC_REG_PMC1);
537 MACbSoftwareReset(priv);
539 /* reset TSF counter */
540 iowrite8(TFTCTL_TSFCNTRST, io_base + MAC_REG_TFTCTL);
541 /* enable TSF counter */
542 iowrite8(TFTCTL_TSFCNTREN, io_base + MAC_REG_TFTCTL);
547 * Set the chip with current rx descriptor address
551 * io_base - Base Address for MAC
552 * curr_desc_addr - Descriptor Address
559 void MACvSetCurrRx0DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
561 void __iomem *io_base = priv->PortOffset;
563 unsigned char org_dma_ctl;
565 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL0);
566 if (org_dma_ctl & DMACTL_RUN)
567 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0 + 2);
569 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
570 if (!(ioread8(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
574 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR0);
575 if (org_dma_ctl & DMACTL_RUN)
576 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0);
581 * Set the chip with current rx descriptor address
585 * io_base - Base Address for MAC
586 * curr_desc_addr - Descriptor Address
593 void MACvSetCurrRx1DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
595 void __iomem *io_base = priv->PortOffset;
597 unsigned char org_dma_ctl;
599 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL1);
600 if (org_dma_ctl & DMACTL_RUN)
601 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1 + 2);
603 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
604 if (!(ioread8(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
608 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR1);
609 if (org_dma_ctl & DMACTL_RUN)
610 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1);
616 * Set the chip with current tx0 descriptor address
620 * io_base - Base Address for MAC
621 * curr_desc_addr - Descriptor Address
628 void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv,
631 void __iomem *io_base = priv->PortOffset;
633 unsigned char org_dma_ctl;
635 org_dma_ctl = ioread8(io_base + MAC_REG_TXDMACTL0);
636 if (org_dma_ctl & DMACTL_RUN)
637 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0 + 2);
639 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
640 if (!(ioread8(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
644 iowrite32(curr_desc_addr, io_base + MAC_REG_TXDMAPTR0);
645 if (org_dma_ctl & DMACTL_RUN)
646 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0);
651 * Set the chip with current AC0 descriptor address
655 * io_base - Base Address for MAC
656 * curr_desc_addr - Descriptor Address
663 /* TxDMA1 = AC0DMA */
664 void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv,
667 void __iomem *io_base = priv->PortOffset;
669 unsigned char org_dma_ctl;
671 org_dma_ctl = ioread8(io_base + MAC_REG_AC0DMACTL);
672 if (org_dma_ctl & DMACTL_RUN)
673 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL + 2);
675 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
676 if (!(ioread8(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
679 if (ww == W_MAX_TIMEOUT)
680 pr_debug(" DBG_PORT80(0x26)\n");
681 iowrite32(curr_desc_addr, io_base + MAC_REG_AC0DMAPTR);
682 if (org_dma_ctl & DMACTL_RUN)
683 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL);
686 void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv,
689 if (iTxType == TYPE_AC0DMA)
690 MACvSetCurrAC0DescAddrEx(priv, curr_desc_addr);
691 else if (iTxType == TYPE_TXDMA0)
692 MACvSetCurrTx0DescAddrEx(priv, curr_desc_addr);
697 * Micro Second Delay via MAC
701 * io_base - Base Address for MAC
702 * uDelay - Delay time (timer resolution is 4 us)
709 void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay)
711 void __iomem *io_base = priv->PortOffset;
712 unsigned char byValue;
715 iowrite8(0, io_base + MAC_REG_TMCTL0);
716 iowrite32(uDelay, io_base + MAC_REG_TMDATA0);
717 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL0);
718 for (ii = 0; ii < 66; ii++) { /* assume max PCI clock is 66Mhz */
719 for (uu = 0; uu < uDelay; uu++) {
720 byValue = ioread8(io_base + MAC_REG_TMCTL0);
721 if ((byValue == 0) ||
722 (byValue & TMCTL_TSUSP)) {
723 iowrite8(0, io_base + MAC_REG_TMCTL0);
728 iowrite8(0, io_base + MAC_REG_TMCTL0);
733 * Micro Second One shot timer via MAC
737 * io_base - Base Address for MAC
738 * uDelay - Delay time
745 void MACvOneShotTimer1MicroSec(struct vnt_private *priv,
746 unsigned int uDelayTime)
748 void __iomem *io_base = priv->PortOffset;
750 iowrite8(0, io_base + MAC_REG_TMCTL1);
751 iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1);
752 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL1);
755 void MACvSetMISCFifo(struct vnt_private *priv, unsigned short offset,
758 void __iomem *io_base = priv->PortOffset;
762 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
763 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
764 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
767 bool MACbPSWakeup(struct vnt_private *priv)
769 void __iomem *io_base = priv->PortOffset;
772 if (MACbIsRegBitsOff(priv, MAC_REG_PSCTL, PSCTL_PS))
776 MACvRegBitsOff(io_base, MAC_REG_PSCTL, PSCTL_PSEN);
778 /* Check if SyncFlushOK */
779 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
780 if (ioread8(io_base + MAC_REG_PSCTL) & PSCTL_WAKEDONE)
783 if (ww == W_MAX_TIMEOUT) {
784 pr_debug(" DBG_PORT80(0x33)\n");
792 * Set the Key by MISCFIFO
796 * io_base - Base Address for MAC
805 void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
806 unsigned int uEntryIdx, unsigned int uKeyIdx,
807 unsigned char *pbyAddr, u32 *pdwKey,
808 unsigned char byLocalID)
810 void __iomem *io_base = priv->PortOffset;
811 unsigned short offset;
818 pr_debug("MACvSetKeyEntry\n");
819 offset = MISCFIFO_KEYETRY0;
820 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
825 data |= MAKEWORD(*(pbyAddr + 4), *(pbyAddr + 5));
826 pr_debug("1. offset: %d, Data: %X, KeyCtl:%X\n",
827 offset, data, wKeyCtl);
829 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
830 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
831 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
835 data |= *(pbyAddr + 3);
837 data |= *(pbyAddr + 2);
839 data |= *(pbyAddr + 1);
842 pr_debug("2. offset: %d, Data: %X\n", offset, data);
844 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
845 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
846 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
849 offset += (uKeyIdx * 4);
850 for (ii = 0; ii < 4; ii++) {
851 /* always push 128 bits */
852 pr_debug("3.(%d) offset: %d, Data: %X\n",
853 ii, offset + ii, *pdwKey);
854 iowrite16(offset + ii, io_base + MAC_REG_MISCFFNDEX);
855 iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA);
856 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
862 * Disable the Key Entry by MISCFIFO
866 * io_base - Base Address for MAC
874 void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx)
876 void __iomem *io_base = priv->PortOffset;
877 unsigned short offset;
879 offset = MISCFIFO_KEYETRY0;
880 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
882 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
883 iowrite32(0, io_base + MAC_REG_MISCFFDATA);
884 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);