drivers/staging/vt6655/mac.h

   1 /*
   2  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  *
  20  * File: mac.h
  21  *
  22  * Purpose: MAC routines
  23  *
  24  * Author: Tevin Chen
  25  *
  26  * Date: May 21, 1996
  27  *
  28  * Revision History:
  29  *      07-01-2003 Bryan YC Fan:  Re-write codes to support VT3253 spec.
  30  *      08-25-2003 Kyle Hsu:      Porting MAC functions from sim53.
  31  *      09-03-2003 Bryan YC Fan:  Add MACvDisableProtectMD & MACvEnableProtectMD
  32  */
  33
  34 #ifndef __MAC_H__
  35 #define __MAC_H__
  36
  37 #include "ttype.h"
  38 #include "tmacro.h"
  39 #include "upc.h"
  40
  41 /*---------------------  Export Definitions -------------------------*/
  42 //
  43 // Registers in the MAC
  44 //
  45 #define MAC_MAX_CONTEXT_SIZE_PAGE0  256
  46 #define MAC_MAX_CONTEXT_SIZE_PAGE1  128
  47
  48 // Registers not related to 802.11b
  49 #define MAC_REG_BCFG0       0x00
  50 #define MAC_REG_BCFG1       0x01
  51 #define MAC_REG_FCR0        0x02
  52 #define MAC_REG_FCR1        0x03
  53 #define MAC_REG_BISTCMD     0x04
  54 #define MAC_REG_BISTSR0     0x05
  55 #define MAC_REG_BISTSR1     0x06
  56 #define MAC_REG_BISTSR2     0x07
  57 #define MAC_REG_I2MCSR      0x08
  58 #define MAC_REG_I2MTGID     0x09
  59 #define MAC_REG_I2MTGAD     0x0A
  60 #define MAC_REG_I2MCFG      0x0B
  61 #define MAC_REG_I2MDIPT     0x0C
  62 #define MAC_REG_I2MDOPT     0x0E
  63 #define MAC_REG_PMC0        0x10
  64 #define MAC_REG_PMC1        0x11
  65 #define MAC_REG_STICKHW     0x12
  66 #define MAC_REG_LOCALID     0x14
  67 #define MAC_REG_TESTCFG     0x15
  68 #define MAC_REG_JUMPER0     0x16
  69 #define MAC_REG_JUMPER1     0x17
  70 #define MAC_REG_TMCTL0      0x18
  71 #define MAC_REG_TMCTL1      0x19
  72 #define MAC_REG_TMDATA0     0x1C
  73 // MAC Parameter related
  74 #define MAC_REG_LRT         0x20        //
  75 #define MAC_REG_SRT         0x21        //
  76 #define MAC_REG_SIFS        0x22        //
  77 #define MAC_REG_DIFS        0x23        //
  78 #define MAC_REG_EIFS        0x24        //
  79 #define MAC_REG_SLOT        0x25        //
  80 #define MAC_REG_BI          0x26        //
  81 #define MAC_REG_CWMAXMIN0   0x28        //
  82 #define MAC_REG_LINKOFFTOTM 0x2A
  83 #define MAC_REG_SWTMOT      0x2B
  84 #define MAC_REG_MIBCNTR     0x2C
  85 #define MAC_REG_RTSOKCNT    0x2C
  86 #define MAC_REG_RTSFAILCNT  0x2D
  87 #define MAC_REG_ACKFAILCNT  0x2E
  88 #define MAC_REG_FCSERRCNT   0x2F
  89 // TSF Related
  90 #define MAC_REG_TSFCNTR     0x30        //
  91 #define MAC_REG_NEXTTBTT    0x38        //
  92 #define MAC_REG_TSFOFST     0x40        //
  93 #define MAC_REG_TFTCTL      0x48        //
  94 // WMAC Control/Status Related
  95 #define MAC_REG_ENCFG       0x4C        //
  96 #define MAC_REG_PAGE1SEL    0x4F        //
  97 #define MAC_REG_CFG         0x50        //
  98 #define MAC_REG_TEST        0x52        //
  99 #define MAC_REG_HOSTCR      0x54        //
 100 #define MAC_REG_MACCR       0x55        //
 101 #define MAC_REG_RCR         0x56        //
 102 #define MAC_REG_TCR         0x57        //
 103 #define MAC_REG_IMR         0x58        //
 104 #define MAC_REG_ISR         0x5C
 105 // Power Saving Related
 106 #define MAC_REG_PSCFG       0x60        //
 107 #define MAC_REG_PSCTL       0x61        //
 108 #define MAC_REG_PSPWRSIG    0x62        //
 109 #define MAC_REG_BBCR13      0x63
 110 #define MAC_REG_AIDATIM     0x64
 111 #define MAC_REG_PWBT        0x66
 112 #define MAC_REG_WAKEOKTMR   0x68
 113 #define MAC_REG_CALTMR      0x69
 114 #define MAC_REG_SYNSPACCNT  0x6A
 115 #define MAC_REG_WAKSYNOPT   0x6B
 116 // Baseband/IF Control Group
 117 #define MAC_REG_BBREGCTL    0x6C        //
 118 #define MAC_REG_CHANNEL     0x6D
 119 #define MAC_REG_BBREGADR    0x6E
 120 #define MAC_REG_BBREGDATA   0x6F
 121 #define MAC_REG_IFREGCTL    0x70        //
 122 #define MAC_REG_IFDATA      0x71        //
 123 #define MAC_REG_ITRTMSET    0x74        //
 124 #define MAC_REG_PAPEDELAY   0x77
 125 #define MAC_REG_SOFTPWRCTL  0x78        //
 126 #define MAC_REG_GPIOCTL0    0x7A        //
 127 #define MAC_REG_GPIOCTL1    0x7B        //
 128
 129 // MAC DMA Related Group
 130 #define MAC_REG_TXDMACTL0   0x7C        //
 131 #define MAC_REG_TXDMAPTR0   0x80        //
 132 #define MAC_REG_AC0DMACTL   0x84        //
 133 #define MAC_REG_AC0DMAPTR   0x88        //
 134 #define MAC_REG_BCNDMACTL   0x8C        //
 135 #define MAC_REG_BCNDMAPTR   0x90        //
 136 #define MAC_REG_RXDMACTL0   0x94        //
 137 #define MAC_REG_RXDMAPTR0   0x98        //
 138 #define MAC_REG_RXDMACTL1   0x9C        //
 139 #define MAC_REG_RXDMAPTR1   0xA0        //
 140 #define MAC_REG_SYNCDMACTL  0xA4        //
 141 #define MAC_REG_SYNCDMAPTR  0xA8
 142 #define MAC_REG_ATIMDMACTL  0xAC
 143 #define MAC_REG_ATIMDMAPTR  0xB0
 144 // MiscFF PIO related
 145 #define MAC_REG_MISCFFNDEX  0xB4
 146 #define MAC_REG_MISCFFCTL   0xB6
 147 #define MAC_REG_MISCFFDATA  0xB8
 148 // Extend SW Timer
 149 #define MAC_REG_TMDATA1     0xBC
 150 // WOW Related Group
 151 #define MAC_REG_WAKEUPEN0   0xC0
 152 #define MAC_REG_WAKEUPEN1   0xC1
 153 #define MAC_REG_WAKEUPSR0   0xC2
 154 #define MAC_REG_WAKEUPSR1   0xC3
 155 #define MAC_REG_WAKE128_0   0xC4
 156 #define MAC_REG_WAKE128_1   0xD4
 157 #define MAC_REG_WAKE128_2   0xE4
 158 #define MAC_REG_WAKE128_3   0xF4
 159
 160 /////////////// Page 1 ///////////////////
 161 #define MAC_REG_CRC_128_0   0x04
 162 #define MAC_REG_CRC_128_1   0x06
 163 #define MAC_REG_CRC_128_2   0x08
 164 #define MAC_REG_CRC_128_3   0x0A
 165 // MAC Configuration Group
 166 #define MAC_REG_PAR0        0x0C
 167 #define MAC_REG_PAR4        0x10
 168 #define MAC_REG_BSSID0      0x14
 169 #define MAC_REG_BSSID4      0x18
 170 #define MAC_REG_MAR0        0x1C
 171 #define MAC_REG_MAR4        0x20
 172 // MAC RSPPKT INFO Group
 173 #define MAC_REG_RSPINF_B_1  0x24
 174 #define MAC_REG_RSPINF_B_2  0x28
 175 #define MAC_REG_RSPINF_B_5  0x2C
 176 #define MAC_REG_RSPINF_B_11 0x30
 177 #define MAC_REG_RSPINF_A_6  0x34
 178 #define MAC_REG_RSPINF_A_9  0x36
 179 #define MAC_REG_RSPINF_A_12 0x38
 180 #define MAC_REG_RSPINF_A_18 0x3A
 181 #define MAC_REG_RSPINF_A_24 0x3C
 182 #define MAC_REG_RSPINF_A_36 0x3E
 183 #define MAC_REG_RSPINF_A_48 0x40
 184 #define MAC_REG_RSPINF_A_54 0x42
 185 #define MAC_REG_RSPINF_A_72 0x44
 186
 187 // 802.11h relative
 188 #define MAC_REG_QUIETINIT   0x60
 189 #define MAC_REG_QUIETGAP    0x62
 190 #define MAC_REG_QUIETDUR    0x64
 191 #define MAC_REG_MSRCTL      0x66
 192 #define MAC_REG_MSRBBSTS    0x67
 193 #define MAC_REG_MSRSTART    0x68
 194 #define MAC_REG_MSRDURATION 0x70
 195 #define MAC_REG_CCAFRACTION 0x72
 196 #define MAC_REG_PWRCCK      0x73
 197 #define MAC_REG_PWROFDM     0x7C
 198
 199 //
 200 // Bits in the BCFG0 register
 201 //
 202 #define BCFG0_PERROFF       0x40
 203 #define BCFG0_MRDMDIS       0x20
 204 #define BCFG0_MRDLDIS       0x10
 205 #define BCFG0_MWMEN         0x08
 206 #define BCFG0_VSERREN       0x02
 207 #define BCFG0_LATMEN        0x01
 208
 209 //
 210 // Bits in the BCFG1 register
 211 //
 212 #define BCFG1_CFUNOPT       0x80
 213 #define BCFG1_CREQOPT       0x40
 214 #define BCFG1_DMA8          0x10
 215 #define BCFG1_ARBITOPT      0x08
 216 #define BCFG1_PCIMEN        0x04
 217 #define BCFG1_MIOEN         0x02
 218 #define BCFG1_CISDLYEN      0x01
 219
 220 // Bits in RAMBIST registers
 221 #define BISTCMD_TSTPAT5     0x00        //
 222 #define BISTCMD_TSTPATA     0x80        //
 223 #define BISTCMD_TSTERR      0x20        //
 224 #define BISTCMD_TSTPATF     0x18        //
 225 #define BISTCMD_TSTPAT0     0x10        //
 226 #define BISTCMD_TSTMODE     0x04        //
 227 #define BISTCMD_TSTITTX     0x03        //
 228 #define BISTCMD_TSTATRX     0x02        //
 229 #define BISTCMD_TSTATTX     0x01        //
 230 #define BISTCMD_TSTRX       0x00        //
 231 #define BISTSR0_BISTGO      0x01        //
 232 #define BISTSR1_TSTSR       0x01        //
 233 #define BISTSR2_CMDPRTEN    0x02        //
 234 #define BISTSR2_RAMTSTEN    0x01        //
 235
 236 //
 237 // Bits in the I2MCFG EEPROM register
 238 //
 239 #define I2MCFG_BOUNDCTL     0x80
 240 #define I2MCFG_WAITCTL      0x20
 241 #define I2MCFG_SCLOECTL     0x10
 242 #define I2MCFG_WBUSYCTL     0x08
 243 #define I2MCFG_NORETRY      0x04
 244 #define I2MCFG_I2MLDSEQ     0x02
 245 #define I2MCFG_I2CMFAST     0x01
 246
 247 //
 248 // Bits in the I2MCSR EEPROM register
 249 //
 250 #define I2MCSR_EEMW         0x80
 251 #define I2MCSR_EEMR         0x40
 252 #define I2MCSR_AUTOLD       0x08
 253 #define I2MCSR_NACK         0x02
 254 #define I2MCSR_DONE         0x01
 255
 256 //
 257 // Bits in the PMC1 register
 258 //
 259 #define SPS_RST             0x80
 260 #define PCISTIKY            0x40
 261 #define PME_OVR             0x02
 262
 263 //
 264 // Bits in the STICKYHW register
 265 //
 266 #define STICKHW_DS1_SHADOW  0x02
 267 #define STICKHW_DS0_SHADOW  0x01
 268
 269 //
 270 // Bits in the TMCTL register
 271 //
 272 #define TMCTL_TSUSP         0x04
 273 #define TMCTL_TMD           0x02
 274 #define TMCTL_TE            0x01
 275
 276 //
 277 // Bits in the TFTCTL register
 278 //
 279 #define TFTCTL_HWUTSF       0x80        //
 280 #define TFTCTL_TBTTSYNC     0x40
 281 #define TFTCTL_HWUTSFEN     0x20
 282 #define TFTCTL_TSFCNTRRD    0x10        //
 283 #define TFTCTL_TBTTSYNCEN   0x08        //
 284 #define TFTCTL_TSFSYNCEN    0x04        //
 285 #define TFTCTL_TSFCNTRST    0x02        //
 286 #define TFTCTL_TSFCNTREN    0x01        //
 287
 288 //
 289 // Bits in the EnhanceCFG register
 290 //
 291 #define EnCFG_BarkerPream   0x00020000
 292 #define EnCFG_NXTBTTCFPSTR  0x00010000
 293 #define EnCFG_BcnSusClr     0x00000200
 294 #define EnCFG_BcnSusInd     0x00000100
 295 #define EnCFG_CFP_ProtectEn 0x00000040
 296 #define EnCFG_ProtectMd     0x00000020
 297 #define EnCFG_HwParCFP      0x00000010
 298 #define EnCFG_CFNULRSP      0x00000004
 299 #define EnCFG_BBType_MASK   0x00000003
 300 #define EnCFG_BBType_g      0x00000002
 301 #define EnCFG_BBType_b      0x00000001
 302 #define EnCFG_BBType_a      0x00000000
 303
 304 //
 305 // Bits in the Page1Sel register
 306 //
 307 #define PAGE1_SEL           0x01
 308
 309 //
 310 // Bits in the CFG register
 311 //
 312 #define CFG_TKIPOPT         0x80
 313 #define CFG_RXDMAOPT        0x40
 314 #define CFG_TMOT_SW         0x20
 315 #define CFG_TMOT_HWLONG     0x10
 316 #define CFG_TMOT_HW         0x00
 317 #define CFG_CFPENDOPT       0x08
 318 #define CFG_BCNSUSEN        0x04
 319 #define CFG_NOTXTIMEOUT     0x02
 320 #define CFG_NOBUFOPT        0x01
 321
 322 //
 323 // Bits in the TEST register
 324 //
 325 #define TEST_LBEXT          0x80        //
 326 #define TEST_LBINT          0x40        //
 327 #define TEST_LBNONE         0x00        //
 328 #define TEST_SOFTINT        0x20        //
 329 #define TEST_CONTTX         0x10        //
 330 #define TEST_TXPE           0x08        //
 331 #define TEST_NAVDIS         0x04        //
 332 #define TEST_NOCTS          0x02        //
 333 #define TEST_NOACK          0x01        //
 334
 335 //
 336 // Bits in the HOSTCR register
 337 //
 338 #define HOSTCR_TXONST       0x80        //
 339 #define HOSTCR_RXONST       0x40        //
 340 #define HOSTCR_ADHOC        0x20        // Network Type 1 = Ad-hoc
 341 #define HOSTCR_AP           0x10        // Port Type 1 = AP
 342 #define HOSTCR_TXON         0x08        //0000 1000
 343 #define HOSTCR_RXON         0x04        //0000 0100
 344 #define HOSTCR_MACEN        0x02        //0000 0010
 345 #define HOSTCR_SOFTRST      0x01        //0000 0001
 346
 347 //
 348 // Bits in the MACCR register
 349 //
 350 #define MACCR_SYNCFLUSHOK   0x04        //
 351 #define MACCR_SYNCFLUSH     0x02        //
 352 #define MACCR_CLRNAV        0x01        //
 353
 354 // Bits in the MAC_REG_GPIOCTL0 register
 355 //
 356 #define LED_ACTSET           0x01        //
 357 #define LED_RFOFF            0x02        //
 358 #define LED_NOCONNECT        0x04        //
 359 //
 360 // Bits in the RCR register
 361 //
 362 #define RCR_SSID            0x80
 363 #define RCR_RXALLTYPE       0x40        //
 364 #define RCR_UNICAST         0x20        //
 365 #define RCR_BROADCAST       0x10        //
 366 #define RCR_MULTICAST       0x08        //
 367 #define RCR_WPAERR          0x04        //
 368 #define RCR_ERRCRC          0x02        //
 369 #define RCR_BSSID           0x01        //
 370
 371 //
 372 // Bits in the TCR register
 373 //
 374 #define TCR_SYNCDCFOPT      0x02        //
 375 #define TCR_AUTOBCNTX       0x01        // Beacon automatically transmit enable
 376
 377 //
 378 // Bits in the IMR register
 379 //
 380 #define IMR_MEASURESTART    0x80000000      //
 381 #define IMR_QUIETSTART      0x20000000      //
 382 #define IMR_RADARDETECT     0x10000000      //
 383 #define IMR_MEASUREEND      0x08000000      //
 384 #define IMR_SOFTTIMER1      0x00200000      //
 385 #define IMR_RXDMA1          0x00001000      //0000 0000 0001 0000 0000 0000
 386 #define IMR_RXNOBUF         0x00000800      //
 387 #define IMR_MIBNEARFULL     0x00000400      //
 388 #define IMR_SOFTINT         0x00000200      //
 389 #define IMR_FETALERR        0x00000100      //
 390 #define IMR_WATCHDOG        0x00000080      //
 391 #define IMR_SOFTTIMER       0x00000040      //
 392 #define IMR_GPIO            0x00000020      //
 393 #define IMR_TBTT            0x00000010      //
 394 #define IMR_RXDMA0          0x00000008      //
 395 #define IMR_BNTX            0x00000004      //
 396 #define IMR_AC0DMA          0x00000002      //
 397 #define IMR_TXDMA0          0x00000001      //
 398
 399 //
 400 // Bits in the ISR register
 401 //
 402
 403 #define ISR_MEASURESTART    0x80000000      //
 404 #define ISR_QUIETSTART      0x20000000      //
 405 #define ISR_RADARDETECT     0x10000000      //
 406 #define ISR_MEASUREEND      0x08000000      //
 407 #define ISR_SOFTTIMER1      0x00200000      //
 408 #define ISR_RXDMA1          0x00001000      //0000 0000 0001 0000 0000 0000
 409 #define ISR_RXNOBUF         0x00000800      //0000 0000 0000 1000 0000 0000
 410 #define ISR_MIBNEARFULL     0x00000400      //0000 0000 0000 0100 0000 0000
 411 #define ISR_SOFTINT         0x00000200      //
 412 #define ISR_FETALERR        0x00000100      //
 413 #define ISR_WATCHDOG        0x00000080      //
 414 #define ISR_SOFTTIMER       0x00000040      //
 415 #define ISR_GPIO            0x00000020      //
 416 #define ISR_TBTT            0x00000010      //
 417 #define ISR_RXDMA0          0x00000008      //
 418 #define ISR_BNTX            0x00000004      //
 419 #define ISR_AC0DMA          0x00000002      //
 420 #define ISR_TXDMA0          0x00000001      //
 421
 422 //
 423 // Bits in the PSCFG register
 424 //
 425 #define PSCFG_PHILIPMD      0x40        //
 426 #define PSCFG_WAKECALEN     0x20        //
 427 #define PSCFG_WAKETMREN     0x10        //
 428 #define PSCFG_BBPSPROG      0x08        //
 429 #define PSCFG_WAKESYN       0x04        //
 430 #define PSCFG_SLEEPSYN      0x02        //
 431 #define PSCFG_AUTOSLEEP     0x01        //
 432
 433 //
 434 // Bits in the PSCTL register
 435 //
 436 #define PSCTL_WAKEDONE      0x20        //
 437 #define PSCTL_PS            0x10        //
 438 #define PSCTL_GO2DOZE       0x08        //
 439 #define PSCTL_LNBCN         0x04        //
 440 #define PSCTL_ALBCN         0x02        //
 441 #define PSCTL_PSEN          0x01        //
 442
 443 //
 444 // Bits in the PSPWSIG register
 445 //
 446 #define PSSIG_WPE3          0x80        //
 447 #define PSSIG_WPE2          0x40        //
 448 #define PSSIG_WPE1          0x20        //
 449 #define PSSIG_WRADIOPE      0x10        //
 450 #define PSSIG_SPE3          0x08        //
 451 #define PSSIG_SPE2          0x04        //
 452 #define PSSIG_SPE1          0x02        //
 453 #define PSSIG_SRADIOPE      0x01        //
 454
 455 //
 456 // Bits in the BBREGCTL register
 457 //
 458 #define BBREGCTL_DONE       0x04        //
 459 #define BBREGCTL_REGR       0x02        //
 460 #define BBREGCTL_REGW       0x01        //
 461
 462 //
 463 // Bits in the IFREGCTL register
 464 //
 465 #define IFREGCTL_DONE       0x04        //
 466 #define IFREGCTL_IFRF       0x02        //
 467 #define IFREGCTL_REGW       0x01        //
 468
 469 //
 470 // Bits in the SOFTPWRCTL register
 471 //
 472 #define SOFTPWRCTL_RFLEOPT      0x0800  //
 473 #define SOFTPWRCTL_TXPEINV      0x0200  //
 474 #define SOFTPWRCTL_SWPECTI      0x0100  //
 475 #define SOFTPWRCTL_SWPAPE       0x0020  //
 476 #define SOFTPWRCTL_SWCALEN      0x0010  //
 477 #define SOFTPWRCTL_SWRADIO_PE   0x0008  //
 478 #define SOFTPWRCTL_SWPE2        0x0004  //
 479 #define SOFTPWRCTL_SWPE1        0x0002  //
 480 #define SOFTPWRCTL_SWPE3        0x0001  //
 481
 482 //
 483 // Bits in the GPIOCTL1 register
 484 //
 485 #define GPIO1_DATA1             0x20    //
 486 #define GPIO1_MD1               0x10    //
 487 #define GPIO1_DATA0             0x02    //
 488 #define GPIO1_MD0               0x01    //
 489
 490 //
 491 // Bits in the DMACTL register
 492 //
 493 #define DMACTL_CLRRUN       0x00080000  //
 494 #define DMACTL_RUN          0x00000008  //
 495 #define DMACTL_WAKE         0x00000004  //
 496 #define DMACTL_DEAD         0x00000002  //
 497 #define DMACTL_ACTIVE       0x00000001  //
 498 //
 499 // Bits in the RXDMACTL0 register
 500 //
 501 #define RX_PERPKT           0x00000100  //
 502 #define RX_PERPKTCLR        0x01000000  //
 503 //
 504 // Bits in the BCNDMACTL register
 505 //
 506 #define BEACON_READY        0x01        //
 507 //
 508 // Bits in the MISCFFCTL register
 509 //
 510 #define MISCFFCTL_WRITE     0x0001      //
 511
 512 //
 513 // Bits in WAKEUPEN0
 514 //
 515 #define WAKEUPEN0_DIRPKT    0x10
 516 #define WAKEUPEN0_LINKOFF   0x08
 517 #define WAKEUPEN0_ATIMEN    0x04
 518 #define WAKEUPEN0_TIMEN     0x02
 519 #define WAKEUPEN0_MAGICEN   0x01
 520
 521 //
 522 // Bits in WAKEUPEN1
 523 //
 524 #define WAKEUPEN1_128_3     0x08
 525 #define WAKEUPEN1_128_2     0x04
 526 #define WAKEUPEN1_128_1     0x02
 527 #define WAKEUPEN1_128_0     0x01
 528
 529 //
 530 // Bits in WAKEUPSR0
 531 //
 532 #define WAKEUPSR0_DIRPKT    0x10
 533 #define WAKEUPSR0_LINKOFF   0x08
 534 #define WAKEUPSR0_ATIMEN    0x04
 535 #define WAKEUPSR0_TIMEN     0x02
 536 #define WAKEUPSR0_MAGICEN   0x01
 537
 538 //
 539 // Bits in WAKEUPSR1
 540 //
 541 #define WAKEUPSR1_128_3     0x08
 542 #define WAKEUPSR1_128_2     0x04
 543 #define WAKEUPSR1_128_1     0x02
 544 #define WAKEUPSR1_128_0     0x01
 545
 546 //
 547 // Bits in the MAC_REG_GPIOCTL register
 548 //
 549 #define GPIO0_MD            0x01        //
 550 #define GPIO0_DATA          0x02        //
 551 #define GPIO0_INTMD         0x04        //
 552 #define GPIO1_MD            0x10        //
 553 #define GPIO1_DATA          0x20        //
 554
 555 //
 556 // Bits in the MSRCTL register
 557 //
 558 #define MSRCTL_FINISH       0x80
 559 #define MSRCTL_READY        0x40
 560 #define MSRCTL_RADARDETECT  0x20
 561 #define MSRCTL_EN           0x10
 562 #define MSRCTL_QUIETTXCHK   0x08
 563 #define MSRCTL_QUIETRPT     0x04
 564 #define MSRCTL_QUIETINT     0x02
 565 #define MSRCTL_QUIETEN      0x01
 566 //
 567 // Bits in the MSRCTL1 register
 568 //
 569 #define MSRCTL1_TXPWR       0x08
 570 #define MSRCTL1_CSAPAREN    0x04
 571 #define MSRCTL1_TXPAUSE     0x01
 572
 573 // Loopback mode
 574 #define MAC_LB_EXT          0x02        //
 575 #define MAC_LB_INTERNAL     0x01        //
 576 #define MAC_LB_NONE         0x00        //
 577
 578 // Ethernet address filter type
 579 #define PKT_TYPE_NONE           0x00    // turn off receiver
 580 #define PKT_TYPE_ALL_MULTICAST  0x80
 581 #define PKT_TYPE_PROMISCUOUS    0x40
 582 #define PKT_TYPE_DIRECTED       0x20    // obsolete, directed address is always accepted
 583 #define PKT_TYPE_BROADCAST      0x10
 584 #define PKT_TYPE_MULTICAST      0x08
 585 #define PKT_TYPE_ERROR_WPA      0x04
 586 #define PKT_TYPE_ERROR_CRC      0x02
 587 #define PKT_TYPE_BSSID          0x01
 588
 589 #define Default_BI              0x200
 590
 591 // MiscFIFO Offset
 592 #define MISCFIFO_KEYETRY0       32
 593 #define MISCFIFO_KEYENTRYSIZE   22
 594 #define MISCFIFO_SYNINFO_IDX    10
 595 #define MISCFIFO_SYNDATA_IDX    11
 596 #define MISCFIFO_SYNDATASIZE    21
 597
 598 // enabled mask value of irq
 599 #define IMR_MASK_VALUE     (IMR_SOFTTIMER1 |    \
 600                             IMR_RXDMA1 |        \
 601                             IMR_RXNOBUF |       \
 602                             IMR_MIBNEARFULL |   \
 603                             IMR_SOFTINT |       \
 604                             IMR_FETALERR |      \
 605                             IMR_WATCHDOG |      \
 606                             IMR_SOFTTIMER |     \
 607                             IMR_GPIO |          \
 608                             IMR_TBTT |          \
 609                             IMR_RXDMA0 |        \
 610                             IMR_BNTX |          \
 611                             IMR_AC0DMA |        \
 612                             IMR_TXDMA0)
 613
 614 // max time out delay time
 615 #define W_MAX_TIMEOUT       0xFFF0U     //
 616
 617 // wait time within loop
 618 #define CB_DELAY_LOOP_WAIT  10          // 10ms
 619
 620 //
 621 // revision id
 622 //
 623 #define REV_ID_VT3253_A0    0x00
 624 #define REV_ID_VT3253_A1    0x01
 625 #define REV_ID_VT3253_B0    0x08
 626 #define REV_ID_VT3253_B1    0x09
 627
 628 /*---------------------  Export Types  ------------------------------*/
 629
 630 /*---------------------  Export Macros ------------------------------*/
 631
 632 #define MACvRegBitsOn(dwIoBase, byRegOfs, byBits)                       \
 633 do {                                                                    \
 634         unsigned char byData;                                           \
 635         VNSvInPortB(dwIoBase + byRegOfs, &byData);                      \
 636         VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits));           \
 637 } while (0)
 638
 639 #define MACvWordRegBitsOn(dwIoBase, byRegOfs, wBits)                    \
 640 do {                                                                    \
 641         unsigned short wData;                                           \
 642         VNSvInPortW(dwIoBase + byRegOfs, &wData);                       \
 643         VNSvOutPortW(dwIoBase + byRegOfs, wData | (wBits));             \
 644 } while (0)
 645
 646 #define MACvDWordRegBitsOn(dwIoBase, byRegOfs, dwBits)                  \
 647 do {                                                                    \
 648         unsigned long dwData;                                           \
 649         VNSvInPortD(dwIoBase + byRegOfs, &dwData);                      \
 650         VNSvOutPortD(dwIoBase + byRegOfs, dwData | (dwBits));           \
 651 } while (0)
 652
 653 #define MACvRegBitsOnEx(dwIoBase, byRegOfs, byMask, byBits)             \
 654 do {                                                                    \
 655         unsigned char byData;                                           \
 656         VNSvInPortB(dwIoBase + byRegOfs, &byData);                      \
 657         byData &= byMask;                                               \
 658         VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits));           \
 659 } while (0)
 660
 661 #define MACvRegBitsOff(dwIoBase, byRegOfs, byBits)                      \
 662 do {                                                                    \
 663         unsigned char byData;                                           \
 664         VNSvInPortB(dwIoBase + byRegOfs, &byData);                      \
 665         VNSvOutPortB(dwIoBase + byRegOfs, byData & ~(byBits));          \
 666 } while (0)
 667
 668 #define MACvWordRegBitsOff(dwIoBase, byRegOfs, wBits)                   \
 669 do {                                                                    \
 670         unsigned short wData;                                           \
 671         VNSvInPortW(dwIoBase + byRegOfs, &wData);                       \
 672         VNSvOutPortW(dwIoBase + byRegOfs, wData & ~(wBits));            \
 673 } while (0)
 674
 675 #define MACvDWordRegBitsOff(dwIoBase, byRegOfs, dwBits)                 \
 676 do {                                                                    \
 677         unsigned long dwData;                                           \
 678         VNSvInPortD(dwIoBase + byRegOfs, &dwData);                      \
 679         VNSvOutPortD(dwIoBase + byRegOfs, dwData & ~(dwBits));          \
 680 } while (0)
 681
 682 #define MACvGetCurrRx0DescAddr(dwIoBase, pdwCurrDescAddr)       \
 683         VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR0,               \
 684                     (unsigned long *)pdwCurrDescAddr)
 685
 686 #define MACvGetCurrRx1DescAddr(dwIoBase, pdwCurrDescAddr)       \
 687         VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR1,               \
 688                     (unsigned long *)pdwCurrDescAddr)
 689
 690 #define MACvGetCurrTx0DescAddr(dwIoBase, pdwCurrDescAddr)       \
 691         VNSvInPortD(dwIoBase + MAC_REG_TXDMAPTR0,               \
 692                     (unsigned long *)pdwCurrDescAddr)
 693
 694 #define MACvGetCurrAC0DescAddr(dwIoBase, pdwCurrDescAddr)       \
 695         VNSvInPortD(dwIoBase + MAC_REG_AC0DMAPTR,               \
 696                     (unsigned long *)pdwCurrDescAddr)
 697
 698 #define MACvGetCurrSyncDescAddr(dwIoBase, pdwCurrDescAddr)      \
 699         VNSvInPortD(dwIoBase + MAC_REG_SYNCDMAPTR,              \
 700                     (unsigned long *)pdwCurrDescAddr)
 701
 702 #define MACvGetCurrATIMDescAddr(dwIoBase, pdwCurrDescAddr)      \
 703         VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR,              \
 704                     (unsigned long *)pdwCurrDescAddr)
 705
 706 // set the chip with current BCN tx descriptor address
 707 #define MACvSetCurrBCNTxDescAddr(dwIoBase, dwCurrDescAddr)      \
 708         VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR,              \
 709                      dwCurrDescAddr)
 710
 711 // set the chip with current BCN length
 712 #define MACvSetCurrBCNLength(dwIoBase, wCurrBCNLength)          \
 713         VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2,            \
 714                      wCurrBCNLength)
 715
 716 #define MACvReadBSSIDAddress(dwIoBase, pbyEtherAddr)            \
 717 do {                                                            \
 718         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);           \
 719         VNSvInPortB(dwIoBase + MAC_REG_BSSID0,                  \
 720                     (unsigned char *)pbyEtherAddr);             \
 721         VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 1,              \
 722                     pbyEtherAddr + 1);                          \
 723         VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 2,              \
 724                     pbyEtherAddr + 2);                          \
 725         VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 3,              \
 726                     pbyEtherAddr + 3);                          \
 727         VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 4,              \
 728                     pbyEtherAddr + 4);                          \
 729         VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 5,              \
 730                     pbyEtherAddr + 5);                          \
 731         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);           \
 732 } while (0)
 733
 734 #define MACvWriteBSSIDAddress(dwIoBase, pbyEtherAddr)           \
 735 do {                                                            \
 736         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);           \
 737         VNSvOutPortB(dwIoBase + MAC_REG_BSSID0,                 \
 738                      *(pbyEtherAddr));                          \
 739         VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 1,             \
 740                      *(pbyEtherAddr + 1));                      \
 741         VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 2,             \
 742                      *(pbyEtherAddr + 2));                      \
 743         VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 3,             \
 744                      *(pbyEtherAddr + 3));                      \
 745         VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 4,             \
 746                      *(pbyEtherAddr + 4));                      \
 747         VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 5,             \
 748                      *(pbyEtherAddr + 5));                      \
 749         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);           \
 750 } while (0)
 751
 752 #define MACvReadEtherAddress(dwIoBase, pbyEtherAddr)            \
 753 do {                                                            \
 754         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);           \
 755         VNSvInPortB(dwIoBase + MAC_REG_PAR0,                    \
 756                     (unsigned char *)pbyEtherAddr);             \
 757         VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 1,                \
 758                     pbyEtherAddr + 1);                          \
 759         VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 2,                \
 760                     pbyEtherAddr + 2);                          \
 761         VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 3,                \
 762                     pbyEtherAddr + 3);                          \
 763         VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 4,                \
 764                     pbyEtherAddr + 4);                          \
 765         VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 5,                \
 766                     pbyEtherAddr + 5);                          \
 767         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);           \
 768 } while (0)
 769
 770 #define MACvWriteEtherAddress(dwIoBase, pbyEtherAddr)           \
 771 do {                                                            \
 772         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);           \
 773         VNSvOutPortB(dwIoBase + MAC_REG_PAR0,                   \
 774                      *pbyEtherAddr);                            \
 775         VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 1,               \
 776                      *(pbyEtherAddr + 1));                      \
 777         VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 2,               \
 778                      *(pbyEtherAddr + 2));                      \
 779         VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 3,               \
 780                      *(pbyEtherAddr + 3));                      \
 781         VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 4,               \
 782                      *(pbyEtherAddr + 4));                      \
 783         VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 5,               \
 784                      *(pbyEtherAddr + 5));                      \
 785         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);           \
 786 } while (0)
 787
 788 #define MACvClearISR(dwIoBase)                                          \
 789         VNSvOutPortD(dwIoBase + MAC_REG_ISR, IMR_MASK_VALUE)
 790
 791 #define MACvStart(dwIoBase)                                             \
 792         VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR,                         \
 793                      (HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON))
 794
 795 #define MACvRx0PerPktMode(dwIoBase)                                     \
 796         VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKT)
 797
 798 #define MACvRx0BufferFillMode(dwIoBase)                                 \
 799         VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKTCLR)
 800
 801 #define MACvRx1PerPktMode(dwIoBase)                                     \
 802         VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKT)
 803
 804 #define MACvRx1BufferFillMode(dwIoBase)                                 \
 805         VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKTCLR)
 806
 807 #define MACvRxOn(dwIoBase)                                              \
 808         MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON)
 809
 810 #define MACvReceive0(dwIoBase)                                          \
 811 do {                                                                    \
 812         unsigned long dwData;                                           \
 813         VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData);             \
 814         if (dwData & DMACTL_RUN)                                        \
 815                 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \
 816         else                                                            \
 817                 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); \
 818 } while (0)
 819
 820 #define MACvReceive1(dwIoBase)                                          \
 821 do {                                                                    \
 822         unsigned long dwData;                                           \
 823         VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData);             \
 824         if (dwData & DMACTL_RUN)                                        \
 825                 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \
 826         else                                                            \
 827                 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); \
 828 } while (0)
 829
 830 #define MACvTxOn(dwIoBase)                                              \
 831         MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON)
 832
 833 #define MACvTransmit0(dwIoBase)                                         \
 834 do {                                                                    \
 835         unsigned long dwData;                                           \
 836         VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData);             \
 837         if (dwData & DMACTL_RUN)                                        \
 838                 VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \
 839         else                                                            \
 840                 VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); \
 841 } while (0)
 842
 843 #define MACvTransmitAC0(dwIoBase)                                       \
 844 do {                                                                    \
 845         unsigned long dwData;                                           \
 846         VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData);             \
 847         if (dwData & DMACTL_RUN)                                        \
 848                 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \
 849         else                                                            \
 850                 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); \
 851 } while (0)
 852
 853 #define MACvTransmitSYNC(dwIoBase)                                      \
 854 do {                                                                    \
 855         unsigned long dwData;                                           \
 856         VNSvInPortD(dwIoBase + MAC_REG_SYNCDMACTL, &dwData);            \
 857         if (dwData & DMACTL_RUN)                                        \
 858                 VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_WAKE); \
 859         else                                                            \
 860                 VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \
 861 } while (0)
 862
 863 #define MACvTransmitATIM(dwIoBase)                                      \
 864 do {                                                                    \
 865         unsigned long dwData;                                           \
 866         VNSvInPortD(dwIoBase + MAC_REG_ATIMDMACTL, &dwData);            \
 867         if (dwData & DMACTL_RUN)                                        \
 868                 VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_WAKE); \
 869         else                                                            \
 870                 VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \
 871 } while (0)
 872
 873 #define MACvTransmitBCN(dwIoBase)                                       \
 874         VNSvOutPortB(dwIoBase + MAC_REG_BCNDMACTL, BEACON_READY)
 875
 876 #define MACvClearStckDS(dwIoBase)                                       \
 877 do {                                                                    \
 878         unsigned char byOrgValue;                                       \
 879         VNSvInPortB(dwIoBase + MAC_REG_STICKHW, &byOrgValue);           \
 880         byOrgValue = byOrgValue & 0xFC;                                 \
 881         VNSvOutPortB(dwIoBase + MAC_REG_STICKHW, byOrgValue);           \
 882 } while (0)
 883
 884 #define MACvReadISR(dwIoBase, pdwValue)                         \
 885         VNSvInPortD(dwIoBase + MAC_REG_ISR, pdwValue)
 886
 887 #define MACvWriteISR(dwIoBase, dwValue)                         \
 888         VNSvOutPortD(dwIoBase + MAC_REG_ISR, dwValue)
 889
 890 #define MACvIntEnable(dwIoBase, dwMask)                         \
 891         VNSvOutPortD(dwIoBase + MAC_REG_IMR, dwMask)
 892
 893 #define MACvIntDisable(dwIoBase)                                \
 894         VNSvOutPortD(dwIoBase + MAC_REG_IMR, 0)
 895
 896 #define MACvSelectPage0(dwIoBase)                               \
 897                 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0)
 898
 899 #define MACvSelectPage1(dwIoBase)                               \
 900         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1)
 901
 902 #define MACvReadMIBCounter(dwIoBase, pdwCounter)                        \
 903         VNSvInPortD(dwIoBase + MAC_REG_MIBCNTR , pdwCounter)
 904
 905 #define MACvPwrEvntDisable(dwIoBase)                                    \
 906         VNSvOutPortW(dwIoBase + MAC_REG_WAKEUPEN0, 0x0000)
 907
 908 #define MACvEnableProtectMD(dwIoBase)                                   \
 909 do {                                                                    \
 910         unsigned long dwOrgValue;                                       \
 911         VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue);            \
 912         dwOrgValue = dwOrgValue | EnCFG_ProtectMd;                      \
 913         VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);             \
 914 } while (0)
 915
 916 #define MACvDisableProtectMD(dwIoBase)                                  \
 917 do {                                                                    \
 918         unsigned long dwOrgValue;                                       \
 919         VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue);            \
 920         dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd;                     \
 921         VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);             \
 922 } while (0)
 923
 924 #define MACvEnableBarkerPreambleMd(dwIoBase)                            \
 925 do {                                                                    \
 926         unsigned long dwOrgValue;                                       \
 927         VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue);            \
 928         dwOrgValue = dwOrgValue | EnCFG_BarkerPream;                    \
 929         VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);             \
 930 } while (0)
 931
 932 #define MACvDisableBarkerPreambleMd(dwIoBase)                           \
 933 do {                                                                    \
 934         unsigned long dwOrgValue;                                       \
 935         VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue);            \
 936         dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream;                   \
 937         VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);             \
 938 } while (0)
 939
 940 #define MACvSetBBType(dwIoBase, byTyp)                                  \
 941 do {                                                                    \
 942         unsigned long dwOrgValue;                                       \
 943         VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue);            \
 944         dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK;                   \
 945         dwOrgValue = dwOrgValue | (unsigned long)byTyp;                 \
 946         VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);             \
 947 } while (0)
 948
 949 #define MACvReadATIMW(dwIoBase, pwCounter)                              \
 950         VNSvInPortW(dwIoBase + MAC_REG_AIDATIM, pwCounter)
 951
 952 #define MACvWriteATIMW(dwIoBase, wCounter)                              \
 953         VNSvOutPortW(dwIoBase + MAC_REG_AIDATIM, wCounter)
 954
 955 #define MACvWriteCRC16_128(dwIoBase, byRegOfs, wCRC)            \
 956 do {                                                            \
 957         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);           \
 958         VNSvOutPortW(dwIoBase + byRegOfs, wCRC);                \
 959         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);           \
 960 } while (0)
 961
 962 #define MACvGPIOIn(dwIoBase, pbyValue)                                  \
 963         VNSvInPortB(dwIoBase + MAC_REG_GPIOCTL1, pbyValue)
 964
 965 #define MACvSetRFLE_LatchBase(dwIoBase)                                 \
 966         MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT)
 967
 968 /*---------------------  Export Classes  ----------------------------*/
 969
 970 /*---------------------  Export Variables  --------------------------*/
 971
 972 /*---------------------  Export Functions  --------------------------*/
 973
 974 extern unsigned short TxRate_iwconfig;//2008-5-8 <add> by chester
 975 void MACvReadAllRegs(void __iomem *dwIoBase, unsigned char *pbyMacRegs);
 976
 977 bool MACbIsRegBitsOn(void __iomem *dwIoBase, unsigned char byRegOfs, unsigned char byTestBits);
 978 bool MACbIsRegBitsOff(void __iomem *dwIoBase, unsigned char byRegOfs, unsigned char byTestBits);
 979
 980 bool MACbIsIntDisable(void __iomem *dwIoBase);
 981
 982 unsigned char MACbyReadMultiAddr(void __iomem *dwIoBase, unsigned int uByteIdx);
 983 void MACvWriteMultiAddr(void __iomem *dwIoBase, unsigned int uByteIdx, unsigned char byData);
 984 void MACvSetMultiAddrByHash(void __iomem *dwIoBase, unsigned char byHashIdx);
 985 void MACvResetMultiAddrByHash(void __iomem *dwIoBase, unsigned char byHashIdx);
 986
 987 void MACvSetRxThreshold(void __iomem *dwIoBase, unsigned char byThreshold);
 988 void MACvGetRxThreshold(void __iomem *dwIoBase, unsigned char *pbyThreshold);
 989
 990 void MACvSetTxThreshold(void __iomem *dwIoBase, unsigned char byThreshold);
 991 void MACvGetTxThreshold(void __iomem *dwIoBase, unsigned char *pbyThreshold);
 992
 993 void MACvSetDmaLength(void __iomem *dwIoBase, unsigned char byDmaLength);
 994 void MACvGetDmaLength(void __iomem *dwIoBase, unsigned char *pbyDmaLength);
 995
 996 void MACvSetShortRetryLimit(void __iomem *dwIoBase, unsigned char byRetryLimit);
 997 void MACvGetShortRetryLimit(void __iomem *dwIoBase, unsigned char *pbyRetryLimit);
 998
 999 void MACvSetLongRetryLimit(void __iomem *dwIoBase, unsigned char byRetryLimit);
1000 void MACvGetLongRetryLimit(void __iomem *dwIoBase, unsigned char *pbyRetryLimit);
1001
1002 void MACvSetLoopbackMode(void __iomem *dwIoBase, unsigned char byLoopbackMode);
1003 bool MACbIsInLoopbackMode(void __iomem *dwIoBase);
1004
1005 void MACvSetPacketFilter(void __iomem *dwIoBase, unsigned short wFilterType);
1006
1007 void MACvSaveContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf);
1008 void MACvRestoreContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf);
1009 bool MACbCompareContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf);
1010
1011 bool MACbSoftwareReset(void __iomem *dwIoBase);
1012 bool MACbSafeSoftwareReset(void __iomem *dwIoBase);
1013 bool MACbSafeRxOff(void __iomem *dwIoBase);
1014 bool MACbSafeTxOff(void __iomem *dwIoBase);
1015 bool MACbSafeStop(void __iomem *dwIoBase);
1016 bool MACbShutdown(void __iomem *dwIoBase);
1017 void MACvInitialize(void __iomem *dwIoBase);
1018 void MACvSetCurrRx0DescAddr(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
1019 void MACvSetCurrRx1DescAddr(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
1020 void MACvSetCurrTXDescAddr(int iTxType, void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
1021 void MACvSetCurrTx0DescAddrEx(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
1022 void MACvSetCurrAC0DescAddrEx(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
1023 void MACvSetCurrSyncDescAddrEx(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
1024 void MACvSetCurrATIMDescAddrEx(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
1025 void MACvTimer0MicroSDelay(void __iomem *dwIoBase, unsigned int uDelay);
1026 void MACvOneShotTimer0MicroSec(void __iomem *dwIoBase, unsigned int uDelayTime);
1027 void MACvOneShotTimer1MicroSec(void __iomem *dwIoBase, unsigned int uDelayTime);
1028
1029 void MACvSetMISCFifo(void __iomem *dwIoBase, unsigned short wOffset, unsigned long dwData);
1030
1031 bool MACbTxDMAOff(void __iomem *dwIoBase, unsigned int idx);
1032
1033 void MACvClearBusSusInd(void __iomem *dwIoBase);
1034 void MACvEnableBusSusEn(void __iomem *dwIoBase);
1035
1036 bool MACbFlushSYNCFifo(void __iomem *dwIoBase);
1037 bool MACbPSWakeup(void __iomem *dwIoBase);
1038
1039 void MACvSetKeyEntry(void __iomem *dwIoBase, unsigned short wKeyCtl, unsigned int uEntryIdx,
1040                      unsigned int uKeyIdx, unsigned char *pbyAddr, u32 *pdwKey, unsigned char byLocalID);
1041 void MACvDisableKeyEntry(void __iomem *dwIoBase, unsigned int uEntryIdx);
1042 void MACvSetDefaultKeyEntry(void __iomem *dwIoBase, unsigned int uKeyLen,
1043                             unsigned int uKeyIdx, unsigned long *pdwKey, unsigned char byLocalID);
1044 void MACvDisableDefaultKey(void __iomem *dwIoBase);
1045 void MACvSetDefaultTKIPKeyEntry(void __iomem *dwIoBase, unsigned int uKeyLen,
1046                                 unsigned int uKeyIdx, unsigned long *pdwKey, unsigned char byLocalID);
1047 void MACvSetDefaultKeyCtl(void __iomem *dwIoBase, unsigned short wKeyCtl, unsigned int uEntryIdx, unsigned char byLocalID);
1048
1049 #endif // __MAC_H__