drivers/staging/vt6655/mac.h

   1 /*
   2  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  *
  20  * File: mac.h
  21  *
  22  * Purpose: MAC routines
  23  *
  24  * Author: Tevin Chen
  25  *
  26  * Date: May 21, 1996
  27  *
  28  * Revision History:
  29  *      07-01-2003 Bryan YC Fan:  Re-write codes to support VT3253 spec.
  30  *      08-25-2003 Kyle Hsu:      Porting MAC functions from sim53.
  31  *      09-03-2003 Bryan YC Fan:  Add MACvDisableProtectMD & MACvEnableProtectMD
  32  */
  33
  34 #ifndef __MAC_H__
  35 #define __MAC_H__
  36
  37 #include "tmacro.h"
  38 #include "upc.h"
  39
  40 /*---------------------  Export Definitions -------------------------*/
  41 //
  42 // Registers in the MAC
  43 //
  44 #define MAC_MAX_CONTEXT_SIZE_PAGE0  256
  45 #define MAC_MAX_CONTEXT_SIZE_PAGE1  128
  46
  47 // Registers not related to 802.11b
  48 #define MAC_REG_BCFG0       0x00
  49 #define MAC_REG_BCFG1       0x01
  50 #define MAC_REG_FCR0        0x02
  51 #define MAC_REG_FCR1        0x03
  52 #define MAC_REG_BISTCMD     0x04
  53 #define MAC_REG_BISTSR0     0x05
  54 #define MAC_REG_BISTSR1     0x06
  55 #define MAC_REG_BISTSR2     0x07
  56 #define MAC_REG_I2MCSR      0x08
  57 #define MAC_REG_I2MTGID     0x09
  58 #define MAC_REG_I2MTGAD     0x0A
  59 #define MAC_REG_I2MCFG      0x0B
  60 #define MAC_REG_I2MDIPT     0x0C
  61 #define MAC_REG_I2MDOPT     0x0E
  62 #define MAC_REG_PMC0        0x10
  63 #define MAC_REG_PMC1        0x11
  64 #define MAC_REG_STICKHW     0x12
  65 #define MAC_REG_LOCALID     0x14
  66 #define MAC_REG_TESTCFG     0x15
  67 #define MAC_REG_JUMPER0     0x16
  68 #define MAC_REG_JUMPER1     0x17
  69 #define MAC_REG_TMCTL0      0x18
  70 #define MAC_REG_TMCTL1      0x19
  71 #define MAC_REG_TMDATA0     0x1C
  72 // MAC Parameter related
  73 #define MAC_REG_LRT         0x20        //
  74 #define MAC_REG_SRT         0x21        //
  75 #define MAC_REG_SIFS        0x22        //
  76 #define MAC_REG_DIFS        0x23        //
  77 #define MAC_REG_EIFS        0x24        //
  78 #define MAC_REG_SLOT        0x25        //
  79 #define MAC_REG_BI          0x26        //
  80 #define MAC_REG_CWMAXMIN0   0x28        //
  81 #define MAC_REG_LINKOFFTOTM 0x2A
  82 #define MAC_REG_SWTMOT      0x2B
  83 #define MAC_REG_MIBCNTR     0x2C
  84 #define MAC_REG_RTSOKCNT    0x2C
  85 #define MAC_REG_RTSFAILCNT  0x2D
  86 #define MAC_REG_ACKFAILCNT  0x2E
  87 #define MAC_REG_FCSERRCNT   0x2F
  88 // TSF Related
  89 #define MAC_REG_TSFCNTR     0x30        //
  90 #define MAC_REG_NEXTTBTT    0x38        //
  91 #define MAC_REG_TSFOFST     0x40        //
  92 #define MAC_REG_TFTCTL      0x48        //
  93 // WMAC Control/Status Related
  94 #define MAC_REG_ENCFG       0x4C        //
  95 #define MAC_REG_PAGE1SEL    0x4F        //
  96 #define MAC_REG_CFG         0x50        //
  97 #define MAC_REG_TEST        0x52        //
  98 #define MAC_REG_HOSTCR      0x54        //
  99 #define MAC_REG_MACCR       0x55        //
 100 #define MAC_REG_RCR         0x56        //
 101 #define MAC_REG_TCR         0x57        //
 102 #define MAC_REG_IMR         0x58        //
 103 #define MAC_REG_ISR         0x5C
 104 // Power Saving Related
 105 #define MAC_REG_PSCFG       0x60        //
 106 #define MAC_REG_PSCTL       0x61        //
 107 #define MAC_REG_PSPWRSIG    0x62        //
 108 #define MAC_REG_BBCR13      0x63
 109 #define MAC_REG_AIDATIM     0x64
 110 #define MAC_REG_PWBT        0x66
 111 #define MAC_REG_WAKEOKTMR   0x68
 112 #define MAC_REG_CALTMR      0x69
 113 #define MAC_REG_SYNSPACCNT  0x6A
 114 #define MAC_REG_WAKSYNOPT   0x6B
 115 // Baseband/IF Control Group
 116 #define MAC_REG_BBREGCTL    0x6C        //
 117 #define MAC_REG_CHANNEL     0x6D
 118 #define MAC_REG_BBREGADR    0x6E
 119 #define MAC_REG_BBREGDATA   0x6F
 120 #define MAC_REG_IFREGCTL    0x70        //
 121 #define MAC_REG_IFDATA      0x71        //
 122 #define MAC_REG_ITRTMSET    0x74        //
 123 #define MAC_REG_PAPEDELAY   0x77
 124 #define MAC_REG_SOFTPWRCTL  0x78        //
 125 #define MAC_REG_GPIOCTL0    0x7A        //
 126 #define MAC_REG_GPIOCTL1    0x7B        //
 127
 128 // MAC DMA Related Group
 129 #define MAC_REG_TXDMACTL0   0x7C        //
 130 #define MAC_REG_TXDMAPTR0   0x80        //
 131 #define MAC_REG_AC0DMACTL   0x84        //
 132 #define MAC_REG_AC0DMAPTR   0x88        //
 133 #define MAC_REG_BCNDMACTL   0x8C        //
 134 #define MAC_REG_BCNDMAPTR   0x90        //
 135 #define MAC_REG_RXDMACTL0   0x94        //
 136 #define MAC_REG_RXDMAPTR0   0x98        //
 137 #define MAC_REG_RXDMACTL1   0x9C        //
 138 #define MAC_REG_RXDMAPTR1   0xA0        //
 139 #define MAC_REG_SYNCDMACTL  0xA4        //
 140 #define MAC_REG_SYNCDMAPTR  0xA8
 141 #define MAC_REG_ATIMDMACTL  0xAC
 142 #define MAC_REG_ATIMDMAPTR  0xB0
 143 // MiscFF PIO related
 144 #define MAC_REG_MISCFFNDEX  0xB4
 145 #define MAC_REG_MISCFFCTL   0xB6
 146 #define MAC_REG_MISCFFDATA  0xB8
 147 // Extend SW Timer
 148 #define MAC_REG_TMDATA1     0xBC
 149 // WOW Related Group
 150 #define MAC_REG_WAKEUPEN0   0xC0
 151 #define MAC_REG_WAKEUPEN1   0xC1
 152 #define MAC_REG_WAKEUPSR0   0xC2
 153 #define MAC_REG_WAKEUPSR1   0xC3
 154 #define MAC_REG_WAKE128_0   0xC4
 155 #define MAC_REG_WAKE128_1   0xD4
 156 #define MAC_REG_WAKE128_2   0xE4
 157 #define MAC_REG_WAKE128_3   0xF4
 158
 159 /////////////// Page 1 ///////////////////
 160 #define MAC_REG_CRC_128_0   0x04
 161 #define MAC_REG_CRC_128_1   0x06
 162 #define MAC_REG_CRC_128_2   0x08
 163 #define MAC_REG_CRC_128_3   0x0A
 164 // MAC Configuration Group
 165 #define MAC_REG_PAR0        0x0C
 166 #define MAC_REG_PAR4        0x10
 167 #define MAC_REG_BSSID0      0x14
 168 #define MAC_REG_BSSID4      0x18
 169 #define MAC_REG_MAR0        0x1C
 170 #define MAC_REG_MAR4        0x20
 171 // MAC RSPPKT INFO Group
 172 #define MAC_REG_RSPINF_B_1  0x24
 173 #define MAC_REG_RSPINF_B_2  0x28
 174 #define MAC_REG_RSPINF_B_5  0x2C
 175 #define MAC_REG_RSPINF_B_11 0x30
 176 #define MAC_REG_RSPINF_A_6  0x34
 177 #define MAC_REG_RSPINF_A_9  0x36
 178 #define MAC_REG_RSPINF_A_12 0x38
 179 #define MAC_REG_RSPINF_A_18 0x3A
 180 #define MAC_REG_RSPINF_A_24 0x3C
 181 #define MAC_REG_RSPINF_A_36 0x3E
 182 #define MAC_REG_RSPINF_A_48 0x40
 183 #define MAC_REG_RSPINF_A_54 0x42
 184 #define MAC_REG_RSPINF_A_72 0x44
 185
 186 // 802.11h relative
 187 #define MAC_REG_QUIETINIT   0x60
 188 #define MAC_REG_QUIETGAP    0x62
 189 #define MAC_REG_QUIETDUR    0x64
 190 #define MAC_REG_MSRCTL      0x66
 191 #define MAC_REG_MSRBBSTS    0x67
 192 #define MAC_REG_MSRSTART    0x68
 193 #define MAC_REG_MSRDURATION 0x70
 194 #define MAC_REG_CCAFRACTION 0x72
 195 #define MAC_REG_PWRCCK      0x73
 196 #define MAC_REG_PWROFDM     0x7C
 197
 198 //
 199 // Bits in the BCFG0 register
 200 //
 201 #define BCFG0_PERROFF       0x40
 202 #define BCFG0_MRDMDIS       0x20
 203 #define BCFG0_MRDLDIS       0x10
 204 #define BCFG0_MWMEN         0x08
 205 #define BCFG0_VSERREN       0x02
 206 #define BCFG0_LATMEN        0x01
 207
 208 //
 209 // Bits in the BCFG1 register
 210 //
 211 #define BCFG1_CFUNOPT       0x80
 212 #define BCFG1_CREQOPT       0x40
 213 #define BCFG1_DMA8          0x10
 214 #define BCFG1_ARBITOPT      0x08
 215 #define BCFG1_PCIMEN        0x04
 216 #define BCFG1_MIOEN         0x02
 217 #define BCFG1_CISDLYEN      0x01
 218
 219 // Bits in RAMBIST registers
 220 #define BISTCMD_TSTPAT5     0x00        //
 221 #define BISTCMD_TSTPATA     0x80        //
 222 #define BISTCMD_TSTERR      0x20        //
 223 #define BISTCMD_TSTPATF     0x18        //
 224 #define BISTCMD_TSTPAT0     0x10        //
 225 #define BISTCMD_TSTMODE     0x04        //
 226 #define BISTCMD_TSTITTX     0x03        //
 227 #define BISTCMD_TSTATRX     0x02        //
 228 #define BISTCMD_TSTATTX     0x01        //
 229 #define BISTCMD_TSTRX       0x00        //
 230 #define BISTSR0_BISTGO      0x01        //
 231 #define BISTSR1_TSTSR       0x01        //
 232 #define BISTSR2_CMDPRTEN    0x02        //
 233 #define BISTSR2_RAMTSTEN    0x01        //
 234
 235 //
 236 // Bits in the I2MCFG EEPROM register
 237 //
 238 #define I2MCFG_BOUNDCTL     0x80
 239 #define I2MCFG_WAITCTL      0x20
 240 #define I2MCFG_SCLOECTL     0x10
 241 #define I2MCFG_WBUSYCTL     0x08
 242 #define I2MCFG_NORETRY      0x04
 243 #define I2MCFG_I2MLDSEQ     0x02
 244 #define I2MCFG_I2CMFAST     0x01
 245
 246 //
 247 // Bits in the I2MCSR EEPROM register
 248 //
 249 #define I2MCSR_EEMW         0x80
 250 #define I2MCSR_EEMR         0x40
 251 #define I2MCSR_AUTOLD       0x08
 252 #define I2MCSR_NACK         0x02
 253 #define I2MCSR_DONE         0x01
 254
 255 //
 256 // Bits in the PMC1 register
 257 //
 258 #define SPS_RST             0x80
 259 #define PCISTIKY            0x40
 260 #define PME_OVR             0x02
 261
 262 //
 263 // Bits in the STICKYHW register
 264 //
 265 #define STICKHW_DS1_SHADOW  0x02
 266 #define STICKHW_DS0_SHADOW  0x01
 267
 268 //
 269 // Bits in the TMCTL register
 270 //
 271 #define TMCTL_TSUSP         0x04
 272 #define TMCTL_TMD           0x02
 273 #define TMCTL_TE            0x01
 274
 275 //
 276 // Bits in the TFTCTL register
 277 //
 278 #define TFTCTL_HWUTSF       0x80        //
 279 #define TFTCTL_TBTTSYNC     0x40
 280 #define TFTCTL_HWUTSFEN     0x20
 281 #define TFTCTL_TSFCNTRRD    0x10        //
 282 #define TFTCTL_TBTTSYNCEN   0x08        //
 283 #define TFTCTL_TSFSYNCEN    0x04        //
 284 #define TFTCTL_TSFCNTRST    0x02        //
 285 #define TFTCTL_TSFCNTREN    0x01        //
 286
 287 //
 288 // Bits in the EnhanceCFG register
 289 //
 290 #define EnCFG_BarkerPream   0x00020000
 291 #define EnCFG_NXTBTTCFPSTR  0x00010000
 292 #define EnCFG_BcnSusClr     0x00000200
 293 #define EnCFG_BcnSusInd     0x00000100
 294 #define EnCFG_CFP_ProtectEn 0x00000040
 295 #define EnCFG_ProtectMd     0x00000020
 296 #define EnCFG_HwParCFP      0x00000010
 297 #define EnCFG_CFNULRSP      0x00000004
 298 #define EnCFG_BBType_MASK   0x00000003
 299 #define EnCFG_BBType_g      0x00000002
 300 #define EnCFG_BBType_b      0x00000001
 301 #define EnCFG_BBType_a      0x00000000
 302
 303 //
 304 // Bits in the Page1Sel register
 305 //
 306 #define PAGE1_SEL           0x01
 307
 308 //
 309 // Bits in the CFG register
 310 //
 311 #define CFG_TKIPOPT         0x80
 312 #define CFG_RXDMAOPT        0x40
 313 #define CFG_TMOT_SW         0x20
 314 #define CFG_TMOT_HWLONG     0x10
 315 #define CFG_TMOT_HW         0x00
 316 #define CFG_CFPENDOPT       0x08
 317 #define CFG_BCNSUSEN        0x04
 318 #define CFG_NOTXTIMEOUT     0x02
 319 #define CFG_NOBUFOPT        0x01
 320
 321 //
 322 // Bits in the TEST register
 323 //
 324 #define TEST_LBEXT          0x80        //
 325 #define TEST_LBINT          0x40        //
 326 #define TEST_LBNONE         0x00        //
 327 #define TEST_SOFTINT        0x20        //
 328 #define TEST_CONTTX         0x10        //
 329 #define TEST_TXPE           0x08        //
 330 #define TEST_NAVDIS         0x04        //
 331 #define TEST_NOCTS          0x02        //
 332 #define TEST_NOACK          0x01        //
 333
 334 //
 335 // Bits in the HOSTCR register
 336 //
 337 #define HOSTCR_TXONST       0x80        //
 338 #define HOSTCR_RXONST       0x40        //
 339 #define HOSTCR_ADHOC        0x20        // Network Type 1 = Ad-hoc
 340 #define HOSTCR_AP           0x10        // Port Type 1 = AP
 341 #define HOSTCR_TXON         0x08        //0000 1000
 342 #define HOSTCR_RXON         0x04        //0000 0100
 343 #define HOSTCR_MACEN        0x02        //0000 0010
 344 #define HOSTCR_SOFTRST      0x01        //0000 0001
 345
 346 //
 347 // Bits in the MACCR register
 348 //
 349 #define MACCR_SYNCFLUSHOK   0x04        //
 350 #define MACCR_SYNCFLUSH     0x02        //
 351 #define MACCR_CLRNAV        0x01        //
 352
 353 // Bits in the MAC_REG_GPIOCTL0 register
 354 //
 355 #define LED_ACTSET           0x01        //
 356 #define LED_RFOFF            0x02        //
 357 #define LED_NOCONNECT        0x04        //
 358 //
 359 // Bits in the RCR register
 360 //
 361 #define RCR_SSID            0x80
 362 #define RCR_RXALLTYPE       0x40        //
 363 #define RCR_UNICAST         0x20        //
 364 #define RCR_BROADCAST       0x10        //
 365 #define RCR_MULTICAST       0x08        //
 366 #define RCR_WPAERR          0x04        //
 367 #define RCR_ERRCRC          0x02        //
 368 #define RCR_BSSID           0x01        //
 369
 370 //
 371 // Bits in the TCR register
 372 //
 373 #define TCR_SYNCDCFOPT      0x02        //
 374 #define TCR_AUTOBCNTX       0x01        // Beacon automatically transmit enable
 375
 376 //
 377 // Bits in the IMR register
 378 //
 379 #define IMR_MEASURESTART    0x80000000      //
 380 #define IMR_QUIETSTART      0x20000000      //
 381 #define IMR_RADARDETECT     0x10000000      //
 382 #define IMR_MEASUREEND      0x08000000      //
 383 #define IMR_SOFTTIMER1      0x00200000      //
 384 #define IMR_RXDMA1          0x00001000      //0000 0000 0001 0000 0000 0000
 385 #define IMR_RXNOBUF         0x00000800      //
 386 #define IMR_MIBNEARFULL     0x00000400      //
 387 #define IMR_SOFTINT         0x00000200      //
 388 #define IMR_FETALERR        0x00000100      //
 389 #define IMR_WATCHDOG        0x00000080      //
 390 #define IMR_SOFTTIMER       0x00000040      //
 391 #define IMR_GPIO            0x00000020      //
 392 #define IMR_TBTT            0x00000010      //
 393 #define IMR_RXDMA0          0x00000008      //
 394 #define IMR_BNTX            0x00000004      //
 395 #define IMR_AC0DMA          0x00000002      //
 396 #define IMR_TXDMA0          0x00000001      //
 397
 398 //
 399 // Bits in the ISR register
 400 //
 401
 402 #define ISR_MEASURESTART    0x80000000      //
 403 #define ISR_QUIETSTART      0x20000000      //
 404 #define ISR_RADARDETECT     0x10000000      //
 405 #define ISR_MEASUREEND      0x08000000      //
 406 #define ISR_SOFTTIMER1      0x00200000      //
 407 #define ISR_RXDMA1          0x00001000      //0000 0000 0001 0000 0000 0000
 408 #define ISR_RXNOBUF         0x00000800      //0000 0000 0000 1000 0000 0000
 409 #define ISR_MIBNEARFULL     0x00000400      //0000 0000 0000 0100 0000 0000
 410 #define ISR_SOFTINT         0x00000200      //
 411 #define ISR_FETALERR        0x00000100      //
 412 #define ISR_WATCHDOG        0x00000080      //
 413 #define ISR_SOFTTIMER       0x00000040      //
 414 #define ISR_GPIO            0x00000020      //
 415 #define ISR_TBTT            0x00000010      //
 416 #define ISR_RXDMA0          0x00000008      //
 417 #define ISR_BNTX            0x00000004      //
 418 #define ISR_AC0DMA          0x00000002      //
 419 #define ISR_TXDMA0          0x00000001      //
 420
 421 //
 422 // Bits in the PSCFG register
 423 //
 424 #define PSCFG_PHILIPMD      0x40        //
 425 #define PSCFG_WAKECALEN     0x20        //
 426 #define PSCFG_WAKETMREN     0x10        //
 427 #define PSCFG_BBPSPROG      0x08        //
 428 #define PSCFG_WAKESYN       0x04        //
 429 #define PSCFG_SLEEPSYN      0x02        //
 430 #define PSCFG_AUTOSLEEP     0x01        //
 431
 432 //
 433 // Bits in the PSCTL register
 434 //
 435 #define PSCTL_WAKEDONE      0x20        //
 436 #define PSCTL_PS            0x10        //
 437 #define PSCTL_GO2DOZE       0x08        //
 438 #define PSCTL_LNBCN         0x04        //
 439 #define PSCTL_ALBCN         0x02        //
 440 #define PSCTL_PSEN          0x01        //
 441
 442 //
 443 // Bits in the PSPWSIG register
 444 //
 445 #define PSSIG_WPE3          0x80        //
 446 #define PSSIG_WPE2          0x40        //
 447 #define PSSIG_WPE1          0x20        //
 448 #define PSSIG_WRADIOPE      0x10        //
 449 #define PSSIG_SPE3          0x08        //
 450 #define PSSIG_SPE2          0x04        //
 451 #define PSSIG_SPE1          0x02        //
 452 #define PSSIG_SRADIOPE      0x01        //
 453
 454 //
 455 // Bits in the BBREGCTL register
 456 //
 457 #define BBREGCTL_DONE       0x04        //
 458 #define BBREGCTL_REGR       0x02        //
 459 #define BBREGCTL_REGW       0x01        //
 460
 461 //
 462 // Bits in the IFREGCTL register
 463 //
 464 #define IFREGCTL_DONE       0x04        //
 465 #define IFREGCTL_IFRF       0x02        //
 466 #define IFREGCTL_REGW       0x01        //
 467
 468 //
 469 // Bits in the SOFTPWRCTL register
 470 //
 471 #define SOFTPWRCTL_RFLEOPT      0x0800  //
 472 #define SOFTPWRCTL_TXPEINV      0x0200  //
 473 #define SOFTPWRCTL_SWPECTI      0x0100  //
 474 #define SOFTPWRCTL_SWPAPE       0x0020  //
 475 #define SOFTPWRCTL_SWCALEN      0x0010  //
 476 #define SOFTPWRCTL_SWRADIO_PE   0x0008  //
 477 #define SOFTPWRCTL_SWPE2        0x0004  //
 478 #define SOFTPWRCTL_SWPE1        0x0002  //
 479 #define SOFTPWRCTL_SWPE3        0x0001  //
 480
 481 //
 482 // Bits in the GPIOCTL1 register
 483 //
 484 #define GPIO1_DATA1             0x20    //
 485 #define GPIO1_MD1               0x10    //
 486 #define GPIO1_DATA0             0x02    //
 487 #define GPIO1_MD0               0x01    //
 488
 489 //
 490 // Bits in the DMACTL register
 491 //
 492 #define DMACTL_CLRRUN       0x00080000  //
 493 #define DMACTL_RUN          0x00000008  //
 494 #define DMACTL_WAKE         0x00000004  //
 495 #define DMACTL_DEAD         0x00000002  //
 496 #define DMACTL_ACTIVE       0x00000001  //
 497 //
 498 // Bits in the RXDMACTL0 register
 499 //
 500 #define RX_PERPKT           0x00000100  //
 501 #define RX_PERPKTCLR        0x01000000  //
 502 //
 503 // Bits in the BCNDMACTL register
 504 //
 505 #define BEACON_READY        0x01        //
 506 //
 507 // Bits in the MISCFFCTL register
 508 //
 509 #define MISCFFCTL_WRITE     0x0001      //
 510
 511 //
 512 // Bits in WAKEUPEN0
 513 //
 514 #define WAKEUPEN0_DIRPKT    0x10
 515 #define WAKEUPEN0_LINKOFF   0x08
 516 #define WAKEUPEN0_ATIMEN    0x04
 517 #define WAKEUPEN0_TIMEN     0x02
 518 #define WAKEUPEN0_MAGICEN   0x01
 519
 520 //
 521 // Bits in WAKEUPEN1
 522 //
 523 #define WAKEUPEN1_128_3     0x08
 524 #define WAKEUPEN1_128_2     0x04
 525 #define WAKEUPEN1_128_1     0x02
 526 #define WAKEUPEN1_128_0     0x01
 527
 528 //
 529 // Bits in WAKEUPSR0
 530 //
 531 #define WAKEUPSR0_DIRPKT    0x10
 532 #define WAKEUPSR0_LINKOFF   0x08
 533 #define WAKEUPSR0_ATIMEN    0x04
 534 #define WAKEUPSR0_TIMEN     0x02
 535 #define WAKEUPSR0_MAGICEN   0x01
 536
 537 //
 538 // Bits in WAKEUPSR1
 539 //
 540 #define WAKEUPSR1_128_3     0x08
 541 #define WAKEUPSR1_128_2     0x04
 542 #define WAKEUPSR1_128_1     0x02
 543 #define WAKEUPSR1_128_0     0x01
 544
 545 //
 546 // Bits in the MAC_REG_GPIOCTL register
 547 //
 548 #define GPIO0_MD            0x01        //
 549 #define GPIO0_DATA          0x02        //
 550 #define GPIO0_INTMD         0x04        //
 551 #define GPIO1_MD            0x10        //
 552 #define GPIO1_DATA          0x20        //
 553
 554 //
 555 // Bits in the MSRCTL register
 556 //
 557 #define MSRCTL_FINISH       0x80
 558 #define MSRCTL_READY        0x40
 559 #define MSRCTL_RADARDETECT  0x20
 560 #define MSRCTL_EN           0x10
 561 #define MSRCTL_QUIETTXCHK   0x08
 562 #define MSRCTL_QUIETRPT     0x04
 563 #define MSRCTL_QUIETINT     0x02
 564 #define MSRCTL_QUIETEN      0x01
 565 //
 566 // Bits in the MSRCTL1 register
 567 //
 568 #define MSRCTL1_TXPWR       0x08
 569 #define MSRCTL1_CSAPAREN    0x04
 570 #define MSRCTL1_TXPAUSE     0x01
 571
 572 // Loopback mode
 573 #define MAC_LB_EXT          0x02        //
 574 #define MAC_LB_INTERNAL     0x01        //
 575 #define MAC_LB_NONE         0x00        //
 576
 577 // Ethernet address filter type
 578 #define PKT_TYPE_NONE           0x00    // turn off receiver
 579 #define PKT_TYPE_ALL_MULTICAST  0x80
 580 #define PKT_TYPE_PROMISCUOUS    0x40
 581 #define PKT_TYPE_DIRECTED       0x20    // obsolete, directed address is always accepted
 582 #define PKT_TYPE_BROADCAST      0x10
 583 #define PKT_TYPE_MULTICAST      0x08
 584 #define PKT_TYPE_ERROR_WPA      0x04
 585 #define PKT_TYPE_ERROR_CRC      0x02
 586 #define PKT_TYPE_BSSID          0x01
 587
 588 #define Default_BI              0x200
 589
 590 // MiscFIFO Offset
 591 #define MISCFIFO_KEYETRY0       32
 592 #define MISCFIFO_KEYENTRYSIZE   22
 593 #define MISCFIFO_SYNINFO_IDX    10
 594 #define MISCFIFO_SYNDATA_IDX    11
 595 #define MISCFIFO_SYNDATASIZE    21
 596
 597 // enabled mask value of irq
 598 #define IMR_MASK_VALUE     (IMR_SOFTTIMER1 |    \
 599                             IMR_RXDMA1 |        \
 600                             IMR_RXNOBUF |       \
 601                             IMR_MIBNEARFULL |   \
 602                             IMR_SOFTINT |       \
 603                             IMR_FETALERR |      \
 604                             IMR_WATCHDOG |      \
 605                             IMR_SOFTTIMER |     \
 606                             IMR_GPIO |          \
 607                             IMR_TBTT |          \
 608                             IMR_RXDMA0 |        \
 609                             IMR_BNTX |          \
 610                             IMR_AC0DMA |        \
 611                             IMR_TXDMA0)
 612
 613 // max time out delay time
 614 #define W_MAX_TIMEOUT       0xFFF0U     //
 615
 616 // wait time within loop
 617 #define CB_DELAY_LOOP_WAIT  10          // 10ms
 618
 619 //
 620 // revision id
 621 //
 622 #define REV_ID_VT3253_A0    0x00
 623 #define REV_ID_VT3253_A1    0x01
 624 #define REV_ID_VT3253_B0    0x08
 625 #define REV_ID_VT3253_B1    0x09
 626
 627 /*---------------------  Export Types  ------------------------------*/
 628
 629 /*---------------------  Export Macros ------------------------------*/
 630
 631 #define MACvRegBitsOn(dwIoBase, byRegOfs, byBits)                       \
 632 do {                                                                    \
 633         unsigned char byData;                                           \
 634         VNSvInPortB(dwIoBase + byRegOfs, &byData);                      \
 635         VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits));           \
 636 } while (0)
 637
 638 #define MACvWordRegBitsOn(dwIoBase, byRegOfs, wBits)                    \
 639 do {                                                                    \
 640         unsigned short wData;                                           \
 641         VNSvInPortW(dwIoBase + byRegOfs, &wData);                       \
 642         VNSvOutPortW(dwIoBase + byRegOfs, wData | (wBits));             \
 643 } while (0)
 644
 645 #define MACvDWordRegBitsOn(dwIoBase, byRegOfs, dwBits)                  \
 646 do {                                                                    \
 647         unsigned long dwData;                                           \
 648         VNSvInPortD(dwIoBase + byRegOfs, &dwData);                      \
 649         VNSvOutPortD(dwIoBase + byRegOfs, dwData | (dwBits));           \
 650 } while (0)
 651
 652 #define MACvRegBitsOnEx(dwIoBase, byRegOfs, byMask, byBits)             \
 653 do {                                                                    \
 654         unsigned char byData;                                           \
 655         VNSvInPortB(dwIoBase + byRegOfs, &byData);                      \
 656         byData &= byMask;                                               \
 657         VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits));           \
 658 } while (0)
 659
 660 #define MACvRegBitsOff(dwIoBase, byRegOfs, byBits)                      \
 661 do {                                                                    \
 662         unsigned char byData;                                           \
 663         VNSvInPortB(dwIoBase + byRegOfs, &byData);                      \
 664         VNSvOutPortB(dwIoBase + byRegOfs, byData & ~(byBits));          \
 665 } while (0)
 666
 667 #define MACvWordRegBitsOff(dwIoBase, byRegOfs, wBits)                   \
 668 do {                                                                    \
 669         unsigned short wData;                                           \
 670         VNSvInPortW(dwIoBase + byRegOfs, &wData);                       \
 671         VNSvOutPortW(dwIoBase + byRegOfs, wData & ~(wBits));            \
 672 } while (0)
 673
 674 #define MACvDWordRegBitsOff(dwIoBase, byRegOfs, dwBits)                 \
 675 do {                                                                    \
 676         unsigned long dwData;                                           \
 677         VNSvInPortD(dwIoBase + byRegOfs, &dwData);                      \
 678         VNSvOutPortD(dwIoBase + byRegOfs, dwData & ~(dwBits));          \
 679 } while (0)
 680
 681 #define MACvGetCurrRx0DescAddr(dwIoBase, pdwCurrDescAddr)       \
 682         VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR0,               \
 683                     (unsigned long *)pdwCurrDescAddr)
 684
 685 #define MACvGetCurrRx1DescAddr(dwIoBase, pdwCurrDescAddr)       \
 686         VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR1,               \
 687                     (unsigned long *)pdwCurrDescAddr)
 688
 689 #define MACvGetCurrTx0DescAddr(dwIoBase, pdwCurrDescAddr)       \
 690         VNSvInPortD(dwIoBase + MAC_REG_TXDMAPTR0,               \
 691                     (unsigned long *)pdwCurrDescAddr)
 692
 693 #define MACvGetCurrAC0DescAddr(dwIoBase, pdwCurrDescAddr)       \
 694         VNSvInPortD(dwIoBase + MAC_REG_AC0DMAPTR,               \
 695                     (unsigned long *)pdwCurrDescAddr)
 696
 697 #define MACvGetCurrSyncDescAddr(dwIoBase, pdwCurrDescAddr)      \
 698         VNSvInPortD(dwIoBase + MAC_REG_SYNCDMAPTR,              \
 699                     (unsigned long *)pdwCurrDescAddr)
 700
 701 #define MACvGetCurrATIMDescAddr(dwIoBase, pdwCurrDescAddr)      \
 702         VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR,              \
 703                     (unsigned long *)pdwCurrDescAddr)
 704
 705 // set the chip with current BCN tx descriptor address
 706 #define MACvSetCurrBCNTxDescAddr(dwIoBase, dwCurrDescAddr)      \
 707         VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR,              \
 708                      dwCurrDescAddr)
 709
 710 // set the chip with current BCN length
 711 #define MACvSetCurrBCNLength(dwIoBase, wCurrBCNLength)          \
 712         VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2,            \
 713                      wCurrBCNLength)
 714
 715 #define MACvReadBSSIDAddress(dwIoBase, pbyEtherAddr)            \
 716 do {                                                            \
 717         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);           \
 718         VNSvInPortB(dwIoBase + MAC_REG_BSSID0,                  \
 719                     (unsigned char *)pbyEtherAddr);             \
 720         VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 1,              \
 721                     pbyEtherAddr + 1);                          \
 722         VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 2,              \
 723                     pbyEtherAddr + 2);                          \
 724         VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 3,              \
 725                     pbyEtherAddr + 3);                          \
 726         VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 4,              \
 727                     pbyEtherAddr + 4);                          \
 728         VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 5,              \
 729                     pbyEtherAddr + 5);                          \
 730         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);           \
 731 } while (0)
 732
 733 #define MACvWriteBSSIDAddress(dwIoBase, pbyEtherAddr)           \
 734 do {                                                            \
 735         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);           \
 736         VNSvOutPortB(dwIoBase + MAC_REG_BSSID0,                 \
 737                      *(pbyEtherAddr));                          \
 738         VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 1,             \
 739                      *(pbyEtherAddr + 1));                      \
 740         VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 2,             \
 741                      *(pbyEtherAddr + 2));                      \
 742         VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 3,             \
 743                      *(pbyEtherAddr + 3));                      \
 744         VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 4,             \
 745                      *(pbyEtherAddr + 4));                      \
 746         VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 5,             \
 747                      *(pbyEtherAddr + 5));                      \
 748         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);           \
 749 } while (0)
 750
 751 #define MACvReadEtherAddress(dwIoBase, pbyEtherAddr)            \
 752 do {                                                            \
 753         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);           \
 754         VNSvInPortB(dwIoBase + MAC_REG_PAR0,                    \
 755                     (unsigned char *)pbyEtherAddr);             \
 756         VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 1,                \
 757                     pbyEtherAddr + 1);                          \
 758         VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 2,                \
 759                     pbyEtherAddr + 2);                          \
 760         VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 3,                \
 761                     pbyEtherAddr + 3);                          \
 762         VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 4,                \
 763                     pbyEtherAddr + 4);                          \
 764         VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 5,                \
 765                     pbyEtherAddr + 5);                          \
 766         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);           \
 767 } while (0)
 768
 769 #define MACvWriteEtherAddress(dwIoBase, pbyEtherAddr)           \
 770 do {                                                            \
 771         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);           \
 772         VNSvOutPortB(dwIoBase + MAC_REG_PAR0,                   \
 773                      *pbyEtherAddr);                            \
 774         VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 1,               \
 775                      *(pbyEtherAddr + 1));                      \
 776         VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 2,               \
 777                      *(pbyEtherAddr + 2));                      \
 778         VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 3,               \
 779                      *(pbyEtherAddr + 3));                      \
 780         VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 4,               \
 781                      *(pbyEtherAddr + 4));                      \
 782         VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 5,               \
 783                      *(pbyEtherAddr + 5));                      \
 784         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);           \
 785 } while (0)
 786
 787 #define MACvClearISR(dwIoBase)                                          \
 788         VNSvOutPortD(dwIoBase + MAC_REG_ISR, IMR_MASK_VALUE)
 789
 790 #define MACvStart(dwIoBase)                                             \
 791         VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR,                         \
 792                      (HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON))
 793
 794 #define MACvRx0PerPktMode(dwIoBase)                                     \
 795         VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKT)
 796
 797 #define MACvRx0BufferFillMode(dwIoBase)                                 \
 798         VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKTCLR)
 799
 800 #define MACvRx1PerPktMode(dwIoBase)                                     \
 801         VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKT)
 802
 803 #define MACvRx1BufferFillMode(dwIoBase)                                 \
 804         VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKTCLR)
 805
 806 #define MACvRxOn(dwIoBase)                                              \
 807         MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON)
 808
 809 #define MACvReceive0(dwIoBase)                                          \
 810 do {                                                                    \
 811         unsigned long dwData;                                           \
 812         VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData);             \
 813         if (dwData & DMACTL_RUN)                                        \
 814                 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \
 815         else                                                            \
 816                 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); \
 817 } while (0)
 818
 819 #define MACvReceive1(dwIoBase)                                          \
 820 do {                                                                    \
 821         unsigned long dwData;                                           \
 822         VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData);             \
 823         if (dwData & DMACTL_RUN)                                        \
 824                 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \
 825         else                                                            \
 826                 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); \
 827 } while (0)
 828
 829 #define MACvTxOn(dwIoBase)                                              \
 830         MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON)
 831
 832 #define MACvTransmit0(dwIoBase)                                         \
 833 do {                                                                    \
 834         unsigned long dwData;                                           \
 835         VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData);             \
 836         if (dwData & DMACTL_RUN)                                        \
 837                 VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \
 838         else                                                            \
 839                 VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); \
 840 } while (0)
 841
 842 #define MACvTransmitAC0(dwIoBase)                                       \
 843 do {                                                                    \
 844         unsigned long dwData;                                           \
 845         VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData);             \
 846         if (dwData & DMACTL_RUN)                                        \
 847                 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \
 848         else                                                            \
 849                 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); \
 850 } while (0)
 851
 852 #define MACvTransmitSYNC(dwIoBase)                                      \
 853 do {                                                                    \
 854         unsigned long dwData;                                           \
 855         VNSvInPortD(dwIoBase + MAC_REG_SYNCDMACTL, &dwData);            \
 856         if (dwData & DMACTL_RUN)                                        \
 857                 VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_WAKE); \
 858         else                                                            \
 859                 VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \
 860 } while (0)
 861
 862 #define MACvTransmitATIM(dwIoBase)                                      \
 863 do {                                                                    \
 864         unsigned long dwData;                                           \
 865         VNSvInPortD(dwIoBase + MAC_REG_ATIMDMACTL, &dwData);            \
 866         if (dwData & DMACTL_RUN)                                        \
 867                 VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_WAKE); \
 868         else                                                            \
 869                 VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \
 870 } while (0)
 871
 872 #define MACvTransmitBCN(dwIoBase)                                       \
 873         VNSvOutPortB(dwIoBase + MAC_REG_BCNDMACTL, BEACON_READY)
 874
 875 #define MACvClearStckDS(dwIoBase)                                       \
 876 do {                                                                    \
 877         unsigned char byOrgValue;                                       \
 878         VNSvInPortB(dwIoBase + MAC_REG_STICKHW, &byOrgValue);           \
 879         byOrgValue = byOrgValue & 0xFC;                                 \
 880         VNSvOutPortB(dwIoBase + MAC_REG_STICKHW, byOrgValue);           \
 881 } while (0)
 882
 883 #define MACvReadISR(dwIoBase, pdwValue)                         \
 884         VNSvInPortD(dwIoBase + MAC_REG_ISR, pdwValue)
 885
 886 #define MACvWriteISR(dwIoBase, dwValue)                         \
 887         VNSvOutPortD(dwIoBase + MAC_REG_ISR, dwValue)
 888
 889 #define MACvIntEnable(dwIoBase, dwMask)                         \
 890         VNSvOutPortD(dwIoBase + MAC_REG_IMR, dwMask)
 891
 892 #define MACvIntDisable(dwIoBase)                                \
 893         VNSvOutPortD(dwIoBase + MAC_REG_IMR, 0)
 894
 895 #define MACvSelectPage0(dwIoBase)                               \
 896                 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0)
 897
 898 #define MACvSelectPage1(dwIoBase)                               \
 899         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1)
 900
 901 #define MACvReadMIBCounter(dwIoBase, pdwCounter)                        \
 902         VNSvInPortD(dwIoBase + MAC_REG_MIBCNTR , pdwCounter)
 903
 904 #define MACvPwrEvntDisable(dwIoBase)                                    \
 905         VNSvOutPortW(dwIoBase + MAC_REG_WAKEUPEN0, 0x0000)
 906
 907 #define MACvEnableProtectMD(dwIoBase)                                   \
 908 do {                                                                    \
 909         unsigned long dwOrgValue;                                       \
 910         VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue);            \
 911         dwOrgValue = dwOrgValue | EnCFG_ProtectMd;                      \
 912         VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);             \
 913 } while (0)
 914
 915 #define MACvDisableProtectMD(dwIoBase)                                  \
 916 do {                                                                    \
 917         unsigned long dwOrgValue;                                       \
 918         VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue);            \
 919         dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd;                     \
 920         VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);             \
 921 } while (0)
 922
 923 #define MACvEnableBarkerPreambleMd(dwIoBase)                            \
 924 do {                                                                    \
 925         unsigned long dwOrgValue;                                       \
 926         VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue);            \
 927         dwOrgValue = dwOrgValue | EnCFG_BarkerPream;                    \
 928         VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);             \
 929 } while (0)
 930
 931 #define MACvDisableBarkerPreambleMd(dwIoBase)                           \
 932 do {                                                                    \
 933         unsigned long dwOrgValue;                                       \
 934         VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue);            \
 935         dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream;                   \
 936         VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);             \
 937 } while (0)
 938
 939 #define MACvSetBBType(dwIoBase, byTyp)                                  \
 940 do {                                                                    \
 941         unsigned long dwOrgValue;                                       \
 942         VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue);            \
 943         dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK;                   \
 944         dwOrgValue = dwOrgValue | (unsigned long)byTyp;                 \
 945         VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue);             \
 946 } while (0)
 947
 948 #define MACvReadATIMW(dwIoBase, pwCounter)                              \
 949         VNSvInPortW(dwIoBase + MAC_REG_AIDATIM, pwCounter)
 950
 951 #define MACvWriteATIMW(dwIoBase, wCounter)                              \
 952         VNSvOutPortW(dwIoBase + MAC_REG_AIDATIM, wCounter)
 953
 954 #define MACvWriteCRC16_128(dwIoBase, byRegOfs, wCRC)            \
 955 do {                                                            \
 956         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1);           \
 957         VNSvOutPortW(dwIoBase + byRegOfs, wCRC);                \
 958         VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0);           \
 959 } while (0)
 960
 961 #define MACvGPIOIn(dwIoBase, pbyValue)                                  \
 962         VNSvInPortB(dwIoBase + MAC_REG_GPIOCTL1, pbyValue)
 963
 964 #define MACvSetRFLE_LatchBase(dwIoBase)                                 \
 965         MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT)
 966
 967 /*---------------------  Export Classes  ----------------------------*/
 968
 969 /*---------------------  Export Variables  --------------------------*/
 970
 971 /*---------------------  Export Functions  --------------------------*/
 972
 973 extern unsigned short TxRate_iwconfig;//2008-5-8 <add> by chester
 974 void MACvReadAllRegs(void __iomem *dwIoBase, unsigned char *pbyMacRegs);
 975
 976 bool MACbIsRegBitsOn(void __iomem *dwIoBase, unsigned char byRegOfs, unsigned char byTestBits);
 977 bool MACbIsRegBitsOff(void __iomem *dwIoBase, unsigned char byRegOfs, unsigned char byTestBits);
 978
 979 bool MACbIsIntDisable(void __iomem *dwIoBase);
 980
 981 unsigned char MACbyReadMultiAddr(void __iomem *dwIoBase, unsigned int uByteIdx);
 982 void MACvWriteMultiAddr(void __iomem *dwIoBase, unsigned int uByteIdx, unsigned char byData);
 983 void MACvSetMultiAddrByHash(void __iomem *dwIoBase, unsigned char byHashIdx);
 984 void MACvResetMultiAddrByHash(void __iomem *dwIoBase, unsigned char byHashIdx);
 985
 986 void MACvSetRxThreshold(void __iomem *dwIoBase, unsigned char byThreshold);
 987 void MACvGetRxThreshold(void __iomem *dwIoBase, unsigned char *pbyThreshold);
 988
 989 void MACvSetTxThreshold(void __iomem *dwIoBase, unsigned char byThreshold);
 990 void MACvGetTxThreshold(void __iomem *dwIoBase, unsigned char *pbyThreshold);
 991
 992 void MACvSetDmaLength(void __iomem *dwIoBase, unsigned char byDmaLength);
 993 void MACvGetDmaLength(void __iomem *dwIoBase, unsigned char *pbyDmaLength);
 994
 995 void MACvSetShortRetryLimit(void __iomem *dwIoBase, unsigned char byRetryLimit);
 996 void MACvGetShortRetryLimit(void __iomem *dwIoBase, unsigned char *pbyRetryLimit);
 997
 998 void MACvSetLongRetryLimit(void __iomem *dwIoBase, unsigned char byRetryLimit);
 999 void MACvGetLongRetryLimit(void __iomem *dwIoBase, unsigned char *pbyRetryLimit);
1000
1001 void MACvSetLoopbackMode(void __iomem *dwIoBase, unsigned char byLoopbackMode);
1002 bool MACbIsInLoopbackMode(void __iomem *dwIoBase);
1003
1004 void MACvSetPacketFilter(void __iomem *dwIoBase, unsigned short wFilterType);
1005
1006 void MACvSaveContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf);
1007 void MACvRestoreContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf);
1008 bool MACbCompareContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf);
1009
1010 bool MACbSoftwareReset(void __iomem *dwIoBase);
1011 bool MACbSafeSoftwareReset(void __iomem *dwIoBase);
1012 bool MACbSafeRxOff(void __iomem *dwIoBase);
1013 bool MACbSafeTxOff(void __iomem *dwIoBase);
1014 bool MACbSafeStop(void __iomem *dwIoBase);
1015 bool MACbShutdown(void __iomem *dwIoBase);
1016 void MACvInitialize(void __iomem *dwIoBase);
1017 void MACvSetCurrRx0DescAddr(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
1018 void MACvSetCurrRx1DescAddr(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
1019 void MACvSetCurrTXDescAddr(int iTxType, void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
1020 void MACvSetCurrTx0DescAddrEx(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
1021 void MACvSetCurrAC0DescAddrEx(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
1022 void MACvSetCurrSyncDescAddrEx(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
1023 void MACvSetCurrATIMDescAddrEx(void __iomem *dwIoBase, unsigned long dwCurrDescAddr);
1024 void MACvTimer0MicroSDelay(void __iomem *dwIoBase, unsigned int uDelay);
1025 void MACvOneShotTimer0MicroSec(void __iomem *dwIoBase, unsigned int uDelayTime);
1026 void MACvOneShotTimer1MicroSec(void __iomem *dwIoBase, unsigned int uDelayTime);
1027
1028 void MACvSetMISCFifo(void __iomem *dwIoBase, unsigned short wOffset, unsigned long dwData);
1029
1030 bool MACbTxDMAOff(void __iomem *dwIoBase, unsigned int idx);
1031
1032 void MACvClearBusSusInd(void __iomem *dwIoBase);
1033 void MACvEnableBusSusEn(void __iomem *dwIoBase);
1034
1035 bool MACbFlushSYNCFifo(void __iomem *dwIoBase);
1036 bool MACbPSWakeup(void __iomem *dwIoBase);
1037
1038 void MACvSetKeyEntry(void __iomem *dwIoBase, unsigned short wKeyCtl, unsigned int uEntryIdx,
1039                      unsigned int uKeyIdx, unsigned char *pbyAddr, u32 *pdwKey, unsigned char byLocalID);
1040 void MACvDisableKeyEntry(void __iomem *dwIoBase, unsigned int uEntryIdx);
1041 void MACvSetDefaultKeyEntry(void __iomem *dwIoBase, unsigned int uKeyLen,
1042                             unsigned int uKeyIdx, unsigned long *pdwKey, unsigned char byLocalID);
1043 void MACvDisableDefaultKey(void __iomem *dwIoBase);
1044 void MACvSetDefaultTKIPKeyEntry(void __iomem *dwIoBase, unsigned int uKeyLen,
1045                                 unsigned int uKeyIdx, unsigned long *pdwKey, unsigned char byLocalID);
1046 void MACvSetDefaultKeyCtl(void __iomem *dwIoBase, unsigned short wKeyCtl, unsigned int uEntryIdx, unsigned char byLocalID);
1047
1048 #endif // __MAC_H__