Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[cascardo/linux.git] / drivers / thermal / tegra / tegra210-soctherm.c
1 /*
2  * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This software is licensed under the terms of the GNU General Public
5  * License version 2, as published by the Free Software Foundation, and
6  * may be copied, distributed, and modified under those terms.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  */
14
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <soc/tegra/fuse.h>
18
19 #include <dt-bindings/thermal/tegra124-soctherm.h>
20
21 #include "soctherm.h"
22
23 #define TEGRA210_THERMTRIP_ANY_EN_MASK          (0x1 << 31)
24 #define TEGRA210_THERMTRIP_MEM_EN_MASK          (0x1 << 30)
25 #define TEGRA210_THERMTRIP_GPU_EN_MASK          (0x1 << 29)
26 #define TEGRA210_THERMTRIP_CPU_EN_MASK          (0x1 << 28)
27 #define TEGRA210_THERMTRIP_TSENSE_EN_MASK       (0x1 << 27)
28 #define TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK   (0x1ff << 18)
29 #define TEGRA210_THERMTRIP_CPU_THRESH_MASK      (0x1ff << 9)
30 #define TEGRA210_THERMTRIP_TSENSE_THRESH_MASK   0x1ff
31
32 #define TEGRA210_THRESH_GRAIN                   500
33
34 static const struct tegra_tsensor_configuration tegra210_tsensor_config = {
35         .tall = 16300,
36         .tiddq_en = 1,
37         .ten_count = 1,
38         .tsample = 120,
39         .tsample_ate = 480,
40 };
41
42 static const struct tegra_tsensor_group tegra210_tsensor_group_cpu = {
43         .id = TEGRA124_SOCTHERM_SENSOR_CPU,
44         .name = "cpu",
45         .sensor_temp_offset = SENSOR_TEMP1,
46         .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
47         .pdiv = 8,
48         .pdiv_ate = 8,
49         .pdiv_mask = SENSOR_PDIV_CPU_MASK,
50         .pllx_hotspot_diff = 10,
51         .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
52         .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
53         .thermtrip_enable_mask = TEGRA210_THERMTRIP_CPU_EN_MASK,
54         .thermtrip_threshold_mask = TEGRA210_THERMTRIP_CPU_THRESH_MASK,
55 };
56
57 static const struct tegra_tsensor_group tegra210_tsensor_group_gpu = {
58         .id = TEGRA124_SOCTHERM_SENSOR_GPU,
59         .name = "gpu",
60         .sensor_temp_offset = SENSOR_TEMP1,
61         .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
62         .pdiv = 8,
63         .pdiv_ate = 8,
64         .pdiv_mask = SENSOR_PDIV_GPU_MASK,
65         .pllx_hotspot_diff = 5,
66         .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
67         .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
68         .thermtrip_enable_mask = TEGRA210_THERMTRIP_GPU_EN_MASK,
69         .thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK,
70 };
71
72 static const struct tegra_tsensor_group tegra210_tsensor_group_pll = {
73         .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
74         .name = "pll",
75         .sensor_temp_offset = SENSOR_TEMP2,
76         .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
77         .pdiv = 8,
78         .pdiv_ate = 8,
79         .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
80         .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
81         .thermtrip_enable_mask = TEGRA210_THERMTRIP_TSENSE_EN_MASK,
82         .thermtrip_threshold_mask = TEGRA210_THERMTRIP_TSENSE_THRESH_MASK,
83 };
84
85 static const struct tegra_tsensor_group tegra210_tsensor_group_mem = {
86         .id = TEGRA124_SOCTHERM_SENSOR_MEM,
87         .name = "mem",
88         .sensor_temp_offset = SENSOR_TEMP2,
89         .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
90         .pdiv = 8,
91         .pdiv_ate = 8,
92         .pdiv_mask = SENSOR_PDIV_MEM_MASK,
93         .pllx_hotspot_diff = 0,
94         .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
95         .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
96         .thermtrip_enable_mask = TEGRA210_THERMTRIP_MEM_EN_MASK,
97         .thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK,
98 };
99
100 static const struct tegra_tsensor_group *tegra210_tsensor_groups[] = {
101         &tegra210_tsensor_group_cpu,
102         &tegra210_tsensor_group_gpu,
103         &tegra210_tsensor_group_pll,
104         &tegra210_tsensor_group_mem,
105 };
106
107 static const struct tegra_tsensor tegra210_tsensors[] = {
108         {
109                 .name = "cpu0",
110                 .base = 0xc0,
111                 .config = &tegra210_tsensor_config,
112                 .calib_fuse_offset = 0x098,
113                 .fuse_corr_alpha = 1085000,
114                 .fuse_corr_beta = 3244200,
115                 .group = &tegra210_tsensor_group_cpu,
116         }, {
117                 .name = "cpu1",
118                 .base = 0xe0,
119                 .config = &tegra210_tsensor_config,
120                 .calib_fuse_offset = 0x084,
121                 .fuse_corr_alpha = 1126200,
122                 .fuse_corr_beta = -67500,
123                 .group = &tegra210_tsensor_group_cpu,
124         }, {
125                 .name = "cpu2",
126                 .base = 0x100,
127                 .config = &tegra210_tsensor_config,
128                 .calib_fuse_offset = 0x088,
129                 .fuse_corr_alpha = 1098400,
130                 .fuse_corr_beta = 2251100,
131                 .group = &tegra210_tsensor_group_cpu,
132         }, {
133                 .name = "cpu3",
134                 .base = 0x120,
135                 .config = &tegra210_tsensor_config,
136                 .calib_fuse_offset = 0x12c,
137                 .fuse_corr_alpha = 1108000,
138                 .fuse_corr_beta = 602700,
139                 .group = &tegra210_tsensor_group_cpu,
140         }, {
141                 .name = "mem0",
142                 .base = 0x140,
143                 .config = &tegra210_tsensor_config,
144                 .calib_fuse_offset = 0x158,
145                 .fuse_corr_alpha = 1069200,
146                 .fuse_corr_beta = 3549900,
147                 .group = &tegra210_tsensor_group_mem,
148         }, {
149                 .name = "mem1",
150                 .base = 0x160,
151                 .config = &tegra210_tsensor_config,
152                 .calib_fuse_offset = 0x15c,
153                 .fuse_corr_alpha = 1173700,
154                 .fuse_corr_beta = -6263600,
155                 .group = &tegra210_tsensor_group_mem,
156         }, {
157                 .name = "gpu",
158                 .base = 0x180,
159                 .config = &tegra210_tsensor_config,
160                 .calib_fuse_offset = 0x154,
161                 .fuse_corr_alpha = 1074300,
162                 .fuse_corr_beta = 2734900,
163                 .group = &tegra210_tsensor_group_gpu,
164         }, {
165                 .name = "pllx",
166                 .base = 0x1a0,
167                 .config = &tegra210_tsensor_config,
168                 .calib_fuse_offset = 0x160,
169                 .fuse_corr_alpha = 1039700,
170                 .fuse_corr_beta = 6829100,
171                 .group = &tegra210_tsensor_group_pll,
172         },
173 };
174
175 /*
176  * Mask/shift bits in FUSE_TSENSOR_COMMON and
177  * FUSE_TSENSOR_COMMON, which are described in
178  * tegra_soctherm_fuse.c
179  */
180 static const struct tegra_soctherm_fuse tegra210_soctherm_fuse = {
181         .fuse_base_cp_mask = 0x3ff << 11,
182         .fuse_base_cp_shift = 11,
183         .fuse_base_ft_mask = 0x7ff << 21,
184         .fuse_base_ft_shift = 21,
185         .fuse_shift_ft_mask = 0x1f << 6,
186         .fuse_shift_ft_shift = 6,
187         .fuse_spare_realignment = 0,
188 };
189
190 const struct tegra_soctherm_soc tegra210_soctherm = {
191         .tsensors = tegra210_tsensors,
192         .num_tsensors = ARRAY_SIZE(tegra210_tsensors),
193         .ttgs = tegra210_tsensor_groups,
194         .num_ttgs = ARRAY_SIZE(tegra210_tsensor_groups),
195         .tfuse = &tegra210_soctherm_fuse,
196         .thresh_grain = TEGRA210_THRESH_GRAIN,
197 };