2 * Driver for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * A note about mapbase / membase
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
42 #include <linux/sunserialcore.h>
52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59 static struct uart_driver serial8250_reg;
61 static int serial_index(struct uart_port *port)
63 return (serial8250_reg.minor - 64) + port->line;
66 static unsigned int skip_txen_test; /* force skip of txen test at init time */
72 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
74 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
78 #define DEBUG_INTR(fmt...) printk(fmt)
80 #define DEBUG_INTR(fmt...) do { } while (0)
83 #define PASS_LIMIT 512
85 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
88 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89 #define CONFIG_SERIAL_DETECT_IRQ 1
91 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
92 #define CONFIG_SERIAL_MANY_PORTS 1
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
101 #include <asm/serial.h>
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
107 #ifndef SERIAL_PORT_DFNS
108 #define SERIAL_PORT_DFNS
111 static const struct old_serial_port old_serial_port[] = {
112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
115 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
117 #ifdef CONFIG_SERIAL_8250_RSA
119 #define PORT_RSA_MAX 4
120 static unsigned long probe_rsa[PORT_RSA_MAX];
121 static unsigned int probe_rsa_count;
122 #endif /* CONFIG_SERIAL_8250_RSA */
125 struct hlist_node node;
127 spinlock_t lock; /* Protects list not the hash */
128 struct list_head *head;
131 #define NR_IRQ_HASH 32 /* Can be adjusted later */
132 static struct hlist_head irq_lists[NR_IRQ_HASH];
133 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
136 * Here we define the default xmit fifo size used for each type of UART.
138 static const struct serial8250_config uart_config[] = {
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
199 .name = "16C950/954",
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
247 .flags = UART_CAP_FIFO,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_CAP_AFE,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
276 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
283 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
290 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
292 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
299 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
300 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
301 .flags = UART_CAP_FIFO,
308 /* Uart divisor latch read */
309 static int default_serial_dl_read(struct uart_8250_port *up)
311 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
314 /* Uart divisor latch write */
315 static void default_serial_dl_write(struct uart_8250_port *up, int value)
317 serial_out(up, UART_DLL, value & 0xff);
318 serial_out(up, UART_DLM, value >> 8 & 0xff);
321 #ifdef CONFIG_MIPS_ALCHEMY
323 /* Au1x00 UART hardware has a weird register layout */
324 static const u8 au_io_in_map[] = {
334 static const u8 au_io_out_map[] = {
342 static unsigned int au_serial_in(struct uart_port *p, int offset)
344 offset = au_io_in_map[offset] << p->regshift;
345 return __raw_readl(p->membase + offset);
348 static void au_serial_out(struct uart_port *p, int offset, int value)
350 offset = au_io_out_map[offset] << p->regshift;
351 __raw_writel(value, p->membase + offset);
354 /* Au1x00 haven't got a standard divisor latch */
355 static int au_serial_dl_read(struct uart_8250_port *up)
357 return __raw_readl(up->port.membase + 0x28);
360 static void au_serial_dl_write(struct uart_8250_port *up, int value)
362 __raw_writel(value, up->port.membase + 0x28);
367 #ifdef CONFIG_SERIAL_8250_RM9K
391 static unsigned int rm9k_serial_in(struct uart_port *p, int offset)
393 offset = regmap_in[offset] << p->regshift;
394 return readl(p->membase + offset);
397 static void rm9k_serial_out(struct uart_port *p, int offset, int value)
399 offset = regmap_out[offset] << p->regshift;
400 writel(value, p->membase + offset);
403 static int rm9k_serial_dl_read(struct uart_8250_port *up)
405 return ((__raw_readl(up->port.membase + 0x10) << 8) |
406 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff;
409 static void rm9k_serial_dl_write(struct uart_8250_port *up, int value)
411 __raw_writel(value, up->port.membase + 0x08);
412 __raw_writel(value >> 8, up->port.membase + 0x10);
417 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
419 offset = offset << p->regshift;
420 outb(p->hub6 - 1 + offset, p->iobase);
421 return inb(p->iobase + 1);
424 static void hub6_serial_out(struct uart_port *p, int offset, int value)
426 offset = offset << p->regshift;
427 outb(p->hub6 - 1 + offset, p->iobase);
428 outb(value, p->iobase + 1);
431 static unsigned int mem_serial_in(struct uart_port *p, int offset)
433 offset = offset << p->regshift;
434 return readb(p->membase + offset);
437 static void mem_serial_out(struct uart_port *p, int offset, int value)
439 offset = offset << p->regshift;
440 writeb(value, p->membase + offset);
443 static void mem32_serial_out(struct uart_port *p, int offset, int value)
445 offset = offset << p->regshift;
446 writel(value, p->membase + offset);
449 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
451 offset = offset << p->regshift;
452 return readl(p->membase + offset);
455 static unsigned int io_serial_in(struct uart_port *p, int offset)
457 offset = offset << p->regshift;
458 return inb(p->iobase + offset);
461 static void io_serial_out(struct uart_port *p, int offset, int value)
463 offset = offset << p->regshift;
464 outb(value, p->iobase + offset);
467 static int serial8250_default_handle_irq(struct uart_port *port);
468 static int exar_handle_irq(struct uart_port *port);
470 static void set_io_from_upio(struct uart_port *p)
472 struct uart_8250_port *up =
473 container_of(p, struct uart_8250_port, port);
475 up->dl_read = default_serial_dl_read;
476 up->dl_write = default_serial_dl_write;
480 p->serial_in = hub6_serial_in;
481 p->serial_out = hub6_serial_out;
485 p->serial_in = mem_serial_in;
486 p->serial_out = mem_serial_out;
490 p->serial_in = mem32_serial_in;
491 p->serial_out = mem32_serial_out;
494 #ifdef CONFIG_SERIAL_8250_RM9K
496 p->serial_in = rm9k_serial_in;
497 p->serial_out = rm9k_serial_out;
498 up->dl_read = rm9k_serial_dl_read;
499 up->dl_write = rm9k_serial_dl_write;
503 #ifdef CONFIG_MIPS_ALCHEMY
505 p->serial_in = au_serial_in;
506 p->serial_out = au_serial_out;
507 up->dl_read = au_serial_dl_read;
508 up->dl_write = au_serial_dl_write;
513 p->serial_in = io_serial_in;
514 p->serial_out = io_serial_out;
517 /* Remember loaded iotype */
518 up->cur_iotype = p->iotype;
519 p->handle_irq = serial8250_default_handle_irq;
523 serial_port_out_sync(struct uart_port *p, int offset, int value)
529 p->serial_out(p, offset, value);
530 p->serial_in(p, UART_LCR); /* safe, no side-effects */
533 p->serial_out(p, offset, value);
540 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
542 serial_out(up, UART_SCR, offset);
543 serial_out(up, UART_ICR, value);
546 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
550 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
551 serial_out(up, UART_SCR, offset);
552 value = serial_in(up, UART_ICR);
553 serial_icr_write(up, UART_ACR, up->acr);
561 static void serial8250_clear_fifos(struct uart_8250_port *p)
563 if (p->capabilities & UART_CAP_FIFO) {
564 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
565 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
566 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
567 serial_out(p, UART_FCR, 0);
571 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
575 serial8250_clear_fifos(p);
576 fcr = uart_config[p->port.type].fcr;
577 serial_out(p, UART_FCR, fcr);
579 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
582 * IER sleep support. UARTs which have EFRs need the "extended
583 * capability" bit enabled. Note that on XR16C850s, we need to
584 * reset LCR to write to IER.
586 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
589 * Exar UARTs have a SLEEP register that enables or disables
590 * each UART to enter sleep mode separately. On the XR17V35x the
591 * register is accessible to each UART at the UART_EXAR_SLEEP
592 * offset but the UART channel may only write to the corresponding
595 if ((p->port.type == PORT_XR17V35X) ||
596 (p->port.type == PORT_XR17D15X)) {
597 serial_out(p, UART_EXAR_SLEEP, 0xff);
601 if (p->capabilities & UART_CAP_SLEEP) {
602 if (p->capabilities & UART_CAP_EFR) {
603 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
604 serial_out(p, UART_EFR, UART_EFR_ECB);
605 serial_out(p, UART_LCR, 0);
607 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
608 if (p->capabilities & UART_CAP_EFR) {
609 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
610 serial_out(p, UART_EFR, 0);
611 serial_out(p, UART_LCR, 0);
616 #ifdef CONFIG_SERIAL_8250_RSA
618 * Attempts to turn on the RSA FIFO. Returns zero on failure.
619 * We set the port uart clock rate if we succeed.
621 static int __enable_rsa(struct uart_8250_port *up)
626 mode = serial_in(up, UART_RSA_MSR);
627 result = mode & UART_RSA_MSR_FIFO;
630 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
631 mode = serial_in(up, UART_RSA_MSR);
632 result = mode & UART_RSA_MSR_FIFO;
636 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
641 static void enable_rsa(struct uart_8250_port *up)
643 if (up->port.type == PORT_RSA) {
644 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
645 spin_lock_irq(&up->port.lock);
647 spin_unlock_irq(&up->port.lock);
649 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
650 serial_out(up, UART_RSA_FRR, 0);
655 * Attempts to turn off the RSA FIFO. Returns zero on failure.
656 * It is unknown why interrupts were disabled in here. However,
657 * the caller is expected to preserve this behaviour by grabbing
658 * the spinlock before calling this function.
660 static void disable_rsa(struct uart_8250_port *up)
665 if (up->port.type == PORT_RSA &&
666 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
667 spin_lock_irq(&up->port.lock);
669 mode = serial_in(up, UART_RSA_MSR);
670 result = !(mode & UART_RSA_MSR_FIFO);
673 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
674 mode = serial_in(up, UART_RSA_MSR);
675 result = !(mode & UART_RSA_MSR_FIFO);
679 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
680 spin_unlock_irq(&up->port.lock);
683 #endif /* CONFIG_SERIAL_8250_RSA */
686 * This is a quickie test to see how big the FIFO is.
687 * It doesn't work at all the time, more's the pity.
689 static int size_fifo(struct uart_8250_port *up)
691 unsigned char old_fcr, old_mcr, old_lcr;
692 unsigned short old_dl;
695 old_lcr = serial_in(up, UART_LCR);
696 serial_out(up, UART_LCR, 0);
697 old_fcr = serial_in(up, UART_FCR);
698 old_mcr = serial_in(up, UART_MCR);
699 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
700 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
701 serial_out(up, UART_MCR, UART_MCR_LOOP);
702 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
703 old_dl = serial_dl_read(up);
704 serial_dl_write(up, 0x0001);
705 serial_out(up, UART_LCR, 0x03);
706 for (count = 0; count < 256; count++)
707 serial_out(up, UART_TX, count);
708 mdelay(20);/* FIXME - schedule_timeout */
709 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
710 (count < 256); count++)
711 serial_in(up, UART_RX);
712 serial_out(up, UART_FCR, old_fcr);
713 serial_out(up, UART_MCR, old_mcr);
714 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
715 serial_dl_write(up, old_dl);
716 serial_out(up, UART_LCR, old_lcr);
722 * Read UART ID using the divisor method - set DLL and DLM to zero
723 * and the revision will be in DLL and device type in DLM. We
724 * preserve the device state across this.
726 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
728 unsigned char old_dll, old_dlm, old_lcr;
731 old_lcr = serial_in(p, UART_LCR);
732 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
734 old_dll = serial_in(p, UART_DLL);
735 old_dlm = serial_in(p, UART_DLM);
737 serial_out(p, UART_DLL, 0);
738 serial_out(p, UART_DLM, 0);
740 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
742 serial_out(p, UART_DLL, old_dll);
743 serial_out(p, UART_DLM, old_dlm);
744 serial_out(p, UART_LCR, old_lcr);
750 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
751 * When this function is called we know it is at least a StarTech
752 * 16650 V2, but it might be one of several StarTech UARTs, or one of
753 * its clones. (We treat the broken original StarTech 16650 V1 as a
754 * 16550, and why not? Startech doesn't seem to even acknowledge its
757 * What evil have men's minds wrought...
759 static void autoconfig_has_efr(struct uart_8250_port *up)
761 unsigned int id1, id2, id3, rev;
764 * Everything with an EFR has SLEEP
766 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
769 * First we check to see if it's an Oxford Semiconductor UART.
771 * If we have to do this here because some non-National
772 * Semiconductor clone chips lock up if you try writing to the
773 * LSR register (which serial_icr_read does)
777 * Check for Oxford Semiconductor 16C950.
779 * EFR [4] must be set else this test fails.
781 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
782 * claims that it's needed for 952 dual UART's (which are not
783 * recommended for new designs).
786 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
787 serial_out(up, UART_EFR, UART_EFR_ECB);
788 serial_out(up, UART_LCR, 0x00);
789 id1 = serial_icr_read(up, UART_ID1);
790 id2 = serial_icr_read(up, UART_ID2);
791 id3 = serial_icr_read(up, UART_ID3);
792 rev = serial_icr_read(up, UART_REV);
794 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
796 if (id1 == 0x16 && id2 == 0xC9 &&
797 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
798 up->port.type = PORT_16C950;
801 * Enable work around for the Oxford Semiconductor 952 rev B
802 * chip which causes it to seriously miscalculate baud rates
805 if (id3 == 0x52 && rev == 0x01)
806 up->bugs |= UART_BUG_QUOT;
811 * We check for a XR16C850 by setting DLL and DLM to 0, and then
812 * reading back DLL and DLM. The chip type depends on the DLM
814 * 0x10 - XR16C850 and the DLL contains the chip revision.
818 id1 = autoconfig_read_divisor_id(up);
819 DEBUG_AUTOCONF("850id=%04x ", id1);
822 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
823 up->port.type = PORT_16850;
828 * It wasn't an XR16C850.
830 * We distinguish between the '654 and the '650 by counting
831 * how many bytes are in the FIFO. I'm using this for now,
832 * since that's the technique that was sent to me in the
833 * serial driver update, but I'm not convinced this works.
834 * I've had problems doing this in the past. -TYT
836 if (size_fifo(up) == 64)
837 up->port.type = PORT_16654;
839 up->port.type = PORT_16650V2;
843 * We detected a chip without a FIFO. Only two fall into
844 * this category - the original 8250 and the 16450. The
845 * 16450 has a scratch register (accessible with LCR=0)
847 static void autoconfig_8250(struct uart_8250_port *up)
849 unsigned char scratch, status1, status2;
851 up->port.type = PORT_8250;
853 scratch = serial_in(up, UART_SCR);
854 serial_out(up, UART_SCR, 0xa5);
855 status1 = serial_in(up, UART_SCR);
856 serial_out(up, UART_SCR, 0x5a);
857 status2 = serial_in(up, UART_SCR);
858 serial_out(up, UART_SCR, scratch);
860 if (status1 == 0xa5 && status2 == 0x5a)
861 up->port.type = PORT_16450;
864 static int broken_efr(struct uart_8250_port *up)
867 * Exar ST16C2550 "A2" devices incorrectly detect as
868 * having an EFR, and report an ID of 0x0201. See
869 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
871 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
877 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
879 unsigned char status;
881 status = serial_in(up, 0x04); /* EXCR2 */
882 #define PRESL(x) ((x) & 0x30)
883 if (PRESL(status) == 0x10) {
884 /* already in high speed mode */
887 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
888 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
889 serial_out(up, 0x04, status);
895 * We know that the chip has FIFOs. Does it have an EFR? The
896 * EFR is located in the same register position as the IIR and
897 * we know the top two bits of the IIR are currently set. The
898 * EFR should contain zero. Try to read the EFR.
900 static void autoconfig_16550a(struct uart_8250_port *up)
902 unsigned char status1, status2;
903 unsigned int iersave;
905 up->port.type = PORT_16550A;
906 up->capabilities |= UART_CAP_FIFO;
909 * XR17V35x UARTs have an extra divisor register, DLD
910 * that gets enabled with when DLAB is set which will
911 * cause the device to incorrectly match and assign
912 * port type to PORT_16650. The EFR for this UART is
913 * found at offset 0x09. Instead check the Deice ID (DVID)
914 * register for a 2, 4 or 8 port UART.
916 if (up->port.flags & UPF_EXAR_EFR) {
917 status1 = serial_in(up, UART_EXAR_DVID);
918 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
919 DEBUG_AUTOCONF("Exar XR17V35x ");
920 up->port.type = PORT_XR17V35X;
921 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
930 * Check for presence of the EFR when DLAB is set.
931 * Only ST16C650V1 UARTs pass this test.
933 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
934 if (serial_in(up, UART_EFR) == 0) {
935 serial_out(up, UART_EFR, 0xA8);
936 if (serial_in(up, UART_EFR) != 0) {
937 DEBUG_AUTOCONF("EFRv1 ");
938 up->port.type = PORT_16650;
939 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
941 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
943 serial_out(up, UART_EFR, 0);
948 * Maybe it requires 0xbf to be written to the LCR.
949 * (other ST16C650V2 UARTs, TI16C752A, etc)
951 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
952 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
953 DEBUG_AUTOCONF("EFRv2 ");
954 autoconfig_has_efr(up);
959 * Check for a National Semiconductor SuperIO chip.
960 * Attempt to switch to bank 2, read the value of the LOOP bit
961 * from EXCR1. Switch back to bank 0, change it in MCR. Then
962 * switch back to bank 2, read it from EXCR1 again and check
963 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
965 serial_out(up, UART_LCR, 0);
966 status1 = serial_in(up, UART_MCR);
967 serial_out(up, UART_LCR, 0xE0);
968 status2 = serial_in(up, 0x02); /* EXCR1 */
970 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
971 serial_out(up, UART_LCR, 0);
972 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
973 serial_out(up, UART_LCR, 0xE0);
974 status2 = serial_in(up, 0x02); /* EXCR1 */
975 serial_out(up, UART_LCR, 0);
976 serial_out(up, UART_MCR, status1);
978 if ((status2 ^ status1) & UART_MCR_LOOP) {
981 serial_out(up, UART_LCR, 0xE0);
983 quot = serial_dl_read(up);
986 if (ns16550a_goto_highspeed(up))
987 serial_dl_write(up, quot);
989 serial_out(up, UART_LCR, 0);
991 up->port.uartclk = 921600*16;
992 up->port.type = PORT_NS16550A;
993 up->capabilities |= UART_NATSEMI;
999 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1000 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1001 * Try setting it with and without DLAB set. Cheap clones
1002 * set bit 5 without DLAB set.
1004 serial_out(up, UART_LCR, 0);
1005 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1006 status1 = serial_in(up, UART_IIR) >> 5;
1007 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1008 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1009 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1010 status2 = serial_in(up, UART_IIR) >> 5;
1011 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1012 serial_out(up, UART_LCR, 0);
1014 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1016 if (status1 == 6 && status2 == 7) {
1017 up->port.type = PORT_16750;
1018 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1023 * Try writing and reading the UART_IER_UUE bit (b6).
1024 * If it works, this is probably one of the Xscale platform's
1026 * We're going to explicitly set the UUE bit to 0 before
1027 * trying to write and read a 1 just to make sure it's not
1028 * already a 1 and maybe locked there before we even start start.
1030 iersave = serial_in(up, UART_IER);
1031 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1032 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1034 * OK it's in a known zero state, try writing and reading
1035 * without disturbing the current state of the other bits.
1037 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1038 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1041 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1043 DEBUG_AUTOCONF("Xscale ");
1044 up->port.type = PORT_XSCALE;
1045 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1050 * If we got here we couldn't force the IER_UUE bit to 0.
1051 * Log it and continue.
1053 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1055 serial_out(up, UART_IER, iersave);
1058 * Exar uarts have EFR in a weird location
1060 if (up->port.flags & UPF_EXAR_EFR) {
1061 DEBUG_AUTOCONF("Exar XR17D15x ");
1062 up->port.type = PORT_XR17D15X;
1063 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1070 * We distinguish between 16550A and U6 16550A by counting
1071 * how many bytes are in the FIFO.
1073 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1074 up->port.type = PORT_U6_16550A;
1075 up->capabilities |= UART_CAP_AFE;
1080 * This routine is called by rs_init() to initialize a specific serial
1081 * port. It determines what type of UART chip this serial port is
1082 * using: 8250, 16450, 16550, 16550A. The important question is
1083 * whether or not this UART is a 16550A or not, since this will
1084 * determine whether or not we can use its FIFO features or not.
1086 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1088 unsigned char status1, scratch, scratch2, scratch3;
1089 unsigned char save_lcr, save_mcr;
1090 struct uart_port *port = &up->port;
1091 unsigned long flags;
1092 unsigned int old_capabilities;
1094 if (!port->iobase && !port->mapbase && !port->membase)
1097 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1098 serial_index(port), port->iobase, port->membase);
1101 * We really do need global IRQs disabled here - we're going to
1102 * be frobbing the chips IRQ enable register to see if it exists.
1104 spin_lock_irqsave(&port->lock, flags);
1106 up->capabilities = 0;
1109 if (!(port->flags & UPF_BUGGY_UART)) {
1111 * Do a simple existence test first; if we fail this,
1112 * there's no point trying anything else.
1114 * 0x80 is used as a nonsense port to prevent against
1115 * false positives due to ISA bus float. The
1116 * assumption is that 0x80 is a non-existent port;
1117 * which should be safe since include/asm/io.h also
1118 * makes this assumption.
1120 * Note: this is safe as long as MCR bit 4 is clear
1121 * and the device is in "PC" mode.
1123 scratch = serial_in(up, UART_IER);
1124 serial_out(up, UART_IER, 0);
1129 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1130 * 16C754B) allow only to modify them if an EFR bit is set.
1132 scratch2 = serial_in(up, UART_IER) & 0x0f;
1133 serial_out(up, UART_IER, 0x0F);
1137 scratch3 = serial_in(up, UART_IER) & 0x0f;
1138 serial_out(up, UART_IER, scratch);
1139 if (scratch2 != 0 || scratch3 != 0x0F) {
1141 * We failed; there's nothing here
1143 spin_unlock_irqrestore(&port->lock, flags);
1144 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1145 scratch2, scratch3);
1150 save_mcr = serial_in(up, UART_MCR);
1151 save_lcr = serial_in(up, UART_LCR);
1154 * Check to see if a UART is really there. Certain broken
1155 * internal modems based on the Rockwell chipset fail this
1156 * test, because they apparently don't implement the loopback
1157 * test mode. So this test is skipped on the COM 1 through
1158 * COM 4 ports. This *should* be safe, since no board
1159 * manufacturer would be stupid enough to design a board
1160 * that conflicts with COM 1-4 --- we hope!
1162 if (!(port->flags & UPF_SKIP_TEST)) {
1163 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1164 status1 = serial_in(up, UART_MSR) & 0xF0;
1165 serial_out(up, UART_MCR, save_mcr);
1166 if (status1 != 0x90) {
1167 spin_unlock_irqrestore(&port->lock, flags);
1168 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1175 * We're pretty sure there's a port here. Lets find out what
1176 * type of port it is. The IIR top two bits allows us to find
1177 * out if it's 8250 or 16450, 16550, 16550A or later. This
1178 * determines what we test for next.
1180 * We also initialise the EFR (if any) to zero for later. The
1181 * EFR occupies the same register location as the FCR and IIR.
1183 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1184 serial_out(up, UART_EFR, 0);
1185 serial_out(up, UART_LCR, 0);
1187 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1188 scratch = serial_in(up, UART_IIR) >> 6;
1192 autoconfig_8250(up);
1195 port->type = PORT_UNKNOWN;
1198 port->type = PORT_16550;
1201 autoconfig_16550a(up);
1205 #ifdef CONFIG_SERIAL_8250_RSA
1207 * Only probe for RSA ports if we got the region.
1209 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1212 for (i = 0 ; i < probe_rsa_count; ++i) {
1213 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1214 port->type = PORT_RSA;
1221 serial_out(up, UART_LCR, save_lcr);
1223 port->fifosize = uart_config[up->port.type].fifo_size;
1224 old_capabilities = up->capabilities;
1225 up->capabilities = uart_config[port->type].flags;
1226 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1228 if (port->type == PORT_UNKNOWN)
1234 #ifdef CONFIG_SERIAL_8250_RSA
1235 if (port->type == PORT_RSA)
1236 serial_out(up, UART_RSA_FRR, 0);
1238 serial_out(up, UART_MCR, save_mcr);
1239 serial8250_clear_fifos(up);
1240 serial_in(up, UART_RX);
1241 if (up->capabilities & UART_CAP_UUE)
1242 serial_out(up, UART_IER, UART_IER_UUE);
1244 serial_out(up, UART_IER, 0);
1247 spin_unlock_irqrestore(&port->lock, flags);
1248 if (up->capabilities != old_capabilities) {
1250 "ttyS%d: detected caps %08x should be %08x\n",
1251 serial_index(port), old_capabilities,
1255 DEBUG_AUTOCONF("iir=%d ", scratch);
1256 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1259 static void autoconfig_irq(struct uart_8250_port *up)
1261 struct uart_port *port = &up->port;
1262 unsigned char save_mcr, save_ier;
1263 unsigned char save_ICP = 0;
1264 unsigned int ICP = 0;
1268 if (port->flags & UPF_FOURPORT) {
1269 ICP = (port->iobase & 0xfe0) | 0x1f;
1270 save_ICP = inb_p(ICP);
1275 /* forget possible initially masked and pending IRQ */
1276 probe_irq_off(probe_irq_on());
1277 save_mcr = serial_in(up, UART_MCR);
1278 save_ier = serial_in(up, UART_IER);
1279 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1281 irqs = probe_irq_on();
1282 serial_out(up, UART_MCR, 0);
1284 if (port->flags & UPF_FOURPORT) {
1285 serial_out(up, UART_MCR,
1286 UART_MCR_DTR | UART_MCR_RTS);
1288 serial_out(up, UART_MCR,
1289 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1291 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1292 serial_in(up, UART_LSR);
1293 serial_in(up, UART_RX);
1294 serial_in(up, UART_IIR);
1295 serial_in(up, UART_MSR);
1296 serial_out(up, UART_TX, 0xFF);
1298 irq = probe_irq_off(irqs);
1300 serial_out(up, UART_MCR, save_mcr);
1301 serial_out(up, UART_IER, save_ier);
1303 if (port->flags & UPF_FOURPORT)
1304 outb_p(save_ICP, ICP);
1306 port->irq = (irq > 0) ? irq : 0;
1309 static inline void __stop_tx(struct uart_8250_port *p)
1311 if (p->ier & UART_IER_THRI) {
1312 p->ier &= ~UART_IER_THRI;
1313 serial_out(p, UART_IER, p->ier);
1317 static void serial8250_stop_tx(struct uart_port *port)
1319 struct uart_8250_port *up =
1320 container_of(port, struct uart_8250_port, port);
1325 * We really want to stop the transmitter from sending.
1327 if (port->type == PORT_16C950) {
1328 up->acr |= UART_ACR_TXDIS;
1329 serial_icr_write(up, UART_ACR, up->acr);
1333 static void serial8250_start_tx(struct uart_port *port)
1335 struct uart_8250_port *up =
1336 container_of(port, struct uart_8250_port, port);
1338 if (!(up->ier & UART_IER_THRI)) {
1339 up->ier |= UART_IER_THRI;
1340 serial_port_out(port, UART_IER, up->ier);
1342 if (up->bugs & UART_BUG_TXEN) {
1344 lsr = serial_in(up, UART_LSR);
1345 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1346 if ((port->type == PORT_RM9000) ?
1347 (lsr & UART_LSR_THRE) :
1348 (lsr & UART_LSR_TEMT))
1349 serial8250_tx_chars(up);
1354 * Re-enable the transmitter if we disabled it.
1356 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1357 up->acr &= ~UART_ACR_TXDIS;
1358 serial_icr_write(up, UART_ACR, up->acr);
1362 static void serial8250_stop_rx(struct uart_port *port)
1364 struct uart_8250_port *up =
1365 container_of(port, struct uart_8250_port, port);
1367 up->ier &= ~UART_IER_RLSI;
1368 up->port.read_status_mask &= ~UART_LSR_DR;
1369 serial_port_out(port, UART_IER, up->ier);
1372 static void serial8250_enable_ms(struct uart_port *port)
1374 struct uart_8250_port *up =
1375 container_of(port, struct uart_8250_port, port);
1377 /* no MSR capabilities */
1378 if (up->bugs & UART_BUG_NOMSR)
1381 up->ier |= UART_IER_MSI;
1382 serial_port_out(port, UART_IER, up->ier);
1386 * serial8250_rx_chars: processes according to the passed in LSR
1387 * value, and returns the remaining LSR bits not handled
1388 * by this Rx routine.
1391 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1393 struct uart_port *port = &up->port;
1394 struct tty_struct *tty = port->state->port.tty;
1396 int max_count = 256;
1400 if (likely(lsr & UART_LSR_DR))
1401 ch = serial_in(up, UART_RX);
1404 * Intel 82571 has a Serial Over Lan device that will
1405 * set UART_LSR_BI without setting UART_LSR_DR when
1406 * it receives a break. To avoid reading from the
1407 * receive buffer without UART_LSR_DR bit set, we
1408 * just force the read character to be 0
1415 lsr |= up->lsr_saved_flags;
1416 up->lsr_saved_flags = 0;
1418 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1419 if (lsr & UART_LSR_BI) {
1420 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1423 * We do the SysRQ and SAK checking
1424 * here because otherwise the break
1425 * may get masked by ignore_status_mask
1426 * or read_status_mask.
1428 if (uart_handle_break(port))
1430 } else if (lsr & UART_LSR_PE)
1431 port->icount.parity++;
1432 else if (lsr & UART_LSR_FE)
1433 port->icount.frame++;
1434 if (lsr & UART_LSR_OE)
1435 port->icount.overrun++;
1438 * Mask off conditions which should be ignored.
1440 lsr &= port->read_status_mask;
1442 if (lsr & UART_LSR_BI) {
1443 DEBUG_INTR("handling break....");
1445 } else if (lsr & UART_LSR_PE)
1447 else if (lsr & UART_LSR_FE)
1450 if (uart_handle_sysrq_char(port, ch))
1453 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1456 lsr = serial_in(up, UART_LSR);
1457 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1458 spin_unlock(&port->lock);
1459 tty_flip_buffer_push(tty);
1460 spin_lock(&port->lock);
1463 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1465 void serial8250_tx_chars(struct uart_8250_port *up)
1467 struct uart_port *port = &up->port;
1468 struct circ_buf *xmit = &port->state->xmit;
1472 serial_out(up, UART_TX, port->x_char);
1477 if (uart_tx_stopped(port)) {
1478 serial8250_stop_tx(port);
1481 if (uart_circ_empty(xmit)) {
1486 count = up->tx_loadsz;
1488 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1489 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1491 if (uart_circ_empty(xmit))
1493 } while (--count > 0);
1495 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1496 uart_write_wakeup(port);
1498 DEBUG_INTR("THRE...");
1500 if (uart_circ_empty(xmit))
1503 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1505 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1507 struct uart_port *port = &up->port;
1508 unsigned int status = serial_in(up, UART_MSR);
1510 status |= up->msr_saved_flags;
1511 up->msr_saved_flags = 0;
1512 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1513 port->state != NULL) {
1514 if (status & UART_MSR_TERI)
1516 if (status & UART_MSR_DDSR)
1518 if (status & UART_MSR_DDCD)
1519 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1520 if (status & UART_MSR_DCTS)
1521 uart_handle_cts_change(port, status & UART_MSR_CTS);
1523 wake_up_interruptible(&port->state->port.delta_msr_wait);
1528 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1531 * This handles the interrupt from one port.
1533 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1535 unsigned char status;
1536 unsigned long flags;
1537 struct uart_8250_port *up =
1538 container_of(port, struct uart_8250_port, port);
1540 if (iir & UART_IIR_NO_INT)
1543 spin_lock_irqsave(&port->lock, flags);
1545 status = serial_port_in(port, UART_LSR);
1547 DEBUG_INTR("status = %x...", status);
1549 if (status & (UART_LSR_DR | UART_LSR_BI))
1550 status = serial8250_rx_chars(up, status);
1551 serial8250_modem_status(up);
1552 if (status & UART_LSR_THRE)
1553 serial8250_tx_chars(up);
1555 spin_unlock_irqrestore(&port->lock, flags);
1558 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1560 static int serial8250_default_handle_irq(struct uart_port *port)
1562 unsigned int iir = serial_port_in(port, UART_IIR);
1564 return serial8250_handle_irq(port, iir);
1568 * These Exar UARTs have an extra interrupt indicator that could
1569 * fire for a few unimplemented interrupts. One of which is a
1570 * wakeup event when coming out of sleep. Put this here just
1571 * to be on the safe side that these interrupts don't go unhandled.
1573 static int exar_handle_irq(struct uart_port *port)
1575 unsigned char int0, int1, int2, int3;
1576 unsigned int iir = serial_port_in(port, UART_IIR);
1579 ret = serial8250_handle_irq(port, iir);
1581 if ((port->type == PORT_XR17V35X) ||
1582 (port->type == PORT_XR17D15X)) {
1583 int0 = serial_port_in(port, 0x80);
1584 int1 = serial_port_in(port, 0x81);
1585 int2 = serial_port_in(port, 0x82);
1586 int3 = serial_port_in(port, 0x83);
1593 * This is the serial driver's interrupt routine.
1595 * Arjan thinks the old way was overly complex, so it got simplified.
1596 * Alan disagrees, saying that need the complexity to handle the weird
1597 * nature of ISA shared interrupts. (This is a special exception.)
1599 * In order to handle ISA shared interrupts properly, we need to check
1600 * that all ports have been serviced, and therefore the ISA interrupt
1601 * line has been de-asserted.
1603 * This means we need to loop through all ports. checking that they
1604 * don't have an interrupt pending.
1606 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1608 struct irq_info *i = dev_id;
1609 struct list_head *l, *end = NULL;
1610 int pass_counter = 0, handled = 0;
1612 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1614 spin_lock(&i->lock);
1618 struct uart_8250_port *up;
1619 struct uart_port *port;
1621 up = list_entry(l, struct uart_8250_port, list);
1624 if (port->handle_irq(port)) {
1627 } else if (end == NULL)
1632 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1633 /* If we hit this, we're dead. */
1634 printk_ratelimited(KERN_ERR
1635 "serial8250: too much work for irq%d\n", irq);
1640 spin_unlock(&i->lock);
1642 DEBUG_INTR("end.\n");
1644 return IRQ_RETVAL(handled);
1648 * To support ISA shared interrupts, we need to have one interrupt
1649 * handler that ensures that the IRQ line has been deasserted
1650 * before returning. Failing to do this will result in the IRQ
1651 * line being stuck active, and, since ISA irqs are edge triggered,
1652 * no more IRQs will be seen.
1654 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1656 spin_lock_irq(&i->lock);
1658 if (!list_empty(i->head)) {
1659 if (i->head == &up->list)
1660 i->head = i->head->next;
1661 list_del(&up->list);
1663 BUG_ON(i->head != &up->list);
1666 spin_unlock_irq(&i->lock);
1667 /* List empty so throw away the hash node */
1668 if (i->head == NULL) {
1669 hlist_del(&i->node);
1674 static int serial_link_irq_chain(struct uart_8250_port *up)
1676 struct hlist_head *h;
1677 struct hlist_node *n;
1679 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1681 mutex_lock(&hash_mutex);
1683 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1685 hlist_for_each(n, h) {
1686 i = hlist_entry(n, struct irq_info, node);
1687 if (i->irq == up->port.irq)
1692 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1694 mutex_unlock(&hash_mutex);
1697 spin_lock_init(&i->lock);
1698 i->irq = up->port.irq;
1699 hlist_add_head(&i->node, h);
1701 mutex_unlock(&hash_mutex);
1703 spin_lock_irq(&i->lock);
1706 list_add(&up->list, i->head);
1707 spin_unlock_irq(&i->lock);
1711 INIT_LIST_HEAD(&up->list);
1712 i->head = &up->list;
1713 spin_unlock_irq(&i->lock);
1714 irq_flags |= up->port.irqflags;
1715 ret = request_irq(up->port.irq, serial8250_interrupt,
1716 irq_flags, "serial", i);
1718 serial_do_unlink(i, up);
1724 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1727 struct hlist_node *n;
1728 struct hlist_head *h;
1730 mutex_lock(&hash_mutex);
1732 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1734 hlist_for_each(n, h) {
1735 i = hlist_entry(n, struct irq_info, node);
1736 if (i->irq == up->port.irq)
1741 BUG_ON(i->head == NULL);
1743 if (list_empty(i->head))
1744 free_irq(up->port.irq, i);
1746 serial_do_unlink(i, up);
1747 mutex_unlock(&hash_mutex);
1751 * This function is used to handle ports that do not have an
1752 * interrupt. This doesn't work very well for 16450's, but gives
1753 * barely passable results for a 16550A. (Although at the expense
1754 * of much CPU overhead).
1756 static void serial8250_timeout(unsigned long data)
1758 struct uart_8250_port *up = (struct uart_8250_port *)data;
1760 up->port.handle_irq(&up->port);
1761 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1764 static void serial8250_backup_timeout(unsigned long data)
1766 struct uart_8250_port *up = (struct uart_8250_port *)data;
1767 unsigned int iir, ier = 0, lsr;
1768 unsigned long flags;
1770 spin_lock_irqsave(&up->port.lock, flags);
1773 * Must disable interrupts or else we risk racing with the interrupt
1777 ier = serial_in(up, UART_IER);
1778 serial_out(up, UART_IER, 0);
1781 iir = serial_in(up, UART_IIR);
1784 * This should be a safe test for anyone who doesn't trust the
1785 * IIR bits on their UART, but it's specifically designed for
1786 * the "Diva" UART used on the management processor on many HP
1787 * ia64 and parisc boxes.
1789 lsr = serial_in(up, UART_LSR);
1790 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1791 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1792 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1793 (lsr & UART_LSR_THRE)) {
1794 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1795 iir |= UART_IIR_THRI;
1798 if (!(iir & UART_IIR_NO_INT))
1799 serial8250_tx_chars(up);
1802 serial_out(up, UART_IER, ier);
1804 spin_unlock_irqrestore(&up->port.lock, flags);
1806 /* Standard timer interval plus 0.2s to keep the port running */
1807 mod_timer(&up->timer,
1808 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1811 static unsigned int serial8250_tx_empty(struct uart_port *port)
1813 struct uart_8250_port *up =
1814 container_of(port, struct uart_8250_port, port);
1815 unsigned long flags;
1818 spin_lock_irqsave(&port->lock, flags);
1819 lsr = serial_port_in(port, UART_LSR);
1820 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1821 spin_unlock_irqrestore(&port->lock, flags);
1823 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1826 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1828 struct uart_8250_port *up =
1829 container_of(port, struct uart_8250_port, port);
1830 unsigned int status;
1833 status = serial8250_modem_status(up);
1836 if (status & UART_MSR_DCD)
1838 if (status & UART_MSR_RI)
1840 if (status & UART_MSR_DSR)
1842 if (status & UART_MSR_CTS)
1847 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1849 struct uart_8250_port *up =
1850 container_of(port, struct uart_8250_port, port);
1851 unsigned char mcr = 0;
1853 if (mctrl & TIOCM_RTS)
1854 mcr |= UART_MCR_RTS;
1855 if (mctrl & TIOCM_DTR)
1856 mcr |= UART_MCR_DTR;
1857 if (mctrl & TIOCM_OUT1)
1858 mcr |= UART_MCR_OUT1;
1859 if (mctrl & TIOCM_OUT2)
1860 mcr |= UART_MCR_OUT2;
1861 if (mctrl & TIOCM_LOOP)
1862 mcr |= UART_MCR_LOOP;
1864 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1866 serial_port_out(port, UART_MCR, mcr);
1869 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1871 struct uart_8250_port *up =
1872 container_of(port, struct uart_8250_port, port);
1873 unsigned long flags;
1875 spin_lock_irqsave(&port->lock, flags);
1876 if (break_state == -1)
1877 up->lcr |= UART_LCR_SBC;
1879 up->lcr &= ~UART_LCR_SBC;
1880 serial_port_out(port, UART_LCR, up->lcr);
1881 spin_unlock_irqrestore(&port->lock, flags);
1885 * Wait for transmitter & holding register to empty
1887 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1889 unsigned int status, tmout = 10000;
1891 /* Wait up to 10ms for the character(s) to be sent. */
1893 status = serial_in(up, UART_LSR);
1895 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1897 if ((status & bits) == bits)
1904 /* Wait up to 1s for flow control if necessary */
1905 if (up->port.flags & UPF_CONS_FLOW) {
1907 for (tmout = 1000000; tmout; tmout--) {
1908 unsigned int msr = serial_in(up, UART_MSR);
1909 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1910 if (msr & UART_MSR_CTS)
1913 touch_nmi_watchdog();
1918 #ifdef CONFIG_CONSOLE_POLL
1920 * Console polling routines for writing and reading from the uart while
1921 * in an interrupt or debug context.
1924 static int serial8250_get_poll_char(struct uart_port *port)
1926 unsigned char lsr = serial_port_in(port, UART_LSR);
1928 if (!(lsr & UART_LSR_DR))
1929 return NO_POLL_CHAR;
1931 return serial_port_in(port, UART_RX);
1935 static void serial8250_put_poll_char(struct uart_port *port,
1939 struct uart_8250_port *up =
1940 container_of(port, struct uart_8250_port, port);
1943 * First save the IER then disable the interrupts
1945 ier = serial_port_in(port, UART_IER);
1946 if (up->capabilities & UART_CAP_UUE)
1947 serial_port_out(port, UART_IER, UART_IER_UUE);
1949 serial_port_out(port, UART_IER, 0);
1951 wait_for_xmitr(up, BOTH_EMPTY);
1953 * Send the character out.
1954 * If a LF, also do CR...
1956 serial_port_out(port, UART_TX, c);
1958 wait_for_xmitr(up, BOTH_EMPTY);
1959 serial_port_out(port, UART_TX, 13);
1963 * Finally, wait for transmitter to become empty
1964 * and restore the IER
1966 wait_for_xmitr(up, BOTH_EMPTY);
1967 serial_port_out(port, UART_IER, ier);
1970 #endif /* CONFIG_CONSOLE_POLL */
1972 static int serial8250_startup(struct uart_port *port)
1974 struct uart_8250_port *up =
1975 container_of(port, struct uart_8250_port, port);
1976 unsigned long flags;
1977 unsigned char lsr, iir;
1980 if (port->type == PORT_8250_CIR)
1983 port->fifosize = uart_config[up->port.type].fifo_size;
1984 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1985 up->capabilities = uart_config[up->port.type].flags;
1988 if (port->iotype != up->cur_iotype)
1989 set_io_from_upio(port);
1991 if (port->type == PORT_16C950) {
1992 /* Wake up and initialize UART */
1994 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1995 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1996 serial_port_out(port, UART_IER, 0);
1997 serial_port_out(port, UART_LCR, 0);
1998 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1999 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2000 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2001 serial_port_out(port, UART_LCR, 0);
2004 #ifdef CONFIG_SERIAL_8250_RSA
2006 * If this is an RSA port, see if we can kick it up to the
2007 * higher speed clock.
2013 * Clear the FIFO buffers and disable them.
2014 * (they will be reenabled in set_termios())
2016 serial8250_clear_fifos(up);
2019 * Clear the interrupt registers.
2021 serial_port_in(port, UART_LSR);
2022 serial_port_in(port, UART_RX);
2023 serial_port_in(port, UART_IIR);
2024 serial_port_in(port, UART_MSR);
2027 * At this point, there's no way the LSR could still be 0xff;
2028 * if it is, then bail out, because there's likely no UART
2031 if (!(port->flags & UPF_BUGGY_UART) &&
2032 (serial_port_in(port, UART_LSR) == 0xff)) {
2033 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2034 serial_index(port));
2039 * For a XR16C850, we need to set the trigger levels
2041 if (port->type == PORT_16850) {
2044 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2046 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2047 serial_port_out(port, UART_FCTR,
2048 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2049 serial_port_out(port, UART_TRG, UART_TRG_96);
2050 serial_port_out(port, UART_FCTR,
2051 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2052 serial_port_out(port, UART_TRG, UART_TRG_96);
2054 serial_port_out(port, UART_LCR, 0);
2060 * Test for UARTs that do not reassert THRE when the
2061 * transmitter is idle and the interrupt has already
2062 * been cleared. Real 16550s should always reassert
2063 * this interrupt whenever the transmitter is idle and
2064 * the interrupt is enabled. Delays are necessary to
2065 * allow register changes to become visible.
2067 spin_lock_irqsave(&port->lock, flags);
2068 if (up->port.irqflags & IRQF_SHARED)
2069 disable_irq_nosync(port->irq);
2071 wait_for_xmitr(up, UART_LSR_THRE);
2072 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2073 udelay(1); /* allow THRE to set */
2074 iir1 = serial_port_in(port, UART_IIR);
2075 serial_port_out(port, UART_IER, 0);
2076 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2077 udelay(1); /* allow a working UART time to re-assert THRE */
2078 iir = serial_port_in(port, UART_IIR);
2079 serial_port_out(port, UART_IER, 0);
2081 if (port->irqflags & IRQF_SHARED)
2082 enable_irq(port->irq);
2083 spin_unlock_irqrestore(&port->lock, flags);
2086 * If the interrupt is not reasserted, or we otherwise
2087 * don't trust the iir, setup a timer to kick the UART
2088 * on a regular basis.
2090 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2091 up->port.flags & UPF_BUG_THRE) {
2092 up->bugs |= UART_BUG_THRE;
2093 pr_debug("ttyS%d - using backup timer\n",
2094 serial_index(port));
2099 * The above check will only give an accurate result the first time
2100 * the port is opened so this value needs to be preserved.
2102 if (up->bugs & UART_BUG_THRE) {
2103 up->timer.function = serial8250_backup_timeout;
2104 up->timer.data = (unsigned long)up;
2105 mod_timer(&up->timer, jiffies +
2106 uart_poll_timeout(port) + HZ / 5);
2110 * If the "interrupt" for this port doesn't correspond with any
2111 * hardware interrupt, we use a timer-based system. The original
2112 * driver used to do this with IRQ0.
2115 up->timer.data = (unsigned long)up;
2116 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2118 retval = serial_link_irq_chain(up);
2124 * Now, initialize the UART
2126 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2128 spin_lock_irqsave(&port->lock, flags);
2129 if (up->port.flags & UPF_FOURPORT) {
2131 up->port.mctrl |= TIOCM_OUT1;
2134 * Most PC uarts need OUT2 raised to enable interrupts.
2137 up->port.mctrl |= TIOCM_OUT2;
2139 serial8250_set_mctrl(port, port->mctrl);
2141 /* Serial over Lan (SoL) hack:
2142 Intel 8257x Gigabit ethernet chips have a
2143 16550 emulation, to be used for Serial Over Lan.
2144 Those chips take a longer time than a normal
2145 serial device to signalize that a transmission
2146 data was queued. Due to that, the above test generally
2147 fails. One solution would be to delay the reading of
2148 iir. However, this is not reliable, since the timeout
2149 is variable. So, let's just don't test if we receive
2150 TX irq. This way, we'll never enable UART_BUG_TXEN.
2152 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2153 goto dont_test_tx_en;
2156 * Do a quick test to see if we receive an
2157 * interrupt when we enable the TX irq.
2159 serial_port_out(port, UART_IER, UART_IER_THRI);
2160 lsr = serial_port_in(port, UART_LSR);
2161 iir = serial_port_in(port, UART_IIR);
2162 serial_port_out(port, UART_IER, 0);
2164 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2165 if (!(up->bugs & UART_BUG_TXEN)) {
2166 up->bugs |= UART_BUG_TXEN;
2167 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2168 serial_index(port));
2171 up->bugs &= ~UART_BUG_TXEN;
2175 spin_unlock_irqrestore(&port->lock, flags);
2178 * Clear the interrupt registers again for luck, and clear the
2179 * saved flags to avoid getting false values from polling
2180 * routines or the previous session.
2182 serial_port_in(port, UART_LSR);
2183 serial_port_in(port, UART_RX);
2184 serial_port_in(port, UART_IIR);
2185 serial_port_in(port, UART_MSR);
2186 up->lsr_saved_flags = 0;
2187 up->msr_saved_flags = 0;
2190 * Finally, enable interrupts. Note: Modem status interrupts
2191 * are set via set_termios(), which will be occurring imminently
2192 * anyway, so we don't enable them here.
2194 up->ier = UART_IER_RLSI | UART_IER_RDI;
2195 serial_port_out(port, UART_IER, up->ier);
2197 if (port->flags & UPF_FOURPORT) {
2200 * Enable interrupts on the AST Fourport board
2202 icp = (port->iobase & 0xfe0) | 0x01f;
2210 static void serial8250_shutdown(struct uart_port *port)
2212 struct uart_8250_port *up =
2213 container_of(port, struct uart_8250_port, port);
2214 unsigned long flags;
2217 * Disable interrupts from this port
2220 serial_port_out(port, UART_IER, 0);
2222 spin_lock_irqsave(&port->lock, flags);
2223 if (port->flags & UPF_FOURPORT) {
2224 /* reset interrupts on the AST Fourport board */
2225 inb((port->iobase & 0xfe0) | 0x1f);
2226 port->mctrl |= TIOCM_OUT1;
2228 port->mctrl &= ~TIOCM_OUT2;
2230 serial8250_set_mctrl(port, port->mctrl);
2231 spin_unlock_irqrestore(&port->lock, flags);
2234 * Disable break condition and FIFOs
2236 serial_port_out(port, UART_LCR,
2237 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2238 serial8250_clear_fifos(up);
2240 #ifdef CONFIG_SERIAL_8250_RSA
2242 * Reset the RSA board back to 115kbps compat mode.
2248 * Read data port to reset things, and then unlink from
2251 serial_port_in(port, UART_RX);
2253 del_timer_sync(&up->timer);
2254 up->timer.function = serial8250_timeout;
2256 serial_unlink_irq_chain(up);
2259 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2264 * Handle magic divisors for baud rates above baud_base on
2265 * SMSC SuperIO chips.
2267 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2268 baud == (port->uartclk/4))
2270 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2271 baud == (port->uartclk/8))
2274 quot = uart_get_divisor(port, baud);
2280 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2281 struct ktermios *old)
2283 struct uart_8250_port *up =
2284 container_of(port, struct uart_8250_port, port);
2285 unsigned char cval, fcr = 0;
2286 unsigned long flags;
2287 unsigned int baud, quot;
2290 switch (termios->c_cflag & CSIZE) {
2292 cval = UART_LCR_WLEN5;
2295 cval = UART_LCR_WLEN6;
2298 cval = UART_LCR_WLEN7;
2302 cval = UART_LCR_WLEN8;
2306 if (termios->c_cflag & CSTOPB)
2307 cval |= UART_LCR_STOP;
2308 if (termios->c_cflag & PARENB) {
2309 cval |= UART_LCR_PARITY;
2310 if (up->bugs & UART_BUG_PARITY)
2313 if (!(termios->c_cflag & PARODD))
2314 cval |= UART_LCR_EPAR;
2316 if (termios->c_cflag & CMSPAR)
2317 cval |= UART_LCR_SPAR;
2321 * Ask the core to calculate the divisor for us.
2323 baud = uart_get_baud_rate(port, termios, old,
2324 port->uartclk / 16 / 0xffff,
2325 port->uartclk / 16);
2326 quot = serial8250_get_divisor(port, baud);
2329 * Oxford Semi 952 rev B workaround
2331 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2334 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2335 fcr = uart_config[port->type].fcr;
2336 if (baud < 2400 || fifo_bug) {
2337 fcr &= ~UART_FCR_TRIGGER_MASK;
2338 fcr |= UART_FCR_TRIGGER_1;
2343 * MCR-based auto flow control. When AFE is enabled, RTS will be
2344 * deasserted when the receive FIFO contains more characters than
2345 * the trigger, or the MCR RTS bit is cleared. In the case where
2346 * the remote UART is not using CTS auto flow control, we must
2347 * have sufficient FIFO entries for the latency of the remote
2348 * UART to respond. IOW, at least 32 bytes of FIFO.
2350 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2351 up->mcr &= ~UART_MCR_AFE;
2352 if (termios->c_cflag & CRTSCTS)
2353 up->mcr |= UART_MCR_AFE;
2357 * Ok, we're now changing the port state. Do it with
2358 * interrupts disabled.
2360 spin_lock_irqsave(&port->lock, flags);
2363 * Update the per-port timeout.
2365 uart_update_timeout(port, termios->c_cflag, baud);
2367 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2368 if (termios->c_iflag & INPCK)
2369 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2370 if (termios->c_iflag & (BRKINT | PARMRK))
2371 port->read_status_mask |= UART_LSR_BI;
2374 * Characteres to ignore
2376 port->ignore_status_mask = 0;
2377 if (termios->c_iflag & IGNPAR)
2378 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2379 if (termios->c_iflag & IGNBRK) {
2380 port->ignore_status_mask |= UART_LSR_BI;
2382 * If we're ignoring parity and break indicators,
2383 * ignore overruns too (for real raw support).
2385 if (termios->c_iflag & IGNPAR)
2386 port->ignore_status_mask |= UART_LSR_OE;
2390 * ignore all characters if CREAD is not set
2392 if ((termios->c_cflag & CREAD) == 0)
2393 port->ignore_status_mask |= UART_LSR_DR;
2396 * CTS flow control flag and modem status interrupts
2398 up->ier &= ~UART_IER_MSI;
2399 if (!(up->bugs & UART_BUG_NOMSR) &&
2400 UART_ENABLE_MS(&up->port, termios->c_cflag))
2401 up->ier |= UART_IER_MSI;
2402 if (up->capabilities & UART_CAP_UUE)
2403 up->ier |= UART_IER_UUE;
2404 if (up->capabilities & UART_CAP_RTOIE)
2405 up->ier |= UART_IER_RTOIE;
2407 serial_port_out(port, UART_IER, up->ier);
2409 if (up->capabilities & UART_CAP_EFR) {
2410 unsigned char efr = 0;
2412 * TI16C752/Startech hardware flow control. FIXME:
2413 * - TI16C752 requires control thresholds to be set.
2414 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2416 if (termios->c_cflag & CRTSCTS)
2417 efr |= UART_EFR_CTS;
2419 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2420 if (port->flags & UPF_EXAR_EFR)
2421 serial_port_out(port, UART_XR_EFR, efr);
2423 serial_port_out(port, UART_EFR, efr);
2426 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2427 if (is_omap1510_8250(up)) {
2428 if (baud == 115200) {
2430 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2432 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2436 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2437 * otherwise just set DLAB
2439 if (up->capabilities & UART_NATSEMI)
2440 serial_port_out(port, UART_LCR, 0xe0);
2442 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
2444 serial_dl_write(up, quot);
2447 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2448 * is written without DLAB set, this mode will be disabled.
2450 if (port->type == PORT_16750)
2451 serial_port_out(port, UART_FCR, fcr);
2453 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
2454 up->lcr = cval; /* Save LCR */
2455 if (port->type != PORT_16750) {
2456 /* emulated UARTs (Lucent Venus 167x) need two steps */
2457 if (fcr & UART_FCR_ENABLE_FIFO)
2458 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2459 serial_port_out(port, UART_FCR, fcr); /* set fcr */
2461 serial8250_set_mctrl(port, port->mctrl);
2462 spin_unlock_irqrestore(&port->lock, flags);
2463 /* Don't rewrite B0 */
2464 if (tty_termios_baud_rate(termios))
2465 tty_termios_encode_baud_rate(termios, baud, baud);
2467 EXPORT_SYMBOL(serial8250_do_set_termios);
2470 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2471 struct ktermios *old)
2473 if (port->set_termios)
2474 port->set_termios(port, termios, old);
2476 serial8250_do_set_termios(port, termios, old);
2480 serial8250_set_ldisc(struct uart_port *port, int new)
2483 port->flags |= UPF_HARDPPS_CD;
2484 serial8250_enable_ms(port);
2486 port->flags &= ~UPF_HARDPPS_CD;
2490 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2491 unsigned int oldstate)
2493 struct uart_8250_port *p =
2494 container_of(port, struct uart_8250_port, port);
2496 serial8250_set_sleep(p, state != 0);
2498 EXPORT_SYMBOL(serial8250_do_pm);
2501 serial8250_pm(struct uart_port *port, unsigned int state,
2502 unsigned int oldstate)
2505 port->pm(port, state, oldstate);
2507 serial8250_do_pm(port, state, oldstate);
2510 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2512 if (pt->port.iotype == UPIO_AU)
2514 if (is_omap1_8250(pt))
2515 return 0x16 << pt->port.regshift;
2517 return 8 << pt->port.regshift;
2521 * Resource handling.
2523 static int serial8250_request_std_resource(struct uart_8250_port *up)
2525 unsigned int size = serial8250_port_size(up);
2526 struct uart_port *port = &up->port;
2529 switch (port->iotype) {
2537 if (!request_mem_region(port->mapbase, size, "serial")) {
2542 if (port->flags & UPF_IOREMAP) {
2543 port->membase = ioremap_nocache(port->mapbase, size);
2544 if (!port->membase) {
2545 release_mem_region(port->mapbase, size);
2553 if (!request_region(port->iobase, size, "serial"))
2560 static void serial8250_release_std_resource(struct uart_8250_port *up)
2562 unsigned int size = serial8250_port_size(up);
2563 struct uart_port *port = &up->port;
2565 switch (port->iotype) {
2573 if (port->flags & UPF_IOREMAP) {
2574 iounmap(port->membase);
2575 port->membase = NULL;
2578 release_mem_region(port->mapbase, size);
2583 release_region(port->iobase, size);
2588 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2590 unsigned long start = UART_RSA_BASE << up->port.regshift;
2591 unsigned int size = 8 << up->port.regshift;
2592 struct uart_port *port = &up->port;
2595 switch (port->iotype) {
2598 start += port->iobase;
2599 if (request_region(start, size, "serial-rsa"))
2609 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2611 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2612 unsigned int size = 8 << up->port.regshift;
2613 struct uart_port *port = &up->port;
2615 switch (port->iotype) {
2618 release_region(port->iobase + offset, size);
2623 static void serial8250_release_port(struct uart_port *port)
2625 struct uart_8250_port *up =
2626 container_of(port, struct uart_8250_port, port);
2628 serial8250_release_std_resource(up);
2629 if (port->type == PORT_RSA)
2630 serial8250_release_rsa_resource(up);
2633 static int serial8250_request_port(struct uart_port *port)
2635 struct uart_8250_port *up =
2636 container_of(port, struct uart_8250_port, port);
2639 if (port->type == PORT_8250_CIR)
2642 ret = serial8250_request_std_resource(up);
2643 if (ret == 0 && port->type == PORT_RSA) {
2644 ret = serial8250_request_rsa_resource(up);
2646 serial8250_release_std_resource(up);
2652 static void serial8250_config_port(struct uart_port *port, int flags)
2654 struct uart_8250_port *up =
2655 container_of(port, struct uart_8250_port, port);
2656 int probeflags = PROBE_ANY;
2659 if (port->type == PORT_8250_CIR)
2663 * Find the region that we can probe for. This in turn
2664 * tells us whether we can probe for the type of port.
2666 ret = serial8250_request_std_resource(up);
2670 ret = serial8250_request_rsa_resource(up);
2672 probeflags &= ~PROBE_RSA;
2674 if (port->iotype != up->cur_iotype)
2675 set_io_from_upio(port);
2677 if (flags & UART_CONFIG_TYPE)
2678 autoconfig(up, probeflags);
2680 /* if access method is AU, it is a 16550 with a quirk */
2681 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2682 up->bugs |= UART_BUG_NOMSR;
2684 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2687 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
2688 serial8250_release_rsa_resource(up);
2689 if (port->type == PORT_UNKNOWN)
2690 serial8250_release_std_resource(up);
2692 /* Fixme: probably not the best place for this */
2693 if ((port->type == PORT_XR17V35X) ||
2694 (port->type == PORT_XR17D15X))
2695 port->handle_irq = exar_handle_irq;
2699 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2701 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2702 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2703 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2704 ser->type == PORT_STARTECH)
2710 serial8250_type(struct uart_port *port)
2712 int type = port->type;
2714 if (type >= ARRAY_SIZE(uart_config))
2716 return uart_config[type].name;
2719 static struct uart_ops serial8250_pops = {
2720 .tx_empty = serial8250_tx_empty,
2721 .set_mctrl = serial8250_set_mctrl,
2722 .get_mctrl = serial8250_get_mctrl,
2723 .stop_tx = serial8250_stop_tx,
2724 .start_tx = serial8250_start_tx,
2725 .stop_rx = serial8250_stop_rx,
2726 .enable_ms = serial8250_enable_ms,
2727 .break_ctl = serial8250_break_ctl,
2728 .startup = serial8250_startup,
2729 .shutdown = serial8250_shutdown,
2730 .set_termios = serial8250_set_termios,
2731 .set_ldisc = serial8250_set_ldisc,
2732 .pm = serial8250_pm,
2733 .type = serial8250_type,
2734 .release_port = serial8250_release_port,
2735 .request_port = serial8250_request_port,
2736 .config_port = serial8250_config_port,
2737 .verify_port = serial8250_verify_port,
2738 #ifdef CONFIG_CONSOLE_POLL
2739 .poll_get_char = serial8250_get_poll_char,
2740 .poll_put_char = serial8250_put_poll_char,
2744 static struct uart_8250_port serial8250_ports[UART_NR];
2746 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2747 unsigned short *capabilities);
2749 void serial8250_set_isa_configurator(
2750 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2752 serial8250_isa_config = v;
2754 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2756 static void __init serial8250_isa_init_ports(void)
2758 struct uart_8250_port *up;
2759 static int first = 1;
2766 if (nr_uarts > UART_NR)
2769 for (i = 0; i < nr_uarts; i++) {
2770 struct uart_8250_port *up = &serial8250_ports[i];
2771 struct uart_port *port = &up->port;
2774 spin_lock_init(&port->lock);
2776 init_timer(&up->timer);
2777 up->timer.function = serial8250_timeout;
2778 up->cur_iotype = 0xFF;
2781 * ALPHA_KLUDGE_MCR needs to be killed.
2783 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2784 up->mcr_force = ALPHA_KLUDGE_MCR;
2786 port->ops = &serial8250_pops;
2790 irqflag = IRQF_SHARED;
2792 for (i = 0, up = serial8250_ports;
2793 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2795 struct uart_port *port = &up->port;
2797 port->iobase = old_serial_port[i].port;
2798 port->irq = irq_canonicalize(old_serial_port[i].irq);
2799 port->irqflags = old_serial_port[i].irqflags;
2800 port->uartclk = old_serial_port[i].baud_base * 16;
2801 port->flags = old_serial_port[i].flags;
2802 port->hub6 = old_serial_port[i].hub6;
2803 port->membase = old_serial_port[i].iomem_base;
2804 port->iotype = old_serial_port[i].io_type;
2805 port->regshift = old_serial_port[i].iomem_reg_shift;
2806 set_io_from_upio(port);
2807 port->irqflags |= irqflag;
2808 if (serial8250_isa_config != NULL)
2809 serial8250_isa_config(i, &up->port, &up->capabilities);
2815 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2817 up->port.type = type;
2818 up->port.fifosize = uart_config[type].fifo_size;
2819 up->capabilities = uart_config[type].flags;
2820 up->tx_loadsz = uart_config[type].tx_loadsz;
2824 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2828 for (i = 0; i < nr_uarts; i++) {
2829 struct uart_8250_port *up = &serial8250_ports[i];
2836 if (up->port.flags & UPF_FIXED_TYPE)
2837 serial8250_init_fixed_type_port(up, up->port.type);
2839 uart_add_one_port(drv, &up->port);
2843 #ifdef CONFIG_SERIAL_8250_CONSOLE
2845 static void serial8250_console_putchar(struct uart_port *port, int ch)
2847 struct uart_8250_port *up =
2848 container_of(port, struct uart_8250_port, port);
2850 wait_for_xmitr(up, UART_LSR_THRE);
2851 serial_port_out(port, UART_TX, ch);
2855 * Print a string to the serial port trying not to disturb
2856 * any possible real use of the port...
2858 * The console_lock must be held when we get here.
2861 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2863 struct uart_8250_port *up = &serial8250_ports[co->index];
2864 struct uart_port *port = &up->port;
2865 unsigned long flags;
2869 touch_nmi_watchdog();
2871 local_irq_save(flags);
2873 /* serial8250_handle_irq() already took the lock */
2875 } else if (oops_in_progress) {
2876 locked = spin_trylock(&port->lock);
2878 spin_lock(&port->lock);
2881 * First save the IER then disable the interrupts
2883 ier = serial_port_in(port, UART_IER);
2885 if (up->capabilities & UART_CAP_UUE)
2886 serial_port_out(port, UART_IER, UART_IER_UUE);
2888 serial_port_out(port, UART_IER, 0);
2890 uart_console_write(port, s, count, serial8250_console_putchar);
2893 * Finally, wait for transmitter to become empty
2894 * and restore the IER
2896 wait_for_xmitr(up, BOTH_EMPTY);
2897 serial_port_out(port, UART_IER, ier);
2900 * The receive handling will happen properly because the
2901 * receive ready bit will still be set; it is not cleared
2902 * on read. However, modem control will not, we must
2903 * call it if we have saved something in the saved flags
2904 * while processing with interrupts off.
2906 if (up->msr_saved_flags)
2907 serial8250_modem_status(up);
2910 spin_unlock(&port->lock);
2911 local_irq_restore(flags);
2914 static int __init serial8250_console_setup(struct console *co, char *options)
2916 struct uart_port *port;
2923 * Check whether an invalid uart number has been specified, and
2924 * if so, search for the first available port that does have
2927 if (co->index >= nr_uarts)
2929 port = &serial8250_ports[co->index].port;
2930 if (!port->iobase && !port->membase)
2934 uart_parse_options(options, &baud, &parity, &bits, &flow);
2936 return uart_set_options(port, co, baud, parity, bits, flow);
2939 static int serial8250_console_early_setup(void)
2941 return serial8250_find_port_for_earlycon();
2944 static struct console serial8250_console = {
2946 .write = serial8250_console_write,
2947 .device = uart_console_device,
2948 .setup = serial8250_console_setup,
2949 .early_setup = serial8250_console_early_setup,
2950 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2952 .data = &serial8250_reg,
2955 static int __init serial8250_console_init(void)
2957 serial8250_isa_init_ports();
2958 register_console(&serial8250_console);
2961 console_initcall(serial8250_console_init);
2963 int serial8250_find_port(struct uart_port *p)
2966 struct uart_port *port;
2968 for (line = 0; line < nr_uarts; line++) {
2969 port = &serial8250_ports[line].port;
2970 if (uart_match_port(p, port))
2976 #define SERIAL8250_CONSOLE &serial8250_console
2978 #define SERIAL8250_CONSOLE NULL
2981 static struct uart_driver serial8250_reg = {
2982 .owner = THIS_MODULE,
2983 .driver_name = "serial",
2987 .cons = SERIAL8250_CONSOLE,
2991 * early_serial_setup - early registration for 8250 ports
2993 * Setup an 8250 port structure prior to console initialisation. Use
2994 * after console initialisation will cause undefined behaviour.
2996 int __init early_serial_setup(struct uart_port *port)
2998 struct uart_port *p;
3000 if (port->line >= ARRAY_SIZE(serial8250_ports))
3003 serial8250_isa_init_ports();
3004 p = &serial8250_ports[port->line].port;
3005 p->iobase = port->iobase;
3006 p->membase = port->membase;
3008 p->irqflags = port->irqflags;
3009 p->uartclk = port->uartclk;
3010 p->fifosize = port->fifosize;
3011 p->regshift = port->regshift;
3012 p->iotype = port->iotype;
3013 p->flags = port->flags;
3014 p->mapbase = port->mapbase;
3015 p->private_data = port->private_data;
3016 p->type = port->type;
3017 p->line = port->line;
3019 set_io_from_upio(p);
3020 if (port->serial_in)
3021 p->serial_in = port->serial_in;
3022 if (port->serial_out)
3023 p->serial_out = port->serial_out;
3024 if (port->handle_irq)
3025 p->handle_irq = port->handle_irq;
3027 p->handle_irq = serial8250_default_handle_irq;
3033 * serial8250_suspend_port - suspend one serial port
3034 * @line: serial line number
3036 * Suspend one serial port.
3038 void serial8250_suspend_port(int line)
3040 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3044 * serial8250_resume_port - resume one serial port
3045 * @line: serial line number
3047 * Resume one serial port.
3049 void serial8250_resume_port(int line)
3051 struct uart_8250_port *up = &serial8250_ports[line];
3052 struct uart_port *port = &up->port;
3054 if (up->capabilities & UART_NATSEMI) {
3055 /* Ensure it's still in high speed mode */
3056 serial_port_out(port, UART_LCR, 0xE0);
3058 ns16550a_goto_highspeed(up);
3060 serial_port_out(port, UART_LCR, 0);
3061 port->uartclk = 921600*16;
3063 uart_resume_port(&serial8250_reg, port);
3067 * Register a set of serial devices attached to a platform device. The
3068 * list is terminated with a zero flags entry, which means we expect
3069 * all entries to have at least UPF_BOOT_AUTOCONF set.
3071 static int serial8250_probe(struct platform_device *dev)
3073 struct plat_serial8250_port *p = dev->dev.platform_data;
3074 struct uart_8250_port uart;
3075 int ret, i, irqflag = 0;
3077 memset(&uart, 0, sizeof(uart));
3080 irqflag = IRQF_SHARED;
3082 for (i = 0; p && p->flags != 0; p++, i++) {
3083 uart.port.iobase = p->iobase;
3084 uart.port.membase = p->membase;
3085 uart.port.irq = p->irq;
3086 uart.port.irqflags = p->irqflags;
3087 uart.port.uartclk = p->uartclk;
3088 uart.port.regshift = p->regshift;
3089 uart.port.iotype = p->iotype;
3090 uart.port.flags = p->flags;
3091 uart.port.mapbase = p->mapbase;
3092 uart.port.hub6 = p->hub6;
3093 uart.port.private_data = p->private_data;
3094 uart.port.type = p->type;
3095 uart.port.serial_in = p->serial_in;
3096 uart.port.serial_out = p->serial_out;
3097 uart.port.handle_irq = p->handle_irq;
3098 uart.port.handle_break = p->handle_break;
3099 uart.port.set_termios = p->set_termios;
3100 uart.port.pm = p->pm;
3101 uart.port.dev = &dev->dev;
3102 uart.port.irqflags |= irqflag;
3103 ret = serial8250_register_8250_port(&uart);
3105 dev_err(&dev->dev, "unable to register port at index %d "
3106 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3107 p->iobase, (unsigned long long)p->mapbase,
3115 * Remove serial ports registered against a platform device.
3117 static int serial8250_remove(struct platform_device *dev)
3121 for (i = 0; i < nr_uarts; i++) {
3122 struct uart_8250_port *up = &serial8250_ports[i];
3124 if (up->port.dev == &dev->dev)
3125 serial8250_unregister_port(i);
3130 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3134 for (i = 0; i < UART_NR; i++) {
3135 struct uart_8250_port *up = &serial8250_ports[i];
3137 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3138 uart_suspend_port(&serial8250_reg, &up->port);
3144 static int serial8250_resume(struct platform_device *dev)
3148 for (i = 0; i < UART_NR; i++) {
3149 struct uart_8250_port *up = &serial8250_ports[i];
3151 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3152 serial8250_resume_port(i);
3158 static struct platform_driver serial8250_isa_driver = {
3159 .probe = serial8250_probe,
3160 .remove = serial8250_remove,
3161 .suspend = serial8250_suspend,
3162 .resume = serial8250_resume,
3164 .name = "serial8250",
3165 .owner = THIS_MODULE,
3170 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3171 * in the table in include/asm/serial.h
3173 static struct platform_device *serial8250_isa_devs;
3176 * serial8250_register_8250_port and serial8250_unregister_port allows for
3177 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3178 * modems and PCI multiport cards.
3180 static DEFINE_MUTEX(serial_mutex);
3182 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3187 * First, find a port entry which matches.
3189 for (i = 0; i < nr_uarts; i++)
3190 if (uart_match_port(&serial8250_ports[i].port, port))
3191 return &serial8250_ports[i];
3194 * We didn't find a matching entry, so look for the first
3195 * free entry. We look for one which hasn't been previously
3196 * used (indicated by zero iobase).
3198 for (i = 0; i < nr_uarts; i++)
3199 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3200 serial8250_ports[i].port.iobase == 0)
3201 return &serial8250_ports[i];
3204 * That also failed. Last resort is to find any entry which
3205 * doesn't have a real port associated with it.
3207 for (i = 0; i < nr_uarts; i++)
3208 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3209 return &serial8250_ports[i];
3215 * serial8250_register_8250_port - register a serial port
3216 * @up: serial port template
3218 * Configure the serial port specified by the request. If the
3219 * port exists and is in use, it is hung up and unregistered
3222 * The port is then probed and if necessary the IRQ is autodetected
3223 * If this fails an error is returned.
3225 * On success the port is ready to use and the line number is returned.
3227 int serial8250_register_8250_port(struct uart_8250_port *up)
3229 struct uart_8250_port *uart;
3232 if (up->port.uartclk == 0)
3235 mutex_lock(&serial_mutex);
3237 uart = serial8250_find_match_or_unused(&up->port);
3238 if (uart && uart->port.type != PORT_8250_CIR) {
3240 uart_remove_one_port(&serial8250_reg, &uart->port);
3242 uart->port.iobase = up->port.iobase;
3243 uart->port.membase = up->port.membase;
3244 uart->port.irq = up->port.irq;
3245 uart->port.irqflags = up->port.irqflags;
3246 uart->port.uartclk = up->port.uartclk;
3247 uart->port.fifosize = up->port.fifosize;
3248 uart->port.regshift = up->port.regshift;
3249 uart->port.iotype = up->port.iotype;
3250 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
3251 uart->bugs = up->bugs;
3252 uart->port.mapbase = up->port.mapbase;
3253 uart->port.private_data = up->port.private_data;
3255 uart->port.dev = up->port.dev;
3257 if (up->port.flags & UPF_FIXED_TYPE)
3258 serial8250_init_fixed_type_port(uart, up->port.type);
3260 set_io_from_upio(&uart->port);
3261 /* Possibly override default I/O functions. */
3262 if (up->port.serial_in)
3263 uart->port.serial_in = up->port.serial_in;
3264 if (up->port.serial_out)
3265 uart->port.serial_out = up->port.serial_out;
3266 if (up->port.handle_irq)
3267 uart->port.handle_irq = up->port.handle_irq;
3268 /* Possibly override set_termios call */
3269 if (up->port.set_termios)
3270 uart->port.set_termios = up->port.set_termios;
3272 uart->port.pm = up->port.pm;
3273 if (up->port.handle_break)
3274 uart->port.handle_break = up->port.handle_break;
3276 uart->dl_read = up->dl_read;
3278 uart->dl_write = up->dl_write;
3280 if (serial8250_isa_config != NULL)
3281 serial8250_isa_config(0, &uart->port,
3282 &uart->capabilities);
3284 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3286 ret = uart->port.line;
3288 mutex_unlock(&serial_mutex);
3292 EXPORT_SYMBOL(serial8250_register_8250_port);
3295 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3296 * @line: serial line number
3298 * Remove one serial port. This may not be called from interrupt
3299 * context. We hand the port back to the our control.
3301 void serial8250_unregister_port(int line)
3303 struct uart_8250_port *uart = &serial8250_ports[line];
3305 mutex_lock(&serial_mutex);
3306 uart_remove_one_port(&serial8250_reg, &uart->port);
3307 if (serial8250_isa_devs) {
3308 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3309 uart->port.type = PORT_UNKNOWN;
3310 uart->port.dev = &serial8250_isa_devs->dev;
3311 uart->capabilities = uart_config[uart->port.type].flags;
3312 uart_add_one_port(&serial8250_reg, &uart->port);
3314 uart->port.dev = NULL;
3316 mutex_unlock(&serial_mutex);
3318 EXPORT_SYMBOL(serial8250_unregister_port);
3320 static int __init serial8250_init(void)
3324 serial8250_isa_init_ports();
3326 printk(KERN_INFO "Serial: 8250/16550 driver, "
3327 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3328 share_irqs ? "en" : "dis");
3331 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3333 serial8250_reg.nr = UART_NR;
3334 ret = uart_register_driver(&serial8250_reg);
3339 ret = serial8250_pnp_init();
3341 goto unreg_uart_drv;
3343 serial8250_isa_devs = platform_device_alloc("serial8250",
3344 PLAT8250_DEV_LEGACY);
3345 if (!serial8250_isa_devs) {
3350 ret = platform_device_add(serial8250_isa_devs);
3354 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3356 ret = platform_driver_register(&serial8250_isa_driver);
3360 platform_device_del(serial8250_isa_devs);
3362 platform_device_put(serial8250_isa_devs);
3364 serial8250_pnp_exit();
3367 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3369 uart_unregister_driver(&serial8250_reg);
3375 static void __exit serial8250_exit(void)
3377 struct platform_device *isa_dev = serial8250_isa_devs;
3380 * This tells serial8250_unregister_port() not to re-register
3381 * the ports (thereby making serial8250_isa_driver permanently
3384 serial8250_isa_devs = NULL;
3386 platform_driver_unregister(&serial8250_isa_driver);
3387 platform_device_unregister(isa_dev);
3389 serial8250_pnp_exit();
3392 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3394 uart_unregister_driver(&serial8250_reg);
3398 module_init(serial8250_init);
3399 module_exit(serial8250_exit);
3401 EXPORT_SYMBOL(serial8250_suspend_port);
3402 EXPORT_SYMBOL(serial8250_resume_port);
3404 MODULE_LICENSE("GPL");
3405 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3407 module_param(share_irqs, uint, 0644);
3408 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3411 module_param(nr_uarts, uint, 0644);
3412 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3414 module_param(skip_txen_test, uint, 0644);
3415 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3417 #ifdef CONFIG_SERIAL_8250_RSA
3418 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3419 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3421 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);