2 * Driver for Motorola IMX serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
49 #include <linux/of_device.h>
53 #include <linux/platform_data/serial-imx.h>
55 /* Register definitions */
56 #define URXD0 0x0 /* Receiver Register */
57 #define URTX0 0x40 /* Transmitter Register */
58 #define UCR1 0x80 /* Control Register 1 */
59 #define UCR2 0x84 /* Control Register 2 */
60 #define UCR3 0x88 /* Control Register 3 */
61 #define UCR4 0x8c /* Control Register 4 */
62 #define UFCR 0x90 /* FIFO Control Register */
63 #define USR1 0x94 /* Status Register 1 */
64 #define USR2 0x98 /* Status Register 2 */
65 #define UESC 0x9c /* Escape Character Register */
66 #define UTIM 0xa0 /* Escape Timer Register */
67 #define UBIR 0xa4 /* BRM Incremental Register */
68 #define UBMR 0xa8 /* BRM Modulator Register */
69 #define UBRC 0xac /* Baud Rate Count Register */
70 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
71 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
72 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
74 /* UART Control Register Bit Fields.*/
75 #define URXD_CHARRDY (1<<15)
76 #define URXD_ERR (1<<14)
77 #define URXD_OVRRUN (1<<13)
78 #define URXD_FRMERR (1<<12)
79 #define URXD_BRK (1<<11)
80 #define URXD_PRERR (1<<10)
81 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
82 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87 #define UCR1_IREN (1<<7) /* Infrared interface enable */
88 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90 #define UCR1_SNDBRK (1<<4) /* Send break */
91 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
93 #define UCR1_DOZE (1<<1) /* Doze */
94 #define UCR1_UARTEN (1<<0) /* UART enabled */
95 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97 #define UCR2_CTSC (1<<13) /* CTS pin control */
98 #define UCR2_CTS (1<<12) /* Clear to send */
99 #define UCR2_ESCEN (1<<11) /* Escape enable */
100 #define UCR2_PREN (1<<8) /* Parity enable */
101 #define UCR2_PROE (1<<7) /* Parity odd/even */
102 #define UCR2_STPB (1<<6) /* Stop */
103 #define UCR2_WS (1<<5) /* Word size */
104 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
106 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
107 #define UCR2_RXEN (1<<1) /* Receiver enabled */
108 #define UCR2_SRST (1<<0) /* SW reset */
109 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
110 #define UCR3_PARERREN (1<<12) /* Parity enable */
111 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
112 #define UCR3_DSR (1<<10) /* Data set ready */
113 #define UCR3_DCD (1<<9) /* Data carrier detect */
114 #define UCR3_RI (1<<8) /* Ring indicator */
115 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
116 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
117 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
118 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
119 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
120 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
121 #define UCR3_BPEN (1<<0) /* Preset registers enable */
122 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
123 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
124 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
125 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
126 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
127 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
128 #define UCR4_IRSC (1<<5) /* IR special case */
129 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
130 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
131 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
132 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
133 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
134 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
135 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
136 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
137 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
138 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
139 #define USR1_RTSS (1<<14) /* RTS pin status */
140 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
141 #define USR1_RTSD (1<<12) /* RTS delta */
142 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
143 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
144 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
145 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
146 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
147 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
148 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
149 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
150 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
151 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
152 #define USR2_IDLE (1<<12) /* Idle condition */
153 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
154 #define USR2_WAKE (1<<7) /* Wake */
155 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
156 #define USR2_TXDC (1<<3) /* Transmitter complete */
157 #define USR2_BRCD (1<<2) /* Break condition */
158 #define USR2_ORE (1<<1) /* Overrun error */
159 #define USR2_RDR (1<<0) /* Recv data ready */
160 #define UTS_FRCPERR (1<<13) /* Force parity error */
161 #define UTS_LOOP (1<<12) /* Loop tx and rx */
162 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
163 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
164 #define UTS_TXFULL (1<<4) /* TxFIFO full */
165 #define UTS_RXFULL (1<<3) /* RxFIFO full */
166 #define UTS_SOFTRST (1<<0) /* Software reset */
168 /* We've been assigned a range on the "Low-density serial ports" major */
169 #define SERIAL_IMX_MAJOR 207
170 #define MINOR_START 16
171 #define DEV_NAME "ttymxc"
174 * This determines how often we check the modem status signals
175 * for any change. They generally aren't connected to an IRQ
176 * so we have to poll them. We also check immediately before
177 * filling the TX fifo incase CTS has been dropped.
179 #define MCTRL_TIMEOUT (250*HZ/1000)
181 #define DRIVER_NAME "IMX-uart"
185 /* i.mx21 type uart runs on all i.mx except i.mx1 */
191 /* device type dependent stuff */
192 struct imx_uart_data {
194 enum imx_uart_type devtype;
198 struct uart_port port;
199 struct timer_list timer;
200 unsigned int old_status;
201 int txirq, rxirq, rtsirq;
202 unsigned int have_rtscts:1;
203 unsigned int dte_mode:1;
204 unsigned int use_irda:1;
205 unsigned int irda_inv_rx:1;
206 unsigned int irda_inv_tx:1;
207 unsigned short trcv_delay; /* transceiver delay */
210 const struct imx_uart_data *devdata;
213 struct imx_port_ucrs {
220 #define USE_IRDA(sport) ((sport)->use_irda)
222 #define USE_IRDA(sport) (0)
225 static struct imx_uart_data imx_uart_devdata[] = {
228 .devtype = IMX1_UART,
231 .uts_reg = IMX21_UTS,
232 .devtype = IMX21_UART,
236 static struct platform_device_id imx_uart_devtype[] = {
239 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
241 .name = "imx21-uart",
242 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
247 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
249 static struct of_device_id imx_uart_dt_ids[] = {
250 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
251 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
254 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
256 static inline unsigned uts_reg(struct imx_port *sport)
258 return sport->devdata->uts_reg;
261 static inline int is_imx1_uart(struct imx_port *sport)
263 return sport->devdata->devtype == IMX1_UART;
266 static inline int is_imx21_uart(struct imx_port *sport)
268 return sport->devdata->devtype == IMX21_UART;
272 * Save and restore functions for UCR1, UCR2 and UCR3 registers
274 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE)
275 static void imx_port_ucrs_save(struct uart_port *port,
276 struct imx_port_ucrs *ucr)
278 /* save control registers */
279 ucr->ucr1 = readl(port->membase + UCR1);
280 ucr->ucr2 = readl(port->membase + UCR2);
281 ucr->ucr3 = readl(port->membase + UCR3);
284 static void imx_port_ucrs_restore(struct uart_port *port,
285 struct imx_port_ucrs *ucr)
287 /* restore control registers */
288 writel(ucr->ucr1, port->membase + UCR1);
289 writel(ucr->ucr2, port->membase + UCR2);
290 writel(ucr->ucr3, port->membase + UCR3);
295 * Handle any change of modem status signal since we were last called.
297 static void imx_mctrl_check(struct imx_port *sport)
299 unsigned int status, changed;
301 status = sport->port.ops->get_mctrl(&sport->port);
302 changed = status ^ sport->old_status;
307 sport->old_status = status;
309 if (changed & TIOCM_RI)
310 sport->port.icount.rng++;
311 if (changed & TIOCM_DSR)
312 sport->port.icount.dsr++;
313 if (changed & TIOCM_CAR)
314 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
315 if (changed & TIOCM_CTS)
316 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
318 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
322 * This is our per-port timeout handler, for checking the
323 * modem status signals.
325 static void imx_timeout(unsigned long data)
327 struct imx_port *sport = (struct imx_port *)data;
330 if (sport->port.state) {
331 spin_lock_irqsave(&sport->port.lock, flags);
332 imx_mctrl_check(sport);
333 spin_unlock_irqrestore(&sport->port.lock, flags);
335 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
340 * interrupts disabled on entry
342 static void imx_stop_tx(struct uart_port *port)
344 struct imx_port *sport = (struct imx_port *)port;
347 if (USE_IRDA(sport)) {
348 /* half duplex - wait for end of transmission */
351 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
356 * irda transceiver - wait a bit more to avoid
357 * cutoff, hardware dependent
359 udelay(sport->trcv_delay);
362 * half duplex - reactivate receive mode,
363 * flush receive pipe echo crap
365 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
366 temp = readl(sport->port.membase + UCR1);
367 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
368 writel(temp, sport->port.membase + UCR1);
370 temp = readl(sport->port.membase + UCR4);
371 temp &= ~(UCR4_TCEN);
372 writel(temp, sport->port.membase + UCR4);
374 while (readl(sport->port.membase + URXD0) &
378 temp = readl(sport->port.membase + UCR1);
380 writel(temp, sport->port.membase + UCR1);
382 temp = readl(sport->port.membase + UCR4);
384 writel(temp, sport->port.membase + UCR4);
389 temp = readl(sport->port.membase + UCR1);
390 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
394 * interrupts disabled on entry
396 static void imx_stop_rx(struct uart_port *port)
398 struct imx_port *sport = (struct imx_port *)port;
401 temp = readl(sport->port.membase + UCR2);
402 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
406 * Set the modem control timer to fire immediately.
408 static void imx_enable_ms(struct uart_port *port)
410 struct imx_port *sport = (struct imx_port *)port;
412 mod_timer(&sport->timer, jiffies);
415 static inline void imx_transmit_buffer(struct imx_port *sport)
417 struct circ_buf *xmit = &sport->port.state->xmit;
419 while (!uart_circ_empty(xmit) &&
420 !(readl(sport->port.membase + uts_reg(sport))
422 /* send xmit->buf[xmit->tail]
423 * out the port here */
424 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
425 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
426 sport->port.icount.tx++;
429 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
430 uart_write_wakeup(&sport->port);
432 if (uart_circ_empty(xmit))
433 imx_stop_tx(&sport->port);
437 * interrupts disabled on entry
439 static void imx_start_tx(struct uart_port *port)
441 struct imx_port *sport = (struct imx_port *)port;
444 if (USE_IRDA(sport)) {
445 /* half duplex in IrDA mode; have to disable receive mode */
446 temp = readl(sport->port.membase + UCR4);
447 temp &= ~(UCR4_DREN);
448 writel(temp, sport->port.membase + UCR4);
450 temp = readl(sport->port.membase + UCR1);
451 temp &= ~(UCR1_RRDYEN);
452 writel(temp, sport->port.membase + UCR1);
454 /* Clear any pending ORE flag before enabling interrupt */
455 temp = readl(sport->port.membase + USR2);
456 writel(temp | USR2_ORE, sport->port.membase + USR2);
458 temp = readl(sport->port.membase + UCR4);
460 writel(temp, sport->port.membase + UCR4);
462 temp = readl(sport->port.membase + UCR1);
463 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
465 if (USE_IRDA(sport)) {
466 temp = readl(sport->port.membase + UCR1);
468 writel(temp, sport->port.membase + UCR1);
470 temp = readl(sport->port.membase + UCR4);
472 writel(temp, sport->port.membase + UCR4);
475 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
476 imx_transmit_buffer(sport);
479 static irqreturn_t imx_rtsint(int irq, void *dev_id)
481 struct imx_port *sport = dev_id;
485 spin_lock_irqsave(&sport->port.lock, flags);
487 writel(USR1_RTSD, sport->port.membase + USR1);
488 val = readl(sport->port.membase + USR1) & USR1_RTSS;
489 uart_handle_cts_change(&sport->port, !!val);
490 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
492 spin_unlock_irqrestore(&sport->port.lock, flags);
496 static irqreturn_t imx_txint(int irq, void *dev_id)
498 struct imx_port *sport = dev_id;
499 struct circ_buf *xmit = &sport->port.state->xmit;
502 spin_lock_irqsave(&sport->port.lock, flags);
503 if (sport->port.x_char) {
505 writel(sport->port.x_char, sport->port.membase + URTX0);
509 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
510 imx_stop_tx(&sport->port);
514 imx_transmit_buffer(sport);
516 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
517 uart_write_wakeup(&sport->port);
520 spin_unlock_irqrestore(&sport->port.lock, flags);
524 static irqreturn_t imx_rxint(int irq, void *dev_id)
526 struct imx_port *sport = dev_id;
527 unsigned int rx, flg, ignored = 0;
528 struct tty_port *port = &sport->port.state->port;
529 unsigned long flags, temp;
531 spin_lock_irqsave(&sport->port.lock, flags);
533 while (readl(sport->port.membase + USR2) & USR2_RDR) {
535 sport->port.icount.rx++;
537 rx = readl(sport->port.membase + URXD0);
539 temp = readl(sport->port.membase + USR2);
540 if (temp & USR2_BRCD) {
541 writel(USR2_BRCD, sport->port.membase + USR2);
542 if (uart_handle_break(&sport->port))
546 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
549 if (unlikely(rx & URXD_ERR)) {
551 sport->port.icount.brk++;
552 else if (rx & URXD_PRERR)
553 sport->port.icount.parity++;
554 else if (rx & URXD_FRMERR)
555 sport->port.icount.frame++;
556 if (rx & URXD_OVRRUN)
557 sport->port.icount.overrun++;
559 if (rx & sport->port.ignore_status_mask) {
565 rx &= sport->port.read_status_mask;
569 else if (rx & URXD_PRERR)
571 else if (rx & URXD_FRMERR)
573 if (rx & URXD_OVRRUN)
577 sport->port.sysrq = 0;
581 tty_insert_flip_char(port, rx, flg);
585 spin_unlock_irqrestore(&sport->port.lock, flags);
586 tty_flip_buffer_push(port);
590 static irqreturn_t imx_int(int irq, void *dev_id)
592 struct imx_port *sport = dev_id;
596 sts = readl(sport->port.membase + USR1);
599 imx_rxint(irq, dev_id);
601 if (sts & USR1_TRDY &&
602 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
603 imx_txint(irq, dev_id);
606 imx_rtsint(irq, dev_id);
608 if (sts & USR1_AWAKE)
609 writel(USR1_AWAKE, sport->port.membase + USR1);
611 sts2 = readl(sport->port.membase + USR2);
612 if (sts2 & USR2_ORE) {
613 dev_err(sport->port.dev, "Rx FIFO overrun\n");
614 sport->port.icount.overrun++;
615 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
622 * Return TIOCSER_TEMT when transmitter is not busy.
624 static unsigned int imx_tx_empty(struct uart_port *port)
626 struct imx_port *sport = (struct imx_port *)port;
628 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
632 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
634 static unsigned int imx_get_mctrl(struct uart_port *port)
636 struct imx_port *sport = (struct imx_port *)port;
637 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
639 if (readl(sport->port.membase + USR1) & USR1_RTSS)
642 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
648 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
650 struct imx_port *sport = (struct imx_port *)port;
653 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
655 if (mctrl & TIOCM_RTS)
658 writel(temp, sport->port.membase + UCR2);
662 * Interrupts always disabled.
664 static void imx_break_ctl(struct uart_port *port, int break_state)
666 struct imx_port *sport = (struct imx_port *)port;
667 unsigned long flags, temp;
669 spin_lock_irqsave(&sport->port.lock, flags);
671 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
673 if (break_state != 0)
676 writel(temp, sport->port.membase + UCR1);
678 spin_unlock_irqrestore(&sport->port.lock, flags);
681 #define TXTL 2 /* reset default */
682 #define RXTL 1 /* reset default */
684 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
688 /* set receiver / transmitter trigger level */
689 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
690 val |= TXTL << UFCR_TXTL_SHF | RXTL;
691 writel(val, sport->port.membase + UFCR);
695 /* half the RX buffer size */
698 static int imx_startup(struct uart_port *port)
700 struct imx_port *sport = (struct imx_port *)port;
702 unsigned long flags, temp;
704 if (!uart_console(port)) {
705 retval = clk_prepare_enable(sport->clk_per);
708 retval = clk_prepare_enable(sport->clk_ipg);
710 clk_disable_unprepare(sport->clk_per);
715 imx_setup_ufcr(sport, 0);
717 /* disable the DREN bit (Data Ready interrupt enable) before
720 temp = readl(sport->port.membase + UCR4);
725 /* set the trigger level for CTS */
726 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
727 temp |= CTSTL << UCR4_CTSTL_SHF;
729 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
731 if (USE_IRDA(sport)) {
732 /* reset fifo's and state machines */
734 temp = readl(sport->port.membase + UCR2);
736 writel(temp, sport->port.membase + UCR2);
737 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
744 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
745 * chips only have one interrupt.
747 if (sport->txirq > 0) {
748 retval = request_irq(sport->rxirq, imx_rxint, 0,
753 retval = request_irq(sport->txirq, imx_txint, 0,
758 /* do not use RTS IRQ on IrDA */
759 if (!USE_IRDA(sport)) {
760 retval = request_irq(sport->rtsirq, imx_rtsint, 0,
766 retval = request_irq(sport->port.irq, imx_int, 0,
769 free_irq(sport->port.irq, sport);
774 spin_lock_irqsave(&sport->port.lock, flags);
776 * Finally, clear and enable interrupts
778 writel(USR1_RTSD, sport->port.membase + USR1);
780 temp = readl(sport->port.membase + UCR1);
781 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
783 if (USE_IRDA(sport)) {
785 temp &= ~(UCR1_RTSDEN);
788 writel(temp, sport->port.membase + UCR1);
790 temp = readl(sport->port.membase + UCR2);
791 temp |= (UCR2_RXEN | UCR2_TXEN);
792 if (!sport->have_rtscts)
794 writel(temp, sport->port.membase + UCR2);
796 if (USE_IRDA(sport)) {
800 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
805 if (is_imx21_uart(sport)) {
806 temp = readl(sport->port.membase + UCR3);
807 temp |= IMX21_UCR3_RXDMUXSEL;
808 writel(temp, sport->port.membase + UCR3);
811 if (USE_IRDA(sport)) {
812 temp = readl(sport->port.membase + UCR4);
813 if (sport->irda_inv_rx)
816 temp &= ~(UCR4_INVR);
817 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
819 temp = readl(sport->port.membase + UCR3);
820 if (sport->irda_inv_tx)
823 temp &= ~(UCR3_INVT);
824 writel(temp, sport->port.membase + UCR3);
828 * Enable modem status interrupts
830 imx_enable_ms(&sport->port);
831 spin_unlock_irqrestore(&sport->port.lock, flags);
833 if (USE_IRDA(sport)) {
834 struct imxuart_platform_data *pdata;
835 pdata = sport->port.dev->platform_data;
836 sport->irda_inv_rx = pdata->irda_inv_rx;
837 sport->irda_inv_tx = pdata->irda_inv_tx;
838 sport->trcv_delay = pdata->transceiver_delay;
839 if (pdata->irda_enable)
840 pdata->irda_enable(1);
847 free_irq(sport->txirq, sport);
850 free_irq(sport->rxirq, sport);
855 static void imx_shutdown(struct uart_port *port)
857 struct imx_port *sport = (struct imx_port *)port;
861 spin_lock_irqsave(&sport->port.lock, flags);
862 temp = readl(sport->port.membase + UCR2);
863 temp &= ~(UCR2_TXEN);
864 writel(temp, sport->port.membase + UCR2);
865 spin_unlock_irqrestore(&sport->port.lock, flags);
867 if (USE_IRDA(sport)) {
868 struct imxuart_platform_data *pdata;
869 pdata = sport->port.dev->platform_data;
870 if (pdata->irda_enable)
871 pdata->irda_enable(0);
877 del_timer_sync(&sport->timer);
880 * Free the interrupts
882 if (sport->txirq > 0) {
883 if (!USE_IRDA(sport))
884 free_irq(sport->rtsirq, sport);
885 free_irq(sport->txirq, sport);
886 free_irq(sport->rxirq, sport);
888 free_irq(sport->port.irq, sport);
891 * Disable all interrupts, port and break condition.
894 spin_lock_irqsave(&sport->port.lock, flags);
895 temp = readl(sport->port.membase + UCR1);
896 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
898 temp &= ~(UCR1_IREN);
900 writel(temp, sport->port.membase + UCR1);
901 spin_unlock_irqrestore(&sport->port.lock, flags);
903 if (!uart_console(&sport->port)) {
904 clk_disable_unprepare(sport->clk_per);
905 clk_disable_unprepare(sport->clk_ipg);
910 imx_set_termios(struct uart_port *port, struct ktermios *termios,
911 struct ktermios *old)
913 struct imx_port *sport = (struct imx_port *)port;
915 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
916 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
917 unsigned int div, ufcr;
918 unsigned long num, denom;
922 * If we don't support modem control lines, don't allow
926 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
927 termios->c_cflag |= CLOCAL;
931 * We only support CS7 and CS8.
933 while ((termios->c_cflag & CSIZE) != CS7 &&
934 (termios->c_cflag & CSIZE) != CS8) {
935 termios->c_cflag &= ~CSIZE;
936 termios->c_cflag |= old_csize;
940 if ((termios->c_cflag & CSIZE) == CS8)
941 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
943 ucr2 = UCR2_SRST | UCR2_IRTS;
945 if (termios->c_cflag & CRTSCTS) {
946 if (sport->have_rtscts) {
950 termios->c_cflag &= ~CRTSCTS;
954 if (termios->c_cflag & CSTOPB)
956 if (termios->c_cflag & PARENB) {
958 if (termios->c_cflag & PARODD)
962 del_timer_sync(&sport->timer);
965 * Ask the core to calculate the divisor for us.
967 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
968 quot = uart_get_divisor(port, baud);
970 spin_lock_irqsave(&sport->port.lock, flags);
972 sport->port.read_status_mask = 0;
973 if (termios->c_iflag & INPCK)
974 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
975 if (termios->c_iflag & (BRKINT | PARMRK))
976 sport->port.read_status_mask |= URXD_BRK;
979 * Characters to ignore
981 sport->port.ignore_status_mask = 0;
982 if (termios->c_iflag & IGNPAR)
983 sport->port.ignore_status_mask |= URXD_PRERR;
984 if (termios->c_iflag & IGNBRK) {
985 sport->port.ignore_status_mask |= URXD_BRK;
987 * If we're ignoring parity and break indicators,
988 * ignore overruns too (for real raw support).
990 if (termios->c_iflag & IGNPAR)
991 sport->port.ignore_status_mask |= URXD_OVRRUN;
995 * Update the per-port timeout.
997 uart_update_timeout(port, termios->c_cflag, baud);
1000 * disable interrupts and drain transmitter
1002 old_ucr1 = readl(sport->port.membase + UCR1);
1003 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1004 sport->port.membase + UCR1);
1006 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1009 /* then, disable everything */
1010 old_txrxen = readl(sport->port.membase + UCR2);
1011 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1012 sport->port.membase + UCR2);
1013 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1015 if (USE_IRDA(sport)) {
1017 * use maximum available submodule frequency to
1018 * avoid missing short pulses due to low sampling rate
1022 div = sport->port.uartclk / (baud * 16);
1029 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1030 1 << 16, 1 << 16, &num, &denom);
1032 tdiv64 = sport->port.uartclk;
1034 do_div(tdiv64, denom * 16 * div);
1035 tty_termios_encode_baud_rate(termios,
1036 (speed_t)tdiv64, (speed_t)tdiv64);
1041 ufcr = readl(sport->port.membase + UFCR);
1042 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1043 if (sport->dte_mode)
1044 ufcr |= UFCR_DCEDTE;
1045 writel(ufcr, sport->port.membase + UFCR);
1047 writel(num, sport->port.membase + UBIR);
1048 writel(denom, sport->port.membase + UBMR);
1050 if (is_imx21_uart(sport))
1051 writel(sport->port.uartclk / div / 1000,
1052 sport->port.membase + IMX21_ONEMS);
1054 writel(old_ucr1, sport->port.membase + UCR1);
1056 /* set the parity, stop bits and data size */
1057 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1059 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1060 imx_enable_ms(&sport->port);
1062 spin_unlock_irqrestore(&sport->port.lock, flags);
1065 static const char *imx_type(struct uart_port *port)
1067 struct imx_port *sport = (struct imx_port *)port;
1069 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1073 * Release the memory region(s) being used by 'port'.
1075 static void imx_release_port(struct uart_port *port)
1077 struct platform_device *pdev = to_platform_device(port->dev);
1078 struct resource *mmres;
1080 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1081 release_mem_region(mmres->start, resource_size(mmres));
1085 * Request the memory region(s) being used by 'port'.
1087 static int imx_request_port(struct uart_port *port)
1089 struct platform_device *pdev = to_platform_device(port->dev);
1090 struct resource *mmres;
1093 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1097 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1099 return ret ? 0 : -EBUSY;
1103 * Configure/autoconfigure the port.
1105 static void imx_config_port(struct uart_port *port, int flags)
1107 struct imx_port *sport = (struct imx_port *)port;
1109 if (flags & UART_CONFIG_TYPE &&
1110 imx_request_port(&sport->port) == 0)
1111 sport->port.type = PORT_IMX;
1115 * Verify the new serial_struct (for TIOCSSERIAL).
1116 * The only change we allow are to the flags and type, and
1117 * even then only between PORT_IMX and PORT_UNKNOWN
1120 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1122 struct imx_port *sport = (struct imx_port *)port;
1125 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1127 if (sport->port.irq != ser->irq)
1129 if (ser->io_type != UPIO_MEM)
1131 if (sport->port.uartclk / 16 != ser->baud_base)
1133 if ((void *)sport->port.mapbase != ser->iomem_base)
1135 if (sport->port.iobase != ser->port)
1142 #if defined(CONFIG_CONSOLE_POLL)
1143 static int imx_poll_get_char(struct uart_port *port)
1145 struct imx_port_ucrs old_ucr;
1146 unsigned int status;
1149 /* save control registers */
1150 imx_port_ucrs_save(port, &old_ucr);
1152 /* disable interrupts */
1153 writel(UCR1_UARTEN, port->membase + UCR1);
1154 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1155 port->membase + UCR2);
1156 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1157 port->membase + UCR3);
1161 status = readl(port->membase + USR2);
1162 } while (~status & USR2_RDR);
1165 c = readl(port->membase + URXD0);
1167 /* restore control registers */
1168 imx_port_ucrs_restore(port, &old_ucr);
1173 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1175 struct imx_port_ucrs old_ucr;
1176 unsigned int status;
1178 /* save control registers */
1179 imx_port_ucrs_save(port, &old_ucr);
1181 /* disable interrupts */
1182 writel(UCR1_UARTEN, port->membase + UCR1);
1183 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1184 port->membase + UCR2);
1185 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1186 port->membase + UCR3);
1190 status = readl(port->membase + USR1);
1191 } while (~status & USR1_TRDY);
1194 writel(c, port->membase + URTX0);
1198 status = readl(port->membase + USR2);
1199 } while (~status & USR2_TXDC);
1201 /* restore control registers */
1202 imx_port_ucrs_restore(port, &old_ucr);
1206 static struct uart_ops imx_pops = {
1207 .tx_empty = imx_tx_empty,
1208 .set_mctrl = imx_set_mctrl,
1209 .get_mctrl = imx_get_mctrl,
1210 .stop_tx = imx_stop_tx,
1211 .start_tx = imx_start_tx,
1212 .stop_rx = imx_stop_rx,
1213 .enable_ms = imx_enable_ms,
1214 .break_ctl = imx_break_ctl,
1215 .startup = imx_startup,
1216 .shutdown = imx_shutdown,
1217 .set_termios = imx_set_termios,
1219 .release_port = imx_release_port,
1220 .request_port = imx_request_port,
1221 .config_port = imx_config_port,
1222 .verify_port = imx_verify_port,
1223 #if defined(CONFIG_CONSOLE_POLL)
1224 .poll_get_char = imx_poll_get_char,
1225 .poll_put_char = imx_poll_put_char,
1229 static struct imx_port *imx_ports[UART_NR];
1231 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1232 static void imx_console_putchar(struct uart_port *port, int ch)
1234 struct imx_port *sport = (struct imx_port *)port;
1236 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1239 writel(ch, sport->port.membase + URTX0);
1243 * Interrupts are disabled on entering
1246 imx_console_write(struct console *co, const char *s, unsigned int count)
1248 struct imx_port *sport = imx_ports[co->index];
1249 struct imx_port_ucrs old_ucr;
1251 unsigned long flags = 0;
1254 if (sport->port.sysrq)
1256 else if (oops_in_progress)
1257 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1259 spin_lock_irqsave(&sport->port.lock, flags);
1262 * First, save UCR1/2/3 and then disable interrupts
1264 imx_port_ucrs_save(&sport->port, &old_ucr);
1265 ucr1 = old_ucr.ucr1;
1267 if (is_imx1_uart(sport))
1268 ucr1 |= IMX1_UCR1_UARTCLKEN;
1269 ucr1 |= UCR1_UARTEN;
1270 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1272 writel(ucr1, sport->port.membase + UCR1);
1274 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1276 uart_console_write(&sport->port, s, count, imx_console_putchar);
1279 * Finally, wait for transmitter to become empty
1280 * and restore UCR1/2/3
1282 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1284 imx_port_ucrs_restore(&sport->port, &old_ucr);
1287 spin_unlock_irqrestore(&sport->port.lock, flags);
1291 * If the port was already initialised (eg, by a boot loader),
1292 * try to determine the current setup.
1295 imx_console_get_options(struct imx_port *sport, int *baud,
1296 int *parity, int *bits)
1299 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1300 /* ok, the port was enabled */
1301 unsigned int ucr2, ubir, ubmr, uartclk;
1302 unsigned int baud_raw;
1303 unsigned int ucfr_rfdiv;
1305 ucr2 = readl(sport->port.membase + UCR2);
1308 if (ucr2 & UCR2_PREN) {
1309 if (ucr2 & UCR2_PROE)
1320 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1321 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1323 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1324 if (ucfr_rfdiv == 6)
1327 ucfr_rfdiv = 6 - ucfr_rfdiv;
1329 uartclk = clk_get_rate(sport->clk_per);
1330 uartclk /= ucfr_rfdiv;
1333 * The next code provides exact computation of
1334 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1335 * without need of float support or long long division,
1336 * which would be required to prevent 32bit arithmetic overflow
1338 unsigned int mul = ubir + 1;
1339 unsigned int div = 16 * (ubmr + 1);
1340 unsigned int rem = uartclk % div;
1342 baud_raw = (uartclk / div) * mul;
1343 baud_raw += (rem * mul + div / 2) / div;
1344 *baud = (baud_raw + 50) / 100 * 100;
1347 if (*baud != baud_raw)
1348 pr_info("Console IMX rounded baud rate from %d to %d\n",
1354 imx_console_setup(struct console *co, char *options)
1356 struct imx_port *sport;
1363 * Check whether an invalid uart number has been specified, and
1364 * if so, search for the first available port that does have
1367 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1369 sport = imx_ports[co->index];
1374 uart_parse_options(options, &baud, &parity, &bits, &flow);
1376 imx_console_get_options(sport, &baud, &parity, &bits);
1378 imx_setup_ufcr(sport, 0);
1380 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1383 static struct uart_driver imx_reg;
1384 static struct console imx_console = {
1386 .write = imx_console_write,
1387 .device = uart_console_device,
1388 .setup = imx_console_setup,
1389 .flags = CON_PRINTBUFFER,
1394 #define IMX_CONSOLE &imx_console
1396 #define IMX_CONSOLE NULL
1399 static struct uart_driver imx_reg = {
1400 .owner = THIS_MODULE,
1401 .driver_name = DRIVER_NAME,
1402 .dev_name = DEV_NAME,
1403 .major = SERIAL_IMX_MAJOR,
1404 .minor = MINOR_START,
1405 .nr = ARRAY_SIZE(imx_ports),
1406 .cons = IMX_CONSOLE,
1409 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1411 struct imx_port *sport = platform_get_drvdata(dev);
1414 /* enable wakeup from i.MX UART */
1415 val = readl(sport->port.membase + UCR3);
1417 writel(val, sport->port.membase + UCR3);
1419 uart_suspend_port(&imx_reg, &sport->port);
1424 static int serial_imx_resume(struct platform_device *dev)
1426 struct imx_port *sport = platform_get_drvdata(dev);
1429 /* disable wakeup from i.MX UART */
1430 val = readl(sport->port.membase + UCR3);
1431 val &= ~UCR3_AWAKEN;
1432 writel(val, sport->port.membase + UCR3);
1434 uart_resume_port(&imx_reg, &sport->port);
1441 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1442 * could successfully get all information from dt or a negative errno.
1444 static int serial_imx_probe_dt(struct imx_port *sport,
1445 struct platform_device *pdev)
1447 struct device_node *np = pdev->dev.of_node;
1448 const struct of_device_id *of_id =
1449 of_match_device(imx_uart_dt_ids, &pdev->dev);
1453 /* no device tree device */
1456 ret = of_alias_get_id(np, "serial");
1458 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1461 sport->port.line = ret;
1463 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1464 sport->have_rtscts = 1;
1466 if (of_get_property(np, "fsl,irda-mode", NULL))
1467 sport->use_irda = 1;
1469 if (of_get_property(np, "fsl,dte-mode", NULL))
1470 sport->dte_mode = 1;
1472 sport->devdata = of_id->data;
1477 static inline int serial_imx_probe_dt(struct imx_port *sport,
1478 struct platform_device *pdev)
1484 static void serial_imx_probe_pdata(struct imx_port *sport,
1485 struct platform_device *pdev)
1487 struct imxuart_platform_data *pdata = pdev->dev.platform_data;
1489 sport->port.line = pdev->id;
1490 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1495 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1496 sport->have_rtscts = 1;
1498 if (pdata->flags & IMXUART_IRDA)
1499 sport->use_irda = 1;
1502 static int serial_imx_probe(struct platform_device *pdev)
1504 struct imx_port *sport;
1505 struct imxuart_platform_data *pdata;
1508 struct resource *res;
1510 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1514 ret = serial_imx_probe_dt(sport, pdev);
1516 serial_imx_probe_pdata(sport, pdev);
1520 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1524 base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE);
1528 sport->port.dev = &pdev->dev;
1529 sport->port.mapbase = res->start;
1530 sport->port.membase = base;
1531 sport->port.type = PORT_IMX,
1532 sport->port.iotype = UPIO_MEM;
1533 sport->port.irq = platform_get_irq(pdev, 0);
1534 sport->rxirq = platform_get_irq(pdev, 0);
1535 sport->txirq = platform_get_irq(pdev, 1);
1536 sport->rtsirq = platform_get_irq(pdev, 2);
1537 sport->port.fifosize = 32;
1538 sport->port.ops = &imx_pops;
1539 sport->port.flags = UPF_BOOT_AUTOCONF;
1540 init_timer(&sport->timer);
1541 sport->timer.function = imx_timeout;
1542 sport->timer.data = (unsigned long)sport;
1544 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1545 if (IS_ERR(sport->clk_ipg)) {
1546 ret = PTR_ERR(sport->clk_ipg);
1547 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1551 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1552 if (IS_ERR(sport->clk_per)) {
1553 ret = PTR_ERR(sport->clk_per);
1554 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1558 clk_prepare_enable(sport->clk_per);
1559 clk_prepare_enable(sport->clk_ipg);
1561 sport->port.uartclk = clk_get_rate(sport->clk_per);
1563 imx_ports[sport->port.line] = sport;
1565 pdata = pdev->dev.platform_data;
1566 if (pdata && pdata->init) {
1567 ret = pdata->init(pdev);
1572 ret = uart_add_one_port(&imx_reg, &sport->port);
1575 platform_set_drvdata(pdev, sport);
1577 if (!uart_console(&sport->port)) {
1578 clk_disable_unprepare(sport->clk_per);
1579 clk_disable_unprepare(sport->clk_ipg);
1584 if (pdata && pdata->exit)
1587 clk_disable_unprepare(sport->clk_per);
1588 clk_disable_unprepare(sport->clk_ipg);
1592 static int serial_imx_remove(struct platform_device *pdev)
1594 struct imxuart_platform_data *pdata;
1595 struct imx_port *sport = platform_get_drvdata(pdev);
1597 pdata = pdev->dev.platform_data;
1599 platform_set_drvdata(pdev, NULL);
1601 uart_remove_one_port(&imx_reg, &sport->port);
1603 if (pdata && pdata->exit)
1609 static struct platform_driver serial_imx_driver = {
1610 .probe = serial_imx_probe,
1611 .remove = serial_imx_remove,
1613 .suspend = serial_imx_suspend,
1614 .resume = serial_imx_resume,
1615 .id_table = imx_uart_devtype,
1618 .owner = THIS_MODULE,
1619 .of_match_table = imx_uart_dt_ids,
1623 static int __init imx_serial_init(void)
1627 pr_info("Serial: IMX driver\n");
1629 ret = uart_register_driver(&imx_reg);
1633 ret = platform_driver_register(&serial_imx_driver);
1635 uart_unregister_driver(&imx_reg);
1640 static void __exit imx_serial_exit(void)
1642 platform_driver_unregister(&serial_imx_driver);
1643 uart_unregister_driver(&imx_reg);
1646 module_init(imx_serial_init);
1647 module_exit(imx_serial_exit);
1649 MODULE_AUTHOR("Sascha Hauer");
1650 MODULE_DESCRIPTION("IMX generic serial port driver");
1651 MODULE_LICENSE("GPL");
1652 MODULE_ALIAS("platform:imx-uart");