2 * Device driver for Microgate SyncLink GT serial adapters.
4 * written by Paul Fulghum for Microgate Corporation
7 * Microgate and SyncLink are trademarks of Microgate Corporation
9 * This code is released under the GNU General Public License (GPL)
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
21 * OF THE POSSIBILITY OF SUCH DAMAGE.
25 * DEBUG OUTPUT DEFINITIONS
27 * uncomment lines below to enable specific types of debug output
29 * DBGINFO information - most verbose output
30 * DBGERR serious errors
31 * DBGBH bottom half service routine debugging
32 * DBGISR interrupt service routine debugging
33 * DBGDATA output receive and transmit data
34 * DBGTBUF output transmit DMA buffers and registers
35 * DBGRBUF output receive DMA buffers and registers
38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
43 /*#define DBGTBUF(info) dump_tbufs(info)*/
44 /*#define DBGRBUF(info) dump_rbufs(info)*/
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/signal.h>
50 #include <linux/sched.h>
51 #include <linux/timer.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/tty.h>
55 #include <linux/tty_flip.h>
56 #include <linux/serial.h>
57 #include <linux/major.h>
58 #include <linux/string.h>
59 #include <linux/fcntl.h>
60 #include <linux/ptrace.h>
61 #include <linux/ioport.h>
63 #include <linux/seq_file.h>
64 #include <linux/slab.h>
65 #include <linux/netdevice.h>
66 #include <linux/vmalloc.h>
67 #include <linux/init.h>
68 #include <linux/delay.h>
69 #include <linux/ioctl.h>
70 #include <linux/termios.h>
71 #include <linux/bitops.h>
72 #include <linux/workqueue.h>
73 #include <linux/hdlc.h>
74 #include <linux/synclink.h>
79 #include <asm/types.h>
80 #include <asm/uaccess.h>
82 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
83 #define SYNCLINK_GENERIC_HDLC 1
85 #define SYNCLINK_GENERIC_HDLC 0
89 * module identification
91 static char *driver_name = "SyncLink GT";
92 static char *tty_driver_name = "synclink_gt";
93 static char *tty_dev_prefix = "ttySLG";
94 MODULE_LICENSE("GPL");
95 #define MGSL_MAGIC 0x5401
96 #define MAX_DEVICES 32
98 static struct pci_device_id pci_table[] = {
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {0,}, /* terminate list */
105 MODULE_DEVICE_TABLE(pci, pci_table);
107 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
108 static void remove_one(struct pci_dev *dev);
109 static struct pci_driver pci_driver = {
110 .name = "synclink_gt",
111 .id_table = pci_table,
113 .remove = remove_one,
116 static bool pci_registered;
119 * module configuration and status
121 static struct slgt_info *slgt_device_list;
122 static int slgt_device_count;
125 static int debug_level;
126 static int maxframe[MAX_DEVICES];
128 module_param(ttymajor, int, 0);
129 module_param(debug_level, int, 0);
130 module_param_array(maxframe, int, NULL, 0);
132 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
133 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
134 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
137 * tty support and callbacks
139 static struct tty_driver *serial_driver;
141 static int open(struct tty_struct *tty, struct file * filp);
142 static void close(struct tty_struct *tty, struct file * filp);
143 static void hangup(struct tty_struct *tty);
144 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
146 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
147 static int put_char(struct tty_struct *tty, unsigned char ch);
148 static void send_xchar(struct tty_struct *tty, char ch);
149 static void wait_until_sent(struct tty_struct *tty, int timeout);
150 static int write_room(struct tty_struct *tty);
151 static void flush_chars(struct tty_struct *tty);
152 static void flush_buffer(struct tty_struct *tty);
153 static void tx_hold(struct tty_struct *tty);
154 static void tx_release(struct tty_struct *tty);
156 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
157 static int chars_in_buffer(struct tty_struct *tty);
158 static void throttle(struct tty_struct * tty);
159 static void unthrottle(struct tty_struct * tty);
160 static int set_break(struct tty_struct *tty, int break_state);
163 * generic HDLC support and callbacks
165 #if SYNCLINK_GENERIC_HDLC
166 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
167 static void hdlcdev_tx_done(struct slgt_info *info);
168 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
169 static int hdlcdev_init(struct slgt_info *info);
170 static void hdlcdev_exit(struct slgt_info *info);
175 * device specific structures, macros and functions
178 #define SLGT_MAX_PORTS 4
179 #define SLGT_REG_SIZE 256
182 * conditional wait facility
185 struct cond_wait *next;
190 static void init_cond_wait(struct cond_wait *w, unsigned int data);
191 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
192 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
193 static void flush_cond_wait(struct cond_wait **head);
196 * DMA buffer descriptor and access macros
202 __le32 pbuf; /* physical address of data buffer */
203 __le32 next; /* physical address of next descriptor */
205 /* driver book keeping */
206 char *buf; /* virtual address of data buffer */
207 unsigned int pdesc; /* physical address of this descriptor */
208 dma_addr_t buf_dma_addr;
209 unsigned short buf_count;
212 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
213 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
214 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
215 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
216 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
217 #define desc_count(a) (le16_to_cpu((a).count))
218 #define desc_status(a) (le16_to_cpu((a).status))
219 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
220 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
221 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
222 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
223 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
225 struct _input_signal_events {
237 * device instance data structure
240 void *if_ptr; /* General purpose pointer (used by SPPP) */
241 struct tty_port port;
243 struct slgt_info *next_device; /* device list link */
247 char device_name[25];
248 struct pci_dev *pdev;
250 int port_count; /* count of ports on adapter */
251 int adapter_num; /* adapter instance number */
252 int port_num; /* port instance number */
254 /* array of pointers to port contexts on this adapter */
255 struct slgt_info *port_array[SLGT_MAX_PORTS];
257 int line; /* tty line instance number */
259 struct mgsl_icount icount;
262 int x_char; /* xon/xoff character */
263 unsigned int read_status_mask;
264 unsigned int ignore_status_mask;
266 wait_queue_head_t status_event_wait_q;
267 wait_queue_head_t event_wait_q;
268 struct timer_list tx_timer;
269 struct timer_list rx_timer;
271 unsigned int gpio_present;
272 struct cond_wait *gpio_wait_q;
274 spinlock_t lock; /* spinlock for synchronizing with ISR */
276 struct work_struct task;
282 bool irq_requested; /* true if IRQ requested */
283 bool irq_occurred; /* for diagnostics use */
285 /* device configuration */
287 unsigned int bus_type;
288 unsigned int irq_level;
289 unsigned long irq_flags;
291 unsigned char __iomem * reg_addr; /* memory mapped registers address */
293 bool reg_addr_requested;
295 MGSL_PARAMS params; /* communications parameters */
297 u32 max_frame_size; /* as set by device config */
299 unsigned int rbuf_fill_level;
301 unsigned int if_mode;
302 unsigned int base_clock;
314 unsigned char signals; /* serial signal states */
315 int init_error; /* initialization error */
317 unsigned char *tx_buf;
321 bool drop_rts_on_tx_done;
322 struct _input_signal_events input_signal_events;
324 int dcd_chkcount; /* check counts to prevent */
325 int cts_chkcount; /* too many IRQs if a signal */
326 int dsr_chkcount; /* is floating */
329 char *bufs; /* virtual address of DMA buffer lists */
330 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
332 unsigned int rbuf_count;
333 struct slgt_desc *rbufs;
334 unsigned int rbuf_current;
335 unsigned int rbuf_index;
336 unsigned int rbuf_fill_index;
337 unsigned short rbuf_fill_count;
339 unsigned int tbuf_count;
340 struct slgt_desc *tbufs;
341 unsigned int tbuf_current;
342 unsigned int tbuf_start;
344 unsigned char *tmp_rbuf;
345 unsigned int tmp_rbuf_count;
347 /* SPPP/Cisco HDLC device parts */
351 #if SYNCLINK_GENERIC_HDLC
352 struct net_device *netdev;
357 static MGSL_PARAMS default_params = {
358 .mode = MGSL_MODE_HDLC,
360 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
361 .encoding = HDLC_ENCODING_NRZI_SPACE,
364 .crc_type = HDLC_CRC_16_CCITT,
365 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
366 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
370 .parity = ASYNC_PARITY_NONE
375 #define BH_TRANSMIT 2
377 #define IO_PIN_SHUTDOWN_LIMIT 100
379 #define DMABUFSIZE 256
380 #define DESC_LIST_SIZE 4096
382 #define MASK_PARITY BIT1
383 #define MASK_FRAMING BIT0
384 #define MASK_BREAK BIT14
385 #define MASK_OVERRUN BIT4
387 #define GSR 0x00 /* global status */
388 #define JCR 0x04 /* JTAG control */
389 #define IODR 0x08 /* GPIO direction */
390 #define IOER 0x0c /* GPIO interrupt enable */
391 #define IOVR 0x10 /* GPIO value */
392 #define IOSR 0x14 /* GPIO interrupt status */
393 #define TDR 0x80 /* tx data */
394 #define RDR 0x80 /* rx data */
395 #define TCR 0x82 /* tx control */
396 #define TIR 0x84 /* tx idle */
397 #define TPR 0x85 /* tx preamble */
398 #define RCR 0x86 /* rx control */
399 #define VCR 0x88 /* V.24 control */
400 #define CCR 0x89 /* clock control */
401 #define BDR 0x8a /* baud divisor */
402 #define SCR 0x8c /* serial control */
403 #define SSR 0x8e /* serial status */
404 #define RDCSR 0x90 /* rx DMA control/status */
405 #define TDCSR 0x94 /* tx DMA control/status */
406 #define RDDAR 0x98 /* rx DMA descriptor address */
407 #define TDDAR 0x9c /* tx DMA descriptor address */
408 #define XSR 0x40 /* extended sync pattern */
409 #define XCR 0x44 /* extended control */
412 #define RXBREAK BIT14
413 #define IRQ_TXDATA BIT13
414 #define IRQ_TXIDLE BIT12
415 #define IRQ_TXUNDER BIT11 /* HDLC */
416 #define IRQ_RXDATA BIT10
417 #define IRQ_RXIDLE BIT9 /* HDLC */
418 #define IRQ_RXBREAK BIT9 /* async */
419 #define IRQ_RXOVER BIT8
424 #define IRQ_ALL 0x3ff0
425 #define IRQ_MASTER BIT0
427 #define slgt_irq_on(info, mask) \
428 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
429 #define slgt_irq_off(info, mask) \
430 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
432 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
433 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
435 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
437 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
439 static void msc_set_vcr(struct slgt_info *info);
441 static int startup(struct slgt_info *info);
442 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
443 static void shutdown(struct slgt_info *info);
444 static void program_hw(struct slgt_info *info);
445 static void change_params(struct slgt_info *info);
447 static int register_test(struct slgt_info *info);
448 static int irq_test(struct slgt_info *info);
449 static int loopback_test(struct slgt_info *info);
450 static int adapter_test(struct slgt_info *info);
452 static void reset_adapter(struct slgt_info *info);
453 static void reset_port(struct slgt_info *info);
454 static void async_mode(struct slgt_info *info);
455 static void sync_mode(struct slgt_info *info);
457 static void rx_stop(struct slgt_info *info);
458 static void rx_start(struct slgt_info *info);
459 static void reset_rbufs(struct slgt_info *info);
460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
461 static void rdma_reset(struct slgt_info *info);
462 static bool rx_get_frame(struct slgt_info *info);
463 static bool rx_get_buf(struct slgt_info *info);
465 static void tx_start(struct slgt_info *info);
466 static void tx_stop(struct slgt_info *info);
467 static void tx_set_idle(struct slgt_info *info);
468 static unsigned int free_tbuf_count(struct slgt_info *info);
469 static unsigned int tbuf_bytes(struct slgt_info *info);
470 static void reset_tbufs(struct slgt_info *info);
471 static void tdma_reset(struct slgt_info *info);
472 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
474 static void get_signals(struct slgt_info *info);
475 static void set_signals(struct slgt_info *info);
476 static void enable_loopback(struct slgt_info *info);
477 static void set_rate(struct slgt_info *info, u32 data_rate);
479 static int bh_action(struct slgt_info *info);
480 static void bh_handler(struct work_struct *work);
481 static void bh_transmit(struct slgt_info *info);
482 static void isr_serial(struct slgt_info *info);
483 static void isr_rdma(struct slgt_info *info);
484 static void isr_txeom(struct slgt_info *info, unsigned short status);
485 static void isr_tdma(struct slgt_info *info);
487 static int alloc_dma_bufs(struct slgt_info *info);
488 static void free_dma_bufs(struct slgt_info *info);
489 static int alloc_desc(struct slgt_info *info);
490 static void free_desc(struct slgt_info *info);
491 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
494 static int alloc_tmp_rbuf(struct slgt_info *info);
495 static void free_tmp_rbuf(struct slgt_info *info);
497 static void tx_timeout(unsigned long context);
498 static void rx_timeout(unsigned long context);
503 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
504 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
505 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
506 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
507 static int set_txidle(struct slgt_info *info, int idle_mode);
508 static int tx_enable(struct slgt_info *info, int enable);
509 static int tx_abort(struct slgt_info *info);
510 static int rx_enable(struct slgt_info *info, int enable);
511 static int modem_input_wait(struct slgt_info *info,int arg);
512 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
513 static int tiocmget(struct tty_struct *tty);
514 static int tiocmset(struct tty_struct *tty,
515 unsigned int set, unsigned int clear);
516 static int set_break(struct tty_struct *tty, int break_state);
517 static int get_interface(struct slgt_info *info, int __user *if_mode);
518 static int set_interface(struct slgt_info *info, int if_mode);
519 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
521 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
522 static int get_xsync(struct slgt_info *info, int __user *if_mode);
523 static int set_xsync(struct slgt_info *info, int if_mode);
524 static int get_xctrl(struct slgt_info *info, int __user *if_mode);
525 static int set_xctrl(struct slgt_info *info, int if_mode);
530 static void add_device(struct slgt_info *info);
531 static void device_init(int adapter_num, struct pci_dev *pdev);
532 static int claim_resources(struct slgt_info *info);
533 static void release_resources(struct slgt_info *info);
552 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
556 printk("%s %s data:\n",info->device_name, label);
558 linecount = (count > 16) ? 16 : count;
559 for(i=0; i < linecount; i++)
560 printk("%02X ",(unsigned char)data[i]);
563 for(i=0;i<linecount;i++) {
564 if (data[i]>=040 && data[i]<=0176)
565 printk("%c",data[i]);
575 #define DBGDATA(info, buf, size, label)
579 static void dump_tbufs(struct slgt_info *info)
582 printk("tbuf_current=%d\n", info->tbuf_current);
583 for (i=0 ; i < info->tbuf_count ; i++) {
584 printk("%d: count=%04X status=%04X\n",
585 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
589 #define DBGTBUF(info)
593 static void dump_rbufs(struct slgt_info *info)
596 printk("rbuf_current=%d\n", info->rbuf_current);
597 for (i=0 ; i < info->rbuf_count ; i++) {
598 printk("%d: count=%04X status=%04X\n",
599 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
603 #define DBGRBUF(info)
606 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
610 printk("null struct slgt_info for (%s) in %s\n", devname, name);
613 if (info->magic != MGSL_MAGIC) {
614 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
625 * line discipline callback wrappers
627 * The wrappers maintain line discipline references
628 * while calling into the line discipline.
630 * ldisc_receive_buf - pass receive data to line discipline
632 static void ldisc_receive_buf(struct tty_struct *tty,
633 const __u8 *data, char *flags, int count)
635 struct tty_ldisc *ld;
638 ld = tty_ldisc_ref(tty);
640 if (ld->ops->receive_buf)
641 ld->ops->receive_buf(tty, data, flags, count);
648 static int open(struct tty_struct *tty, struct file *filp)
650 struct slgt_info *info;
655 if (line >= slgt_device_count) {
656 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
660 info = slgt_device_list;
661 while(info && info->line != line)
662 info = info->next_device;
663 if (sanity_check(info, tty->name, "open"))
665 if (info->init_error) {
666 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
670 tty->driver_data = info;
671 info->port.tty = tty;
673 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
675 /* If port is closing, signal caller to try again */
676 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
677 if (info->port.flags & ASYNC_CLOSING)
678 interruptible_sleep_on(&info->port.close_wait);
679 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
680 -EAGAIN : -ERESTARTSYS);
684 mutex_lock(&info->port.mutex);
685 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
687 spin_lock_irqsave(&info->netlock, flags);
688 if (info->netcount) {
690 spin_unlock_irqrestore(&info->netlock, flags);
691 mutex_unlock(&info->port.mutex);
695 spin_unlock_irqrestore(&info->netlock, flags);
697 if (info->port.count == 1) {
698 /* 1st open on this device, init hardware */
699 retval = startup(info);
701 mutex_unlock(&info->port.mutex);
705 mutex_unlock(&info->port.mutex);
706 retval = block_til_ready(tty, filp, info);
708 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
717 info->port.tty = NULL; /* tty layer will release tty struct */
722 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
726 static void close(struct tty_struct *tty, struct file *filp)
728 struct slgt_info *info = tty->driver_data;
730 if (sanity_check(info, tty->name, "close"))
732 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
734 if (tty_port_close_start(&info->port, tty, filp) == 0)
737 mutex_lock(&info->port.mutex);
738 if (info->port.flags & ASYNC_INITIALIZED)
739 wait_until_sent(tty, info->timeout);
741 tty_ldisc_flush(tty);
744 mutex_unlock(&info->port.mutex);
746 tty_port_close_end(&info->port, tty);
747 info->port.tty = NULL;
749 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
752 static void hangup(struct tty_struct *tty)
754 struct slgt_info *info = tty->driver_data;
757 if (sanity_check(info, tty->name, "hangup"))
759 DBGINFO(("%s hangup\n", info->device_name));
763 mutex_lock(&info->port.mutex);
766 spin_lock_irqsave(&info->port.lock, flags);
767 info->port.count = 0;
768 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
769 info->port.tty = NULL;
770 spin_unlock_irqrestore(&info->port.lock, flags);
771 mutex_unlock(&info->port.mutex);
773 wake_up_interruptible(&info->port.open_wait);
776 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
778 struct slgt_info *info = tty->driver_data;
781 DBGINFO(("%s set_termios\n", tty->driver->name));
785 /* Handle transition to B0 status */
786 if (old_termios->c_cflag & CBAUD &&
787 !(tty->termios.c_cflag & CBAUD)) {
788 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
789 spin_lock_irqsave(&info->lock,flags);
791 spin_unlock_irqrestore(&info->lock,flags);
794 /* Handle transition away from B0 status */
795 if (!(old_termios->c_cflag & CBAUD) &&
796 tty->termios.c_cflag & CBAUD) {
797 info->signals |= SerialSignal_DTR;
798 if (!(tty->termios.c_cflag & CRTSCTS) ||
799 !test_bit(TTY_THROTTLED, &tty->flags)) {
800 info->signals |= SerialSignal_RTS;
802 spin_lock_irqsave(&info->lock,flags);
804 spin_unlock_irqrestore(&info->lock,flags);
807 /* Handle turning off CRTSCTS */
808 if (old_termios->c_cflag & CRTSCTS &&
809 !(tty->termios.c_cflag & CRTSCTS)) {
815 static void update_tx_timer(struct slgt_info *info)
818 * use worst case speed of 1200bps to calculate transmit timeout
819 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
821 if (info->params.mode == MGSL_MODE_HDLC) {
822 int timeout = (tbuf_bytes(info) * 7) + 1000;
823 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
827 static int write(struct tty_struct *tty,
828 const unsigned char *buf, int count)
831 struct slgt_info *info = tty->driver_data;
834 if (sanity_check(info, tty->name, "write"))
837 DBGINFO(("%s write count=%d\n", info->device_name, count));
839 if (!info->tx_buf || (count > info->max_frame_size))
842 if (!count || tty->stopped || tty->hw_stopped)
845 spin_lock_irqsave(&info->lock, flags);
847 if (info->tx_count) {
848 /* send accumulated data from send_char() */
849 if (!tx_load(info, info->tx_buf, info->tx_count))
854 if (tx_load(info, buf, count))
858 spin_unlock_irqrestore(&info->lock, flags);
859 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
863 static int put_char(struct tty_struct *tty, unsigned char ch)
865 struct slgt_info *info = tty->driver_data;
869 if (sanity_check(info, tty->name, "put_char"))
871 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
874 spin_lock_irqsave(&info->lock,flags);
875 if (info->tx_count < info->max_frame_size) {
876 info->tx_buf[info->tx_count++] = ch;
879 spin_unlock_irqrestore(&info->lock,flags);
883 static void send_xchar(struct tty_struct *tty, char ch)
885 struct slgt_info *info = tty->driver_data;
888 if (sanity_check(info, tty->name, "send_xchar"))
890 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
893 spin_lock_irqsave(&info->lock,flags);
894 if (!info->tx_enabled)
896 spin_unlock_irqrestore(&info->lock,flags);
900 static void wait_until_sent(struct tty_struct *tty, int timeout)
902 struct slgt_info *info = tty->driver_data;
903 unsigned long orig_jiffies, char_time;
907 if (sanity_check(info, tty->name, "wait_until_sent"))
909 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
910 if (!(info->port.flags & ASYNC_INITIALIZED))
913 orig_jiffies = jiffies;
915 /* Set check interval to 1/5 of estimated time to
916 * send a character, and make it at least 1. The check
917 * interval should also be less than the timeout.
918 * Note: use tight timings here to satisfy the NIST-PCTS.
921 if (info->params.data_rate) {
922 char_time = info->timeout/(32 * 5);
929 char_time = min_t(unsigned long, char_time, timeout);
931 while (info->tx_active) {
932 msleep_interruptible(jiffies_to_msecs(char_time));
933 if (signal_pending(current))
935 if (timeout && time_after(jiffies, orig_jiffies + timeout))
939 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
942 static int write_room(struct tty_struct *tty)
944 struct slgt_info *info = tty->driver_data;
947 if (sanity_check(info, tty->name, "write_room"))
949 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
950 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
954 static void flush_chars(struct tty_struct *tty)
956 struct slgt_info *info = tty->driver_data;
959 if (sanity_check(info, tty->name, "flush_chars"))
961 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
963 if (info->tx_count <= 0 || tty->stopped ||
964 tty->hw_stopped || !info->tx_buf)
967 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
969 spin_lock_irqsave(&info->lock,flags);
970 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
972 spin_unlock_irqrestore(&info->lock,flags);
975 static void flush_buffer(struct tty_struct *tty)
977 struct slgt_info *info = tty->driver_data;
980 if (sanity_check(info, tty->name, "flush_buffer"))
982 DBGINFO(("%s flush_buffer\n", info->device_name));
984 spin_lock_irqsave(&info->lock, flags);
986 spin_unlock_irqrestore(&info->lock, flags);
992 * throttle (stop) transmitter
994 static void tx_hold(struct tty_struct *tty)
996 struct slgt_info *info = tty->driver_data;
999 if (sanity_check(info, tty->name, "tx_hold"))
1001 DBGINFO(("%s tx_hold\n", info->device_name));
1002 spin_lock_irqsave(&info->lock,flags);
1003 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1005 spin_unlock_irqrestore(&info->lock,flags);
1009 * release (start) transmitter
1011 static void tx_release(struct tty_struct *tty)
1013 struct slgt_info *info = tty->driver_data;
1014 unsigned long flags;
1016 if (sanity_check(info, tty->name, "tx_release"))
1018 DBGINFO(("%s tx_release\n", info->device_name));
1019 spin_lock_irqsave(&info->lock, flags);
1020 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1022 spin_unlock_irqrestore(&info->lock, flags);
1026 * Service an IOCTL request
1030 * tty pointer to tty instance data
1031 * cmd IOCTL command code
1032 * arg command argument/context
1034 * Return 0 if success, otherwise error code
1036 static int ioctl(struct tty_struct *tty,
1037 unsigned int cmd, unsigned long arg)
1039 struct slgt_info *info = tty->driver_data;
1040 void __user *argp = (void __user *)arg;
1043 if (sanity_check(info, tty->name, "ioctl"))
1045 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1047 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1048 (cmd != TIOCMIWAIT)) {
1049 if (tty->flags & (1 << TTY_IO_ERROR))
1054 case MGSL_IOCWAITEVENT:
1055 return wait_mgsl_event(info, argp);
1057 return modem_input_wait(info,(int)arg);
1059 return set_gpio(info, argp);
1061 return get_gpio(info, argp);
1062 case MGSL_IOCWAITGPIO:
1063 return wait_gpio(info, argp);
1064 case MGSL_IOCGXSYNC:
1065 return get_xsync(info, argp);
1066 case MGSL_IOCSXSYNC:
1067 return set_xsync(info, (int)arg);
1068 case MGSL_IOCGXCTRL:
1069 return get_xctrl(info, argp);
1070 case MGSL_IOCSXCTRL:
1071 return set_xctrl(info, (int)arg);
1073 mutex_lock(&info->port.mutex);
1075 case MGSL_IOCGPARAMS:
1076 ret = get_params(info, argp);
1078 case MGSL_IOCSPARAMS:
1079 ret = set_params(info, argp);
1081 case MGSL_IOCGTXIDLE:
1082 ret = get_txidle(info, argp);
1084 case MGSL_IOCSTXIDLE:
1085 ret = set_txidle(info, (int)arg);
1087 case MGSL_IOCTXENABLE:
1088 ret = tx_enable(info, (int)arg);
1090 case MGSL_IOCRXENABLE:
1091 ret = rx_enable(info, (int)arg);
1093 case MGSL_IOCTXABORT:
1094 ret = tx_abort(info);
1096 case MGSL_IOCGSTATS:
1097 ret = get_stats(info, argp);
1100 ret = get_interface(info, argp);
1103 ret = set_interface(info,(int)arg);
1108 mutex_unlock(&info->port.mutex);
1112 static int get_icount(struct tty_struct *tty,
1113 struct serial_icounter_struct *icount)
1116 struct slgt_info *info = tty->driver_data;
1117 struct mgsl_icount cnow; /* kernel counter temps */
1118 unsigned long flags;
1120 spin_lock_irqsave(&info->lock,flags);
1121 cnow = info->icount;
1122 spin_unlock_irqrestore(&info->lock,flags);
1124 icount->cts = cnow.cts;
1125 icount->dsr = cnow.dsr;
1126 icount->rng = cnow.rng;
1127 icount->dcd = cnow.dcd;
1128 icount->rx = cnow.rx;
1129 icount->tx = cnow.tx;
1130 icount->frame = cnow.frame;
1131 icount->overrun = cnow.overrun;
1132 icount->parity = cnow.parity;
1133 icount->brk = cnow.brk;
1134 icount->buf_overrun = cnow.buf_overrun;
1140 * support for 32 bit ioctl calls on 64 bit systems
1142 #ifdef CONFIG_COMPAT
1143 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1145 struct MGSL_PARAMS32 tmp_params;
1147 DBGINFO(("%s get_params32\n", info->device_name));
1148 memset(&tmp_params, 0, sizeof(tmp_params));
1149 tmp_params.mode = (compat_ulong_t)info->params.mode;
1150 tmp_params.loopback = info->params.loopback;
1151 tmp_params.flags = info->params.flags;
1152 tmp_params.encoding = info->params.encoding;
1153 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1154 tmp_params.addr_filter = info->params.addr_filter;
1155 tmp_params.crc_type = info->params.crc_type;
1156 tmp_params.preamble_length = info->params.preamble_length;
1157 tmp_params.preamble = info->params.preamble;
1158 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1159 tmp_params.data_bits = info->params.data_bits;
1160 tmp_params.stop_bits = info->params.stop_bits;
1161 tmp_params.parity = info->params.parity;
1162 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1167 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1169 struct MGSL_PARAMS32 tmp_params;
1171 DBGINFO(("%s set_params32\n", info->device_name));
1172 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1175 spin_lock(&info->lock);
1176 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1177 info->base_clock = tmp_params.clock_speed;
1179 info->params.mode = tmp_params.mode;
1180 info->params.loopback = tmp_params.loopback;
1181 info->params.flags = tmp_params.flags;
1182 info->params.encoding = tmp_params.encoding;
1183 info->params.clock_speed = tmp_params.clock_speed;
1184 info->params.addr_filter = tmp_params.addr_filter;
1185 info->params.crc_type = tmp_params.crc_type;
1186 info->params.preamble_length = tmp_params.preamble_length;
1187 info->params.preamble = tmp_params.preamble;
1188 info->params.data_rate = tmp_params.data_rate;
1189 info->params.data_bits = tmp_params.data_bits;
1190 info->params.stop_bits = tmp_params.stop_bits;
1191 info->params.parity = tmp_params.parity;
1193 spin_unlock(&info->lock);
1200 static long slgt_compat_ioctl(struct tty_struct *tty,
1201 unsigned int cmd, unsigned long arg)
1203 struct slgt_info *info = tty->driver_data;
1204 int rc = -ENOIOCTLCMD;
1206 if (sanity_check(info, tty->name, "compat_ioctl"))
1208 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1212 case MGSL_IOCSPARAMS32:
1213 rc = set_params32(info, compat_ptr(arg));
1216 case MGSL_IOCGPARAMS32:
1217 rc = get_params32(info, compat_ptr(arg));
1220 case MGSL_IOCGPARAMS:
1221 case MGSL_IOCSPARAMS:
1222 case MGSL_IOCGTXIDLE:
1223 case MGSL_IOCGSTATS:
1224 case MGSL_IOCWAITEVENT:
1228 case MGSL_IOCWAITGPIO:
1229 case MGSL_IOCGXSYNC:
1230 case MGSL_IOCGXCTRL:
1231 case MGSL_IOCSTXIDLE:
1232 case MGSL_IOCTXENABLE:
1233 case MGSL_IOCRXENABLE:
1234 case MGSL_IOCTXABORT:
1237 case MGSL_IOCSXSYNC:
1238 case MGSL_IOCSXCTRL:
1239 rc = ioctl(tty, cmd, arg);
1243 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1247 #define slgt_compat_ioctl NULL
1248 #endif /* ifdef CONFIG_COMPAT */
1253 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1256 unsigned long flags;
1258 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1259 info->device_name, info->phys_reg_addr,
1260 info->irq_level, info->max_frame_size);
1262 /* output current serial signal states */
1263 spin_lock_irqsave(&info->lock,flags);
1265 spin_unlock_irqrestore(&info->lock,flags);
1269 if (info->signals & SerialSignal_RTS)
1270 strcat(stat_buf, "|RTS");
1271 if (info->signals & SerialSignal_CTS)
1272 strcat(stat_buf, "|CTS");
1273 if (info->signals & SerialSignal_DTR)
1274 strcat(stat_buf, "|DTR");
1275 if (info->signals & SerialSignal_DSR)
1276 strcat(stat_buf, "|DSR");
1277 if (info->signals & SerialSignal_DCD)
1278 strcat(stat_buf, "|CD");
1279 if (info->signals & SerialSignal_RI)
1280 strcat(stat_buf, "|RI");
1282 if (info->params.mode != MGSL_MODE_ASYNC) {
1283 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1284 info->icount.txok, info->icount.rxok);
1285 if (info->icount.txunder)
1286 seq_printf(m, " txunder:%d", info->icount.txunder);
1287 if (info->icount.txabort)
1288 seq_printf(m, " txabort:%d", info->icount.txabort);
1289 if (info->icount.rxshort)
1290 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1291 if (info->icount.rxlong)
1292 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1293 if (info->icount.rxover)
1294 seq_printf(m, " rxover:%d", info->icount.rxover);
1295 if (info->icount.rxcrc)
1296 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1298 seq_printf(m, "\tASYNC tx:%d rx:%d",
1299 info->icount.tx, info->icount.rx);
1300 if (info->icount.frame)
1301 seq_printf(m, " fe:%d", info->icount.frame);
1302 if (info->icount.parity)
1303 seq_printf(m, " pe:%d", info->icount.parity);
1304 if (info->icount.brk)
1305 seq_printf(m, " brk:%d", info->icount.brk);
1306 if (info->icount.overrun)
1307 seq_printf(m, " oe:%d", info->icount.overrun);
1310 /* Append serial signal status to end */
1311 seq_printf(m, " %s\n", stat_buf+1);
1313 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1314 info->tx_active,info->bh_requested,info->bh_running,
1318 /* Called to print information about devices
1320 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1322 struct slgt_info *info;
1324 seq_puts(m, "synclink_gt driver\n");
1326 info = slgt_device_list;
1329 info = info->next_device;
1334 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1336 return single_open(file, synclink_gt_proc_show, NULL);
1339 static const struct file_operations synclink_gt_proc_fops = {
1340 .owner = THIS_MODULE,
1341 .open = synclink_gt_proc_open,
1343 .llseek = seq_lseek,
1344 .release = single_release,
1348 * return count of bytes in transmit buffer
1350 static int chars_in_buffer(struct tty_struct *tty)
1352 struct slgt_info *info = tty->driver_data;
1354 if (sanity_check(info, tty->name, "chars_in_buffer"))
1356 count = tbuf_bytes(info);
1357 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1362 * signal remote device to throttle send data (our receive data)
1364 static void throttle(struct tty_struct * tty)
1366 struct slgt_info *info = tty->driver_data;
1367 unsigned long flags;
1369 if (sanity_check(info, tty->name, "throttle"))
1371 DBGINFO(("%s throttle\n", info->device_name));
1373 send_xchar(tty, STOP_CHAR(tty));
1374 if (tty->termios.c_cflag & CRTSCTS) {
1375 spin_lock_irqsave(&info->lock,flags);
1376 info->signals &= ~SerialSignal_RTS;
1378 spin_unlock_irqrestore(&info->lock,flags);
1383 * signal remote device to stop throttling send data (our receive data)
1385 static void unthrottle(struct tty_struct * tty)
1387 struct slgt_info *info = tty->driver_data;
1388 unsigned long flags;
1390 if (sanity_check(info, tty->name, "unthrottle"))
1392 DBGINFO(("%s unthrottle\n", info->device_name));
1397 send_xchar(tty, START_CHAR(tty));
1399 if (tty->termios.c_cflag & CRTSCTS) {
1400 spin_lock_irqsave(&info->lock,flags);
1401 info->signals |= SerialSignal_RTS;
1403 spin_unlock_irqrestore(&info->lock,flags);
1408 * set or clear transmit break condition
1409 * break_state -1=set break condition, 0=clear
1411 static int set_break(struct tty_struct *tty, int break_state)
1413 struct slgt_info *info = tty->driver_data;
1414 unsigned short value;
1415 unsigned long flags;
1417 if (sanity_check(info, tty->name, "set_break"))
1419 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1421 spin_lock_irqsave(&info->lock,flags);
1422 value = rd_reg16(info, TCR);
1423 if (break_state == -1)
1427 wr_reg16(info, TCR, value);
1428 spin_unlock_irqrestore(&info->lock,flags);
1432 #if SYNCLINK_GENERIC_HDLC
1435 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1436 * set encoding and frame check sequence (FCS) options
1438 * dev pointer to network device structure
1439 * encoding serial encoding setting
1440 * parity FCS setting
1442 * returns 0 if success, otherwise error code
1444 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1445 unsigned short parity)
1447 struct slgt_info *info = dev_to_port(dev);
1448 unsigned char new_encoding;
1449 unsigned short new_crctype;
1451 /* return error if TTY interface open */
1452 if (info->port.count)
1455 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1459 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1460 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1461 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1462 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1463 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1464 default: return -EINVAL;
1469 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1470 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1471 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1472 default: return -EINVAL;
1475 info->params.encoding = new_encoding;
1476 info->params.crc_type = new_crctype;
1478 /* if network interface up, reprogram hardware */
1486 * called by generic HDLC layer to send frame
1488 * skb socket buffer containing HDLC frame
1489 * dev pointer to network device structure
1491 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1492 struct net_device *dev)
1494 struct slgt_info *info = dev_to_port(dev);
1495 unsigned long flags;
1497 DBGINFO(("%s hdlc_xmit\n", dev->name));
1500 return NETDEV_TX_OK;
1502 /* stop sending until this frame completes */
1503 netif_stop_queue(dev);
1505 /* update network statistics */
1506 dev->stats.tx_packets++;
1507 dev->stats.tx_bytes += skb->len;
1509 /* save start time for transmit timeout detection */
1510 dev->trans_start = jiffies;
1512 spin_lock_irqsave(&info->lock, flags);
1513 tx_load(info, skb->data, skb->len);
1514 spin_unlock_irqrestore(&info->lock, flags);
1516 /* done with socket buffer, so free it */
1519 return NETDEV_TX_OK;
1523 * called by network layer when interface enabled
1524 * claim resources and initialize hardware
1526 * dev pointer to network device structure
1528 * returns 0 if success, otherwise error code
1530 static int hdlcdev_open(struct net_device *dev)
1532 struct slgt_info *info = dev_to_port(dev);
1534 unsigned long flags;
1536 if (!try_module_get(THIS_MODULE))
1539 DBGINFO(("%s hdlcdev_open\n", dev->name));
1541 /* generic HDLC layer open processing */
1542 if ((rc = hdlc_open(dev)))
1545 /* arbitrate between network and tty opens */
1546 spin_lock_irqsave(&info->netlock, flags);
1547 if (info->port.count != 0 || info->netcount != 0) {
1548 DBGINFO(("%s hdlc_open busy\n", dev->name));
1549 spin_unlock_irqrestore(&info->netlock, flags);
1553 spin_unlock_irqrestore(&info->netlock, flags);
1555 /* claim resources and init adapter */
1556 if ((rc = startup(info)) != 0) {
1557 spin_lock_irqsave(&info->netlock, flags);
1559 spin_unlock_irqrestore(&info->netlock, flags);
1563 /* assert DTR and RTS, apply hardware settings */
1564 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1567 /* enable network layer transmit */
1568 dev->trans_start = jiffies;
1569 netif_start_queue(dev);
1571 /* inform generic HDLC layer of current DCD status */
1572 spin_lock_irqsave(&info->lock, flags);
1574 spin_unlock_irqrestore(&info->lock, flags);
1575 if (info->signals & SerialSignal_DCD)
1576 netif_carrier_on(dev);
1578 netif_carrier_off(dev);
1583 * called by network layer when interface is disabled
1584 * shutdown hardware and release resources
1586 * dev pointer to network device structure
1588 * returns 0 if success, otherwise error code
1590 static int hdlcdev_close(struct net_device *dev)
1592 struct slgt_info *info = dev_to_port(dev);
1593 unsigned long flags;
1595 DBGINFO(("%s hdlcdev_close\n", dev->name));
1597 netif_stop_queue(dev);
1599 /* shutdown adapter and release resources */
1604 spin_lock_irqsave(&info->netlock, flags);
1606 spin_unlock_irqrestore(&info->netlock, flags);
1608 module_put(THIS_MODULE);
1613 * called by network layer to process IOCTL call to network device
1615 * dev pointer to network device structure
1616 * ifr pointer to network interface request structure
1617 * cmd IOCTL command code
1619 * returns 0 if success, otherwise error code
1621 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1623 const size_t size = sizeof(sync_serial_settings);
1624 sync_serial_settings new_line;
1625 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1626 struct slgt_info *info = dev_to_port(dev);
1629 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1631 /* return error if TTY interface open */
1632 if (info->port.count)
1635 if (cmd != SIOCWANDEV)
1636 return hdlc_ioctl(dev, ifr, cmd);
1638 memset(&new_line, 0, sizeof(new_line));
1640 switch(ifr->ifr_settings.type) {
1641 case IF_GET_IFACE: /* return current sync_serial_settings */
1643 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1644 if (ifr->ifr_settings.size < size) {
1645 ifr->ifr_settings.size = size; /* data size wanted */
1649 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1650 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1651 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1652 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1655 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1656 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1657 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1658 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1659 default: new_line.clock_type = CLOCK_DEFAULT;
1662 new_line.clock_rate = info->params.clock_speed;
1663 new_line.loopback = info->params.loopback ? 1:0;
1665 if (copy_to_user(line, &new_line, size))
1669 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1671 if(!capable(CAP_NET_ADMIN))
1673 if (copy_from_user(&new_line, line, size))
1676 switch (new_line.clock_type)
1678 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1679 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1680 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1681 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1682 case CLOCK_DEFAULT: flags = info->params.flags &
1683 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1684 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1685 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1686 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1687 default: return -EINVAL;
1690 if (new_line.loopback != 0 && new_line.loopback != 1)
1693 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1694 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1695 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1696 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1697 info->params.flags |= flags;
1699 info->params.loopback = new_line.loopback;
1701 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1702 info->params.clock_speed = new_line.clock_rate;
1704 info->params.clock_speed = 0;
1706 /* if network interface up, reprogram hardware */
1712 return hdlc_ioctl(dev, ifr, cmd);
1717 * called by network layer when transmit timeout is detected
1719 * dev pointer to network device structure
1721 static void hdlcdev_tx_timeout(struct net_device *dev)
1723 struct slgt_info *info = dev_to_port(dev);
1724 unsigned long flags;
1726 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1728 dev->stats.tx_errors++;
1729 dev->stats.tx_aborted_errors++;
1731 spin_lock_irqsave(&info->lock,flags);
1733 spin_unlock_irqrestore(&info->lock,flags);
1735 netif_wake_queue(dev);
1739 * called by device driver when transmit completes
1740 * reenable network layer transmit if stopped
1742 * info pointer to device instance information
1744 static void hdlcdev_tx_done(struct slgt_info *info)
1746 if (netif_queue_stopped(info->netdev))
1747 netif_wake_queue(info->netdev);
1751 * called by device driver when frame received
1752 * pass frame to network layer
1754 * info pointer to device instance information
1755 * buf pointer to buffer contianing frame data
1756 * size count of data bytes in buf
1758 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1760 struct sk_buff *skb = dev_alloc_skb(size);
1761 struct net_device *dev = info->netdev;
1763 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1766 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1767 dev->stats.rx_dropped++;
1771 memcpy(skb_put(skb, size), buf, size);
1773 skb->protocol = hdlc_type_trans(skb, dev);
1775 dev->stats.rx_packets++;
1776 dev->stats.rx_bytes += size;
1781 static const struct net_device_ops hdlcdev_ops = {
1782 .ndo_open = hdlcdev_open,
1783 .ndo_stop = hdlcdev_close,
1784 .ndo_change_mtu = hdlc_change_mtu,
1785 .ndo_start_xmit = hdlc_start_xmit,
1786 .ndo_do_ioctl = hdlcdev_ioctl,
1787 .ndo_tx_timeout = hdlcdev_tx_timeout,
1791 * called by device driver when adding device instance
1792 * do generic HDLC initialization
1794 * info pointer to device instance information
1796 * returns 0 if success, otherwise error code
1798 static int hdlcdev_init(struct slgt_info *info)
1801 struct net_device *dev;
1804 /* allocate and initialize network and HDLC layer objects */
1806 if (!(dev = alloc_hdlcdev(info))) {
1807 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1811 /* for network layer reporting purposes only */
1812 dev->mem_start = info->phys_reg_addr;
1813 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1814 dev->irq = info->irq_level;
1816 /* network layer callbacks and settings */
1817 dev->netdev_ops = &hdlcdev_ops;
1818 dev->watchdog_timeo = 10 * HZ;
1819 dev->tx_queue_len = 50;
1821 /* generic HDLC layer callbacks and settings */
1822 hdlc = dev_to_hdlc(dev);
1823 hdlc->attach = hdlcdev_attach;
1824 hdlc->xmit = hdlcdev_xmit;
1826 /* register objects with HDLC layer */
1827 if ((rc = register_hdlc_device(dev))) {
1828 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1838 * called by device driver when removing device instance
1839 * do generic HDLC cleanup
1841 * info pointer to device instance information
1843 static void hdlcdev_exit(struct slgt_info *info)
1845 unregister_hdlc_device(info->netdev);
1846 free_netdev(info->netdev);
1847 info->netdev = NULL;
1850 #endif /* ifdef CONFIG_HDLC */
1853 * get async data from rx DMA buffers
1855 static void rx_async(struct slgt_info *info)
1857 struct tty_struct *tty = info->port.tty;
1858 struct mgsl_icount *icount = &info->icount;
1859 unsigned int start, end;
1861 unsigned char status;
1862 struct slgt_desc *bufs = info->rbufs;
1868 start = end = info->rbuf_current;
1870 while(desc_complete(bufs[end])) {
1871 count = desc_count(bufs[end]) - info->rbuf_index;
1872 p = bufs[end].buf + info->rbuf_index;
1874 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1875 DBGDATA(info, p, count, "rx");
1877 for(i=0 ; i < count; i+=2, p+=2) {
1883 if ((status = *(p+1) & (BIT1 + BIT0))) {
1886 else if (status & BIT0)
1888 /* discard char if tty control flags say so */
1889 if (status & info->ignore_status_mask)
1893 else if (status & BIT0)
1896 tty_insert_flip_char(&info->port, ch, stat);
1901 /* receive buffer not completed */
1902 info->rbuf_index += i;
1903 mod_timer(&info->rx_timer, jiffies + 1);
1907 info->rbuf_index = 0;
1908 free_rbufs(info, end, end);
1910 if (++end == info->rbuf_count)
1913 /* if entire list searched then no frame available */
1919 tty_flip_buffer_push(tty);
1923 * return next bottom half action to perform
1925 static int bh_action(struct slgt_info *info)
1927 unsigned long flags;
1930 spin_lock_irqsave(&info->lock,flags);
1932 if (info->pending_bh & BH_RECEIVE) {
1933 info->pending_bh &= ~BH_RECEIVE;
1935 } else if (info->pending_bh & BH_TRANSMIT) {
1936 info->pending_bh &= ~BH_TRANSMIT;
1938 } else if (info->pending_bh & BH_STATUS) {
1939 info->pending_bh &= ~BH_STATUS;
1942 /* Mark BH routine as complete */
1943 info->bh_running = false;
1944 info->bh_requested = false;
1948 spin_unlock_irqrestore(&info->lock,flags);
1954 * perform bottom half processing
1956 static void bh_handler(struct work_struct *work)
1958 struct slgt_info *info = container_of(work, struct slgt_info, task);
1963 info->bh_running = true;
1965 while((action = bh_action(info))) {
1968 DBGBH(("%s bh receive\n", info->device_name));
1969 switch(info->params.mode) {
1970 case MGSL_MODE_ASYNC:
1973 case MGSL_MODE_HDLC:
1974 while(rx_get_frame(info));
1977 case MGSL_MODE_MONOSYNC:
1978 case MGSL_MODE_BISYNC:
1979 case MGSL_MODE_XSYNC:
1980 while(rx_get_buf(info));
1983 /* restart receiver if rx DMA buffers exhausted */
1984 if (info->rx_restart)
1991 DBGBH(("%s bh status\n", info->device_name));
1992 info->ri_chkcount = 0;
1993 info->dsr_chkcount = 0;
1994 info->dcd_chkcount = 0;
1995 info->cts_chkcount = 0;
1998 DBGBH(("%s unknown action\n", info->device_name));
2002 DBGBH(("%s bh_handler exit\n", info->device_name));
2005 static void bh_transmit(struct slgt_info *info)
2007 struct tty_struct *tty = info->port.tty;
2009 DBGBH(("%s bh_transmit\n", info->device_name));
2014 static void dsr_change(struct slgt_info *info, unsigned short status)
2016 if (status & BIT3) {
2017 info->signals |= SerialSignal_DSR;
2018 info->input_signal_events.dsr_up++;
2020 info->signals &= ~SerialSignal_DSR;
2021 info->input_signal_events.dsr_down++;
2023 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2024 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2025 slgt_irq_off(info, IRQ_DSR);
2029 wake_up_interruptible(&info->status_event_wait_q);
2030 wake_up_interruptible(&info->event_wait_q);
2031 info->pending_bh |= BH_STATUS;
2034 static void cts_change(struct slgt_info *info, unsigned short status)
2036 if (status & BIT2) {
2037 info->signals |= SerialSignal_CTS;
2038 info->input_signal_events.cts_up++;
2040 info->signals &= ~SerialSignal_CTS;
2041 info->input_signal_events.cts_down++;
2043 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2044 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2045 slgt_irq_off(info, IRQ_CTS);
2049 wake_up_interruptible(&info->status_event_wait_q);
2050 wake_up_interruptible(&info->event_wait_q);
2051 info->pending_bh |= BH_STATUS;
2053 if (tty_port_cts_enabled(&info->port)) {
2054 if (info->port.tty) {
2055 if (info->port.tty->hw_stopped) {
2056 if (info->signals & SerialSignal_CTS) {
2057 info->port.tty->hw_stopped = 0;
2058 info->pending_bh |= BH_TRANSMIT;
2062 if (!(info->signals & SerialSignal_CTS))
2063 info->port.tty->hw_stopped = 1;
2069 static void dcd_change(struct slgt_info *info, unsigned short status)
2071 if (status & BIT1) {
2072 info->signals |= SerialSignal_DCD;
2073 info->input_signal_events.dcd_up++;
2075 info->signals &= ~SerialSignal_DCD;
2076 info->input_signal_events.dcd_down++;
2078 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2079 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2080 slgt_irq_off(info, IRQ_DCD);
2084 #if SYNCLINK_GENERIC_HDLC
2085 if (info->netcount) {
2086 if (info->signals & SerialSignal_DCD)
2087 netif_carrier_on(info->netdev);
2089 netif_carrier_off(info->netdev);
2092 wake_up_interruptible(&info->status_event_wait_q);
2093 wake_up_interruptible(&info->event_wait_q);
2094 info->pending_bh |= BH_STATUS;
2096 if (info->port.flags & ASYNC_CHECK_CD) {
2097 if (info->signals & SerialSignal_DCD)
2098 wake_up_interruptible(&info->port.open_wait);
2101 tty_hangup(info->port.tty);
2106 static void ri_change(struct slgt_info *info, unsigned short status)
2108 if (status & BIT0) {
2109 info->signals |= SerialSignal_RI;
2110 info->input_signal_events.ri_up++;
2112 info->signals &= ~SerialSignal_RI;
2113 info->input_signal_events.ri_down++;
2115 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2116 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2117 slgt_irq_off(info, IRQ_RI);
2121 wake_up_interruptible(&info->status_event_wait_q);
2122 wake_up_interruptible(&info->event_wait_q);
2123 info->pending_bh |= BH_STATUS;
2126 static void isr_rxdata(struct slgt_info *info)
2128 unsigned int count = info->rbuf_fill_count;
2129 unsigned int i = info->rbuf_fill_index;
2132 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2133 reg = rd_reg16(info, RDR);
2134 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2135 if (desc_complete(info->rbufs[i])) {
2136 /* all buffers full */
2138 info->rx_restart = 1;
2141 info->rbufs[i].buf[count++] = (unsigned char)reg;
2142 /* async mode saves status byte to buffer for each data byte */
2143 if (info->params.mode == MGSL_MODE_ASYNC)
2144 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2145 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2146 /* buffer full or end of frame */
2147 set_desc_count(info->rbufs[i], count);
2148 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2149 info->rbuf_fill_count = count = 0;
2150 if (++i == info->rbuf_count)
2152 info->pending_bh |= BH_RECEIVE;
2156 info->rbuf_fill_index = i;
2157 info->rbuf_fill_count = count;
2160 static void isr_serial(struct slgt_info *info)
2162 unsigned short status = rd_reg16(info, SSR);
2164 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2166 wr_reg16(info, SSR, status); /* clear pending */
2168 info->irq_occurred = true;
2170 if (info->params.mode == MGSL_MODE_ASYNC) {
2171 if (status & IRQ_TXIDLE) {
2172 if (info->tx_active)
2173 isr_txeom(info, status);
2175 if (info->rx_pio && (status & IRQ_RXDATA))
2177 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2179 /* process break detection if tty control allows */
2180 if (info->port.tty) {
2181 if (!(status & info->ignore_status_mask)) {
2182 if (info->read_status_mask & MASK_BREAK) {
2183 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2184 if (info->port.flags & ASYNC_SAK)
2185 do_SAK(info->port.tty);
2191 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2192 isr_txeom(info, status);
2193 if (info->rx_pio && (status & IRQ_RXDATA))
2195 if (status & IRQ_RXIDLE) {
2196 if (status & RXIDLE)
2197 info->icount.rxidle++;
2199 info->icount.exithunt++;
2200 wake_up_interruptible(&info->event_wait_q);
2203 if (status & IRQ_RXOVER)
2207 if (status & IRQ_DSR)
2208 dsr_change(info, status);
2209 if (status & IRQ_CTS)
2210 cts_change(info, status);
2211 if (status & IRQ_DCD)
2212 dcd_change(info, status);
2213 if (status & IRQ_RI)
2214 ri_change(info, status);
2217 static void isr_rdma(struct slgt_info *info)
2219 unsigned int status = rd_reg32(info, RDCSR);
2221 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2223 /* RDCSR (rx DMA control/status)
2226 * 06 save status byte to DMA buffer
2228 * 04 eol (end of list)
2229 * 03 eob (end of buffer)
2234 wr_reg32(info, RDCSR, status); /* clear pending */
2236 if (status & (BIT5 + BIT4)) {
2237 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2238 info->rx_restart = true;
2240 info->pending_bh |= BH_RECEIVE;
2243 static void isr_tdma(struct slgt_info *info)
2245 unsigned int status = rd_reg32(info, TDCSR);
2247 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2249 /* TDCSR (tx DMA control/status)
2253 * 04 eol (end of list)
2254 * 03 eob (end of buffer)
2259 wr_reg32(info, TDCSR, status); /* clear pending */
2261 if (status & (BIT5 + BIT4 + BIT3)) {
2262 // another transmit buffer has completed
2263 // run bottom half to get more send data from user
2264 info->pending_bh |= BH_TRANSMIT;
2269 * return true if there are unsent tx DMA buffers, otherwise false
2271 * if there are unsent buffers then info->tbuf_start
2272 * is set to index of first unsent buffer
2274 static bool unsent_tbufs(struct slgt_info *info)
2276 unsigned int i = info->tbuf_current;
2280 * search backwards from last loaded buffer (precedes tbuf_current)
2281 * for first unsent buffer (desc_count > 0)
2288 i = info->tbuf_count - 1;
2289 if (!desc_count(info->tbufs[i]))
2291 info->tbuf_start = i;
2293 } while (i != info->tbuf_current);
2298 static void isr_txeom(struct slgt_info *info, unsigned short status)
2300 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2302 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2304 if (status & IRQ_TXUNDER) {
2305 unsigned short val = rd_reg16(info, TCR);
2306 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2307 wr_reg16(info, TCR, val); /* clear reset bit */
2310 if (info->tx_active) {
2311 if (info->params.mode != MGSL_MODE_ASYNC) {
2312 if (status & IRQ_TXUNDER)
2313 info->icount.txunder++;
2314 else if (status & IRQ_TXIDLE)
2315 info->icount.txok++;
2318 if (unsent_tbufs(info)) {
2320 update_tx_timer(info);
2323 info->tx_active = false;
2325 del_timer(&info->tx_timer);
2327 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2328 info->signals &= ~SerialSignal_RTS;
2329 info->drop_rts_on_tx_done = false;
2333 #if SYNCLINK_GENERIC_HDLC
2335 hdlcdev_tx_done(info);
2339 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2343 info->pending_bh |= BH_TRANSMIT;
2348 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2350 struct cond_wait *w, *prev;
2352 /* wake processes waiting for specific transitions */
2353 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2354 if (w->data & changed) {
2356 wake_up_interruptible(&w->q);
2358 prev->next = w->next;
2360 info->gpio_wait_q = w->next;
2366 /* interrupt service routine
2368 * irq interrupt number
2369 * dev_id device ID supplied during interrupt registration
2371 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2373 struct slgt_info *info = dev_id;
2377 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2379 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2380 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2381 info->irq_occurred = true;
2382 for(i=0; i < info->port_count ; i++) {
2383 if (info->port_array[i] == NULL)
2385 spin_lock(&info->port_array[i]->lock);
2386 if (gsr & (BIT8 << i))
2387 isr_serial(info->port_array[i]);
2388 if (gsr & (BIT16 << (i*2)))
2389 isr_rdma(info->port_array[i]);
2390 if (gsr & (BIT17 << (i*2)))
2391 isr_tdma(info->port_array[i]);
2392 spin_unlock(&info->port_array[i]->lock);
2396 if (info->gpio_present) {
2398 unsigned int changed;
2399 spin_lock(&info->lock);
2400 while ((changed = rd_reg32(info, IOSR)) != 0) {
2401 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2402 /* read latched state of GPIO signals */
2403 state = rd_reg32(info, IOVR);
2404 /* clear pending GPIO interrupt bits */
2405 wr_reg32(info, IOSR, changed);
2406 for (i=0 ; i < info->port_count ; i++) {
2407 if (info->port_array[i] != NULL)
2408 isr_gpio(info->port_array[i], changed, state);
2411 spin_unlock(&info->lock);
2414 for(i=0; i < info->port_count ; i++) {
2415 struct slgt_info *port = info->port_array[i];
2418 spin_lock(&port->lock);
2419 if ((port->port.count || port->netcount) &&
2420 port->pending_bh && !port->bh_running &&
2421 !port->bh_requested) {
2422 DBGISR(("%s bh queued\n", port->device_name));
2423 schedule_work(&port->task);
2424 port->bh_requested = true;
2426 spin_unlock(&port->lock);
2429 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2433 static int startup(struct slgt_info *info)
2435 DBGINFO(("%s startup\n", info->device_name));
2437 if (info->port.flags & ASYNC_INITIALIZED)
2440 if (!info->tx_buf) {
2441 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2442 if (!info->tx_buf) {
2443 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2448 info->pending_bh = 0;
2450 memset(&info->icount, 0, sizeof(info->icount));
2452 /* program hardware for current parameters */
2453 change_params(info);
2456 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2458 info->port.flags |= ASYNC_INITIALIZED;
2464 * called by close() and hangup() to shutdown hardware
2466 static void shutdown(struct slgt_info *info)
2468 unsigned long flags;
2470 if (!(info->port.flags & ASYNC_INITIALIZED))
2473 DBGINFO(("%s shutdown\n", info->device_name));
2475 /* clear status wait queue because status changes */
2476 /* can't happen after shutting down the hardware */
2477 wake_up_interruptible(&info->status_event_wait_q);
2478 wake_up_interruptible(&info->event_wait_q);
2480 del_timer_sync(&info->tx_timer);
2481 del_timer_sync(&info->rx_timer);
2483 kfree(info->tx_buf);
2484 info->tx_buf = NULL;
2486 spin_lock_irqsave(&info->lock,flags);
2491 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2493 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2494 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2498 flush_cond_wait(&info->gpio_wait_q);
2500 spin_unlock_irqrestore(&info->lock,flags);
2503 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2505 info->port.flags &= ~ASYNC_INITIALIZED;
2508 static void program_hw(struct slgt_info *info)
2510 unsigned long flags;
2512 spin_lock_irqsave(&info->lock,flags);
2517 if (info->params.mode != MGSL_MODE_ASYNC ||
2525 info->dcd_chkcount = 0;
2526 info->cts_chkcount = 0;
2527 info->ri_chkcount = 0;
2528 info->dsr_chkcount = 0;
2530 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2533 if (info->netcount ||
2534 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2537 spin_unlock_irqrestore(&info->lock,flags);
2541 * reconfigure adapter based on new parameters
2543 static void change_params(struct slgt_info *info)
2548 if (!info->port.tty)
2550 DBGINFO(("%s change_params\n", info->device_name));
2552 cflag = info->port.tty->termios.c_cflag;
2554 /* if B0 rate (hangup) specified then negate DTR and RTS */
2555 /* otherwise assert DTR and RTS */
2557 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2559 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2561 /* byte size and parity */
2563 switch (cflag & CSIZE) {
2564 case CS5: info->params.data_bits = 5; break;
2565 case CS6: info->params.data_bits = 6; break;
2566 case CS7: info->params.data_bits = 7; break;
2567 case CS8: info->params.data_bits = 8; break;
2568 default: info->params.data_bits = 7; break;
2571 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2574 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2576 info->params.parity = ASYNC_PARITY_NONE;
2578 /* calculate number of jiffies to transmit a full
2579 * FIFO (32 bytes) at specified data rate
2581 bits_per_char = info->params.data_bits +
2582 info->params.stop_bits + 1;
2584 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2586 if (info->params.data_rate) {
2587 info->timeout = (32*HZ*bits_per_char) /
2588 info->params.data_rate;
2590 info->timeout += HZ/50; /* Add .02 seconds of slop */
2592 if (cflag & CRTSCTS)
2593 info->port.flags |= ASYNC_CTS_FLOW;
2595 info->port.flags &= ~ASYNC_CTS_FLOW;
2598 info->port.flags &= ~ASYNC_CHECK_CD;
2600 info->port.flags |= ASYNC_CHECK_CD;
2602 /* process tty input control flags */
2604 info->read_status_mask = IRQ_RXOVER;
2605 if (I_INPCK(info->port.tty))
2606 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2607 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2608 info->read_status_mask |= MASK_BREAK;
2609 if (I_IGNPAR(info->port.tty))
2610 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2611 if (I_IGNBRK(info->port.tty)) {
2612 info->ignore_status_mask |= MASK_BREAK;
2613 /* If ignoring parity and break indicators, ignore
2614 * overruns too. (For real raw support).
2616 if (I_IGNPAR(info->port.tty))
2617 info->ignore_status_mask |= MASK_OVERRUN;
2623 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2625 DBGINFO(("%s get_stats\n", info->device_name));
2627 memset(&info->icount, 0, sizeof(info->icount));
2629 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2635 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2637 DBGINFO(("%s get_params\n", info->device_name));
2638 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2643 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2645 unsigned long flags;
2646 MGSL_PARAMS tmp_params;
2648 DBGINFO(("%s set_params\n", info->device_name));
2649 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2652 spin_lock_irqsave(&info->lock, flags);
2653 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2654 info->base_clock = tmp_params.clock_speed;
2656 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2657 spin_unlock_irqrestore(&info->lock, flags);
2664 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2666 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2667 if (put_user(info->idle_mode, idle_mode))
2672 static int set_txidle(struct slgt_info *info, int idle_mode)
2674 unsigned long flags;
2675 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2676 spin_lock_irqsave(&info->lock,flags);
2677 info->idle_mode = idle_mode;
2678 if (info->params.mode != MGSL_MODE_ASYNC)
2680 spin_unlock_irqrestore(&info->lock,flags);
2684 static int tx_enable(struct slgt_info *info, int enable)
2686 unsigned long flags;
2687 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2688 spin_lock_irqsave(&info->lock,flags);
2690 if (!info->tx_enabled)
2693 if (info->tx_enabled)
2696 spin_unlock_irqrestore(&info->lock,flags);
2701 * abort transmit HDLC frame
2703 static int tx_abort(struct slgt_info *info)
2705 unsigned long flags;
2706 DBGINFO(("%s tx_abort\n", info->device_name));
2707 spin_lock_irqsave(&info->lock,flags);
2709 spin_unlock_irqrestore(&info->lock,flags);
2713 static int rx_enable(struct slgt_info *info, int enable)
2715 unsigned long flags;
2716 unsigned int rbuf_fill_level;
2717 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2718 spin_lock_irqsave(&info->lock,flags);
2720 * enable[31..16] = receive DMA buffer fill level
2721 * 0 = noop (leave fill level unchanged)
2722 * fill level must be multiple of 4 and <= buffer size
2724 rbuf_fill_level = ((unsigned int)enable) >> 16;
2725 if (rbuf_fill_level) {
2726 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2727 spin_unlock_irqrestore(&info->lock, flags);
2730 info->rbuf_fill_level = rbuf_fill_level;
2731 if (rbuf_fill_level < 128)
2732 info->rx_pio = 1; /* PIO mode */
2734 info->rx_pio = 0; /* DMA mode */
2735 rx_stop(info); /* restart receiver to use new fill level */
2739 * enable[1..0] = receiver enable command
2742 * 2 = enable or force hunt mode if already enabled
2746 if (!info->rx_enabled)
2748 else if (enable == 2) {
2749 /* force hunt mode (write 1 to RCR[3]) */
2750 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2753 if (info->rx_enabled)
2756 spin_unlock_irqrestore(&info->lock,flags);
2761 * wait for specified event to occur
2763 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2765 unsigned long flags;
2768 struct mgsl_icount cprev, cnow;
2771 struct _input_signal_events oldsigs, newsigs;
2772 DECLARE_WAITQUEUE(wait, current);
2774 if (get_user(mask, mask_ptr))
2777 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2779 spin_lock_irqsave(&info->lock,flags);
2781 /* return immediately if state matches requested events */
2786 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2787 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2788 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2789 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2791 spin_unlock_irqrestore(&info->lock,flags);
2795 /* save current irq counts */
2796 cprev = info->icount;
2797 oldsigs = info->input_signal_events;
2799 /* enable hunt and idle irqs if needed */
2800 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2801 unsigned short val = rd_reg16(info, SCR);
2802 if (!(val & IRQ_RXIDLE))
2803 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2806 set_current_state(TASK_INTERRUPTIBLE);
2807 add_wait_queue(&info->event_wait_q, &wait);
2809 spin_unlock_irqrestore(&info->lock,flags);
2813 if (signal_pending(current)) {
2818 /* get current irq counts */
2819 spin_lock_irqsave(&info->lock,flags);
2820 cnow = info->icount;
2821 newsigs = info->input_signal_events;
2822 set_current_state(TASK_INTERRUPTIBLE);
2823 spin_unlock_irqrestore(&info->lock,flags);
2825 /* if no change, wait aborted for some reason */
2826 if (newsigs.dsr_up == oldsigs.dsr_up &&
2827 newsigs.dsr_down == oldsigs.dsr_down &&
2828 newsigs.dcd_up == oldsigs.dcd_up &&
2829 newsigs.dcd_down == oldsigs.dcd_down &&
2830 newsigs.cts_up == oldsigs.cts_up &&
2831 newsigs.cts_down == oldsigs.cts_down &&
2832 newsigs.ri_up == oldsigs.ri_up &&
2833 newsigs.ri_down == oldsigs.ri_down &&
2834 cnow.exithunt == cprev.exithunt &&
2835 cnow.rxidle == cprev.rxidle) {
2841 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2842 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2843 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2844 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2845 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2846 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2847 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2848 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2849 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2850 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2858 remove_wait_queue(&info->event_wait_q, &wait);
2859 set_current_state(TASK_RUNNING);
2862 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2863 spin_lock_irqsave(&info->lock,flags);
2864 if (!waitqueue_active(&info->event_wait_q)) {
2865 /* disable enable exit hunt mode/idle rcvd IRQs */
2867 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2869 spin_unlock_irqrestore(&info->lock,flags);
2873 rc = put_user(events, mask_ptr);
2877 static int get_interface(struct slgt_info *info, int __user *if_mode)
2879 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2880 if (put_user(info->if_mode, if_mode))
2885 static int set_interface(struct slgt_info *info, int if_mode)
2887 unsigned long flags;
2890 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2891 spin_lock_irqsave(&info->lock,flags);
2892 info->if_mode = if_mode;
2896 /* TCR (tx control) 07 1=RTS driver control */
2897 val = rd_reg16(info, TCR);
2898 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2902 wr_reg16(info, TCR, val);
2904 spin_unlock_irqrestore(&info->lock,flags);
2908 static int get_xsync(struct slgt_info *info, int __user *xsync)
2910 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2911 if (put_user(info->xsync, xsync))
2917 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2919 * sync pattern is contained in least significant bytes of value
2920 * most significant byte of sync pattern is oldest (1st sent/detected)
2922 static int set_xsync(struct slgt_info *info, int xsync)
2924 unsigned long flags;
2926 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2927 spin_lock_irqsave(&info->lock, flags);
2928 info->xsync = xsync;
2929 wr_reg32(info, XSR, xsync);
2930 spin_unlock_irqrestore(&info->lock, flags);
2934 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2936 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2937 if (put_user(info->xctrl, xctrl))
2943 * set extended control options
2945 * xctrl[31:19] reserved, must be zero
2946 * xctrl[18:17] extended sync pattern length in bytes
2947 * 00 = 1 byte in xsr[7:0]
2948 * 01 = 2 bytes in xsr[15:0]
2949 * 10 = 3 bytes in xsr[23:0]
2950 * 11 = 4 bytes in xsr[31:0]
2951 * xctrl[16] 1 = enable terminal count, 0=disabled
2952 * xctrl[15:0] receive terminal count for fixed length packets
2953 * value is count minus one (0 = 1 byte packet)
2954 * when terminal count is reached, receiver
2955 * automatically returns to hunt mode and receive
2956 * FIFO contents are flushed to DMA buffers with
2957 * end of frame (EOF) status
2959 static int set_xctrl(struct slgt_info *info, int xctrl)
2961 unsigned long flags;
2963 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2964 spin_lock_irqsave(&info->lock, flags);
2965 info->xctrl = xctrl;
2966 wr_reg32(info, XCR, xctrl);
2967 spin_unlock_irqrestore(&info->lock, flags);
2972 * set general purpose IO pin state and direction
2975 * state each bit indicates a pin state
2976 * smask set bit indicates pin state to set
2977 * dir each bit indicates a pin direction (0=input, 1=output)
2978 * dmask set bit indicates pin direction to set
2980 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2982 unsigned long flags;
2983 struct gpio_desc gpio;
2986 if (!info->gpio_present)
2988 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2990 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2991 info->device_name, gpio.state, gpio.smask,
2992 gpio.dir, gpio.dmask));
2994 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2996 data = rd_reg32(info, IODR);
2997 data |= gpio.dmask & gpio.dir;
2998 data &= ~(gpio.dmask & ~gpio.dir);
2999 wr_reg32(info, IODR, data);
3002 data = rd_reg32(info, IOVR);
3003 data |= gpio.smask & gpio.state;
3004 data &= ~(gpio.smask & ~gpio.state);
3005 wr_reg32(info, IOVR, data);
3007 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3013 * get general purpose IO pin state and direction
3015 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3017 struct gpio_desc gpio;
3018 if (!info->gpio_present)
3020 gpio.state = rd_reg32(info, IOVR);
3021 gpio.smask = 0xffffffff;
3022 gpio.dir = rd_reg32(info, IODR);
3023 gpio.dmask = 0xffffffff;
3024 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3026 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3027 info->device_name, gpio.state, gpio.dir));
3032 * conditional wait facility
3034 static void init_cond_wait(struct cond_wait *w, unsigned int data)
3036 init_waitqueue_head(&w->q);
3037 init_waitqueue_entry(&w->wait, current);
3041 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3043 set_current_state(TASK_INTERRUPTIBLE);
3044 add_wait_queue(&w->q, &w->wait);
3049 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3051 struct cond_wait *w, *prev;
3052 remove_wait_queue(&cw->q, &cw->wait);
3053 set_current_state(TASK_RUNNING);
3054 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3057 prev->next = w->next;
3065 static void flush_cond_wait(struct cond_wait **head)
3067 while (*head != NULL) {
3068 wake_up_interruptible(&(*head)->q);
3069 *head = (*head)->next;
3074 * wait for general purpose I/O pin(s) to enter specified state
3077 * state - bit indicates target pin state
3078 * smask - set bit indicates watched pin
3080 * The wait ends when at least one watched pin enters the specified
3081 * state. When 0 (no error) is returned, user_gpio->state is set to the
3082 * state of all GPIO pins when the wait ends.
3084 * Note: Each pin may be a dedicated input, dedicated output, or
3085 * configurable input/output. The number and configuration of pins
3086 * varies with the specific adapter model. Only input pins (dedicated
3087 * or configured) can be monitored with this function.
3089 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3091 unsigned long flags;
3093 struct gpio_desc gpio;
3094 struct cond_wait wait;
3097 if (!info->gpio_present)
3099 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3101 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3102 info->device_name, gpio.state, gpio.smask));
3103 /* ignore output pins identified by set IODR bit */
3104 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3106 init_cond_wait(&wait, gpio.smask);
3108 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3109 /* enable interrupts for watched pins */
3110 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3111 /* get current pin states */
3112 state = rd_reg32(info, IOVR);
3114 if (gpio.smask & ~(state ^ gpio.state)) {
3115 /* already in target state */
3118 /* wait for target state */
3119 add_cond_wait(&info->gpio_wait_q, &wait);
3120 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3122 if (signal_pending(current))
3125 gpio.state = wait.data;
3126 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3127 remove_cond_wait(&info->gpio_wait_q, &wait);
3130 /* disable all GPIO interrupts if no waiting processes */
3131 if (info->gpio_wait_q == NULL)
3132 wr_reg32(info, IOER, 0);
3133 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3135 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3140 static int modem_input_wait(struct slgt_info *info,int arg)
3142 unsigned long flags;
3144 struct mgsl_icount cprev, cnow;
3145 DECLARE_WAITQUEUE(wait, current);
3147 /* save current irq counts */
3148 spin_lock_irqsave(&info->lock,flags);
3149 cprev = info->icount;
3150 add_wait_queue(&info->status_event_wait_q, &wait);
3151 set_current_state(TASK_INTERRUPTIBLE);
3152 spin_unlock_irqrestore(&info->lock,flags);
3156 if (signal_pending(current)) {
3161 /* get new irq counts */
3162 spin_lock_irqsave(&info->lock,flags);
3163 cnow = info->icount;
3164 set_current_state(TASK_INTERRUPTIBLE);
3165 spin_unlock_irqrestore(&info->lock,flags);
3167 /* if no change, wait aborted for some reason */
3168 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3169 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3174 /* check for change in caller specified modem input */
3175 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3176 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3177 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3178 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3185 remove_wait_queue(&info->status_event_wait_q, &wait);
3186 set_current_state(TASK_RUNNING);
3191 * return state of serial control and status signals
3193 static int tiocmget(struct tty_struct *tty)
3195 struct slgt_info *info = tty->driver_data;
3196 unsigned int result;
3197 unsigned long flags;
3199 spin_lock_irqsave(&info->lock,flags);
3201 spin_unlock_irqrestore(&info->lock,flags);
3203 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3204 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3205 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3206 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3207 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3208 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3210 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3215 * set modem control signals (DTR/RTS)
3217 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3218 * TIOCMSET = set/clear signal values
3219 * value bit mask for command
3221 static int tiocmset(struct tty_struct *tty,
3222 unsigned int set, unsigned int clear)
3224 struct slgt_info *info = tty->driver_data;
3225 unsigned long flags;
3227 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3229 if (set & TIOCM_RTS)
3230 info->signals |= SerialSignal_RTS;
3231 if (set & TIOCM_DTR)
3232 info->signals |= SerialSignal_DTR;
3233 if (clear & TIOCM_RTS)
3234 info->signals &= ~SerialSignal_RTS;
3235 if (clear & TIOCM_DTR)
3236 info->signals &= ~SerialSignal_DTR;
3238 spin_lock_irqsave(&info->lock,flags);
3240 spin_unlock_irqrestore(&info->lock,flags);
3244 static int carrier_raised(struct tty_port *port)
3246 unsigned long flags;
3247 struct slgt_info *info = container_of(port, struct slgt_info, port);
3249 spin_lock_irqsave(&info->lock,flags);
3251 spin_unlock_irqrestore(&info->lock,flags);
3252 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3255 static void dtr_rts(struct tty_port *port, int on)
3257 unsigned long flags;
3258 struct slgt_info *info = container_of(port, struct slgt_info, port);
3260 spin_lock_irqsave(&info->lock,flags);
3262 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3264 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3266 spin_unlock_irqrestore(&info->lock,flags);
3271 * block current process until the device is ready to open
3273 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3274 struct slgt_info *info)
3276 DECLARE_WAITQUEUE(wait, current);
3278 bool do_clocal = false;
3279 bool extra_count = false;
3280 unsigned long flags;
3282 struct tty_port *port = &info->port;
3284 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3286 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3287 /* nonblock mode is set or port is not enabled */
3288 port->flags |= ASYNC_NORMAL_ACTIVE;
3292 if (tty->termios.c_cflag & CLOCAL)
3295 /* Wait for carrier detect and the line to become
3296 * free (i.e., not in use by the callout). While we are in
3297 * this loop, port->count is dropped by one, so that
3298 * close() knows when to free things. We restore it upon
3299 * exit, either normal or abnormal.
3303 add_wait_queue(&port->open_wait, &wait);
3305 spin_lock_irqsave(&info->lock, flags);
3306 if (!tty_hung_up_p(filp)) {
3310 spin_unlock_irqrestore(&info->lock, flags);
3311 port->blocked_open++;
3314 if ((tty->termios.c_cflag & CBAUD))
3315 tty_port_raise_dtr_rts(port);
3317 set_current_state(TASK_INTERRUPTIBLE);
3319 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3320 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3321 -EAGAIN : -ERESTARTSYS;
3325 cd = tty_port_carrier_raised(port);
3327 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3330 if (signal_pending(current)) {
3331 retval = -ERESTARTSYS;
3335 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3341 set_current_state(TASK_RUNNING);
3342 remove_wait_queue(&port->open_wait, &wait);
3346 port->blocked_open--;
3349 port->flags |= ASYNC_NORMAL_ACTIVE;
3351 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3356 * allocate buffers used for calling line discipline receive_buf
3357 * directly in synchronous mode
3358 * note: add 5 bytes to max frame size to allow appending
3359 * 32-bit CRC and status byte when configured to do so
3361 static int alloc_tmp_rbuf(struct slgt_info *info)
3363 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3364 if (info->tmp_rbuf == NULL)
3366 /* unused flag buffer to satisfy receive_buf calling interface */
3367 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3368 if (!info->flag_buf) {
3369 kfree(info->tmp_rbuf);
3370 info->tmp_rbuf = NULL;
3376 static void free_tmp_rbuf(struct slgt_info *info)
3378 kfree(info->tmp_rbuf);
3379 info->tmp_rbuf = NULL;
3380 kfree(info->flag_buf);
3381 info->flag_buf = NULL;
3385 * allocate DMA descriptor lists.
3387 static int alloc_desc(struct slgt_info *info)
3392 /* allocate memory to hold descriptor lists */
3393 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3394 if (info->bufs == NULL)
3397 memset(info->bufs, 0, DESC_LIST_SIZE);
3399 info->rbufs = (struct slgt_desc*)info->bufs;
3400 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3402 pbufs = (unsigned int)info->bufs_dma_addr;
3405 * Build circular lists of descriptors
3408 for (i=0; i < info->rbuf_count; i++) {
3409 /* physical address of this descriptor */
3410 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3412 /* physical address of next descriptor */
3413 if (i == info->rbuf_count - 1)
3414 info->rbufs[i].next = cpu_to_le32(pbufs);
3416 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3417 set_desc_count(info->rbufs[i], DMABUFSIZE);
3420 for (i=0; i < info->tbuf_count; i++) {
3421 /* physical address of this descriptor */
3422 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3424 /* physical address of next descriptor */
3425 if (i == info->tbuf_count - 1)
3426 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3428 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3434 static void free_desc(struct slgt_info *info)
3436 if (info->bufs != NULL) {
3437 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3444 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3447 for (i=0; i < count; i++) {
3448 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3450 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3455 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3458 for (i=0; i < count; i++) {
3459 if (bufs[i].buf == NULL)
3461 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3466 static int alloc_dma_bufs(struct slgt_info *info)
3468 info->rbuf_count = 32;
3469 info->tbuf_count = 32;
3471 if (alloc_desc(info) < 0 ||
3472 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3473 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3474 alloc_tmp_rbuf(info) < 0) {
3475 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3482 static void free_dma_bufs(struct slgt_info *info)
3485 free_bufs(info, info->rbufs, info->rbuf_count);
3486 free_bufs(info, info->tbufs, info->tbuf_count);
3489 free_tmp_rbuf(info);
3492 static int claim_resources(struct slgt_info *info)
3494 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3495 DBGERR(("%s reg addr conflict, addr=%08X\n",
3496 info->device_name, info->phys_reg_addr));
3497 info->init_error = DiagStatus_AddressConflict;
3501 info->reg_addr_requested = true;
3503 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3504 if (!info->reg_addr) {
3505 DBGERR(("%s can't map device registers, addr=%08X\n",
3506 info->device_name, info->phys_reg_addr));
3507 info->init_error = DiagStatus_CantAssignPciResources;
3513 release_resources(info);
3517 static void release_resources(struct slgt_info *info)
3519 if (info->irq_requested) {
3520 free_irq(info->irq_level, info);
3521 info->irq_requested = false;
3524 if (info->reg_addr_requested) {
3525 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3526 info->reg_addr_requested = false;
3529 if (info->reg_addr) {
3530 iounmap(info->reg_addr);
3531 info->reg_addr = NULL;
3535 /* Add the specified device instance data structure to the
3536 * global linked list of devices and increment the device count.
3538 static void add_device(struct slgt_info *info)
3542 info->next_device = NULL;
3543 info->line = slgt_device_count;
3544 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3546 if (info->line < MAX_DEVICES) {
3547 if (maxframe[info->line])
3548 info->max_frame_size = maxframe[info->line];
3551 slgt_device_count++;
3553 if (!slgt_device_list)
3554 slgt_device_list = info;
3556 struct slgt_info *current_dev = slgt_device_list;
3557 while(current_dev->next_device)
3558 current_dev = current_dev->next_device;
3559 current_dev->next_device = info;
3562 if (info->max_frame_size < 4096)
3563 info->max_frame_size = 4096;
3564 else if (info->max_frame_size > 65535)
3565 info->max_frame_size = 65535;
3567 switch(info->pdev->device) {
3568 case SYNCLINK_GT_DEVICE_ID:
3571 case SYNCLINK_GT2_DEVICE_ID:
3574 case SYNCLINK_GT4_DEVICE_ID:
3577 case SYNCLINK_AC_DEVICE_ID:
3579 info->params.mode = MGSL_MODE_ASYNC;
3582 devstr = "(unknown model)";
3584 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3585 devstr, info->device_name, info->phys_reg_addr,
3586 info->irq_level, info->max_frame_size);
3588 #if SYNCLINK_GENERIC_HDLC
3593 static const struct tty_port_operations slgt_port_ops = {
3594 .carrier_raised = carrier_raised,
3599 * allocate device instance structure, return NULL on failure
3601 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3603 struct slgt_info *info;
3605 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3608 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3609 driver_name, adapter_num, port_num));
3611 tty_port_init(&info->port);
3612 info->port.ops = &slgt_port_ops;
3613 info->magic = MGSL_MAGIC;
3614 INIT_WORK(&info->task, bh_handler);
3615 info->max_frame_size = 4096;
3616 info->base_clock = 14745600;
3617 info->rbuf_fill_level = DMABUFSIZE;
3618 info->port.close_delay = 5*HZ/10;
3619 info->port.closing_wait = 30*HZ;
3620 init_waitqueue_head(&info->status_event_wait_q);
3621 init_waitqueue_head(&info->event_wait_q);
3622 spin_lock_init(&info->netlock);
3623 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3624 info->idle_mode = HDLC_TXIDLE_FLAGS;
3625 info->adapter_num = adapter_num;
3626 info->port_num = port_num;
3628 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3629 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3631 /* Copy configuration info to device instance data */
3633 info->irq_level = pdev->irq;
3634 info->phys_reg_addr = pci_resource_start(pdev,0);
3636 info->bus_type = MGSL_BUS_TYPE_PCI;
3637 info->irq_flags = IRQF_SHARED;
3639 info->init_error = -1; /* assume error, set to 0 on successful init */
3645 static void device_init(int adapter_num, struct pci_dev *pdev)
3647 struct slgt_info *port_array[SLGT_MAX_PORTS];
3651 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3653 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3656 /* allocate device instances for all ports */
3657 for (i=0; i < port_count; ++i) {
3658 port_array[i] = alloc_dev(adapter_num, i, pdev);
3659 if (port_array[i] == NULL) {
3660 for (--i; i >= 0; --i) {
3661 tty_port_destroy(&port_array[i]->port);
3662 kfree(port_array[i]);
3668 /* give copy of port_array to all ports and add to device list */
3669 for (i=0; i < port_count; ++i) {
3670 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3671 add_device(port_array[i]);
3672 port_array[i]->port_count = port_count;
3673 spin_lock_init(&port_array[i]->lock);
3676 /* Allocate and claim adapter resources */
3677 if (!claim_resources(port_array[0])) {
3679 alloc_dma_bufs(port_array[0]);
3681 /* copy resource information from first port to others */
3682 for (i = 1; i < port_count; ++i) {
3683 port_array[i]->irq_level = port_array[0]->irq_level;
3684 port_array[i]->reg_addr = port_array[0]->reg_addr;
3685 alloc_dma_bufs(port_array[i]);
3688 if (request_irq(port_array[0]->irq_level,
3690 port_array[0]->irq_flags,
3691 port_array[0]->device_name,
3692 port_array[0]) < 0) {
3693 DBGERR(("%s request_irq failed IRQ=%d\n",
3694 port_array[0]->device_name,
3695 port_array[0]->irq_level));
3697 port_array[0]->irq_requested = true;
3698 adapter_test(port_array[0]);
3699 for (i=1 ; i < port_count ; i++) {
3700 port_array[i]->init_error = port_array[0]->init_error;
3701 port_array[i]->gpio_present = port_array[0]->gpio_present;
3706 for (i = 0; i < port_count; ++i) {
3707 struct slgt_info *info = port_array[i];
3708 tty_port_register_device(&info->port, serial_driver, info->line,
3713 static int init_one(struct pci_dev *dev,
3714 const struct pci_device_id *ent)
3716 if (pci_enable_device(dev)) {
3717 printk("error enabling pci device %p\n", dev);
3720 pci_set_master(dev);
3721 device_init(slgt_device_count, dev);
3725 static void remove_one(struct pci_dev *dev)
3729 static const struct tty_operations ops = {
3733 .put_char = put_char,
3734 .flush_chars = flush_chars,
3735 .write_room = write_room,
3736 .chars_in_buffer = chars_in_buffer,
3737 .flush_buffer = flush_buffer,
3739 .compat_ioctl = slgt_compat_ioctl,
3740 .throttle = throttle,
3741 .unthrottle = unthrottle,
3742 .send_xchar = send_xchar,
3743 .break_ctl = set_break,
3744 .wait_until_sent = wait_until_sent,
3745 .set_termios = set_termios,
3747 .start = tx_release,
3749 .tiocmget = tiocmget,
3750 .tiocmset = tiocmset,
3751 .get_icount = get_icount,
3752 .proc_fops = &synclink_gt_proc_fops,
3755 static void slgt_cleanup(void)
3758 struct slgt_info *info;
3759 struct slgt_info *tmp;
3761 printk(KERN_INFO "unload %s\n", driver_name);
3763 if (serial_driver) {
3764 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3765 tty_unregister_device(serial_driver, info->line);
3766 if ((rc = tty_unregister_driver(serial_driver)))
3767 DBGERR(("tty_unregister_driver error=%d\n", rc));
3768 put_tty_driver(serial_driver);
3772 info = slgt_device_list;
3775 info = info->next_device;
3778 /* release devices */
3779 info = slgt_device_list;
3781 #if SYNCLINK_GENERIC_HDLC
3784 free_dma_bufs(info);
3785 free_tmp_rbuf(info);
3786 if (info->port_num == 0)
3787 release_resources(info);
3789 info = info->next_device;
3790 tty_port_destroy(&tmp->port);
3795 pci_unregister_driver(&pci_driver);
3799 * Driver initialization entry point.
3801 static int __init slgt_init(void)
3805 printk(KERN_INFO "%s\n", driver_name);
3807 serial_driver = alloc_tty_driver(MAX_DEVICES);
3808 if (!serial_driver) {
3809 printk("%s can't allocate tty driver\n", driver_name);
3813 /* Initialize the tty_driver structure */
3815 serial_driver->driver_name = tty_driver_name;
3816 serial_driver->name = tty_dev_prefix;
3817 serial_driver->major = ttymajor;
3818 serial_driver->minor_start = 64;
3819 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3820 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3821 serial_driver->init_termios = tty_std_termios;
3822 serial_driver->init_termios.c_cflag =
3823 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3824 serial_driver->init_termios.c_ispeed = 9600;
3825 serial_driver->init_termios.c_ospeed = 9600;
3826 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3827 tty_set_operations(serial_driver, &ops);
3828 if ((rc = tty_register_driver(serial_driver)) < 0) {
3829 DBGERR(("%s can't register serial driver\n", driver_name));
3830 put_tty_driver(serial_driver);
3831 serial_driver = NULL;
3835 printk(KERN_INFO "%s, tty major#%d\n",
3836 driver_name, serial_driver->major);
3838 slgt_device_count = 0;
3839 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3840 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3843 pci_registered = true;
3845 if (!slgt_device_list)
3846 printk("%s no devices found\n",driver_name);
3855 static void __exit slgt_exit(void)
3860 module_init(slgt_init);
3861 module_exit(slgt_exit);
3864 * register access routines
3867 #define CALC_REGADDR() \
3868 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3870 reg_addr += (info->port_num) * 32; \
3871 else if (addr >= 0x40) \
3872 reg_addr += (info->port_num) * 16;
3874 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3877 return readb((void __iomem *)reg_addr);
3880 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3883 writeb(value, (void __iomem *)reg_addr);
3886 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3889 return readw((void __iomem *)reg_addr);
3892 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3895 writew(value, (void __iomem *)reg_addr);
3898 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3901 return readl((void __iomem *)reg_addr);
3904 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3907 writel(value, (void __iomem *)reg_addr);
3910 static void rdma_reset(struct slgt_info *info)
3915 wr_reg32(info, RDCSR, BIT1);
3917 /* wait for enable bit cleared */
3918 for(i=0 ; i < 1000 ; i++)
3919 if (!(rd_reg32(info, RDCSR) & BIT0))
3923 static void tdma_reset(struct slgt_info *info)
3928 wr_reg32(info, TDCSR, BIT1);
3930 /* wait for enable bit cleared */
3931 for(i=0 ; i < 1000 ; i++)
3932 if (!(rd_reg32(info, TDCSR) & BIT0))
3937 * enable internal loopback
3938 * TxCLK and RxCLK are generated from BRG
3939 * and TxD is looped back to RxD internally.
3941 static void enable_loopback(struct slgt_info *info)
3943 /* SCR (serial control) BIT2=loopback enable */
3944 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3946 if (info->params.mode != MGSL_MODE_ASYNC) {
3947 /* CCR (clock control)
3948 * 07..05 tx clock source (010 = BRG)
3949 * 04..02 rx clock source (010 = BRG)
3950 * 01 auxclk enable (0 = disable)
3951 * 00 BRG enable (1 = enable)
3955 wr_reg8(info, CCR, 0x49);
3957 /* set speed if available, otherwise use default */
3958 if (info->params.clock_speed)
3959 set_rate(info, info->params.clock_speed);
3961 set_rate(info, 3686400);
3966 * set baud rate generator to specified rate
3968 static void set_rate(struct slgt_info *info, u32 rate)
3971 unsigned int osc = info->base_clock;
3973 /* div = osc/rate - 1
3975 * Round div up if osc/rate is not integer to
3976 * force to next slowest rate.
3981 if (!(osc % rate) && div)
3983 wr_reg16(info, BDR, (unsigned short)div);
3987 static void rx_stop(struct slgt_info *info)
3991 /* disable and reset receiver */
3992 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3993 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3994 wr_reg16(info, RCR, val); /* clear reset bit */
3996 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3998 /* clear pending rx interrupts */
3999 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
4003 info->rx_enabled = false;
4004 info->rx_restart = false;
4007 static void rx_start(struct slgt_info *info)
4011 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
4013 /* clear pending rx overrun IRQ */
4014 wr_reg16(info, SSR, IRQ_RXOVER);
4016 /* reset and disable receiver */
4017 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
4018 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
4019 wr_reg16(info, RCR, val); /* clear reset bit */
4025 /* rx request when rx FIFO not empty */
4026 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
4027 slgt_irq_on(info, IRQ_RXDATA);
4028 if (info->params.mode == MGSL_MODE_ASYNC) {
4029 /* enable saving of rx status */
4030 wr_reg32(info, RDCSR, BIT6);
4033 /* rx request when rx FIFO half full */
4034 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4035 /* set 1st descriptor address */
4036 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4038 if (info->params.mode != MGSL_MODE_ASYNC) {
4039 /* enable rx DMA and DMA interrupt */
4040 wr_reg32(info, RDCSR, (BIT2 + BIT0));
4042 /* enable saving of rx status, rx DMA and DMA interrupt */
4043 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4047 slgt_irq_on(info, IRQ_RXOVER);
4049 /* enable receiver */
4050 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4052 info->rx_restart = false;
4053 info->rx_enabled = true;
4056 static void tx_start(struct slgt_info *info)
4058 if (!info->tx_enabled) {
4060 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4061 info->tx_enabled = true;
4064 if (desc_count(info->tbufs[info->tbuf_start])) {
4065 info->drop_rts_on_tx_done = false;
4067 if (info->params.mode != MGSL_MODE_ASYNC) {
4068 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4070 if (!(info->signals & SerialSignal_RTS)) {
4071 info->signals |= SerialSignal_RTS;
4073 info->drop_rts_on_tx_done = true;
4077 slgt_irq_off(info, IRQ_TXDATA);
4078 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4079 /* clear tx idle and underrun status bits */
4080 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4082 slgt_irq_off(info, IRQ_TXDATA);
4083 slgt_irq_on(info, IRQ_TXIDLE);
4084 /* clear tx idle status bit */
4085 wr_reg16(info, SSR, IRQ_TXIDLE);
4087 /* set 1st descriptor address and start DMA */
4088 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4089 wr_reg32(info, TDCSR, BIT2 + BIT0);
4090 info->tx_active = true;
4094 static void tx_stop(struct slgt_info *info)
4098 del_timer(&info->tx_timer);
4102 /* reset and disable transmitter */
4103 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4104 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4106 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4108 /* clear tx idle and underrun status bit */
4109 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4113 info->tx_enabled = false;
4114 info->tx_active = false;
4117 static void reset_port(struct slgt_info *info)
4119 if (!info->reg_addr)
4125 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4128 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4131 static void reset_adapter(struct slgt_info *info)
4134 for (i=0; i < info->port_count; ++i) {
4135 if (info->port_array[i])
4136 reset_port(info->port_array[i]);
4140 static void async_mode(struct slgt_info *info)
4144 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4150 * 15..13 mode, 010=async
4151 * 12..10 encoding, 000=NRZ
4153 * 08 1=odd parity, 0=even parity
4154 * 07 1=RTS driver control
4156 * 05..04 character length
4161 * 03 0=1 stop bit, 1=2 stop bits
4164 * 00 auto-CTS enable
4168 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4171 if (info->params.parity != ASYNC_PARITY_NONE) {
4173 if (info->params.parity == ASYNC_PARITY_ODD)
4177 switch (info->params.data_bits)
4179 case 6: val |= BIT4; break;
4180 case 7: val |= BIT5; break;
4181 case 8: val |= BIT5 + BIT4; break;
4184 if (info->params.stop_bits != 1)
4187 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4190 wr_reg16(info, TCR, val);
4194 * 15..13 mode, 010=async
4195 * 12..10 encoding, 000=NRZ
4197 * 08 1=odd parity, 0=even parity
4198 * 07..06 reserved, must be 0
4199 * 05..04 character length
4204 * 03 reserved, must be zero
4207 * 00 auto-DCD enable
4211 if (info->params.parity != ASYNC_PARITY_NONE) {
4213 if (info->params.parity == ASYNC_PARITY_ODD)
4217 switch (info->params.data_bits)
4219 case 6: val |= BIT4; break;
4220 case 7: val |= BIT5; break;
4221 case 8: val |= BIT5 + BIT4; break;
4224 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4227 wr_reg16(info, RCR, val);
4229 /* CCR (clock control)
4231 * 07..05 011 = tx clock source is BRG/16
4232 * 04..02 010 = rx clock source is BRG
4233 * 01 0 = auxclk disabled
4234 * 00 1 = BRG enabled
4238 wr_reg8(info, CCR, 0x69);
4242 /* SCR (serial control)
4244 * 15 1=tx req on FIFO half empty
4245 * 14 1=rx req on FIFO half full
4246 * 13 tx data IRQ enable
4247 * 12 tx idle IRQ enable
4248 * 11 rx break on IRQ enable
4249 * 10 rx data IRQ enable
4250 * 09 rx break off IRQ enable
4251 * 08 overrun IRQ enable
4256 * 03 0=16x sampling, 1=8x sampling
4257 * 02 1=txd->rxd internal loopback enable
4258 * 01 reserved, must be zero
4259 * 00 1=master IRQ enable
4261 val = BIT15 + BIT14 + BIT0;
4262 /* JCR[8] : 1 = x8 async mode feature available */
4263 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4264 ((info->base_clock < (info->params.data_rate * 16)) ||
4265 (info->base_clock % (info->params.data_rate * 16)))) {
4266 /* use 8x sampling */
4268 set_rate(info, info->params.data_rate * 8);
4270 /* use 16x sampling */
4271 set_rate(info, info->params.data_rate * 16);
4273 wr_reg16(info, SCR, val);
4275 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4277 if (info->params.loopback)
4278 enable_loopback(info);
4281 static void sync_mode(struct slgt_info *info)
4285 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4293 * 001=raw bit synchronous
4294 * 010=asynchronous/isochronous
4295 * 011=monosync byte synchronous
4296 * 100=bisync byte synchronous
4297 * 101=xsync byte synchronous
4301 * 07 1=RTS driver control
4302 * 06 preamble enable
4303 * 05..04 preamble length
4304 * 03 share open/close flag
4307 * 00 auto-CTS enable
4311 switch(info->params.mode) {
4312 case MGSL_MODE_XSYNC:
4313 val |= BIT15 + BIT13;
4315 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4316 case MGSL_MODE_BISYNC: val |= BIT15; break;
4317 case MGSL_MODE_RAW: val |= BIT13; break;
4319 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4322 switch(info->params.encoding)
4324 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4325 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4326 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4327 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4328 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4329 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4330 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4333 switch (info->params.crc_type & HDLC_CRC_MASK)
4335 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4336 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4339 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4342 switch (info->params.preamble_length)
4344 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4345 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4346 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4349 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4352 wr_reg16(info, TCR, val);
4354 /* TPR (transmit preamble) */
4356 switch (info->params.preamble)
4358 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4359 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4360 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4361 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4362 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4363 default: val = 0x7e; break;
4365 wr_reg8(info, TPR, (unsigned char)val);
4371 * 001=raw bit synchronous
4372 * 010=asynchronous/isochronous
4373 * 011=monosync byte synchronous
4374 * 100=bisync byte synchronous
4375 * 101=xsync byte synchronous
4379 * 07..03 reserved, must be 0
4382 * 00 auto-DCD enable
4386 switch(info->params.mode) {
4387 case MGSL_MODE_XSYNC:
4388 val |= BIT15 + BIT13;
4390 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4391 case MGSL_MODE_BISYNC: val |= BIT15; break;
4392 case MGSL_MODE_RAW: val |= BIT13; break;
4395 switch(info->params.encoding)
4397 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4398 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4399 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4400 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4401 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4402 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4403 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4406 switch (info->params.crc_type & HDLC_CRC_MASK)
4408 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4409 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4412 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4415 wr_reg16(info, RCR, val);
4417 /* CCR (clock control)
4419 * 07..05 tx clock source
4420 * 04..02 rx clock source
4426 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4428 // when RxC source is DPLL, BRG generates 16X DPLL
4429 // reference clock, so take TxC from BRG/16 to get
4430 // transmit clock at actual data rate
4431 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4432 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4434 val |= BIT6; /* 010, txclk = BRG */
4436 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4437 val |= BIT7; /* 100, txclk = DPLL Input */
4438 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4439 val |= BIT5; /* 001, txclk = RXC Input */
4441 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4442 val |= BIT3; /* 010, rxclk = BRG */
4443 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4444 val |= BIT4; /* 100, rxclk = DPLL */
4445 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4446 val |= BIT2; /* 001, rxclk = TXC Input */
4448 if (info->params.clock_speed)
4451 wr_reg8(info, CCR, (unsigned char)val);
4453 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4455 // program DPLL mode
4456 switch(info->params.encoding)
4458 case HDLC_ENCODING_BIPHASE_MARK:
4459 case HDLC_ENCODING_BIPHASE_SPACE:
4461 case HDLC_ENCODING_BIPHASE_LEVEL:
4462 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4463 val = BIT7 + BIT6; break;
4464 default: val = BIT6; // NRZ encodings
4466 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4468 // DPLL requires a 16X reference clock from BRG
4469 set_rate(info, info->params.clock_speed * 16);
4472 set_rate(info, info->params.clock_speed);
4478 /* SCR (serial control)
4480 * 15 1=tx req on FIFO half empty
4481 * 14 1=rx req on FIFO half full
4482 * 13 tx data IRQ enable
4483 * 12 tx idle IRQ enable
4484 * 11 underrun IRQ enable
4485 * 10 rx data IRQ enable
4486 * 09 rx idle IRQ enable
4487 * 08 overrun IRQ enable
4492 * 03 reserved, must be zero
4493 * 02 1=txd->rxd internal loopback enable
4494 * 01 reserved, must be zero
4495 * 00 1=master IRQ enable
4497 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4499 if (info->params.loopback)
4500 enable_loopback(info);
4504 * set transmit idle mode
4506 static void tx_set_idle(struct slgt_info *info)
4511 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4512 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4514 tcr = rd_reg16(info, TCR);
4515 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4516 /* disable preamble, set idle size to 16 bits */
4517 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4518 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4519 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4520 } else if (!(tcr & BIT6)) {
4521 /* preamble is disabled, set idle size to 8 bits */
4522 tcr &= ~(BIT5 + BIT4);
4524 wr_reg16(info, TCR, tcr);
4526 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4527 /* LSB of custom tx idle specified in tx idle register */
4528 val = (unsigned char)(info->idle_mode & 0xff);
4530 /* standard 8 bit idle patterns */
4531 switch(info->idle_mode)
4533 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4534 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4535 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4536 case HDLC_TXIDLE_ZEROS:
4537 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4538 default: val = 0xff;
4542 wr_reg8(info, TIR, val);
4546 * get state of V24 status (input) signals
4548 static void get_signals(struct slgt_info *info)
4550 unsigned short status = rd_reg16(info, SSR);
4552 /* clear all serial signals except DTR and RTS */
4553 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4556 info->signals |= SerialSignal_DSR;
4558 info->signals |= SerialSignal_CTS;
4560 info->signals |= SerialSignal_DCD;
4562 info->signals |= SerialSignal_RI;
4566 * set V.24 Control Register based on current configuration
4568 static void msc_set_vcr(struct slgt_info *info)
4570 unsigned char val = 0;
4572 /* VCR (V.24 control)
4574 * 07..04 serial IF select
4581 switch(info->if_mode & MGSL_INTERFACE_MASK)
4583 case MGSL_INTERFACE_RS232:
4584 val |= BIT5; /* 0010 */
4586 case MGSL_INTERFACE_V35:
4587 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4589 case MGSL_INTERFACE_RS422:
4590 val |= BIT6; /* 0100 */
4594 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4596 if (info->signals & SerialSignal_DTR)
4598 if (info->signals & SerialSignal_RTS)
4600 if (info->if_mode & MGSL_INTERFACE_LL)
4602 if (info->if_mode & MGSL_INTERFACE_RL)
4604 wr_reg8(info, VCR, val);
4608 * set state of V24 control (output) signals
4610 static void set_signals(struct slgt_info *info)
4612 unsigned char val = rd_reg8(info, VCR);
4613 if (info->signals & SerialSignal_DTR)
4617 if (info->signals & SerialSignal_RTS)
4621 wr_reg8(info, VCR, val);
4625 * free range of receive DMA buffers (i to last)
4627 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4632 /* reset current buffer for reuse */
4633 info->rbufs[i].status = 0;
4634 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4637 if (++i == info->rbuf_count)
4640 info->rbuf_current = i;
4644 * mark all receive DMA buffers as free
4646 static void reset_rbufs(struct slgt_info *info)
4648 free_rbufs(info, 0, info->rbuf_count - 1);
4649 info->rbuf_fill_index = 0;
4650 info->rbuf_fill_count = 0;
4654 * pass receive HDLC frame to upper layer
4656 * return true if frame available, otherwise false
4658 static bool rx_get_frame(struct slgt_info *info)
4660 unsigned int start, end;
4661 unsigned short status;
4662 unsigned int framesize = 0;
4663 unsigned long flags;
4664 struct tty_struct *tty = info->port.tty;
4665 unsigned char addr_field = 0xff;
4666 unsigned int crc_size = 0;
4668 switch (info->params.crc_type & HDLC_CRC_MASK) {
4669 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4670 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4677 start = end = info->rbuf_current;
4680 if (!desc_complete(info->rbufs[end]))
4683 if (framesize == 0 && info->params.addr_filter != 0xff)
4684 addr_field = info->rbufs[end].buf[0];
4686 framesize += desc_count(info->rbufs[end]);
4688 if (desc_eof(info->rbufs[end]))
4691 if (++end == info->rbuf_count)
4694 if (end == info->rbuf_current) {
4695 if (info->rx_enabled){
4696 spin_lock_irqsave(&info->lock,flags);
4698 spin_unlock_irqrestore(&info->lock,flags);
4706 * 15 buffer complete
4709 * 02 eof (end of frame)
4713 status = desc_status(info->rbufs[end]);
4715 /* ignore CRC bit if not using CRC (bit is undefined) */
4716 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4719 if (framesize == 0 ||
4720 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4721 free_rbufs(info, start, end);
4725 if (framesize < (2 + crc_size) || status & BIT0) {
4726 info->icount.rxshort++;
4728 } else if (status & BIT1) {
4729 info->icount.rxcrc++;
4730 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4734 #if SYNCLINK_GENERIC_HDLC
4735 if (framesize == 0) {
4736 info->netdev->stats.rx_errors++;
4737 info->netdev->stats.rx_frame_errors++;
4741 DBGBH(("%s rx frame status=%04X size=%d\n",
4742 info->device_name, status, framesize));
4743 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4746 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4747 framesize -= crc_size;
4751 if (framesize > info->max_frame_size + crc_size)
4752 info->icount.rxlong++;
4754 /* copy dma buffer(s) to contiguous temp buffer */
4755 int copy_count = framesize;
4757 unsigned char *p = info->tmp_rbuf;
4758 info->tmp_rbuf_count = framesize;
4760 info->icount.rxok++;
4763 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4764 memcpy(p, info->rbufs[i].buf, partial_count);
4766 copy_count -= partial_count;
4767 if (++i == info->rbuf_count)
4771 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4772 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4776 #if SYNCLINK_GENERIC_HDLC
4778 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4781 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4784 free_rbufs(info, start, end);
4792 * pass receive buffer (RAW synchronous mode) to tty layer
4793 * return true if buffer available, otherwise false
4795 static bool rx_get_buf(struct slgt_info *info)
4797 unsigned int i = info->rbuf_current;
4800 if (!desc_complete(info->rbufs[i]))
4802 count = desc_count(info->rbufs[i]);
4803 switch(info->params.mode) {
4804 case MGSL_MODE_MONOSYNC:
4805 case MGSL_MODE_BISYNC:
4806 case MGSL_MODE_XSYNC:
4807 /* ignore residue in byte synchronous modes */
4808 if (desc_residue(info->rbufs[i]))
4812 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4813 DBGINFO(("rx_get_buf size=%d\n", count));
4815 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4816 info->flag_buf, count);
4817 free_rbufs(info, i, i);
4821 static void reset_tbufs(struct slgt_info *info)
4824 info->tbuf_current = 0;
4825 for (i=0 ; i < info->tbuf_count ; i++) {
4826 info->tbufs[i].status = 0;
4827 info->tbufs[i].count = 0;
4832 * return number of free transmit DMA buffers
4834 static unsigned int free_tbuf_count(struct slgt_info *info)
4836 unsigned int count = 0;
4837 unsigned int i = info->tbuf_current;
4841 if (desc_count(info->tbufs[i]))
4842 break; /* buffer in use */
4844 if (++i == info->tbuf_count)
4846 } while (i != info->tbuf_current);
4848 /* if tx DMA active, last zero count buffer is in use */
4849 if (count && (rd_reg32(info, TDCSR) & BIT0))
4856 * return number of bytes in unsent transmit DMA buffers
4857 * and the serial controller tx FIFO
4859 static unsigned int tbuf_bytes(struct slgt_info *info)
4861 unsigned int total_count = 0;
4862 unsigned int i = info->tbuf_current;
4863 unsigned int reg_value;
4865 unsigned int active_buf_count = 0;
4868 * Add descriptor counts for all tx DMA buffers.
4869 * If count is zero (cleared by DMA controller after read),
4870 * the buffer is complete or is actively being read from.
4872 * Record buf_count of last buffer with zero count starting
4873 * from current ring position. buf_count is mirror
4874 * copy of count and is not cleared by serial controller.
4875 * If DMA controller is active, that buffer is actively
4876 * being read so add to total.
4879 count = desc_count(info->tbufs[i]);
4881 total_count += count;
4882 else if (!total_count)
4883 active_buf_count = info->tbufs[i].buf_count;
4884 if (++i == info->tbuf_count)
4886 } while (i != info->tbuf_current);
4888 /* read tx DMA status register */
4889 reg_value = rd_reg32(info, TDCSR);
4891 /* if tx DMA active, last zero count buffer is in use */
4892 if (reg_value & BIT0)
4893 total_count += active_buf_count;
4895 /* add tx FIFO count = reg_value[15..8] */
4896 total_count += (reg_value >> 8) & 0xff;
4898 /* if transmitter active add one byte for shift register */
4899 if (info->tx_active)
4906 * load data into transmit DMA buffer ring and start transmitter if needed
4907 * return true if data accepted, otherwise false (buffers full)
4909 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4911 unsigned short count;
4913 struct slgt_desc *d;
4915 /* check required buffer space */
4916 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4919 DBGDATA(info, buf, size, "tx");
4922 * copy data to one or more DMA buffers in circular ring
4923 * tbuf_start = first buffer for this data
4924 * tbuf_current = next free buffer
4926 * Copy all data before making data visible to DMA controller by
4927 * setting descriptor count of the first buffer.
4928 * This prevents an active DMA controller from reading the first DMA
4929 * buffers of a frame and stopping before the final buffers are filled.
4932 info->tbuf_start = i = info->tbuf_current;
4935 d = &info->tbufs[i];
4937 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4938 memcpy(d->buf, buf, count);
4944 * set EOF bit for last buffer of HDLC frame or
4945 * for every buffer in raw mode
4947 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4948 info->params.mode == MGSL_MODE_RAW)
4949 set_desc_eof(*d, 1);
4951 set_desc_eof(*d, 0);
4953 /* set descriptor count for all but first buffer */
4954 if (i != info->tbuf_start)
4955 set_desc_count(*d, count);
4956 d->buf_count = count;
4958 if (++i == info->tbuf_count)
4962 info->tbuf_current = i;
4964 /* set first buffer count to make new data visible to DMA controller */
4965 d = &info->tbufs[info->tbuf_start];
4966 set_desc_count(*d, d->buf_count);
4968 /* start transmitter if needed and update transmit timeout */
4969 if (!info->tx_active)
4971 update_tx_timer(info);
4976 static int register_test(struct slgt_info *info)
4978 static unsigned short patterns[] =
4979 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4980 static unsigned int count = ARRAY_SIZE(patterns);
4984 for (i=0 ; i < count ; i++) {
4985 wr_reg16(info, TIR, patterns[i]);
4986 wr_reg16(info, BDR, patterns[(i+1)%count]);
4987 if ((rd_reg16(info, TIR) != patterns[i]) ||
4988 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4993 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4994 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4998 static int irq_test(struct slgt_info *info)
5000 unsigned long timeout;
5001 unsigned long flags;
5002 struct tty_struct *oldtty = info->port.tty;
5003 u32 speed = info->params.data_rate;
5005 info->params.data_rate = 921600;
5006 info->port.tty = NULL;
5008 spin_lock_irqsave(&info->lock, flags);
5010 slgt_irq_on(info, IRQ_TXIDLE);
5012 /* enable transmitter */
5014 (unsigned short)(rd_reg16(info, TCR) | BIT1));
5016 /* write one byte and wait for tx idle */
5017 wr_reg16(info, TDR, 0);
5019 /* assume failure */
5020 info->init_error = DiagStatus_IrqFailure;
5021 info->irq_occurred = false;
5023 spin_unlock_irqrestore(&info->lock, flags);
5026 while(timeout-- && !info->irq_occurred)
5027 msleep_interruptible(10);
5029 spin_lock_irqsave(&info->lock,flags);
5031 spin_unlock_irqrestore(&info->lock,flags);
5033 info->params.data_rate = speed;
5034 info->port.tty = oldtty;
5036 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5037 return info->irq_occurred ? 0 : -ENODEV;
5040 static int loopback_test_rx(struct slgt_info *info)
5042 unsigned char *src, *dest;
5045 if (desc_complete(info->rbufs[0])) {
5046 count = desc_count(info->rbufs[0]);
5047 src = info->rbufs[0].buf;
5048 dest = info->tmp_rbuf;
5050 for( ; count ; count-=2, src+=2) {
5051 /* src=data byte (src+1)=status byte */
5052 if (!(*(src+1) & (BIT9 + BIT8))) {
5055 info->tmp_rbuf_count++;
5058 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5064 static int loopback_test(struct slgt_info *info)
5066 #define TESTFRAMESIZE 20
5068 unsigned long timeout;
5069 u16 count = TESTFRAMESIZE;
5070 unsigned char buf[TESTFRAMESIZE];
5072 unsigned long flags;
5074 struct tty_struct *oldtty = info->port.tty;
5077 memcpy(¶ms, &info->params, sizeof(params));
5079 info->params.mode = MGSL_MODE_ASYNC;
5080 info->params.data_rate = 921600;
5081 info->params.loopback = 1;
5082 info->port.tty = NULL;
5084 /* build and send transmit frame */
5085 for (count = 0; count < TESTFRAMESIZE; ++count)
5086 buf[count] = (unsigned char)count;
5088 info->tmp_rbuf_count = 0;
5089 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5091 /* program hardware for HDLC and enabled receiver */
5092 spin_lock_irqsave(&info->lock,flags);
5095 tx_load(info, buf, count);
5096 spin_unlock_irqrestore(&info->lock, flags);
5098 /* wait for receive complete */
5099 for (timeout = 100; timeout; --timeout) {
5100 msleep_interruptible(10);
5101 if (loopback_test_rx(info)) {
5107 /* verify received frame length and contents */
5108 if (!rc && (info->tmp_rbuf_count != count ||
5109 memcmp(buf, info->tmp_rbuf, count))) {
5113 spin_lock_irqsave(&info->lock,flags);
5114 reset_adapter(info);
5115 spin_unlock_irqrestore(&info->lock,flags);
5117 memcpy(&info->params, ¶ms, sizeof(info->params));
5118 info->port.tty = oldtty;
5120 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5124 static int adapter_test(struct slgt_info *info)
5126 DBGINFO(("testing %s\n", info->device_name));
5127 if (register_test(info) < 0) {
5128 printk("register test failure %s addr=%08X\n",
5129 info->device_name, info->phys_reg_addr);
5130 } else if (irq_test(info) < 0) {
5131 printk("IRQ test failure %s IRQ=%d\n",
5132 info->device_name, info->irq_level);
5133 } else if (loopback_test(info) < 0) {
5134 printk("loopback test failure %s\n", info->device_name);
5136 return info->init_error;
5140 * transmit timeout handler
5142 static void tx_timeout(unsigned long context)
5144 struct slgt_info *info = (struct slgt_info*)context;
5145 unsigned long flags;
5147 DBGINFO(("%s tx_timeout\n", info->device_name));
5148 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5149 info->icount.txtimeout++;
5151 spin_lock_irqsave(&info->lock,flags);
5153 spin_unlock_irqrestore(&info->lock,flags);
5155 #if SYNCLINK_GENERIC_HDLC
5157 hdlcdev_tx_done(info);
5164 * receive buffer polling timer
5166 static void rx_timeout(unsigned long context)
5168 struct slgt_info *info = (struct slgt_info*)context;
5169 unsigned long flags;
5171 DBGINFO(("%s rx_timeout\n", info->device_name));
5172 spin_lock_irqsave(&info->lock, flags);
5173 info->pending_bh |= BH_RECEIVE;
5174 spin_unlock_irqrestore(&info->lock, flags);
5175 bh_handler(&info->task);