2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
7 * written by Paul Fulghum for Microgate Corporation
10 * Microgate and SyncLink are trademarks of Microgate Corporation
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30 # define BREAKPOINT() asm(" int $3");
32 # define BREAKPOINT() { }
35 #define MAX_DEVICES 12
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
53 #include <linux/seq_file.h>
54 #include <linux/slab.h>
55 #include <linux/netdevice.h>
56 #include <linux/vmalloc.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/ioctl.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
74 #define SYNCLINK_GENERIC_HDLC 0
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
82 #include <asm/uaccess.h>
84 static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE /* unsigned char parity; */
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
108 #define BUFFERLISTSIZE 4096
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
113 u16 next; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr; /* lower 16 bits of buffer addr */
115 u8 buf_base; /* upper 8 bits of buffer addr */
117 u16 length; /* length of buffer */
118 u8 status; /* status of buffer */
120 } SCADESC, *PSCADESC;
122 typedef struct _SCADESC_EX
124 /* device driver bookkeeping section */
125 char *virt_addr; /* virtual address of data buffer */
126 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX, *PSCADESC_EX;
129 /* The queue of BH actions to be performed */
132 #define BH_TRANSMIT 2
135 #define IO_PIN_SHUTDOWN_LIMIT 100
137 struct _input_signal_events {
149 * Device instance data structure
151 typedef struct _synclinkmp_info {
152 void *if_ptr; /* General purpose pointer (used by SPPP) */
154 struct tty_port port;
156 unsigned short close_delay;
157 unsigned short closing_wait; /* time to wait before closing */
159 struct mgsl_icount icount;
162 int x_char; /* xon/xoff character */
163 u16 read_status_mask1; /* break detection (SR1 indications) */
164 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf;
172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info *next_device; /* device list link */
176 struct timer_list status_timer; /* input signal status check timer */
178 spinlock_t lock; /* spinlock for synchronizing with ISR */
179 struct work_struct task; /* task structure for scheduling bh */
181 u32 max_frame_size; /* as set by device config */
185 bool bh_running; /* Protection from multiple */
189 int dcd_chkcount; /* check counts to prevent */
190 int cts_chkcount; /* too many IRQs if a signal */
191 int dsr_chkcount; /* is floating */
194 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys;
197 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
198 SCADESC *rx_buf_list; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200 unsigned int current_rx_buf;
202 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
203 SCADESC *tx_buf_list; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf;
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
223 char device_name[25]; /* device instance name */
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
231 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
233 unsigned int irq_level; /* interrupt level */
234 unsigned long irq_flags;
235 bool irq_requested; /* true if IRQ requested */
237 MGSL_PARAMS params; /* communications parameters */
239 unsigned char serial_signals; /* current serial signal states */
241 bool irq_occurred; /* for diagnostics use */
242 unsigned int init_error; /* Initialization startup error */
245 unsigned char* memory_base; /* shared memory address (PCI only) */
246 u32 phys_memory_base;
247 int shared_mem_requested;
249 unsigned char* sca_base; /* HD64570 SCA Memory address */
252 bool sca_base_requested;
254 unsigned char* lcr_base; /* local config registers (PCI only) */
257 int lcr_mem_requested;
259 unsigned char* statctrl_base; /* status/control register memory */
260 u32 phys_statctrl_base;
262 bool sca_statctrl_requested;
266 bool drop_rts_on_tx_done;
268 struct _input_signal_events input_signal_events;
270 /* SPPP/Cisco HDLC device parts */
274 #if SYNCLINK_GENERIC_HDLC
275 struct net_device *netdev;
280 #define MGSL_MAGIC 0x5401
283 * define serial signal status change macros
285 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
286 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
287 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
288 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
290 /* Common Register macros */
309 /* MSCI Register macros */
339 /* Timer Register Macros */
349 /* DMA Controller Register macros */
380 /* combine with timer or DMA register address */
388 /* SCA Command Codes */
391 #define TXENABLE 0x02
392 #define TXDISABLE 0x03
393 #define TXCRCINIT 0x04
394 #define TXCRCEXCL 0x05
398 #define TXBUFCLR 0x09
400 #define RXENABLE 0x12
401 #define RXDISABLE 0x13
402 #define RXCRCINIT 0x14
403 #define RXREJECT 0x15
404 #define SEARCHMP 0x16
405 #define RXCRCEXCL 0x17
406 #define RXCRCCALC 0x18
410 /* DMA command codes */
412 #define FEICLEAR 0x02
446 * Global linked list of SyncLink devices
448 static SLMP_INFO *synclinkmp_device_list = NULL;
449 static int synclinkmp_adapter_count = -1;
450 static int synclinkmp_device_count = 0;
453 * Set this param to non-zero to load eax with the
454 * .text section address and breakpoint on module load.
455 * This is useful for use with gdb and add-symbol-file command.
457 static bool break_on_load = 0;
460 * Driver major number, defaults to zero to get auto
461 * assigned major number. May be forced as module parameter.
463 static int ttymajor = 0;
466 * Array of user specified options for ISA adapters.
468 static int debug_level = 0;
469 static int maxframe[MAX_DEVICES] = {0,};
471 module_param(break_on_load, bool, 0);
472 module_param(ttymajor, int, 0);
473 module_param(debug_level, int, 0);
474 module_param_array(maxframe, int, NULL, 0);
476 static char *driver_name = "SyncLink MultiPort driver";
477 static char *driver_version = "$Revision: 4.38 $";
479 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
480 static void synclinkmp_remove_one(struct pci_dev *dev);
482 static struct pci_device_id synclinkmp_pci_tbl[] = {
483 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
484 { 0, }, /* terminate list */
486 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
488 MODULE_LICENSE("GPL");
490 static struct pci_driver synclinkmp_pci_driver = {
491 .name = "synclinkmp",
492 .id_table = synclinkmp_pci_tbl,
493 .probe = synclinkmp_init_one,
494 .remove = synclinkmp_remove_one,
498 static struct tty_driver *serial_driver;
500 /* number of characters left in xmit buffer before we ask for more */
501 #define WAKEUP_CHARS 256
506 static int open(struct tty_struct *tty, struct file * filp);
507 static void close(struct tty_struct *tty, struct file * filp);
508 static void hangup(struct tty_struct *tty);
509 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
511 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
512 static int put_char(struct tty_struct *tty, unsigned char ch);
513 static void send_xchar(struct tty_struct *tty, char ch);
514 static void wait_until_sent(struct tty_struct *tty, int timeout);
515 static int write_room(struct tty_struct *tty);
516 static void flush_chars(struct tty_struct *tty);
517 static void flush_buffer(struct tty_struct *tty);
518 static void tx_hold(struct tty_struct *tty);
519 static void tx_release(struct tty_struct *tty);
521 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
522 static int chars_in_buffer(struct tty_struct *tty);
523 static void throttle(struct tty_struct * tty);
524 static void unthrottle(struct tty_struct * tty);
525 static int set_break(struct tty_struct *tty, int break_state);
527 #if SYNCLINK_GENERIC_HDLC
528 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
529 static void hdlcdev_tx_done(SLMP_INFO *info);
530 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
531 static int hdlcdev_init(SLMP_INFO *info);
532 static void hdlcdev_exit(SLMP_INFO *info);
537 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
538 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
539 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
540 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
541 static int set_txidle(SLMP_INFO *info, int idle_mode);
542 static int tx_enable(SLMP_INFO *info, int enable);
543 static int tx_abort(SLMP_INFO *info);
544 static int rx_enable(SLMP_INFO *info, int enable);
545 static int modem_input_wait(SLMP_INFO *info,int arg);
546 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
547 static int tiocmget(struct tty_struct *tty);
548 static int tiocmset(struct tty_struct *tty,
549 unsigned int set, unsigned int clear);
550 static int set_break(struct tty_struct *tty, int break_state);
552 static void add_device(SLMP_INFO *info);
553 static void device_init(int adapter_num, struct pci_dev *pdev);
554 static int claim_resources(SLMP_INFO *info);
555 static void release_resources(SLMP_INFO *info);
557 static int startup(SLMP_INFO *info);
558 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
559 static int carrier_raised(struct tty_port *port);
560 static void shutdown(SLMP_INFO *info);
561 static void program_hw(SLMP_INFO *info);
562 static void change_params(SLMP_INFO *info);
564 static bool init_adapter(SLMP_INFO *info);
565 static bool register_test(SLMP_INFO *info);
566 static bool irq_test(SLMP_INFO *info);
567 static bool loopback_test(SLMP_INFO *info);
568 static int adapter_test(SLMP_INFO *info);
569 static bool memory_test(SLMP_INFO *info);
571 static void reset_adapter(SLMP_INFO *info);
572 static void reset_port(SLMP_INFO *info);
573 static void async_mode(SLMP_INFO *info);
574 static void hdlc_mode(SLMP_INFO *info);
576 static void rx_stop(SLMP_INFO *info);
577 static void rx_start(SLMP_INFO *info);
578 static void rx_reset_buffers(SLMP_INFO *info);
579 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
580 static bool rx_get_frame(SLMP_INFO *info);
582 static void tx_start(SLMP_INFO *info);
583 static void tx_stop(SLMP_INFO *info);
584 static void tx_load_fifo(SLMP_INFO *info);
585 static void tx_set_idle(SLMP_INFO *info);
586 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
588 static void get_signals(SLMP_INFO *info);
589 static void set_signals(SLMP_INFO *info);
590 static void enable_loopback(SLMP_INFO *info, int enable);
591 static void set_rate(SLMP_INFO *info, u32 data_rate);
593 static int bh_action(SLMP_INFO *info);
594 static void bh_handler(struct work_struct *work);
595 static void bh_receive(SLMP_INFO *info);
596 static void bh_transmit(SLMP_INFO *info);
597 static void bh_status(SLMP_INFO *info);
598 static void isr_timer(SLMP_INFO *info);
599 static void isr_rxint(SLMP_INFO *info);
600 static void isr_rxrdy(SLMP_INFO *info);
601 static void isr_txint(SLMP_INFO *info);
602 static void isr_txrdy(SLMP_INFO *info);
603 static void isr_rxdmaok(SLMP_INFO *info);
604 static void isr_rxdmaerror(SLMP_INFO *info);
605 static void isr_txdmaok(SLMP_INFO *info);
606 static void isr_txdmaerror(SLMP_INFO *info);
607 static void isr_io_pin(SLMP_INFO *info, u16 status);
609 static int alloc_dma_bufs(SLMP_INFO *info);
610 static void free_dma_bufs(SLMP_INFO *info);
611 static int alloc_buf_list(SLMP_INFO *info);
612 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
613 static int alloc_tmp_rx_buf(SLMP_INFO *info);
614 static void free_tmp_rx_buf(SLMP_INFO *info);
616 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
617 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
618 static void tx_timeout(unsigned long context);
619 static void status_timeout(unsigned long context);
621 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
622 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
623 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
624 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
625 static unsigned char read_status_reg(SLMP_INFO * info);
626 static void write_control_reg(SLMP_INFO * info);
629 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
630 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
631 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
633 static u32 misc_ctrl_value = 0x007e4040;
634 static u32 lcr1_brdr_value = 0x00800028;
636 static u32 read_ahead_count = 8;
638 /* DPCR, DMA Priority Control
640 * 07..05 Not used, must be 0
641 * 04 BRC, bus release condition: 0=all transfers complete
642 * 1=release after 1 xfer on all channels
643 * 03 CCC, channel change condition: 0=every cycle
644 * 1=after each channel completes all xfers
645 * 02..00 PR<2..0>, priority 100=round robin
649 static unsigned char dma_priority = 0x04;
651 // Number of bytes that can be written to shared RAM
652 // in a single write operation
653 static u32 sca_pci_load_interval = 64;
656 * 1st function defined in .text section. Calling this function in
657 * init_module() followed by a breakpoint allows a remote debugger
658 * (gdb) to get the .text address for the add-symbol-file command.
659 * This allows remote debugging of dynamically loadable modules.
661 static void* synclinkmp_get_text_ptr(void);
662 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
664 static inline int sanity_check(SLMP_INFO *info,
665 char *name, const char *routine)
668 static const char *badmagic =
669 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
670 static const char *badinfo =
671 "Warning: null synclinkmp_struct for (%s) in %s\n";
674 printk(badinfo, name, routine);
677 if (info->magic != MGSL_MAGIC) {
678 printk(badmagic, name, routine);
689 * line discipline callback wrappers
691 * The wrappers maintain line discipline references
692 * while calling into the line discipline.
694 * ldisc_receive_buf - pass receive data to line discipline
697 static void ldisc_receive_buf(struct tty_struct *tty,
698 const __u8 *data, char *flags, int count)
700 struct tty_ldisc *ld;
703 ld = tty_ldisc_ref(tty);
705 if (ld->ops->receive_buf)
706 ld->ops->receive_buf(tty, data, flags, count);
713 static int install(struct tty_driver *driver, struct tty_struct *tty)
716 int line = tty->index;
718 if (line >= synclinkmp_device_count) {
719 printk("%s(%d): open with invalid line #%d.\n",
720 __FILE__,__LINE__,line);
724 info = synclinkmp_device_list;
725 while (info && info->line != line)
726 info = info->next_device;
727 if (sanity_check(info, tty->name, "open"))
729 if (info->init_error) {
730 printk("%s(%d):%s device is not allocated, init error=%d\n",
731 __FILE__, __LINE__, info->device_name,
736 tty->driver_data = info;
738 return tty_port_install(&info->port, driver, tty);
741 /* Called when a port is opened. Init and enable port.
743 static int open(struct tty_struct *tty, struct file *filp)
745 SLMP_INFO *info = tty->driver_data;
749 info->port.tty = tty;
751 if (debug_level >= DEBUG_LEVEL_INFO)
752 printk("%s(%d):%s open(), old ref count = %d\n",
753 __FILE__,__LINE__,tty->driver->name, info->port.count);
755 /* If port is closing, signal caller to try again */
756 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
757 if (info->port.flags & ASYNC_CLOSING)
758 interruptible_sleep_on(&info->port.close_wait);
759 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
760 -EAGAIN : -ERESTARTSYS);
764 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
766 spin_lock_irqsave(&info->netlock, flags);
767 if (info->netcount) {
769 spin_unlock_irqrestore(&info->netlock, flags);
773 spin_unlock_irqrestore(&info->netlock, flags);
775 if (info->port.count == 1) {
776 /* 1st open on this device, init hardware */
777 retval = startup(info);
782 retval = block_til_ready(tty, filp, info);
784 if (debug_level >= DEBUG_LEVEL_INFO)
785 printk("%s(%d):%s block_til_ready() returned %d\n",
786 __FILE__,__LINE__, info->device_name, retval);
790 if (debug_level >= DEBUG_LEVEL_INFO)
791 printk("%s(%d):%s open() success\n",
792 __FILE__,__LINE__, info->device_name);
798 info->port.tty = NULL; /* tty layer will release tty struct */
806 /* Called when port is closed. Wait for remaining data to be
807 * sent. Disable port and free resources.
809 static void close(struct tty_struct *tty, struct file *filp)
811 SLMP_INFO * info = tty->driver_data;
813 if (sanity_check(info, tty->name, "close"))
816 if (debug_level >= DEBUG_LEVEL_INFO)
817 printk("%s(%d):%s close() entry, count=%d\n",
818 __FILE__,__LINE__, info->device_name, info->port.count);
820 if (tty_port_close_start(&info->port, tty, filp) == 0)
823 mutex_lock(&info->port.mutex);
824 if (info->port.flags & ASYNC_INITIALIZED)
825 wait_until_sent(tty, info->timeout);
828 tty_ldisc_flush(tty);
830 mutex_unlock(&info->port.mutex);
832 tty_port_close_end(&info->port, tty);
833 info->port.tty = NULL;
835 if (debug_level >= DEBUG_LEVEL_INFO)
836 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
837 tty->driver->name, info->port.count);
840 /* Called by tty_hangup() when a hangup is signaled.
841 * This is the same as closing all open descriptors for the port.
843 static void hangup(struct tty_struct *tty)
845 SLMP_INFO *info = tty->driver_data;
848 if (debug_level >= DEBUG_LEVEL_INFO)
849 printk("%s(%d):%s hangup()\n",
850 __FILE__,__LINE__, info->device_name );
852 if (sanity_check(info, tty->name, "hangup"))
855 mutex_lock(&info->port.mutex);
859 spin_lock_irqsave(&info->port.lock, flags);
860 info->port.count = 0;
861 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
862 info->port.tty = NULL;
863 spin_unlock_irqrestore(&info->port.lock, flags);
864 mutex_unlock(&info->port.mutex);
866 wake_up_interruptible(&info->port.open_wait);
869 /* Set new termios settings
871 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
873 SLMP_INFO *info = tty->driver_data;
876 if (debug_level >= DEBUG_LEVEL_INFO)
877 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
882 /* Handle transition to B0 status */
883 if (old_termios->c_cflag & CBAUD &&
884 !(tty->termios.c_cflag & CBAUD)) {
885 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
886 spin_lock_irqsave(&info->lock,flags);
888 spin_unlock_irqrestore(&info->lock,flags);
891 /* Handle transition away from B0 status */
892 if (!(old_termios->c_cflag & CBAUD) &&
893 tty->termios.c_cflag & CBAUD) {
894 info->serial_signals |= SerialSignal_DTR;
895 if (!(tty->termios.c_cflag & CRTSCTS) ||
896 !test_bit(TTY_THROTTLED, &tty->flags)) {
897 info->serial_signals |= SerialSignal_RTS;
899 spin_lock_irqsave(&info->lock,flags);
901 spin_unlock_irqrestore(&info->lock,flags);
904 /* Handle turning off CRTSCTS */
905 if (old_termios->c_cflag & CRTSCTS &&
906 !(tty->termios.c_cflag & CRTSCTS)) {
912 /* Send a block of data
916 * tty pointer to tty information structure
917 * buf pointer to buffer containing send data
918 * count size of send data in bytes
920 * Return Value: number of characters written
922 static int write(struct tty_struct *tty,
923 const unsigned char *buf, int count)
926 SLMP_INFO *info = tty->driver_data;
929 if (debug_level >= DEBUG_LEVEL_INFO)
930 printk("%s(%d):%s write() count=%d\n",
931 __FILE__,__LINE__,info->device_name,count);
933 if (sanity_check(info, tty->name, "write"))
939 if (info->params.mode == MGSL_MODE_HDLC) {
940 if (count > info->max_frame_size) {
946 if (info->tx_count) {
947 /* send accumulated data from send_char() calls */
948 /* as frame and wait before accepting more data. */
949 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
952 ret = info->tx_count = count;
953 tx_load_dma_buffer(info, buf, count);
958 c = min_t(int, count,
959 min(info->max_frame_size - info->tx_count - 1,
960 info->max_frame_size - info->tx_put));
964 memcpy(info->tx_buf + info->tx_put, buf, c);
966 spin_lock_irqsave(&info->lock,flags);
968 if (info->tx_put >= info->max_frame_size)
969 info->tx_put -= info->max_frame_size;
971 spin_unlock_irqrestore(&info->lock,flags);
978 if (info->params.mode == MGSL_MODE_HDLC) {
980 ret = info->tx_count = 0;
983 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
986 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
987 spin_lock_irqsave(&info->lock,flags);
988 if (!info->tx_active)
990 spin_unlock_irqrestore(&info->lock,flags);
994 if (debug_level >= DEBUG_LEVEL_INFO)
995 printk( "%s(%d):%s write() returning=%d\n",
996 __FILE__,__LINE__,info->device_name,ret);
1000 /* Add a character to the transmit buffer.
1002 static int put_char(struct tty_struct *tty, unsigned char ch)
1004 SLMP_INFO *info = tty->driver_data;
1005 unsigned long flags;
1008 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1009 printk( "%s(%d):%s put_char(%d)\n",
1010 __FILE__,__LINE__,info->device_name,ch);
1013 if (sanity_check(info, tty->name, "put_char"))
1019 spin_lock_irqsave(&info->lock,flags);
1021 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1022 !info->tx_active ) {
1024 if (info->tx_count < info->max_frame_size - 1) {
1025 info->tx_buf[info->tx_put++] = ch;
1026 if (info->tx_put >= info->max_frame_size)
1027 info->tx_put -= info->max_frame_size;
1033 spin_unlock_irqrestore(&info->lock,flags);
1037 /* Send a high-priority XON/XOFF character
1039 static void send_xchar(struct tty_struct *tty, char ch)
1041 SLMP_INFO *info = tty->driver_data;
1042 unsigned long flags;
1044 if (debug_level >= DEBUG_LEVEL_INFO)
1045 printk("%s(%d):%s send_xchar(%d)\n",
1046 __FILE__,__LINE__, info->device_name, ch );
1048 if (sanity_check(info, tty->name, "send_xchar"))
1053 /* Make sure transmit interrupts are on */
1054 spin_lock_irqsave(&info->lock,flags);
1055 if (!info->tx_enabled)
1057 spin_unlock_irqrestore(&info->lock,flags);
1061 /* Wait until the transmitter is empty.
1063 static void wait_until_sent(struct tty_struct *tty, int timeout)
1065 SLMP_INFO * info = tty->driver_data;
1066 unsigned long orig_jiffies, char_time;
1071 if (debug_level >= DEBUG_LEVEL_INFO)
1072 printk("%s(%d):%s wait_until_sent() entry\n",
1073 __FILE__,__LINE__, info->device_name );
1075 if (sanity_check(info, tty->name, "wait_until_sent"))
1078 if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags))
1081 orig_jiffies = jiffies;
1083 /* Set check interval to 1/5 of estimated time to
1084 * send a character, and make it at least 1. The check
1085 * interval should also be less than the timeout.
1086 * Note: use tight timings here to satisfy the NIST-PCTS.
1089 if ( info->params.data_rate ) {
1090 char_time = info->timeout/(32 * 5);
1097 char_time = min_t(unsigned long, char_time, timeout);
1099 if ( info->params.mode == MGSL_MODE_HDLC ) {
1100 while (info->tx_active) {
1101 msleep_interruptible(jiffies_to_msecs(char_time));
1102 if (signal_pending(current))
1104 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1109 * TODO: determine if there is something similar to USC16C32
1110 * TXSTATUS_ALL_SENT status
1112 while ( info->tx_active && info->tx_enabled) {
1113 msleep_interruptible(jiffies_to_msecs(char_time));
1114 if (signal_pending(current))
1116 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1122 if (debug_level >= DEBUG_LEVEL_INFO)
1123 printk("%s(%d):%s wait_until_sent() exit\n",
1124 __FILE__,__LINE__, info->device_name );
1127 /* Return the count of free bytes in transmit buffer
1129 static int write_room(struct tty_struct *tty)
1131 SLMP_INFO *info = tty->driver_data;
1134 if (sanity_check(info, tty->name, "write_room"))
1137 if (info->params.mode == MGSL_MODE_HDLC) {
1138 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1140 ret = info->max_frame_size - info->tx_count - 1;
1145 if (debug_level >= DEBUG_LEVEL_INFO)
1146 printk("%s(%d):%s write_room()=%d\n",
1147 __FILE__, __LINE__, info->device_name, ret);
1152 /* enable transmitter and send remaining buffered characters
1154 static void flush_chars(struct tty_struct *tty)
1156 SLMP_INFO *info = tty->driver_data;
1157 unsigned long flags;
1159 if ( debug_level >= DEBUG_LEVEL_INFO )
1160 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1161 __FILE__,__LINE__,info->device_name,info->tx_count);
1163 if (sanity_check(info, tty->name, "flush_chars"))
1166 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1170 if ( debug_level >= DEBUG_LEVEL_INFO )
1171 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1172 __FILE__,__LINE__,info->device_name );
1174 spin_lock_irqsave(&info->lock,flags);
1176 if (!info->tx_active) {
1177 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1179 /* operating in synchronous (frame oriented) mode */
1180 /* copy data from circular tx_buf to */
1181 /* transmit DMA buffer. */
1182 tx_load_dma_buffer(info,
1183 info->tx_buf,info->tx_count);
1188 spin_unlock_irqrestore(&info->lock,flags);
1191 /* Discard all data in the send buffer
1193 static void flush_buffer(struct tty_struct *tty)
1195 SLMP_INFO *info = tty->driver_data;
1196 unsigned long flags;
1198 if (debug_level >= DEBUG_LEVEL_INFO)
1199 printk("%s(%d):%s flush_buffer() entry\n",
1200 __FILE__,__LINE__, info->device_name );
1202 if (sanity_check(info, tty->name, "flush_buffer"))
1205 spin_lock_irqsave(&info->lock,flags);
1206 info->tx_count = info->tx_put = info->tx_get = 0;
1207 del_timer(&info->tx_timer);
1208 spin_unlock_irqrestore(&info->lock,flags);
1213 /* throttle (stop) transmitter
1215 static void tx_hold(struct tty_struct *tty)
1217 SLMP_INFO *info = tty->driver_data;
1218 unsigned long flags;
1220 if (sanity_check(info, tty->name, "tx_hold"))
1223 if ( debug_level >= DEBUG_LEVEL_INFO )
1224 printk("%s(%d):%s tx_hold()\n",
1225 __FILE__,__LINE__,info->device_name);
1227 spin_lock_irqsave(&info->lock,flags);
1228 if (info->tx_enabled)
1230 spin_unlock_irqrestore(&info->lock,flags);
1233 /* release (start) transmitter
1235 static void tx_release(struct tty_struct *tty)
1237 SLMP_INFO *info = tty->driver_data;
1238 unsigned long flags;
1240 if (sanity_check(info, tty->name, "tx_release"))
1243 if ( debug_level >= DEBUG_LEVEL_INFO )
1244 printk("%s(%d):%s tx_release()\n",
1245 __FILE__,__LINE__,info->device_name);
1247 spin_lock_irqsave(&info->lock,flags);
1248 if (!info->tx_enabled)
1250 spin_unlock_irqrestore(&info->lock,flags);
1253 /* Service an IOCTL request
1257 * tty pointer to tty instance data
1258 * cmd IOCTL command code
1259 * arg command argument/context
1261 * Return Value: 0 if success, otherwise error code
1263 static int ioctl(struct tty_struct *tty,
1264 unsigned int cmd, unsigned long arg)
1266 SLMP_INFO *info = tty->driver_data;
1267 void __user *argp = (void __user *)arg;
1269 if (debug_level >= DEBUG_LEVEL_INFO)
1270 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1271 info->device_name, cmd );
1273 if (sanity_check(info, tty->name, "ioctl"))
1276 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1277 (cmd != TIOCMIWAIT)) {
1278 if (tty->flags & (1 << TTY_IO_ERROR))
1283 case MGSL_IOCGPARAMS:
1284 return get_params(info, argp);
1285 case MGSL_IOCSPARAMS:
1286 return set_params(info, argp);
1287 case MGSL_IOCGTXIDLE:
1288 return get_txidle(info, argp);
1289 case MGSL_IOCSTXIDLE:
1290 return set_txidle(info, (int)arg);
1291 case MGSL_IOCTXENABLE:
1292 return tx_enable(info, (int)arg);
1293 case MGSL_IOCRXENABLE:
1294 return rx_enable(info, (int)arg);
1295 case MGSL_IOCTXABORT:
1296 return tx_abort(info);
1297 case MGSL_IOCGSTATS:
1298 return get_stats(info, argp);
1299 case MGSL_IOCWAITEVENT:
1300 return wait_mgsl_event(info, argp);
1301 case MGSL_IOCLOOPTXDONE:
1302 return 0; // TODO: Not supported, need to document
1303 /* Wait for modem input (DCD,RI,DSR,CTS) change
1304 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1307 return modem_input_wait(info,(int)arg);
1310 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1311 * Return: write counters to the user passed counter struct
1312 * NB: both 1->0 and 0->1 transitions are counted except for
1313 * RI where only 0->1 is counted.
1316 return -ENOIOCTLCMD;
1321 static int get_icount(struct tty_struct *tty,
1322 struct serial_icounter_struct *icount)
1324 SLMP_INFO *info = tty->driver_data;
1325 struct mgsl_icount cnow; /* kernel counter temps */
1326 unsigned long flags;
1328 spin_lock_irqsave(&info->lock,flags);
1329 cnow = info->icount;
1330 spin_unlock_irqrestore(&info->lock,flags);
1332 icount->cts = cnow.cts;
1333 icount->dsr = cnow.dsr;
1334 icount->rng = cnow.rng;
1335 icount->dcd = cnow.dcd;
1336 icount->rx = cnow.rx;
1337 icount->tx = cnow.tx;
1338 icount->frame = cnow.frame;
1339 icount->overrun = cnow.overrun;
1340 icount->parity = cnow.parity;
1341 icount->brk = cnow.brk;
1342 icount->buf_overrun = cnow.buf_overrun;
1348 * /proc fs routines....
1351 static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1354 unsigned long flags;
1356 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1357 "\tIRQ=%d MaxFrameSize=%u\n",
1359 info->phys_sca_base,
1360 info->phys_memory_base,
1361 info->phys_statctrl_base,
1362 info->phys_lcr_base,
1364 info->max_frame_size );
1366 /* output current serial signal states */
1367 spin_lock_irqsave(&info->lock,flags);
1369 spin_unlock_irqrestore(&info->lock,flags);
1373 if (info->serial_signals & SerialSignal_RTS)
1374 strcat(stat_buf, "|RTS");
1375 if (info->serial_signals & SerialSignal_CTS)
1376 strcat(stat_buf, "|CTS");
1377 if (info->serial_signals & SerialSignal_DTR)
1378 strcat(stat_buf, "|DTR");
1379 if (info->serial_signals & SerialSignal_DSR)
1380 strcat(stat_buf, "|DSR");
1381 if (info->serial_signals & SerialSignal_DCD)
1382 strcat(stat_buf, "|CD");
1383 if (info->serial_signals & SerialSignal_RI)
1384 strcat(stat_buf, "|RI");
1386 if (info->params.mode == MGSL_MODE_HDLC) {
1387 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1388 info->icount.txok, info->icount.rxok);
1389 if (info->icount.txunder)
1390 seq_printf(m, " txunder:%d", info->icount.txunder);
1391 if (info->icount.txabort)
1392 seq_printf(m, " txabort:%d", info->icount.txabort);
1393 if (info->icount.rxshort)
1394 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1395 if (info->icount.rxlong)
1396 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1397 if (info->icount.rxover)
1398 seq_printf(m, " rxover:%d", info->icount.rxover);
1399 if (info->icount.rxcrc)
1400 seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1402 seq_printf(m, "\tASYNC tx:%d rx:%d",
1403 info->icount.tx, info->icount.rx);
1404 if (info->icount.frame)
1405 seq_printf(m, " fe:%d", info->icount.frame);
1406 if (info->icount.parity)
1407 seq_printf(m, " pe:%d", info->icount.parity);
1408 if (info->icount.brk)
1409 seq_printf(m, " brk:%d", info->icount.brk);
1410 if (info->icount.overrun)
1411 seq_printf(m, " oe:%d", info->icount.overrun);
1414 /* Append serial signal status to end */
1415 seq_printf(m, " %s\n", stat_buf+1);
1417 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1418 info->tx_active,info->bh_requested,info->bh_running,
1422 /* Called to print information about devices
1424 static int synclinkmp_proc_show(struct seq_file *m, void *v)
1428 seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1430 info = synclinkmp_device_list;
1433 info = info->next_device;
1438 static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1440 return single_open(file, synclinkmp_proc_show, NULL);
1443 static const struct file_operations synclinkmp_proc_fops = {
1444 .owner = THIS_MODULE,
1445 .open = synclinkmp_proc_open,
1447 .llseek = seq_lseek,
1448 .release = single_release,
1451 /* Return the count of bytes in transmit buffer
1453 static int chars_in_buffer(struct tty_struct *tty)
1455 SLMP_INFO *info = tty->driver_data;
1457 if (sanity_check(info, tty->name, "chars_in_buffer"))
1460 if (debug_level >= DEBUG_LEVEL_INFO)
1461 printk("%s(%d):%s chars_in_buffer()=%d\n",
1462 __FILE__, __LINE__, info->device_name, info->tx_count);
1464 return info->tx_count;
1467 /* Signal remote device to throttle send data (our receive data)
1469 static void throttle(struct tty_struct * tty)
1471 SLMP_INFO *info = tty->driver_data;
1472 unsigned long flags;
1474 if (debug_level >= DEBUG_LEVEL_INFO)
1475 printk("%s(%d):%s throttle() entry\n",
1476 __FILE__,__LINE__, info->device_name );
1478 if (sanity_check(info, tty->name, "throttle"))
1482 send_xchar(tty, STOP_CHAR(tty));
1484 if (tty->termios.c_cflag & CRTSCTS) {
1485 spin_lock_irqsave(&info->lock,flags);
1486 info->serial_signals &= ~SerialSignal_RTS;
1488 spin_unlock_irqrestore(&info->lock,flags);
1492 /* Signal remote device to stop throttling send data (our receive data)
1494 static void unthrottle(struct tty_struct * tty)
1496 SLMP_INFO *info = tty->driver_data;
1497 unsigned long flags;
1499 if (debug_level >= DEBUG_LEVEL_INFO)
1500 printk("%s(%d):%s unthrottle() entry\n",
1501 __FILE__,__LINE__, info->device_name );
1503 if (sanity_check(info, tty->name, "unthrottle"))
1510 send_xchar(tty, START_CHAR(tty));
1513 if (tty->termios.c_cflag & CRTSCTS) {
1514 spin_lock_irqsave(&info->lock,flags);
1515 info->serial_signals |= SerialSignal_RTS;
1517 spin_unlock_irqrestore(&info->lock,flags);
1521 /* set or clear transmit break condition
1522 * break_state -1=set break condition, 0=clear
1524 static int set_break(struct tty_struct *tty, int break_state)
1526 unsigned char RegValue;
1527 SLMP_INFO * info = tty->driver_data;
1528 unsigned long flags;
1530 if (debug_level >= DEBUG_LEVEL_INFO)
1531 printk("%s(%d):%s set_break(%d)\n",
1532 __FILE__,__LINE__, info->device_name, break_state);
1534 if (sanity_check(info, tty->name, "set_break"))
1537 spin_lock_irqsave(&info->lock,flags);
1538 RegValue = read_reg(info, CTL);
1539 if (break_state == -1)
1543 write_reg(info, CTL, RegValue);
1544 spin_unlock_irqrestore(&info->lock,flags);
1548 #if SYNCLINK_GENERIC_HDLC
1551 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1552 * set encoding and frame check sequence (FCS) options
1554 * dev pointer to network device structure
1555 * encoding serial encoding setting
1556 * parity FCS setting
1558 * returns 0 if success, otherwise error code
1560 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1561 unsigned short parity)
1563 SLMP_INFO *info = dev_to_port(dev);
1564 unsigned char new_encoding;
1565 unsigned short new_crctype;
1567 /* return error if TTY interface open */
1568 if (info->port.count)
1573 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1574 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1575 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1576 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1577 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1578 default: return -EINVAL;
1583 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1584 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1585 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1586 default: return -EINVAL;
1589 info->params.encoding = new_encoding;
1590 info->params.crc_type = new_crctype;
1592 /* if network interface up, reprogram hardware */
1600 * called by generic HDLC layer to send frame
1602 * skb socket buffer containing HDLC frame
1603 * dev pointer to network device structure
1605 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1606 struct net_device *dev)
1608 SLMP_INFO *info = dev_to_port(dev);
1609 unsigned long flags;
1611 if (debug_level >= DEBUG_LEVEL_INFO)
1612 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1614 /* stop sending until this frame completes */
1615 netif_stop_queue(dev);
1617 /* copy data to device buffers */
1618 info->tx_count = skb->len;
1619 tx_load_dma_buffer(info, skb->data, skb->len);
1621 /* update network statistics */
1622 dev->stats.tx_packets++;
1623 dev->stats.tx_bytes += skb->len;
1625 /* done with socket buffer, so free it */
1628 /* save start time for transmit timeout detection */
1629 dev->trans_start = jiffies;
1631 /* start hardware transmitter if necessary */
1632 spin_lock_irqsave(&info->lock,flags);
1633 if (!info->tx_active)
1635 spin_unlock_irqrestore(&info->lock,flags);
1637 return NETDEV_TX_OK;
1641 * called by network layer when interface enabled
1642 * claim resources and initialize hardware
1644 * dev pointer to network device structure
1646 * returns 0 if success, otherwise error code
1648 static int hdlcdev_open(struct net_device *dev)
1650 SLMP_INFO *info = dev_to_port(dev);
1652 unsigned long flags;
1654 if (debug_level >= DEBUG_LEVEL_INFO)
1655 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1657 /* generic HDLC layer open processing */
1658 if ((rc = hdlc_open(dev)))
1661 /* arbitrate between network and tty opens */
1662 spin_lock_irqsave(&info->netlock, flags);
1663 if (info->port.count != 0 || info->netcount != 0) {
1664 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1665 spin_unlock_irqrestore(&info->netlock, flags);
1669 spin_unlock_irqrestore(&info->netlock, flags);
1671 /* claim resources and init adapter */
1672 if ((rc = startup(info)) != 0) {
1673 spin_lock_irqsave(&info->netlock, flags);
1675 spin_unlock_irqrestore(&info->netlock, flags);
1679 /* assert DTR and RTS, apply hardware settings */
1680 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1683 /* enable network layer transmit */
1684 dev->trans_start = jiffies;
1685 netif_start_queue(dev);
1687 /* inform generic HDLC layer of current DCD status */
1688 spin_lock_irqsave(&info->lock, flags);
1690 spin_unlock_irqrestore(&info->lock, flags);
1691 if (info->serial_signals & SerialSignal_DCD)
1692 netif_carrier_on(dev);
1694 netif_carrier_off(dev);
1699 * called by network layer when interface is disabled
1700 * shutdown hardware and release resources
1702 * dev pointer to network device structure
1704 * returns 0 if success, otherwise error code
1706 static int hdlcdev_close(struct net_device *dev)
1708 SLMP_INFO *info = dev_to_port(dev);
1709 unsigned long flags;
1711 if (debug_level >= DEBUG_LEVEL_INFO)
1712 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1714 netif_stop_queue(dev);
1716 /* shutdown adapter and release resources */
1721 spin_lock_irqsave(&info->netlock, flags);
1723 spin_unlock_irqrestore(&info->netlock, flags);
1729 * called by network layer to process IOCTL call to network device
1731 * dev pointer to network device structure
1732 * ifr pointer to network interface request structure
1733 * cmd IOCTL command code
1735 * returns 0 if success, otherwise error code
1737 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1739 const size_t size = sizeof(sync_serial_settings);
1740 sync_serial_settings new_line;
1741 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1742 SLMP_INFO *info = dev_to_port(dev);
1745 if (debug_level >= DEBUG_LEVEL_INFO)
1746 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1748 /* return error if TTY interface open */
1749 if (info->port.count)
1752 if (cmd != SIOCWANDEV)
1753 return hdlc_ioctl(dev, ifr, cmd);
1755 switch(ifr->ifr_settings.type) {
1756 case IF_GET_IFACE: /* return current sync_serial_settings */
1758 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1759 if (ifr->ifr_settings.size < size) {
1760 ifr->ifr_settings.size = size; /* data size wanted */
1764 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1765 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1766 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1767 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1770 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1771 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1772 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1773 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1774 default: new_line.clock_type = CLOCK_DEFAULT;
1777 new_line.clock_rate = info->params.clock_speed;
1778 new_line.loopback = info->params.loopback ? 1:0;
1780 if (copy_to_user(line, &new_line, size))
1784 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1786 if(!capable(CAP_NET_ADMIN))
1788 if (copy_from_user(&new_line, line, size))
1791 switch (new_line.clock_type)
1793 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1794 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1795 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1796 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1797 case CLOCK_DEFAULT: flags = info->params.flags &
1798 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1799 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1800 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1801 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1802 default: return -EINVAL;
1805 if (new_line.loopback != 0 && new_line.loopback != 1)
1808 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1809 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1810 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1811 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1812 info->params.flags |= flags;
1814 info->params.loopback = new_line.loopback;
1816 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1817 info->params.clock_speed = new_line.clock_rate;
1819 info->params.clock_speed = 0;
1821 /* if network interface up, reprogram hardware */
1827 return hdlc_ioctl(dev, ifr, cmd);
1832 * called by network layer when transmit timeout is detected
1834 * dev pointer to network device structure
1836 static void hdlcdev_tx_timeout(struct net_device *dev)
1838 SLMP_INFO *info = dev_to_port(dev);
1839 unsigned long flags;
1841 if (debug_level >= DEBUG_LEVEL_INFO)
1842 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1844 dev->stats.tx_errors++;
1845 dev->stats.tx_aborted_errors++;
1847 spin_lock_irqsave(&info->lock,flags);
1849 spin_unlock_irqrestore(&info->lock,flags);
1851 netif_wake_queue(dev);
1855 * called by device driver when transmit completes
1856 * reenable network layer transmit if stopped
1858 * info pointer to device instance information
1860 static void hdlcdev_tx_done(SLMP_INFO *info)
1862 if (netif_queue_stopped(info->netdev))
1863 netif_wake_queue(info->netdev);
1867 * called by device driver when frame received
1868 * pass frame to network layer
1870 * info pointer to device instance information
1871 * buf pointer to buffer contianing frame data
1872 * size count of data bytes in buf
1874 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1876 struct sk_buff *skb = dev_alloc_skb(size);
1877 struct net_device *dev = info->netdev;
1879 if (debug_level >= DEBUG_LEVEL_INFO)
1880 printk("hdlcdev_rx(%s)\n",dev->name);
1883 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1885 dev->stats.rx_dropped++;
1889 memcpy(skb_put(skb, size), buf, size);
1891 skb->protocol = hdlc_type_trans(skb, dev);
1893 dev->stats.rx_packets++;
1894 dev->stats.rx_bytes += size;
1899 static const struct net_device_ops hdlcdev_ops = {
1900 .ndo_open = hdlcdev_open,
1901 .ndo_stop = hdlcdev_close,
1902 .ndo_change_mtu = hdlc_change_mtu,
1903 .ndo_start_xmit = hdlc_start_xmit,
1904 .ndo_do_ioctl = hdlcdev_ioctl,
1905 .ndo_tx_timeout = hdlcdev_tx_timeout,
1909 * called by device driver when adding device instance
1910 * do generic HDLC initialization
1912 * info pointer to device instance information
1914 * returns 0 if success, otherwise error code
1916 static int hdlcdev_init(SLMP_INFO *info)
1919 struct net_device *dev;
1922 /* allocate and initialize network and HDLC layer objects */
1924 if (!(dev = alloc_hdlcdev(info))) {
1925 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1929 /* for network layer reporting purposes only */
1930 dev->mem_start = info->phys_sca_base;
1931 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1932 dev->irq = info->irq_level;
1934 /* network layer callbacks and settings */
1935 dev->netdev_ops = &hdlcdev_ops;
1936 dev->watchdog_timeo = 10 * HZ;
1937 dev->tx_queue_len = 50;
1939 /* generic HDLC layer callbacks and settings */
1940 hdlc = dev_to_hdlc(dev);
1941 hdlc->attach = hdlcdev_attach;
1942 hdlc->xmit = hdlcdev_xmit;
1944 /* register objects with HDLC layer */
1945 if ((rc = register_hdlc_device(dev))) {
1946 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1956 * called by device driver when removing device instance
1957 * do generic HDLC cleanup
1959 * info pointer to device instance information
1961 static void hdlcdev_exit(SLMP_INFO *info)
1963 unregister_hdlc_device(info->netdev);
1964 free_netdev(info->netdev);
1965 info->netdev = NULL;
1968 #endif /* CONFIG_HDLC */
1971 /* Return next bottom half action to perform.
1972 * Return Value: BH action code or 0 if nothing to do.
1974 static int bh_action(SLMP_INFO *info)
1976 unsigned long flags;
1979 spin_lock_irqsave(&info->lock,flags);
1981 if (info->pending_bh & BH_RECEIVE) {
1982 info->pending_bh &= ~BH_RECEIVE;
1984 } else if (info->pending_bh & BH_TRANSMIT) {
1985 info->pending_bh &= ~BH_TRANSMIT;
1987 } else if (info->pending_bh & BH_STATUS) {
1988 info->pending_bh &= ~BH_STATUS;
1993 /* Mark BH routine as complete */
1994 info->bh_running = false;
1995 info->bh_requested = false;
1998 spin_unlock_irqrestore(&info->lock,flags);
2003 /* Perform bottom half processing of work items queued by ISR.
2005 static void bh_handler(struct work_struct *work)
2007 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2013 if ( debug_level >= DEBUG_LEVEL_BH )
2014 printk( "%s(%d):%s bh_handler() entry\n",
2015 __FILE__,__LINE__,info->device_name);
2017 info->bh_running = true;
2019 while((action = bh_action(info)) != 0) {
2021 /* Process work item */
2022 if ( debug_level >= DEBUG_LEVEL_BH )
2023 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2024 __FILE__,__LINE__,info->device_name, action);
2038 /* unknown work item ID */
2039 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2040 __FILE__,__LINE__,info->device_name,action);
2045 if ( debug_level >= DEBUG_LEVEL_BH )
2046 printk( "%s(%d):%s bh_handler() exit\n",
2047 __FILE__,__LINE__,info->device_name);
2050 static void bh_receive(SLMP_INFO *info)
2052 if ( debug_level >= DEBUG_LEVEL_BH )
2053 printk( "%s(%d):%s bh_receive()\n",
2054 __FILE__,__LINE__,info->device_name);
2056 while( rx_get_frame(info) );
2059 static void bh_transmit(SLMP_INFO *info)
2061 struct tty_struct *tty = info->port.tty;
2063 if ( debug_level >= DEBUG_LEVEL_BH )
2064 printk( "%s(%d):%s bh_transmit() entry\n",
2065 __FILE__,__LINE__,info->device_name);
2071 static void bh_status(SLMP_INFO *info)
2073 if ( debug_level >= DEBUG_LEVEL_BH )
2074 printk( "%s(%d):%s bh_status() entry\n",
2075 __FILE__,__LINE__,info->device_name);
2077 info->ri_chkcount = 0;
2078 info->dsr_chkcount = 0;
2079 info->dcd_chkcount = 0;
2080 info->cts_chkcount = 0;
2083 static void isr_timer(SLMP_INFO * info)
2085 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2087 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2088 write_reg(info, IER2, 0);
2090 /* TMCS, Timer Control/Status Register
2092 * 07 CMF, Compare match flag (read only) 1=match
2093 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2094 * 05 Reserved, must be 0
2095 * 04 TME, Timer Enable
2096 * 03..00 Reserved, must be 0
2100 write_reg(info, (unsigned char)(timer + TMCS), 0);
2102 info->irq_occurred = true;
2104 if ( debug_level >= DEBUG_LEVEL_ISR )
2105 printk("%s(%d):%s isr_timer()\n",
2106 __FILE__,__LINE__,info->device_name);
2109 static void isr_rxint(SLMP_INFO * info)
2111 struct tty_struct *tty = info->port.tty;
2112 struct mgsl_icount *icount = &info->icount;
2113 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2114 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2116 /* clear status bits */
2118 write_reg(info, SR1, status);
2121 write_reg(info, SR2, status2);
2123 if ( debug_level >= DEBUG_LEVEL_ISR )
2124 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2125 __FILE__,__LINE__,info->device_name,status,status2);
2127 if (info->params.mode == MGSL_MODE_ASYNC) {
2128 if (status & BRKD) {
2131 /* process break detection if tty control
2132 * is not set to ignore it
2134 if (!(status & info->ignore_status_mask1)) {
2135 if (info->read_status_mask1 & BRKD) {
2136 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2137 if (tty && (info->port.flags & ASYNC_SAK))
2144 if (status & (FLGD|IDLD)) {
2146 info->icount.exithunt++;
2147 else if (status & IDLD)
2148 info->icount.rxidle++;
2149 wake_up_interruptible(&info->event_wait_q);
2153 if (status & CDCD) {
2154 /* simulate a common modem status change interrupt
2157 get_signals( info );
2159 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2164 * handle async rx data interrupts
2166 static void isr_rxrdy(SLMP_INFO * info)
2169 unsigned char DataByte;
2170 struct mgsl_icount *icount = &info->icount;
2172 if ( debug_level >= DEBUG_LEVEL_ISR )
2173 printk("%s(%d):%s isr_rxrdy\n",
2174 __FILE__,__LINE__,info->device_name);
2176 while((status = read_reg(info,CST0)) & BIT0)
2180 DataByte = read_reg(info,TRB);
2184 if ( status & (PE + FRME + OVRN) ) {
2185 printk("%s(%d):%s rxerr=%04X\n",
2186 __FILE__,__LINE__,info->device_name,status);
2188 /* update error statistics */
2191 else if (status & FRME)
2193 else if (status & OVRN)
2196 /* discard char if tty control flags say so */
2197 if (status & info->ignore_status_mask2)
2200 status &= info->read_status_mask2;
2204 else if (status & FRME)
2206 if (status & OVRN) {
2207 /* Overrun is special, since it's
2208 * reported immediately, and doesn't
2209 * affect the current character
2213 } /* end of if (error) */
2215 tty_insert_flip_char(&info->port, DataByte, flag);
2217 tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
2220 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2221 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2222 __FILE__,__LINE__,info->device_name,
2223 icount->rx,icount->brk,icount->parity,
2224 icount->frame,icount->overrun);
2227 tty_flip_buffer_push(&info->port);
2230 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2232 if ( debug_level >= DEBUG_LEVEL_ISR )
2233 printk("%s(%d):%s isr_txeom status=%02x\n",
2234 __FILE__,__LINE__,info->device_name,status);
2236 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2237 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2238 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2240 if (status & UDRN) {
2241 write_reg(info, CMD, TXRESET);
2242 write_reg(info, CMD, TXENABLE);
2244 write_reg(info, CMD, TXBUFCLR);
2246 /* disable and clear tx interrupts */
2247 info->ie0_value &= ~TXRDYE;
2248 info->ie1_value &= ~(IDLE + UDRN);
2249 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2250 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2252 if ( info->tx_active ) {
2253 if (info->params.mode != MGSL_MODE_ASYNC) {
2255 info->icount.txunder++;
2256 else if (status & IDLE)
2257 info->icount.txok++;
2260 info->tx_active = false;
2261 info->tx_count = info->tx_put = info->tx_get = 0;
2263 del_timer(&info->tx_timer);
2265 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2266 info->serial_signals &= ~SerialSignal_RTS;
2267 info->drop_rts_on_tx_done = false;
2271 #if SYNCLINK_GENERIC_HDLC
2273 hdlcdev_tx_done(info);
2277 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2281 info->pending_bh |= BH_TRANSMIT;
2288 * handle tx status interrupts
2290 static void isr_txint(SLMP_INFO * info)
2292 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2294 /* clear status bits */
2295 write_reg(info, SR1, status);
2297 if ( debug_level >= DEBUG_LEVEL_ISR )
2298 printk("%s(%d):%s isr_txint status=%02x\n",
2299 __FILE__,__LINE__,info->device_name,status);
2301 if (status & (UDRN + IDLE))
2302 isr_txeom(info, status);
2304 if (status & CCTS) {
2305 /* simulate a common modem status change interrupt
2308 get_signals( info );
2310 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2316 * handle async tx data interrupts
2318 static void isr_txrdy(SLMP_INFO * info)
2320 if ( debug_level >= DEBUG_LEVEL_ISR )
2321 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2322 __FILE__,__LINE__,info->device_name,info->tx_count);
2324 if (info->params.mode != MGSL_MODE_ASYNC) {
2325 /* disable TXRDY IRQ, enable IDLE IRQ */
2326 info->ie0_value &= ~TXRDYE;
2327 info->ie1_value |= IDLE;
2328 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2332 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2337 if ( info->tx_count )
2338 tx_load_fifo( info );
2340 info->tx_active = false;
2341 info->ie0_value &= ~TXRDYE;
2342 write_reg(info, IE0, info->ie0_value);
2345 if (info->tx_count < WAKEUP_CHARS)
2346 info->pending_bh |= BH_TRANSMIT;
2349 static void isr_rxdmaok(SLMP_INFO * info)
2351 /* BIT7 = EOT (end of transfer)
2352 * BIT6 = EOM (end of message/frame)
2354 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2356 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2357 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2359 if ( debug_level >= DEBUG_LEVEL_ISR )
2360 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2361 __FILE__,__LINE__,info->device_name,status);
2363 info->pending_bh |= BH_RECEIVE;
2366 static void isr_rxdmaerror(SLMP_INFO * info)
2368 /* BIT5 = BOF (buffer overflow)
2369 * BIT4 = COF (counter overflow)
2371 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2373 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2374 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2376 if ( debug_level >= DEBUG_LEVEL_ISR )
2377 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2378 __FILE__,__LINE__,info->device_name,status);
2380 info->rx_overflow = true;
2381 info->pending_bh |= BH_RECEIVE;
2384 static void isr_txdmaok(SLMP_INFO * info)
2386 unsigned char status_reg1 = read_reg(info, SR1);
2388 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2389 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2390 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2392 if ( debug_level >= DEBUG_LEVEL_ISR )
2393 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2394 __FILE__,__LINE__,info->device_name,status_reg1);
2396 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2397 write_reg16(info, TRC0, 0);
2398 info->ie0_value |= TXRDYE;
2399 write_reg(info, IE0, info->ie0_value);
2402 static void isr_txdmaerror(SLMP_INFO * info)
2404 /* BIT5 = BOF (buffer overflow)
2405 * BIT4 = COF (counter overflow)
2407 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2409 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2410 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2412 if ( debug_level >= DEBUG_LEVEL_ISR )
2413 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2414 __FILE__,__LINE__,info->device_name,status);
2417 /* handle input serial signal changes
2419 static void isr_io_pin( SLMP_INFO *info, u16 status )
2421 struct mgsl_icount *icount;
2423 if ( debug_level >= DEBUG_LEVEL_ISR )
2424 printk("%s(%d):isr_io_pin status=%04X\n",
2425 __FILE__,__LINE__,status);
2427 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2428 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2429 icount = &info->icount;
2430 /* update input line counters */
2431 if (status & MISCSTATUS_RI_LATCHED) {
2433 if ( status & SerialSignal_RI )
2434 info->input_signal_events.ri_up++;
2436 info->input_signal_events.ri_down++;
2438 if (status & MISCSTATUS_DSR_LATCHED) {
2440 if ( status & SerialSignal_DSR )
2441 info->input_signal_events.dsr_up++;
2443 info->input_signal_events.dsr_down++;
2445 if (status & MISCSTATUS_DCD_LATCHED) {
2446 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2447 info->ie1_value &= ~CDCD;
2448 write_reg(info, IE1, info->ie1_value);
2451 if (status & SerialSignal_DCD) {
2452 info->input_signal_events.dcd_up++;
2454 info->input_signal_events.dcd_down++;
2455 #if SYNCLINK_GENERIC_HDLC
2456 if (info->netcount) {
2457 if (status & SerialSignal_DCD)
2458 netif_carrier_on(info->netdev);
2460 netif_carrier_off(info->netdev);
2464 if (status & MISCSTATUS_CTS_LATCHED)
2466 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2467 info->ie1_value &= ~CCTS;
2468 write_reg(info, IE1, info->ie1_value);
2471 if ( status & SerialSignal_CTS )
2472 info->input_signal_events.cts_up++;
2474 info->input_signal_events.cts_down++;
2476 wake_up_interruptible(&info->status_event_wait_q);
2477 wake_up_interruptible(&info->event_wait_q);
2479 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2480 (status & MISCSTATUS_DCD_LATCHED) ) {
2481 if ( debug_level >= DEBUG_LEVEL_ISR )
2482 printk("%s CD now %s...", info->device_name,
2483 (status & SerialSignal_DCD) ? "on" : "off");
2484 if (status & SerialSignal_DCD)
2485 wake_up_interruptible(&info->port.open_wait);
2487 if ( debug_level >= DEBUG_LEVEL_ISR )
2488 printk("doing serial hangup...");
2490 tty_hangup(info->port.tty);
2494 if (tty_port_cts_enabled(&info->port) &&
2495 (status & MISCSTATUS_CTS_LATCHED) ) {
2496 if ( info->port.tty ) {
2497 if (info->port.tty->hw_stopped) {
2498 if (status & SerialSignal_CTS) {
2499 if ( debug_level >= DEBUG_LEVEL_ISR )
2500 printk("CTS tx start...");
2501 info->port.tty->hw_stopped = 0;
2503 info->pending_bh |= BH_TRANSMIT;
2507 if (!(status & SerialSignal_CTS)) {
2508 if ( debug_level >= DEBUG_LEVEL_ISR )
2509 printk("CTS tx stop...");
2510 info->port.tty->hw_stopped = 1;
2518 info->pending_bh |= BH_STATUS;
2521 /* Interrupt service routine entry point.
2524 * irq interrupt number that caused interrupt
2525 * dev_id device ID supplied during interrupt registration
2526 * regs interrupted processor context
2528 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2530 SLMP_INFO *info = dev_id;
2531 unsigned char status, status0, status1=0;
2532 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2533 unsigned char timerstatus0, timerstatus1=0;
2534 unsigned char shift;
2538 if ( debug_level >= DEBUG_LEVEL_ISR )
2539 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2540 __FILE__, __LINE__, info->irq_level);
2542 spin_lock(&info->lock);
2546 /* get status for SCA0 (ports 0-1) */
2547 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2548 status0 = (unsigned char)tmp;
2549 dmastatus0 = (unsigned char)(tmp>>8);
2550 timerstatus0 = read_reg(info, ISR2);
2552 if ( debug_level >= DEBUG_LEVEL_ISR )
2553 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2554 __FILE__, __LINE__, info->device_name,
2555 status0, dmastatus0, timerstatus0);
2557 if (info->port_count == 4) {
2558 /* get status for SCA1 (ports 2-3) */
2559 tmp = read_reg16(info->port_array[2], ISR0);
2560 status1 = (unsigned char)tmp;
2561 dmastatus1 = (unsigned char)(tmp>>8);
2562 timerstatus1 = read_reg(info->port_array[2], ISR2);
2564 if ( debug_level >= DEBUG_LEVEL_ISR )
2565 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2566 __FILE__,__LINE__,info->device_name,
2567 status1,dmastatus1,timerstatus1);
2570 if (!status0 && !dmastatus0 && !timerstatus0 &&
2571 !status1 && !dmastatus1 && !timerstatus1)
2574 for(i=0; i < info->port_count ; i++) {
2575 if (info->port_array[i] == NULL)
2579 dmastatus = dmastatus0;
2582 dmastatus = dmastatus1;
2585 shift = i & 1 ? 4 :0;
2587 if (status & BIT0 << shift)
2588 isr_rxrdy(info->port_array[i]);
2589 if (status & BIT1 << shift)
2590 isr_txrdy(info->port_array[i]);
2591 if (status & BIT2 << shift)
2592 isr_rxint(info->port_array[i]);
2593 if (status & BIT3 << shift)
2594 isr_txint(info->port_array[i]);
2596 if (dmastatus & BIT0 << shift)
2597 isr_rxdmaerror(info->port_array[i]);
2598 if (dmastatus & BIT1 << shift)
2599 isr_rxdmaok(info->port_array[i]);
2600 if (dmastatus & BIT2 << shift)
2601 isr_txdmaerror(info->port_array[i]);
2602 if (dmastatus & BIT3 << shift)
2603 isr_txdmaok(info->port_array[i]);
2606 if (timerstatus0 & (BIT5 | BIT4))
2607 isr_timer(info->port_array[0]);
2608 if (timerstatus0 & (BIT7 | BIT6))
2609 isr_timer(info->port_array[1]);
2610 if (timerstatus1 & (BIT5 | BIT4))
2611 isr_timer(info->port_array[2]);
2612 if (timerstatus1 & (BIT7 | BIT6))
2613 isr_timer(info->port_array[3]);
2616 for(i=0; i < info->port_count ; i++) {
2617 SLMP_INFO * port = info->port_array[i];
2619 /* Request bottom half processing if there's something
2620 * for it to do and the bh is not already running.
2622 * Note: startup adapter diags require interrupts.
2623 * do not request bottom half processing if the
2624 * device is not open in a normal mode.
2626 if ( port && (port->port.count || port->netcount) &&
2627 port->pending_bh && !port->bh_running &&
2628 !port->bh_requested ) {
2629 if ( debug_level >= DEBUG_LEVEL_ISR )
2630 printk("%s(%d):%s queueing bh task.\n",
2631 __FILE__,__LINE__,port->device_name);
2632 schedule_work(&port->task);
2633 port->bh_requested = true;
2637 spin_unlock(&info->lock);
2639 if ( debug_level >= DEBUG_LEVEL_ISR )
2640 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2641 __FILE__, __LINE__, info->irq_level);
2645 /* Initialize and start device.
2647 static int startup(SLMP_INFO * info)
2649 if ( debug_level >= DEBUG_LEVEL_INFO )
2650 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2652 if (info->port.flags & ASYNC_INITIALIZED)
2655 if (!info->tx_buf) {
2656 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2657 if (!info->tx_buf) {
2658 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2659 __FILE__,__LINE__,info->device_name);
2664 info->pending_bh = 0;
2666 memset(&info->icount, 0, sizeof(info->icount));
2668 /* program hardware for current parameters */
2671 change_params(info);
2673 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2676 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2678 info->port.flags |= ASYNC_INITIALIZED;
2683 /* Called by close() and hangup() to shutdown hardware
2685 static void shutdown(SLMP_INFO * info)
2687 unsigned long flags;
2689 if (!(info->port.flags & ASYNC_INITIALIZED))
2692 if (debug_level >= DEBUG_LEVEL_INFO)
2693 printk("%s(%d):%s synclinkmp_shutdown()\n",
2694 __FILE__,__LINE__, info->device_name );
2696 /* clear status wait queue because status changes */
2697 /* can't happen after shutting down the hardware */
2698 wake_up_interruptible(&info->status_event_wait_q);
2699 wake_up_interruptible(&info->event_wait_q);
2701 del_timer(&info->tx_timer);
2702 del_timer(&info->status_timer);
2704 kfree(info->tx_buf);
2705 info->tx_buf = NULL;
2707 spin_lock_irqsave(&info->lock,flags);
2711 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2712 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2716 spin_unlock_irqrestore(&info->lock,flags);
2719 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2721 info->port.flags &= ~ASYNC_INITIALIZED;
2724 static void program_hw(SLMP_INFO *info)
2726 unsigned long flags;
2728 spin_lock_irqsave(&info->lock,flags);
2733 info->tx_count = info->tx_put = info->tx_get = 0;
2735 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2742 info->dcd_chkcount = 0;
2743 info->cts_chkcount = 0;
2744 info->ri_chkcount = 0;
2745 info->dsr_chkcount = 0;
2747 info->ie1_value |= (CDCD|CCTS);
2748 write_reg(info, IE1, info->ie1_value);
2752 if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) )
2755 spin_unlock_irqrestore(&info->lock,flags);
2758 /* Reconfigure adapter based on new parameters
2760 static void change_params(SLMP_INFO *info)
2765 if (!info->port.tty)
2768 if (debug_level >= DEBUG_LEVEL_INFO)
2769 printk("%s(%d):%s change_params()\n",
2770 __FILE__,__LINE__, info->device_name );
2772 cflag = info->port.tty->termios.c_cflag;
2774 /* if B0 rate (hangup) specified then negate DTR and RTS */
2775 /* otherwise assert DTR and RTS */
2777 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2779 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2781 /* byte size and parity */
2783 switch (cflag & CSIZE) {
2784 case CS5: info->params.data_bits = 5; break;
2785 case CS6: info->params.data_bits = 6; break;
2786 case CS7: info->params.data_bits = 7; break;
2787 case CS8: info->params.data_bits = 8; break;
2788 /* Never happens, but GCC is too dumb to figure it out */
2789 default: info->params.data_bits = 7; break;
2793 info->params.stop_bits = 2;
2795 info->params.stop_bits = 1;
2797 info->params.parity = ASYNC_PARITY_NONE;
2798 if (cflag & PARENB) {
2800 info->params.parity = ASYNC_PARITY_ODD;
2802 info->params.parity = ASYNC_PARITY_EVEN;
2805 info->params.parity = ASYNC_PARITY_SPACE;
2809 /* calculate number of jiffies to transmit a full
2810 * FIFO (32 bytes) at specified data rate
2812 bits_per_char = info->params.data_bits +
2813 info->params.stop_bits + 1;
2815 /* if port data rate is set to 460800 or less then
2816 * allow tty settings to override, otherwise keep the
2817 * current data rate.
2819 if (info->params.data_rate <= 460800) {
2820 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2823 if ( info->params.data_rate ) {
2824 info->timeout = (32*HZ*bits_per_char) /
2825 info->params.data_rate;
2827 info->timeout += HZ/50; /* Add .02 seconds of slop */
2829 if (cflag & CRTSCTS)
2830 info->port.flags |= ASYNC_CTS_FLOW;
2832 info->port.flags &= ~ASYNC_CTS_FLOW;
2835 info->port.flags &= ~ASYNC_CHECK_CD;
2837 info->port.flags |= ASYNC_CHECK_CD;
2839 /* process tty input control flags */
2841 info->read_status_mask2 = OVRN;
2842 if (I_INPCK(info->port.tty))
2843 info->read_status_mask2 |= PE | FRME;
2844 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2845 info->read_status_mask1 |= BRKD;
2846 if (I_IGNPAR(info->port.tty))
2847 info->ignore_status_mask2 |= PE | FRME;
2848 if (I_IGNBRK(info->port.tty)) {
2849 info->ignore_status_mask1 |= BRKD;
2850 /* If ignoring parity and break indicators, ignore
2851 * overruns too. (For real raw support).
2853 if (I_IGNPAR(info->port.tty))
2854 info->ignore_status_mask2 |= OVRN;
2860 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2864 if (debug_level >= DEBUG_LEVEL_INFO)
2865 printk("%s(%d):%s get_params()\n",
2866 __FILE__,__LINE__, info->device_name);
2869 memset(&info->icount, 0, sizeof(info->icount));
2871 mutex_lock(&info->port.mutex);
2872 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2873 mutex_unlock(&info->port.mutex);
2881 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2884 if (debug_level >= DEBUG_LEVEL_INFO)
2885 printk("%s(%d):%s get_params()\n",
2886 __FILE__,__LINE__, info->device_name);
2888 mutex_lock(&info->port.mutex);
2889 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2890 mutex_unlock(&info->port.mutex);
2892 if ( debug_level >= DEBUG_LEVEL_INFO )
2893 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2894 __FILE__,__LINE__,info->device_name);
2901 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2903 unsigned long flags;
2904 MGSL_PARAMS tmp_params;
2907 if (debug_level >= DEBUG_LEVEL_INFO)
2908 printk("%s(%d):%s set_params\n",
2909 __FILE__,__LINE__,info->device_name );
2910 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2912 if ( debug_level >= DEBUG_LEVEL_INFO )
2913 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2914 __FILE__,__LINE__,info->device_name);
2918 mutex_lock(&info->port.mutex);
2919 spin_lock_irqsave(&info->lock,flags);
2920 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2921 spin_unlock_irqrestore(&info->lock,flags);
2923 change_params(info);
2924 mutex_unlock(&info->port.mutex);
2929 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2933 if (debug_level >= DEBUG_LEVEL_INFO)
2934 printk("%s(%d):%s get_txidle()=%d\n",
2935 __FILE__,__LINE__, info->device_name, info->idle_mode);
2937 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2939 if ( debug_level >= DEBUG_LEVEL_INFO )
2940 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2941 __FILE__,__LINE__,info->device_name);
2948 static int set_txidle(SLMP_INFO * info, int idle_mode)
2950 unsigned long flags;
2952 if (debug_level >= DEBUG_LEVEL_INFO)
2953 printk("%s(%d):%s set_txidle(%d)\n",
2954 __FILE__,__LINE__,info->device_name, idle_mode );
2956 spin_lock_irqsave(&info->lock,flags);
2957 info->idle_mode = idle_mode;
2958 tx_set_idle( info );
2959 spin_unlock_irqrestore(&info->lock,flags);
2963 static int tx_enable(SLMP_INFO * info, int enable)
2965 unsigned long flags;
2967 if (debug_level >= DEBUG_LEVEL_INFO)
2968 printk("%s(%d):%s tx_enable(%d)\n",
2969 __FILE__,__LINE__,info->device_name, enable);
2971 spin_lock_irqsave(&info->lock,flags);
2973 if ( !info->tx_enabled ) {
2977 if ( info->tx_enabled )
2980 spin_unlock_irqrestore(&info->lock,flags);
2984 /* abort send HDLC frame
2986 static int tx_abort(SLMP_INFO * info)
2988 unsigned long flags;
2990 if (debug_level >= DEBUG_LEVEL_INFO)
2991 printk("%s(%d):%s tx_abort()\n",
2992 __FILE__,__LINE__,info->device_name);
2994 spin_lock_irqsave(&info->lock,flags);
2995 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2996 info->ie1_value &= ~UDRN;
2997 info->ie1_value |= IDLE;
2998 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
2999 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
3001 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
3002 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3004 write_reg(info, CMD, TXABORT);
3006 spin_unlock_irqrestore(&info->lock,flags);
3010 static int rx_enable(SLMP_INFO * info, int enable)
3012 unsigned long flags;
3014 if (debug_level >= DEBUG_LEVEL_INFO)
3015 printk("%s(%d):%s rx_enable(%d)\n",
3016 __FILE__,__LINE__,info->device_name,enable);
3018 spin_lock_irqsave(&info->lock,flags);
3020 if ( !info->rx_enabled )
3023 if ( info->rx_enabled )
3026 spin_unlock_irqrestore(&info->lock,flags);
3030 /* wait for specified event to occur
3032 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3034 unsigned long flags;
3037 struct mgsl_icount cprev, cnow;
3040 struct _input_signal_events oldsigs, newsigs;
3041 DECLARE_WAITQUEUE(wait, current);
3043 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3048 if (debug_level >= DEBUG_LEVEL_INFO)
3049 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3050 __FILE__,__LINE__,info->device_name,mask);
3052 spin_lock_irqsave(&info->lock,flags);
3054 /* return immediately if state matches requested events */
3056 s = info->serial_signals;
3059 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3060 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3061 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3062 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3064 spin_unlock_irqrestore(&info->lock,flags);
3068 /* save current irq counts */
3069 cprev = info->icount;
3070 oldsigs = info->input_signal_events;
3072 /* enable hunt and idle irqs if needed */
3073 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3074 unsigned char oldval = info->ie1_value;
3075 unsigned char newval = oldval +
3076 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3077 (mask & MgslEvent_IdleReceived ? IDLD:0);
3078 if ( oldval != newval ) {
3079 info->ie1_value = newval;
3080 write_reg(info, IE1, info->ie1_value);
3084 set_current_state(TASK_INTERRUPTIBLE);
3085 add_wait_queue(&info->event_wait_q, &wait);
3087 spin_unlock_irqrestore(&info->lock,flags);
3091 if (signal_pending(current)) {
3096 /* get current irq counts */
3097 spin_lock_irqsave(&info->lock,flags);
3098 cnow = info->icount;
3099 newsigs = info->input_signal_events;
3100 set_current_state(TASK_INTERRUPTIBLE);
3101 spin_unlock_irqrestore(&info->lock,flags);
3103 /* if no change, wait aborted for some reason */
3104 if (newsigs.dsr_up == oldsigs.dsr_up &&
3105 newsigs.dsr_down == oldsigs.dsr_down &&
3106 newsigs.dcd_up == oldsigs.dcd_up &&
3107 newsigs.dcd_down == oldsigs.dcd_down &&
3108 newsigs.cts_up == oldsigs.cts_up &&
3109 newsigs.cts_down == oldsigs.cts_down &&
3110 newsigs.ri_up == oldsigs.ri_up &&
3111 newsigs.ri_down == oldsigs.ri_down &&
3112 cnow.exithunt == cprev.exithunt &&
3113 cnow.rxidle == cprev.rxidle) {
3119 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3120 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3121 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3122 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3123 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3124 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3125 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3126 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3127 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3128 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3136 remove_wait_queue(&info->event_wait_q, &wait);
3137 set_current_state(TASK_RUNNING);
3140 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3141 spin_lock_irqsave(&info->lock,flags);
3142 if (!waitqueue_active(&info->event_wait_q)) {
3143 /* disable enable exit hunt mode/idle rcvd IRQs */
3144 info->ie1_value &= ~(FLGD|IDLD);
3145 write_reg(info, IE1, info->ie1_value);
3147 spin_unlock_irqrestore(&info->lock,flags);
3151 PUT_USER(rc, events, mask_ptr);
3156 static int modem_input_wait(SLMP_INFO *info,int arg)
3158 unsigned long flags;
3160 struct mgsl_icount cprev, cnow;
3161 DECLARE_WAITQUEUE(wait, current);
3163 /* save current irq counts */
3164 spin_lock_irqsave(&info->lock,flags);
3165 cprev = info->icount;
3166 add_wait_queue(&info->status_event_wait_q, &wait);
3167 set_current_state(TASK_INTERRUPTIBLE);
3168 spin_unlock_irqrestore(&info->lock,flags);
3172 if (signal_pending(current)) {
3177 /* get new irq counts */
3178 spin_lock_irqsave(&info->lock,flags);
3179 cnow = info->icount;
3180 set_current_state(TASK_INTERRUPTIBLE);
3181 spin_unlock_irqrestore(&info->lock,flags);
3183 /* if no change, wait aborted for some reason */
3184 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3185 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3190 /* check for change in caller specified modem input */
3191 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3192 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3193 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3194 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3201 remove_wait_queue(&info->status_event_wait_q, &wait);
3202 set_current_state(TASK_RUNNING);
3206 /* return the state of the serial control and status signals
3208 static int tiocmget(struct tty_struct *tty)
3210 SLMP_INFO *info = tty->driver_data;
3211 unsigned int result;
3212 unsigned long flags;
3214 spin_lock_irqsave(&info->lock,flags);
3216 spin_unlock_irqrestore(&info->lock,flags);
3218 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3219 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3220 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3221 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3222 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3223 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3225 if (debug_level >= DEBUG_LEVEL_INFO)
3226 printk("%s(%d):%s tiocmget() value=%08X\n",
3227 __FILE__,__LINE__, info->device_name, result );
3231 /* set modem control signals (DTR/RTS)
3233 static int tiocmset(struct tty_struct *tty,
3234 unsigned int set, unsigned int clear)
3236 SLMP_INFO *info = tty->driver_data;
3237 unsigned long flags;
3239 if (debug_level >= DEBUG_LEVEL_INFO)
3240 printk("%s(%d):%s tiocmset(%x,%x)\n",
3241 __FILE__,__LINE__,info->device_name, set, clear);
3243 if (set & TIOCM_RTS)
3244 info->serial_signals |= SerialSignal_RTS;
3245 if (set & TIOCM_DTR)
3246 info->serial_signals |= SerialSignal_DTR;
3247 if (clear & TIOCM_RTS)
3248 info->serial_signals &= ~SerialSignal_RTS;
3249 if (clear & TIOCM_DTR)
3250 info->serial_signals &= ~SerialSignal_DTR;
3252 spin_lock_irqsave(&info->lock,flags);
3254 spin_unlock_irqrestore(&info->lock,flags);
3259 static int carrier_raised(struct tty_port *port)
3261 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3262 unsigned long flags;
3264 spin_lock_irqsave(&info->lock,flags);
3266 spin_unlock_irqrestore(&info->lock,flags);
3268 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3271 static void dtr_rts(struct tty_port *port, int on)
3273 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3274 unsigned long flags;
3276 spin_lock_irqsave(&info->lock,flags);
3278 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3280 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3282 spin_unlock_irqrestore(&info->lock,flags);
3285 /* Block the current process until the specified port is ready to open.
3287 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3290 DECLARE_WAITQUEUE(wait, current);
3292 bool do_clocal = false;
3293 bool extra_count = false;
3294 unsigned long flags;
3296 struct tty_port *port = &info->port;
3298 if (debug_level >= DEBUG_LEVEL_INFO)
3299 printk("%s(%d):%s block_til_ready()\n",
3300 __FILE__,__LINE__, tty->driver->name );
3302 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3303 /* nonblock mode is set or port is not enabled */
3304 /* just verify that callout device is not active */
3305 port->flags |= ASYNC_NORMAL_ACTIVE;
3309 if (tty->termios.c_cflag & CLOCAL)
3312 /* Wait for carrier detect and the line to become
3313 * free (i.e., not in use by the callout). While we are in
3314 * this loop, port->count is dropped by one, so that
3315 * close() knows when to free things. We restore it upon
3316 * exit, either normal or abnormal.
3320 add_wait_queue(&port->open_wait, &wait);
3322 if (debug_level >= DEBUG_LEVEL_INFO)
3323 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3324 __FILE__,__LINE__, tty->driver->name, port->count );
3326 spin_lock_irqsave(&info->lock, flags);
3327 if (!tty_hung_up_p(filp)) {
3331 spin_unlock_irqrestore(&info->lock, flags);
3332 port->blocked_open++;
3335 if (tty->termios.c_cflag & CBAUD)
3336 tty_port_raise_dtr_rts(port);
3338 set_current_state(TASK_INTERRUPTIBLE);
3340 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3341 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3342 -EAGAIN : -ERESTARTSYS;
3346 cd = tty_port_carrier_raised(port);
3348 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd))
3351 if (signal_pending(current)) {
3352 retval = -ERESTARTSYS;
3356 if (debug_level >= DEBUG_LEVEL_INFO)
3357 printk("%s(%d):%s block_til_ready() count=%d\n",
3358 __FILE__,__LINE__, tty->driver->name, port->count );
3365 set_current_state(TASK_RUNNING);
3366 remove_wait_queue(&port->open_wait, &wait);
3370 port->blocked_open--;
3372 if (debug_level >= DEBUG_LEVEL_INFO)
3373 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3374 __FILE__,__LINE__, tty->driver->name, port->count );
3377 port->flags |= ASYNC_NORMAL_ACTIVE;
3382 static int alloc_dma_bufs(SLMP_INFO *info)
3384 unsigned short BuffersPerFrame;
3385 unsigned short BufferCount;
3387 // Force allocation to start at 64K boundary for each port.
3388 // This is necessary because *all* buffer descriptors for a port
3389 // *must* be in the same 64K block. All descriptors on a port
3390 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3391 // into the CBP register.
3392 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3394 /* Calculate the number of DMA buffers necessary to hold the */
3395 /* largest allowable frame size. Note: If the max frame size is */
3396 /* not an even multiple of the DMA buffer size then we need to */
3397 /* round the buffer count per frame up one. */
3399 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3400 if ( info->max_frame_size % SCABUFSIZE )
3403 /* calculate total number of data buffers (SCABUFSIZE) possible
3404 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3405 * for the descriptor list (BUFFERLISTSIZE).
3407 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3409 /* limit number of buffers to maximum amount of descriptors */
3410 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3411 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3413 /* use enough buffers to transmit one max size frame */
3414 info->tx_buf_count = BuffersPerFrame + 1;
3416 /* never use more than half the available buffers for transmit */
3417 if (info->tx_buf_count > (BufferCount/2))
3418 info->tx_buf_count = BufferCount/2;
3420 if (info->tx_buf_count > SCAMAXDESC)
3421 info->tx_buf_count = SCAMAXDESC;
3423 /* use remaining buffers for receive */
3424 info->rx_buf_count = BufferCount - info->tx_buf_count;
3426 if (info->rx_buf_count > SCAMAXDESC)
3427 info->rx_buf_count = SCAMAXDESC;
3429 if ( debug_level >= DEBUG_LEVEL_INFO )
3430 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3431 __FILE__,__LINE__, info->device_name,
3432 info->tx_buf_count,info->rx_buf_count);
3434 if ( alloc_buf_list( info ) < 0 ||
3435 alloc_frame_bufs(info,
3437 info->rx_buf_list_ex,
3438 info->rx_buf_count) < 0 ||
3439 alloc_frame_bufs(info,
3441 info->tx_buf_list_ex,
3442 info->tx_buf_count) < 0 ||
3443 alloc_tmp_rx_buf(info) < 0 ) {
3444 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3445 __FILE__,__LINE__, info->device_name);
3449 rx_reset_buffers( info );
3454 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3456 static int alloc_buf_list(SLMP_INFO *info)
3460 /* build list in adapter shared memory */
3461 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3462 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3463 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3465 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3467 /* Save virtual address pointers to the receive and */
3468 /* transmit buffer lists. (Receive 1st). These pointers will */
3469 /* be used by the processor to access the lists. */
3470 info->rx_buf_list = (SCADESC *)info->buffer_list;
3472 info->tx_buf_list = (SCADESC *)info->buffer_list;
3473 info->tx_buf_list += info->rx_buf_count;
3475 /* Build links for circular buffer entry lists (tx and rx)
3477 * Note: links are physical addresses read by the SCA device
3478 * to determine the next buffer entry to use.
3481 for ( i = 0; i < info->rx_buf_count; i++ ) {
3482 /* calculate and store physical address of this buffer entry */
3483 info->rx_buf_list_ex[i].phys_entry =
3484 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3486 /* calculate and store physical address of */
3487 /* next entry in cirular list of entries */
3488 info->rx_buf_list[i].next = info->buffer_list_phys;
3489 if ( i < info->rx_buf_count - 1 )
3490 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3492 info->rx_buf_list[i].length = SCABUFSIZE;
3495 for ( i = 0; i < info->tx_buf_count; i++ ) {
3496 /* calculate and store physical address of this buffer entry */
3497 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3498 ((info->rx_buf_count + i) * sizeof(SCADESC));
3500 /* calculate and store physical address of */
3501 /* next entry in cirular list of entries */
3503 info->tx_buf_list[i].next = info->buffer_list_phys +
3504 info->rx_buf_count * sizeof(SCADESC);
3506 if ( i < info->tx_buf_count - 1 )
3507 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3513 /* Allocate the frame DMA buffers used by the specified buffer list.
3515 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3518 unsigned long phys_addr;
3520 for ( i = 0; i < count; i++ ) {
3521 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3522 phys_addr = info->port_array[0]->last_mem_alloc;
3523 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3525 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3526 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3532 static void free_dma_bufs(SLMP_INFO *info)
3534 info->buffer_list = NULL;
3535 info->rx_buf_list = NULL;
3536 info->tx_buf_list = NULL;
3539 /* allocate buffer large enough to hold max_frame_size.
3540 * This buffer is used to pass an assembled frame to the line discipline.
3542 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3544 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3545 if (info->tmp_rx_buf == NULL)
3547 /* unused flag buffer to satisfy receive_buf calling interface */
3548 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3549 if (!info->flag_buf) {
3550 kfree(info->tmp_rx_buf);
3551 info->tmp_rx_buf = NULL;
3557 static void free_tmp_rx_buf(SLMP_INFO *info)
3559 kfree(info->tmp_rx_buf);
3560 info->tmp_rx_buf = NULL;
3561 kfree(info->flag_buf);
3562 info->flag_buf = NULL;
3565 static int claim_resources(SLMP_INFO *info)
3567 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3568 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3569 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3570 info->init_error = DiagStatus_AddressConflict;
3574 info->shared_mem_requested = true;
3576 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3577 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3578 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3579 info->init_error = DiagStatus_AddressConflict;
3583 info->lcr_mem_requested = true;
3585 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3586 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3587 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3588 info->init_error = DiagStatus_AddressConflict;
3592 info->sca_base_requested = true;
3594 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3595 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3596 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3597 info->init_error = DiagStatus_AddressConflict;
3601 info->sca_statctrl_requested = true;
3603 info->memory_base = ioremap_nocache(info->phys_memory_base,
3605 if (!info->memory_base) {
3606 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3607 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3608 info->init_error = DiagStatus_CantAssignPciResources;
3612 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3613 if (!info->lcr_base) {
3614 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3615 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3616 info->init_error = DiagStatus_CantAssignPciResources;
3619 info->lcr_base += info->lcr_offset;
3621 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3622 if (!info->sca_base) {
3623 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3624 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3625 info->init_error = DiagStatus_CantAssignPciResources;
3628 info->sca_base += info->sca_offset;
3630 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3632 if (!info->statctrl_base) {
3633 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3634 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3635 info->init_error = DiagStatus_CantAssignPciResources;
3638 info->statctrl_base += info->statctrl_offset;
3640 if ( !memory_test(info) ) {
3641 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3642 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3643 info->init_error = DiagStatus_MemoryError;
3650 release_resources( info );
3654 static void release_resources(SLMP_INFO *info)
3656 if ( debug_level >= DEBUG_LEVEL_INFO )
3657 printk( "%s(%d):%s release_resources() entry\n",
3658 __FILE__,__LINE__,info->device_name );
3660 if ( info->irq_requested ) {
3661 free_irq(info->irq_level, info);
3662 info->irq_requested = false;
3665 if ( info->shared_mem_requested ) {
3666 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3667 info->shared_mem_requested = false;
3669 if ( info->lcr_mem_requested ) {
3670 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3671 info->lcr_mem_requested = false;
3673 if ( info->sca_base_requested ) {
3674 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3675 info->sca_base_requested = false;
3677 if ( info->sca_statctrl_requested ) {
3678 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3679 info->sca_statctrl_requested = false;
3682 if (info->memory_base){
3683 iounmap(info->memory_base);
3684 info->memory_base = NULL;
3687 if (info->sca_base) {
3688 iounmap(info->sca_base - info->sca_offset);
3689 info->sca_base=NULL;
3692 if (info->statctrl_base) {
3693 iounmap(info->statctrl_base - info->statctrl_offset);
3694 info->statctrl_base=NULL;
3697 if (info->lcr_base){
3698 iounmap(info->lcr_base - info->lcr_offset);
3699 info->lcr_base = NULL;
3702 if ( debug_level >= DEBUG_LEVEL_INFO )
3703 printk( "%s(%d):%s release_resources() exit\n",
3704 __FILE__,__LINE__,info->device_name );
3707 /* Add the specified device instance data structure to the
3708 * global linked list of devices and increment the device count.
3710 static void add_device(SLMP_INFO *info)
3712 info->next_device = NULL;
3713 info->line = synclinkmp_device_count;
3714 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3716 if (info->line < MAX_DEVICES) {
3717 if (maxframe[info->line])
3718 info->max_frame_size = maxframe[info->line];
3721 synclinkmp_device_count++;
3723 if ( !synclinkmp_device_list )
3724 synclinkmp_device_list = info;
3726 SLMP_INFO *current_dev = synclinkmp_device_list;
3727 while( current_dev->next_device )
3728 current_dev = current_dev->next_device;
3729 current_dev->next_device = info;
3732 if ( info->max_frame_size < 4096 )
3733 info->max_frame_size = 4096;
3734 else if ( info->max_frame_size > 65535 )
3735 info->max_frame_size = 65535;
3737 printk( "SyncLink MultiPort %s: "
3738 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3740 info->phys_sca_base,
3741 info->phys_memory_base,
3742 info->phys_statctrl_base,
3743 info->phys_lcr_base,
3745 info->max_frame_size );
3747 #if SYNCLINK_GENERIC_HDLC
3752 static const struct tty_port_operations port_ops = {
3753 .carrier_raised = carrier_raised,
3757 /* Allocate and initialize a device instance structure
3759 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3761 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3765 info = kzalloc(sizeof(SLMP_INFO),
3769 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3770 __FILE__,__LINE__, adapter_num, port_num);
3772 tty_port_init(&info->port);
3773 info->port.ops = &port_ops;
3774 info->magic = MGSL_MAGIC;
3775 INIT_WORK(&info->task, bh_handler);
3776 info->max_frame_size = 4096;
3777 info->port.close_delay = 5*HZ/10;
3778 info->port.closing_wait = 30*HZ;
3779 init_waitqueue_head(&info->status_event_wait_q);
3780 init_waitqueue_head(&info->event_wait_q);
3781 spin_lock_init(&info->netlock);
3782 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3783 info->idle_mode = HDLC_TXIDLE_FLAGS;
3784 info->adapter_num = adapter_num;
3785 info->port_num = port_num;
3787 /* Copy configuration info to device instance data */
3788 info->irq_level = pdev->irq;
3789 info->phys_lcr_base = pci_resource_start(pdev,0);
3790 info->phys_sca_base = pci_resource_start(pdev,2);
3791 info->phys_memory_base = pci_resource_start(pdev,3);
3792 info->phys_statctrl_base = pci_resource_start(pdev,4);
3794 /* Because veremap only works on page boundaries we must map
3795 * a larger area than is actually implemented for the LCR
3796 * memory range. We map a full page starting at the page boundary.
3798 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3799 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3801 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3802 info->phys_sca_base &= ~(PAGE_SIZE-1);
3804 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3805 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3807 info->bus_type = MGSL_BUS_TYPE_PCI;
3808 info->irq_flags = IRQF_SHARED;
3810 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3811 setup_timer(&info->status_timer, status_timeout,
3812 (unsigned long)info);
3814 /* Store the PCI9050 misc control register value because a flaw
3815 * in the PCI9050 prevents LCR registers from being read if
3816 * BIOS assigns an LCR base address with bit 7 set.
3818 * Only the misc control register is accessed for which only
3819 * write access is needed, so set an initial value and change
3820 * bits to the device instance data as we write the value
3821 * to the actual misc control register.
3823 info->misc_ctrl_value = 0x087e4546;
3825 /* initial port state is unknown - if startup errors
3826 * occur, init_error will be set to indicate the
3827 * problem. Once the port is fully initialized,
3828 * this value will be set to 0 to indicate the
3829 * port is available.
3831 info->init_error = -1;
3837 static void device_init(int adapter_num, struct pci_dev *pdev)
3839 SLMP_INFO *port_array[SCA_MAX_PORTS];
3842 /* allocate device instances for up to SCA_MAX_PORTS devices */
3843 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3844 port_array[port] = alloc_dev(adapter_num,port,pdev);
3845 if( port_array[port] == NULL ) {
3846 for (--port; port >= 0; --port) {
3847 tty_port_destroy(&port_array[port]->port);
3848 kfree(port_array[port]);
3854 /* give copy of port_array to all ports and add to device list */
3855 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3856 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3857 add_device( port_array[port] );
3858 spin_lock_init(&port_array[port]->lock);
3861 /* Allocate and claim adapter resources */
3862 if ( !claim_resources(port_array[0]) ) {
3864 alloc_dma_bufs(port_array[0]);
3866 /* copy resource information from first port to others */
3867 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3868 port_array[port]->lock = port_array[0]->lock;
3869 port_array[port]->irq_level = port_array[0]->irq_level;
3870 port_array[port]->memory_base = port_array[0]->memory_base;
3871 port_array[port]->sca_base = port_array[0]->sca_base;
3872 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3873 port_array[port]->lcr_base = port_array[0]->lcr_base;
3874 alloc_dma_bufs(port_array[port]);
3877 if ( request_irq(port_array[0]->irq_level,
3878 synclinkmp_interrupt,
3879 port_array[0]->irq_flags,
3880 port_array[0]->device_name,
3881 port_array[0]) < 0 ) {
3882 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3884 port_array[0]->device_name,
3885 port_array[0]->irq_level );
3888 port_array[0]->irq_requested = true;
3889 adapter_test(port_array[0]);
3894 static const struct tty_operations ops = {
3899 .put_char = put_char,
3900 .flush_chars = flush_chars,
3901 .write_room = write_room,
3902 .chars_in_buffer = chars_in_buffer,
3903 .flush_buffer = flush_buffer,
3905 .throttle = throttle,
3906 .unthrottle = unthrottle,
3907 .send_xchar = send_xchar,
3908 .break_ctl = set_break,
3909 .wait_until_sent = wait_until_sent,
3910 .set_termios = set_termios,
3912 .start = tx_release,
3914 .tiocmget = tiocmget,
3915 .tiocmset = tiocmset,
3916 .get_icount = get_icount,
3917 .proc_fops = &synclinkmp_proc_fops,
3921 static void synclinkmp_cleanup(void)
3927 printk("Unloading %s %s\n", driver_name, driver_version);
3929 if (serial_driver) {
3930 if ((rc = tty_unregister_driver(serial_driver)))
3931 printk("%s(%d) failed to unregister tty driver err=%d\n",
3932 __FILE__,__LINE__,rc);
3933 put_tty_driver(serial_driver);
3937 info = synclinkmp_device_list;
3940 info = info->next_device;
3943 /* release devices */
3944 info = synclinkmp_device_list;
3946 #if SYNCLINK_GENERIC_HDLC
3949 free_dma_bufs(info);
3950 free_tmp_rx_buf(info);
3951 if ( info->port_num == 0 ) {
3953 write_reg(info, LPR, 1); /* set low power mode */
3954 release_resources(info);
3957 info = info->next_device;
3958 tty_port_destroy(&tmp->port);
3962 pci_unregister_driver(&synclinkmp_pci_driver);
3965 /* Driver initialization entry point.
3968 static int __init synclinkmp_init(void)
3972 if (break_on_load) {
3973 synclinkmp_get_text_ptr();
3977 printk("%s %s\n", driver_name, driver_version);
3979 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3980 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3984 serial_driver = alloc_tty_driver(128);
3985 if (!serial_driver) {
3990 /* Initialize the tty_driver structure */
3992 serial_driver->driver_name = "synclinkmp";
3993 serial_driver->name = "ttySLM";
3994 serial_driver->major = ttymajor;
3995 serial_driver->minor_start = 64;
3996 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3997 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3998 serial_driver->init_termios = tty_std_termios;
3999 serial_driver->init_termios.c_cflag =
4000 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4001 serial_driver->init_termios.c_ispeed = 9600;
4002 serial_driver->init_termios.c_ospeed = 9600;
4003 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4004 tty_set_operations(serial_driver, &ops);
4005 if ((rc = tty_register_driver(serial_driver)) < 0) {
4006 printk("%s(%d):Couldn't register serial driver\n",
4008 put_tty_driver(serial_driver);
4009 serial_driver = NULL;
4013 printk("%s %s, tty major#%d\n",
4014 driver_name, driver_version,
4015 serial_driver->major);
4020 synclinkmp_cleanup();
4024 static void __exit synclinkmp_exit(void)
4026 synclinkmp_cleanup();
4029 module_init(synclinkmp_init);
4030 module_exit(synclinkmp_exit);
4032 /* Set the port for internal loopback mode.
4033 * The TxCLK and RxCLK signals are generated from the BRG and
4034 * the TxD is looped back to the RxD internally.
4036 static void enable_loopback(SLMP_INFO *info, int enable)
4039 /* MD2 (Mode Register 2)
4040 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4042 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4044 /* degate external TxC clock source */
4045 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4046 write_control_reg(info);
4048 /* RXS/TXS (Rx/Tx clock source)
4049 * 07 Reserved, must be 0
4050 * 06..04 Clock Source, 100=BRG
4051 * 03..00 Clock Divisor, 0000=1
4053 write_reg(info, RXS, 0x40);
4054 write_reg(info, TXS, 0x40);
4057 /* MD2 (Mode Register 2)
4058 * 01..00 CNCT<1..0> Channel connection, 0=normal
4060 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4062 /* RXS/TXS (Rx/Tx clock source)
4063 * 07 Reserved, must be 0
4064 * 06..04 Clock Source, 000=RxC/TxC Pin
4065 * 03..00 Clock Divisor, 0000=1
4067 write_reg(info, RXS, 0x00);
4068 write_reg(info, TXS, 0x00);
4071 /* set LinkSpeed if available, otherwise default to 2Mbps */
4072 if (info->params.clock_speed)
4073 set_rate(info, info->params.clock_speed);
4075 set_rate(info, 3686400);
4078 /* Set the baud rate register to the desired speed
4080 * data_rate data rate of clock in bits per second
4081 * A data rate of 0 disables the AUX clock.
4083 static void set_rate( SLMP_INFO *info, u32 data_rate )
4086 unsigned char BRValue;
4089 /* fBRG = fCLK/(TMC * 2^BR)
4091 if (data_rate != 0) {
4092 Divisor = 14745600/data_rate;
4099 if (TMCValue != 1 && TMCValue != 2) {
4100 /* BRValue of 0 provides 50/50 duty cycle *only* when
4101 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4108 /* while TMCValue is too big for TMC register, divide
4109 * by 2 and increment BR exponent.
4111 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4114 write_reg(info, TXS,
4115 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4116 write_reg(info, RXS,
4117 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4118 write_reg(info, TMC, (unsigned char)TMCValue);
4121 write_reg(info, TXS,0);
4122 write_reg(info, RXS,0);
4123 write_reg(info, TMC, 0);
4129 static void rx_stop(SLMP_INFO *info)
4131 if (debug_level >= DEBUG_LEVEL_ISR)
4132 printk("%s(%d):%s rx_stop()\n",
4133 __FILE__,__LINE__, info->device_name );
4135 write_reg(info, CMD, RXRESET);
4137 info->ie0_value &= ~RXRDYE;
4138 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4140 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4141 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4142 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4144 info->rx_enabled = false;
4145 info->rx_overflow = false;
4148 /* enable the receiver
4150 static void rx_start(SLMP_INFO *info)
4154 if (debug_level >= DEBUG_LEVEL_ISR)
4155 printk("%s(%d):%s rx_start()\n",
4156 __FILE__,__LINE__, info->device_name );
4158 write_reg(info, CMD, RXRESET);
4160 if ( info->params.mode == MGSL_MODE_HDLC ) {
4161 /* HDLC, disabe IRQ on rxdata */
4162 info->ie0_value &= ~RXRDYE;
4163 write_reg(info, IE0, info->ie0_value);
4165 /* Reset all Rx DMA buffers and program rx dma */
4166 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4167 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4169 for (i = 0; i < info->rx_buf_count; i++) {
4170 info->rx_buf_list[i].status = 0xff;
4172 // throttle to 4 shared memory writes at a time to prevent
4173 // hogging local bus (keep latency time for DMA requests low).
4175 read_status_reg(info);
4177 info->current_rx_buf = 0;
4179 /* set current/1st descriptor address */
4180 write_reg16(info, RXDMA + CDA,
4181 info->rx_buf_list_ex[0].phys_entry);
4183 /* set new last rx descriptor address */
4184 write_reg16(info, RXDMA + EDA,
4185 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4187 /* set buffer length (shared by all rx dma data buffers) */
4188 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4190 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4191 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4193 /* async, enable IRQ on rxdata */
4194 info->ie0_value |= RXRDYE;
4195 write_reg(info, IE0, info->ie0_value);
4198 write_reg(info, CMD, RXENABLE);
4200 info->rx_overflow = false;
4201 info->rx_enabled = true;
4204 /* Enable the transmitter and send a transmit frame if
4205 * one is loaded in the DMA buffers.
4207 static void tx_start(SLMP_INFO *info)
4209 if (debug_level >= DEBUG_LEVEL_ISR)
4210 printk("%s(%d):%s tx_start() tx_count=%d\n",
4211 __FILE__,__LINE__, info->device_name,info->tx_count );
4213 if (!info->tx_enabled ) {
4214 write_reg(info, CMD, TXRESET);
4215 write_reg(info, CMD, TXENABLE);
4216 info->tx_enabled = true;
4219 if ( info->tx_count ) {
4221 /* If auto RTS enabled and RTS is inactive, then assert */
4222 /* RTS and set a flag indicating that the driver should */
4223 /* negate RTS when the transmission completes. */
4225 info->drop_rts_on_tx_done = false;
4227 if (info->params.mode != MGSL_MODE_ASYNC) {
4229 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4230 get_signals( info );
4231 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4232 info->serial_signals |= SerialSignal_RTS;
4233 set_signals( info );
4234 info->drop_rts_on_tx_done = true;
4238 write_reg16(info, TRC0,
4239 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4241 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4242 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4244 /* set TX CDA (current descriptor address) */
4245 write_reg16(info, TXDMA + CDA,
4246 info->tx_buf_list_ex[0].phys_entry);
4248 /* set TX EDA (last descriptor address) */
4249 write_reg16(info, TXDMA + EDA,
4250 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4252 /* enable underrun IRQ */
4253 info->ie1_value &= ~IDLE;
4254 info->ie1_value |= UDRN;
4255 write_reg(info, IE1, info->ie1_value);
4256 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4258 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4259 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4261 mod_timer(&info->tx_timer, jiffies +
4262 msecs_to_jiffies(5000));
4266 /* async, enable IRQ on txdata */
4267 info->ie0_value |= TXRDYE;
4268 write_reg(info, IE0, info->ie0_value);
4271 info->tx_active = true;
4275 /* stop the transmitter and DMA
4277 static void tx_stop( SLMP_INFO *info )
4279 if (debug_level >= DEBUG_LEVEL_ISR)
4280 printk("%s(%d):%s tx_stop()\n",
4281 __FILE__,__LINE__, info->device_name );
4283 del_timer(&info->tx_timer);
4285 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4286 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4288 write_reg(info, CMD, TXRESET);
4290 info->ie1_value &= ~(UDRN + IDLE);
4291 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4292 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4294 info->ie0_value &= ~TXRDYE;
4295 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4297 info->tx_enabled = false;
4298 info->tx_active = false;
4301 /* Fill the transmit FIFO until the FIFO is full or
4302 * there is no more data to load.
4304 static void tx_load_fifo(SLMP_INFO *info)
4308 /* do nothing is now tx data available and no XON/XOFF pending */
4310 if ( !info->tx_count && !info->x_char )
4313 /* load the Transmit FIFO until FIFOs full or all data sent */
4315 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4317 /* there is more space in the transmit FIFO and */
4318 /* there is more data in transmit buffer */
4320 if ( (info->tx_count > 1) && !info->x_char ) {
4322 TwoBytes[0] = info->tx_buf[info->tx_get++];
4323 if (info->tx_get >= info->max_frame_size)
4324 info->tx_get -= info->max_frame_size;
4325 TwoBytes[1] = info->tx_buf[info->tx_get++];
4326 if (info->tx_get >= info->max_frame_size)
4327 info->tx_get -= info->max_frame_size;
4329 write_reg16(info, TRB, *((u16 *)TwoBytes));
4331 info->tx_count -= 2;
4332 info->icount.tx += 2;
4334 /* only 1 byte left to transmit or 1 FIFO slot left */
4337 /* transmit pending high priority char */
4338 write_reg(info, TRB, info->x_char);
4341 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4342 if (info->tx_get >= info->max_frame_size)
4343 info->tx_get -= info->max_frame_size;
4351 /* Reset a port to a known state
4353 static void reset_port(SLMP_INFO *info)
4355 if (info->sca_base) {
4360 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4363 /* disable all port interrupts */
4364 info->ie0_value = 0;
4365 info->ie1_value = 0;
4366 info->ie2_value = 0;
4367 write_reg(info, IE0, info->ie0_value);
4368 write_reg(info, IE1, info->ie1_value);
4369 write_reg(info, IE2, info->ie2_value);
4371 write_reg(info, CMD, CHRESET);
4375 /* Reset all the ports to a known state.
4377 static void reset_adapter(SLMP_INFO *info)
4381 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4382 if (info->port_array[i])
4383 reset_port(info->port_array[i]);
4387 /* Program port for asynchronous communications.
4389 static void async_mode(SLMP_INFO *info)
4392 unsigned char RegValue;
4397 /* MD0, Mode Register 0
4399 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4400 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4401 * 03 Reserved, must be 0
4402 * 02 CRCCC, CRC Calculation, 0=disabled
4403 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4408 if (info->params.stop_bits != 1)
4410 write_reg(info, MD0, RegValue);
4412 /* MD1, Mode Register 1
4414 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4415 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4416 * 03..02 RXCHR<1..0>, rx char size
4417 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4422 switch (info->params.data_bits) {
4423 case 7: RegValue |= BIT4 + BIT2; break;
4424 case 6: RegValue |= BIT5 + BIT3; break;
4425 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4427 if (info->params.parity != ASYNC_PARITY_NONE) {
4429 if (info->params.parity == ASYNC_PARITY_ODD)
4432 write_reg(info, MD1, RegValue);
4434 /* MD2, Mode Register 2
4436 * 07..02 Reserved, must be 0
4437 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4442 if (info->params.loopback)
4443 RegValue |= (BIT1 + BIT0);
4444 write_reg(info, MD2, RegValue);
4446 /* RXS, Receive clock source
4448 * 07 Reserved, must be 0
4449 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4450 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4453 write_reg(info, RXS, RegValue);
4455 /* TXS, Transmit clock source
4457 * 07 Reserved, must be 0
4458 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4459 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4462 write_reg(info, TXS, RegValue);
4466 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4468 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4469 write_control_reg(info);
4473 /* RRC Receive Ready Control 0
4475 * 07..05 Reserved, must be 0
4476 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4478 write_reg(info, RRC, 0x00);
4480 /* TRC0 Transmit Ready Control 0
4482 * 07..05 Reserved, must be 0
4483 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4485 write_reg(info, TRC0, 0x10);
4487 /* TRC1 Transmit Ready Control 1
4489 * 07..05 Reserved, must be 0
4490 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4492 write_reg(info, TRC1, 0x1e);
4494 /* CTL, MSCI control register
4496 * 07..06 Reserved, set to 0
4497 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4498 * 04 IDLC, idle control, 0=mark 1=idle register
4499 * 03 BRK, break, 0=off 1 =on (async)
4500 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4501 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4502 * 00 RTS, RTS output control, 0=active 1=inactive
4507 if (!(info->serial_signals & SerialSignal_RTS))
4509 write_reg(info, CTL, RegValue);
4511 /* enable status interrupts */
4512 info->ie0_value |= TXINTE + RXINTE;
4513 write_reg(info, IE0, info->ie0_value);
4515 /* enable break detect interrupt */
4516 info->ie1_value = BRKD;
4517 write_reg(info, IE1, info->ie1_value);
4519 /* enable rx overrun interrupt */
4520 info->ie2_value = OVRN;
4521 write_reg(info, IE2, info->ie2_value);
4523 set_rate( info, info->params.data_rate * 16 );
4526 /* Program the SCA for HDLC communications.
4528 static void hdlc_mode(SLMP_INFO *info)
4530 unsigned char RegValue;
4533 // Can't use DPLL because SCA outputs recovered clock on RxC when
4534 // DPLL mode selected. This causes output contention with RxC receiver.
4535 // Use of DPLL would require external hardware to disable RxC receiver
4536 // when DPLL mode selected.
4537 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4539 /* disable DMA interrupts */
4540 write_reg(info, TXDMA + DIR, 0);
4541 write_reg(info, RXDMA + DIR, 0);
4543 /* MD0, Mode Register 0
4545 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4546 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4547 * 03 Reserved, must be 0
4548 * 02 CRCCC, CRC Calculation, 1=enabled
4549 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4550 * 00 CRC0, CRC initial value, 1 = all 1s
4555 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4557 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4559 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4560 RegValue |= BIT2 + BIT1;
4561 write_reg(info, MD0, RegValue);
4563 /* MD1, Mode Register 1
4565 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4566 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4567 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4568 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4573 write_reg(info, MD1, RegValue);
4575 /* MD2, Mode Register 2
4577 * 07 NRZFM, 0=NRZ, 1=FM
4578 * 06..05 CODE<1..0> Encoding, 00=NRZ
4579 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4580 * 02 Reserved, must be 0
4581 * 01..00 CNCT<1..0> Channel connection, 0=normal
4586 switch(info->params.encoding) {
4587 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4588 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4589 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4590 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4592 case HDLC_ENCODING_NRZB: /* not supported */
4593 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4594 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4597 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4600 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4606 write_reg(info, MD2, RegValue);
4609 /* RXS, Receive clock source
4611 * 07 Reserved, must be 0
4612 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4613 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4616 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4618 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4619 RegValue |= BIT6 + BIT5;
4620 write_reg(info, RXS, RegValue);
4622 /* TXS, Transmit clock source
4624 * 07 Reserved, must be 0
4625 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4626 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4629 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4631 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4632 RegValue |= BIT6 + BIT5;
4633 write_reg(info, TXS, RegValue);
4635 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4636 set_rate(info, info->params.clock_speed * DpllDivisor);
4638 set_rate(info, info->params.clock_speed);
4640 /* GPDATA (General Purpose I/O Data Register)
4642 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4644 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4645 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4647 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4648 write_control_reg(info);
4650 /* RRC Receive Ready Control 0
4652 * 07..05 Reserved, must be 0
4653 * 04..00 RRC<4..0> Rx FIFO trigger active
4655 write_reg(info, RRC, rx_active_fifo_level);
4657 /* TRC0 Transmit Ready Control 0
4659 * 07..05 Reserved, must be 0
4660 * 04..00 TRC<4..0> Tx FIFO trigger active
4662 write_reg(info, TRC0, tx_active_fifo_level);
4664 /* TRC1 Transmit Ready Control 1
4666 * 07..05 Reserved, must be 0
4667 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4669 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4671 /* DMR, DMA Mode Register
4673 * 07..05 Reserved, must be 0
4674 * 04 TMOD, Transfer Mode: 1=chained-block
4675 * 03 Reserved, must be 0
4676 * 02 NF, Number of Frames: 1=multi-frame
4677 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4678 * 00 Reserved, must be 0
4682 write_reg(info, TXDMA + DMR, 0x14);
4683 write_reg(info, RXDMA + DMR, 0x14);
4685 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4686 write_reg(info, RXDMA + CPB,
4687 (unsigned char)(info->buffer_list_phys >> 16));
4689 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4690 write_reg(info, TXDMA + CPB,
4691 (unsigned char)(info->buffer_list_phys >> 16));
4693 /* enable status interrupts. other code enables/disables
4694 * the individual sources for these two interrupt classes.
4696 info->ie0_value |= TXINTE + RXINTE;
4697 write_reg(info, IE0, info->ie0_value);
4699 /* CTL, MSCI control register
4701 * 07..06 Reserved, set to 0
4702 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4703 * 04 IDLC, idle control, 0=mark 1=idle register
4704 * 03 BRK, break, 0=off 1 =on (async)
4705 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4706 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4707 * 00 RTS, RTS output control, 0=active 1=inactive
4712 if (!(info->serial_signals & SerialSignal_RTS))
4714 write_reg(info, CTL, RegValue);
4716 /* preamble not supported ! */
4722 set_rate(info, info->params.clock_speed);
4724 if (info->params.loopback)
4725 enable_loopback(info,1);
4728 /* Set the transmit HDLC idle mode
4730 static void tx_set_idle(SLMP_INFO *info)
4732 unsigned char RegValue = 0xff;
4734 /* Map API idle mode to SCA register bits */
4735 switch(info->idle_mode) {
4736 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4737 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4738 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4739 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4740 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4741 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4742 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4745 write_reg(info, IDL, RegValue);
4748 /* Query the adapter for the state of the V24 status (input) signals.
4750 static void get_signals(SLMP_INFO *info)
4752 u16 status = read_reg(info, SR3);
4753 u16 gpstatus = read_status_reg(info);
4756 /* clear all serial signals except DTR and RTS */
4757 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4759 /* set serial signal bits to reflect MISR */
4761 if (!(status & BIT3))
4762 info->serial_signals |= SerialSignal_CTS;
4764 if ( !(status & BIT2))
4765 info->serial_signals |= SerialSignal_DCD;
4767 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4768 if (!(gpstatus & testbit))
4769 info->serial_signals |= SerialSignal_RI;
4771 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4772 if (!(gpstatus & testbit))
4773 info->serial_signals |= SerialSignal_DSR;
4776 /* Set the state of DTR and RTS based on contents of
4777 * serial_signals member of device context.
4779 static void set_signals(SLMP_INFO *info)
4781 unsigned char RegValue;
4784 RegValue = read_reg(info, CTL);
4785 if (info->serial_signals & SerialSignal_RTS)
4789 write_reg(info, CTL, RegValue);
4791 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4792 EnableBit = BIT1 << (info->port_num*2);
4793 if (info->serial_signals & SerialSignal_DTR)
4794 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4796 info->port_array[0]->ctrlreg_value |= EnableBit;
4797 write_control_reg(info);
4800 /*******************/
4801 /* DMA Buffer Code */
4802 /*******************/
4804 /* Set the count for all receive buffers to SCABUFSIZE
4805 * and set the current buffer to the first buffer. This effectively
4806 * makes all buffers free and discards any data in buffers.
4808 static void rx_reset_buffers(SLMP_INFO *info)
4810 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4813 /* Free the buffers used by a received frame
4815 * info pointer to device instance data
4816 * first index of 1st receive buffer of frame
4817 * last index of last receive buffer of frame
4819 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4824 /* reset current buffer for reuse */
4825 info->rx_buf_list[first].status = 0xff;
4827 if (first == last) {
4829 /* set new last rx descriptor address */
4830 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4834 if (first == info->rx_buf_count)
4838 /* set current buffer to next buffer after last buffer of frame */
4839 info->current_rx_buf = first;
4842 /* Return a received frame from the receive DMA buffers.
4843 * Only frames received without errors are returned.
4845 * Return Value: true if frame returned, otherwise false
4847 static bool rx_get_frame(SLMP_INFO *info)
4849 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4850 unsigned short status;
4851 unsigned int framesize = 0;
4852 bool ReturnCode = false;
4853 unsigned long flags;
4854 struct tty_struct *tty = info->port.tty;
4855 unsigned char addr_field = 0xff;
4857 SCADESC_EX *desc_ex;
4860 /* assume no frame returned, set zero length */
4865 * current_rx_buf points to the 1st buffer of the next available
4866 * receive frame. To find the last buffer of the frame look for
4867 * a non-zero status field in the buffer entries. (The status
4868 * field is set by the 16C32 after completing a receive frame.
4870 StartIndex = EndIndex = info->current_rx_buf;
4873 desc = &info->rx_buf_list[EndIndex];
4874 desc_ex = &info->rx_buf_list_ex[EndIndex];
4876 if (desc->status == 0xff)
4877 goto Cleanup; /* current desc still in use, no frames available */
4879 if (framesize == 0 && info->params.addr_filter != 0xff)
4880 addr_field = desc_ex->virt_addr[0];
4882 framesize += desc->length;
4884 /* Status != 0 means last buffer of frame */
4889 if (EndIndex == info->rx_buf_count)
4892 if (EndIndex == info->current_rx_buf) {
4893 /* all buffers have been 'used' but none mark */
4894 /* the end of a frame. Reset buffers and receiver. */
4895 if ( info->rx_enabled ){
4896 spin_lock_irqsave(&info->lock,flags);
4898 spin_unlock_irqrestore(&info->lock,flags);
4905 /* check status of receive frame */
4907 /* frame status is byte stored after frame data
4909 * 7 EOM (end of msg), 1 = last buffer of frame
4910 * 6 Short Frame, 1 = short frame
4911 * 5 Abort, 1 = frame aborted
4912 * 4 Residue, 1 = last byte is partial
4913 * 3 Overrun, 1 = overrun occurred during frame reception
4914 * 2 CRC, 1 = CRC error detected
4917 status = desc->status;
4919 /* ignore CRC bit if not using CRC (bit is undefined) */
4920 /* Note:CRC is not save to data buffer */
4921 if (info->params.crc_type == HDLC_CRC_NONE)
4924 if (framesize == 0 ||
4925 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4926 /* discard 0 byte frames, this seems to occur sometime
4927 * when remote is idling flags.
4929 rx_free_frame_buffers(info, StartIndex, EndIndex);
4936 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4937 /* received frame has errors,
4938 * update counts and mark frame size as 0
4941 info->icount.rxshort++;
4942 else if (status & BIT5)
4943 info->icount.rxabort++;
4944 else if (status & BIT3)
4945 info->icount.rxover++;
4947 info->icount.rxcrc++;
4950 #if SYNCLINK_GENERIC_HDLC
4952 info->netdev->stats.rx_errors++;
4953 info->netdev->stats.rx_frame_errors++;
4958 if ( debug_level >= DEBUG_LEVEL_BH )
4959 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4960 __FILE__,__LINE__,info->device_name,status,framesize);
4962 if ( debug_level >= DEBUG_LEVEL_DATA )
4963 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4964 min_t(unsigned int, framesize, SCABUFSIZE), 0);
4967 if (framesize > info->max_frame_size)
4968 info->icount.rxlong++;
4970 /* copy dma buffer(s) to contiguous intermediate buffer */
4971 int copy_count = framesize;
4972 int index = StartIndex;
4973 unsigned char *ptmp = info->tmp_rx_buf;
4974 info->tmp_rx_buf_count = framesize;
4976 info->icount.rxok++;
4979 int partial_count = min(copy_count,SCABUFSIZE);
4981 info->rx_buf_list_ex[index].virt_addr,
4983 ptmp += partial_count;
4984 copy_count -= partial_count;
4986 if ( ++index == info->rx_buf_count )
4990 #if SYNCLINK_GENERIC_HDLC
4992 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4995 ldisc_receive_buf(tty,info->tmp_rx_buf,
4996 info->flag_buf, framesize);
4999 /* Free the buffers used by this frame. */
5000 rx_free_frame_buffers( info, StartIndex, EndIndex );
5005 if ( info->rx_enabled && info->rx_overflow ) {
5006 /* Receiver is enabled, but needs to restarted due to
5007 * rx buffer overflow. If buffers are empty, restart receiver.
5009 if (info->rx_buf_list[EndIndex].status == 0xff) {
5010 spin_lock_irqsave(&info->lock,flags);
5012 spin_unlock_irqrestore(&info->lock,flags);
5019 /* load the transmit DMA buffer with data
5021 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5023 unsigned short copy_count;
5026 SCADESC_EX *desc_ex;
5028 if ( debug_level >= DEBUG_LEVEL_DATA )
5029 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
5031 /* Copy source buffer to one or more DMA buffers, starting with
5032 * the first transmit dma buffer.
5036 copy_count = min_t(unsigned int, count, SCABUFSIZE);
5038 desc = &info->tx_buf_list[i];
5039 desc_ex = &info->tx_buf_list_ex[i];
5041 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5043 desc->length = copy_count;
5047 count -= copy_count;
5053 if (i >= info->tx_buf_count)
5057 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5058 info->last_tx_buf = ++i;
5061 static bool register_test(SLMP_INFO *info)
5063 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5064 static unsigned int count = ARRAY_SIZE(testval);
5067 unsigned long flags;
5069 spin_lock_irqsave(&info->lock,flags);
5072 /* assume failure */
5073 info->init_error = DiagStatus_AddressFailure;
5075 /* Write bit patterns to various registers but do it out of */
5076 /* sync, then read back and verify values. */
5078 for (i = 0 ; i < count ; i++) {
5079 write_reg(info, TMC, testval[i]);
5080 write_reg(info, IDL, testval[(i+1)%count]);
5081 write_reg(info, SA0, testval[(i+2)%count]);
5082 write_reg(info, SA1, testval[(i+3)%count]);
5084 if ( (read_reg(info, TMC) != testval[i]) ||
5085 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5086 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5087 (read_reg(info, SA1) != testval[(i+3)%count]) )
5095 spin_unlock_irqrestore(&info->lock,flags);
5100 static bool irq_test(SLMP_INFO *info)
5102 unsigned long timeout;
5103 unsigned long flags;
5105 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5107 spin_lock_irqsave(&info->lock,flags);
5110 /* assume failure */
5111 info->init_error = DiagStatus_IrqFailure;
5112 info->irq_occurred = false;
5114 /* setup timer0 on SCA0 to interrupt */
5116 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5117 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5119 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5120 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5123 /* TMCS, Timer Control/Status Register
5125 * 07 CMF, Compare match flag (read only) 1=match
5126 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5127 * 05 Reserved, must be 0
5128 * 04 TME, Timer Enable
5129 * 03..00 Reserved, must be 0
5133 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5135 spin_unlock_irqrestore(&info->lock,flags);
5138 while( timeout-- && !info->irq_occurred ) {
5139 msleep_interruptible(10);
5142 spin_lock_irqsave(&info->lock,flags);
5144 spin_unlock_irqrestore(&info->lock,flags);
5146 return info->irq_occurred;
5149 /* initialize individual SCA device (2 ports)
5151 static bool sca_init(SLMP_INFO *info)
5153 /* set wait controller to single mem partition (low), no wait states */
5154 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5155 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5156 write_reg(info, WCRL, 0); /* wait controller low range */
5157 write_reg(info, WCRM, 0); /* wait controller mid range */
5158 write_reg(info, WCRH, 0); /* wait controller high range */
5160 /* DPCR, DMA Priority Control
5162 * 07..05 Not used, must be 0
5163 * 04 BRC, bus release condition: 0=all transfers complete
5164 * 03 CCC, channel change condition: 0=every cycle
5165 * 02..00 PR<2..0>, priority 100=round robin
5169 write_reg(info, DPCR, dma_priority);
5171 /* DMA Master Enable, BIT7: 1=enable all channels */
5172 write_reg(info, DMER, 0x80);
5174 /* enable all interrupt classes */
5175 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5176 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5177 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5179 /* ITCR, interrupt control register
5180 * 07 IPC, interrupt priority, 0=MSCI->DMA
5181 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5182 * 04 VOS, Vector Output, 0=unmodified vector
5183 * 03..00 Reserved, must be 0
5185 write_reg(info, ITCR, 0);
5190 /* initialize adapter hardware
5192 static bool init_adapter(SLMP_INFO *info)
5196 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5197 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5200 info->misc_ctrl_value |= BIT30;
5201 *MiscCtrl = info->misc_ctrl_value;
5204 * Force at least 170ns delay before clearing
5205 * reset bit. Each read from LCR takes at least
5206 * 30ns so 10 times for 300ns to be safe.
5209 readval = *MiscCtrl;
5211 info->misc_ctrl_value &= ~BIT30;
5212 *MiscCtrl = info->misc_ctrl_value;
5214 /* init control reg (all DTRs off, all clksel=input) */
5215 info->ctrlreg_value = 0xaa;
5216 write_control_reg(info);
5219 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5220 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5222 switch(read_ahead_count)
5225 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5228 lcr1_brdr_value |= BIT5 + BIT4;
5231 lcr1_brdr_value |= BIT5 + BIT3;
5234 lcr1_brdr_value |= BIT5;
5238 *LCR1BRDR = lcr1_brdr_value;
5239 *MiscCtrl = misc_ctrl_value;
5242 sca_init(info->port_array[0]);
5243 sca_init(info->port_array[2]);
5248 /* Loopback an HDLC frame to test the hardware
5249 * interrupt and DMA functions.
5251 static bool loopback_test(SLMP_INFO *info)
5253 #define TESTFRAMESIZE 20
5255 unsigned long timeout;
5256 u16 count = TESTFRAMESIZE;
5257 unsigned char buf[TESTFRAMESIZE];
5259 unsigned long flags;
5261 struct tty_struct *oldtty = info->port.tty;
5262 u32 speed = info->params.clock_speed;
5264 info->params.clock_speed = 3686400;
5265 info->port.tty = NULL;
5267 /* assume failure */
5268 info->init_error = DiagStatus_DmaFailure;
5270 /* build and send transmit frame */
5271 for (count = 0; count < TESTFRAMESIZE;++count)
5272 buf[count] = (unsigned char)count;
5274 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5276 /* program hardware for HDLC and enabled receiver */
5277 spin_lock_irqsave(&info->lock,flags);
5279 enable_loopback(info,1);
5281 info->tx_count = count;
5282 tx_load_dma_buffer(info,buf,count);
5284 spin_unlock_irqrestore(&info->lock,flags);
5286 /* wait for receive complete */
5287 /* Set a timeout for waiting for interrupt. */
5288 for ( timeout = 100; timeout; --timeout ) {
5289 msleep_interruptible(10);
5291 if (rx_get_frame(info)) {
5297 /* verify received frame length and contents */
5299 ( info->tmp_rx_buf_count != count ||
5300 memcmp(buf, info->tmp_rx_buf,count))) {
5304 spin_lock_irqsave(&info->lock,flags);
5305 reset_adapter(info);
5306 spin_unlock_irqrestore(&info->lock,flags);
5308 info->params.clock_speed = speed;
5309 info->port.tty = oldtty;
5314 /* Perform diagnostics on hardware
5316 static int adapter_test( SLMP_INFO *info )
5318 unsigned long flags;
5319 if ( debug_level >= DEBUG_LEVEL_INFO )
5320 printk( "%s(%d):Testing device %s\n",
5321 __FILE__,__LINE__,info->device_name );
5323 spin_lock_irqsave(&info->lock,flags);
5325 spin_unlock_irqrestore(&info->lock,flags);
5327 info->port_array[0]->port_count = 0;
5329 if ( register_test(info->port_array[0]) &&
5330 register_test(info->port_array[1])) {
5332 info->port_array[0]->port_count = 2;
5334 if ( register_test(info->port_array[2]) &&
5335 register_test(info->port_array[3]) )
5336 info->port_array[0]->port_count += 2;
5339 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5340 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5344 if ( !irq_test(info->port_array[0]) ||
5345 !irq_test(info->port_array[1]) ||
5346 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5347 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5348 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5349 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5353 if (!loopback_test(info->port_array[0]) ||
5354 !loopback_test(info->port_array[1]) ||
5355 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5356 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5357 printk( "%s(%d):DMA test failure for device %s\n",
5358 __FILE__,__LINE__,info->device_name);
5362 if ( debug_level >= DEBUG_LEVEL_INFO )
5363 printk( "%s(%d):device %s passed diagnostics\n",
5364 __FILE__,__LINE__,info->device_name );
5366 info->port_array[0]->init_error = 0;
5367 info->port_array[1]->init_error = 0;
5368 if ( info->port_count > 2 ) {
5369 info->port_array[2]->init_error = 0;
5370 info->port_array[3]->init_error = 0;
5376 /* Test the shared memory on a PCI adapter.
5378 static bool memory_test(SLMP_INFO *info)
5380 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5381 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5382 unsigned long count = ARRAY_SIZE(testval);
5384 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5385 unsigned long * addr = (unsigned long *)info->memory_base;
5387 /* Test data lines with test pattern at one location. */
5389 for ( i = 0 ; i < count ; i++ ) {
5391 if ( *addr != testval[i] )
5395 /* Test address lines with incrementing pattern over */
5396 /* entire address range. */
5398 for ( i = 0 ; i < limit ; i++ ) {
5403 addr = (unsigned long *)info->memory_base;
5405 for ( i = 0 ; i < limit ; i++ ) {
5406 if ( *addr != i * 4 )
5411 memset( info->memory_base, 0, SCA_MEM_SIZE );
5415 /* Load data into PCI adapter shared memory.
5417 * The PCI9050 releases control of the local bus
5418 * after completing the current read or write operation.
5420 * While the PCI9050 write FIFO not empty, the
5421 * PCI9050 treats all of the writes as a single transaction
5422 * and does not release the bus. This causes DMA latency problems
5423 * at high speeds when copying large data blocks to the shared memory.
5425 * This function breaks a write into multiple transations by
5426 * interleaving a read which flushes the write FIFO and 'completes'
5427 * the write transation. This allows any pending DMA request to gain control
5428 * of the local bus in a timely fasion.
5430 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5432 /* A load interval of 16 allows for 4 32-bit writes at */
5433 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5435 unsigned short interval = count / sca_pci_load_interval;
5438 for ( i = 0 ; i < interval ; i++ )
5440 memcpy(dest, src, sca_pci_load_interval);
5441 read_status_reg(info);
5442 dest += sca_pci_load_interval;
5443 src += sca_pci_load_interval;
5446 memcpy(dest, src, count % sca_pci_load_interval);
5449 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5454 printk("%s tx data:\n",info->device_name);
5456 printk("%s rx data:\n",info->device_name);
5464 for(i=0;i<linecount;i++)
5465 printk("%02X ",(unsigned char)data[i]);
5468 for(i=0;i<linecount;i++) {
5469 if (data[i]>=040 && data[i]<=0176)
5470 printk("%c",data[i]);
5479 } /* end of trace_block() */
5481 /* called when HDLC frame times out
5482 * update stats and do tx completion processing
5484 static void tx_timeout(unsigned long context)
5486 SLMP_INFO *info = (SLMP_INFO*)context;
5487 unsigned long flags;
5489 if ( debug_level >= DEBUG_LEVEL_INFO )
5490 printk( "%s(%d):%s tx_timeout()\n",
5491 __FILE__,__LINE__,info->device_name);
5492 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5493 info->icount.txtimeout++;
5495 spin_lock_irqsave(&info->lock,flags);
5496 info->tx_active = false;
5497 info->tx_count = info->tx_put = info->tx_get = 0;
5499 spin_unlock_irqrestore(&info->lock,flags);
5501 #if SYNCLINK_GENERIC_HDLC
5503 hdlcdev_tx_done(info);
5509 /* called to periodically check the DSR/RI modem signal input status
5511 static void status_timeout(unsigned long context)
5514 SLMP_INFO *info = (SLMP_INFO*)context;
5515 unsigned long flags;
5516 unsigned char delta;
5519 spin_lock_irqsave(&info->lock,flags);
5521 spin_unlock_irqrestore(&info->lock,flags);
5523 /* check for DSR/RI state change */
5525 delta = info->old_signals ^ info->serial_signals;
5526 info->old_signals = info->serial_signals;
5528 if (delta & SerialSignal_DSR)
5529 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5531 if (delta & SerialSignal_RI)
5532 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5534 if (delta & SerialSignal_DCD)
5535 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5537 if (delta & SerialSignal_CTS)
5538 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5541 isr_io_pin(info,status);
5543 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5547 /* Register Access Routines -
5548 * All registers are memory mapped
5550 #define CALC_REGADDR() \
5551 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5552 if (info->port_num > 1) \
5553 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5554 if ( info->port_num & 1) { \
5556 RegAddr += 0x40; /* DMA access */ \
5557 else if (Addr > 0x1f && Addr < 0x60) \
5558 RegAddr += 0x20; /* MSCI access */ \
5562 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5567 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5573 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5576 return *((u16 *)RegAddr);
5579 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5582 *((u16 *)RegAddr) = Value;
5585 static unsigned char read_status_reg(SLMP_INFO * info)
5587 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5591 static void write_control_reg(SLMP_INFO * info)
5593 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5594 *RegAddr = info->port_array[0]->ctrlreg_value;
5598 static int synclinkmp_init_one (struct pci_dev *dev,
5599 const struct pci_device_id *ent)
5601 if (pci_enable_device(dev)) {
5602 printk("error enabling pci device %p\n", dev);
5605 device_init( ++synclinkmp_adapter_count, dev );
5609 static void synclinkmp_remove_one (struct pci_dev *dev)