drivers/usb/dwc2/core_intr.c

   1 /*
   2  * core_intr.c - DesignWare HS OTG Controller common interrupt handling
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the common interrupt handlers
  39  */
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/io.h>
  47 #include <linux/slab.h>
  48 #include <linux/usb.h>
  49
  50 #include <linux/usb/hcd.h>
  51 #include <linux/usb/ch11.h>
  52
  53 #include "core.h"
  54 #include "hcd.h"
  55
  56 static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
  57 {
  58         switch (hsotg->op_state) {
  59         case OTG_STATE_A_HOST:
  60                 return "a_host";
  61         case OTG_STATE_A_SUSPEND:
  62                 return "a_suspend";
  63         case OTG_STATE_A_PERIPHERAL:
  64                 return "a_peripheral";
  65         case OTG_STATE_B_PERIPHERAL:
  66                 return "b_peripheral";
  67         case OTG_STATE_B_HOST:
  68                 return "b_host";
  69         default:
  70                 return "unknown";
  71         }
  72 }
  73
  74 /**
  75  * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
  76  * When the PRTINT interrupt fires, there are certain status bits in the Host
  77  * Port that needs to get cleared.
  78  *
  79  * @hsotg: Programming view of DWC_otg controller
  80  */
  81 static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
  82 {
  83         u32 hprt0 = readl(hsotg->regs + HPRT0);
  84
  85         if (hprt0 & HPRT0_ENACHG) {
  86                 hprt0 &= ~HPRT0_ENA;
  87                 writel(hprt0, hsotg->regs + HPRT0);
  88         }
  89
  90         /* Clear interrupt */
  91         writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS);
  92 }
  93
  94 /**
  95  * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
  96  *
  97  * @hsotg: Programming view of DWC_otg controller
  98  */
  99 static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
 100 {
 101         dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
 102                  dwc2_is_host_mode(hsotg) ? "Host" : "Device");
 103
 104         /* Clear interrupt */
 105         writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
 106 }
 107
 108 /**
 109  * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
 110  * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
 111  *
 112  * @hsotg: Programming view of DWC_otg controller
 113  */
 114 static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
 115 {
 116         u32 gotgint;
 117         u32 gotgctl;
 118         u32 gintmsk;
 119
 120         gotgint = readl(hsotg->regs + GOTGINT);
 121         gotgctl = readl(hsotg->regs + GOTGCTL);
 122         dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
 123                 dwc2_op_state_str(hsotg));
 124
 125         if (gotgint & GOTGINT_SES_END_DET) {
 126                 dev_dbg(hsotg->dev,
 127                         " ++OTG Interrupt: Session End Detected++ (%s)\n",
 128                         dwc2_op_state_str(hsotg));
 129                 gotgctl = readl(hsotg->regs + GOTGCTL);
 130
 131                 if (hsotg->op_state == OTG_STATE_B_HOST) {
 132                         hsotg->op_state = OTG_STATE_B_PERIPHERAL;
 133                 } else {
 134                         /*
 135                          * If not B_HOST and Device HNP still set, HNP did
 136                          * not succeed!
 137                          */
 138                         if (gotgctl & GOTGCTL_DEVHNPEN) {
 139                                 dev_dbg(hsotg->dev, "Session End Detected\n");
 140                                 dev_err(hsotg->dev,
 141                                         "Device Not Connected/Responding!\n");
 142                         }
 143
 144                         /*
 145                          * If Session End Detected the B-Cable has been
 146                          * disconnected
 147                          */
 148                         /* Reset to a clean state */
 149                         hsotg->lx_state = DWC2_L0;
 150                 }
 151
 152                 gotgctl = readl(hsotg->regs + GOTGCTL);
 153                 gotgctl &= ~GOTGCTL_DEVHNPEN;
 154                 writel(gotgctl, hsotg->regs + GOTGCTL);
 155         }
 156
 157         if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
 158                 dev_dbg(hsotg->dev,
 159                         " ++OTG Interrupt: Session Request Success Status Change++\n");
 160                 gotgctl = readl(hsotg->regs + GOTGCTL);
 161                 if (gotgctl & GOTGCTL_SESREQSCS) {
 162                         if (hsotg->core_params->phy_type ==
 163                                         DWC2_PHY_TYPE_PARAM_FS
 164                             && hsotg->core_params->i2c_enable > 0) {
 165                                 hsotg->srp_success = 1;
 166                         } else {
 167                                 /* Clear Session Request */
 168                                 gotgctl = readl(hsotg->regs + GOTGCTL);
 169                                 gotgctl &= ~GOTGCTL_SESREQ;
 170                                 writel(gotgctl, hsotg->regs + GOTGCTL);
 171                         }
 172                 }
 173         }
 174
 175         if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
 176                 /*
 177                  * Print statements during the HNP interrupt handling
 178                  * can cause it to fail
 179                  */
 180                 gotgctl = readl(hsotg->regs + GOTGCTL);
 181                 /*
 182                  * WA for 3.00a- HW is not setting cur_mode, even sometimes
 183                  * this does not help
 184                  */
 185                 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
 186                         udelay(100);
 187                 if (gotgctl & GOTGCTL_HSTNEGSCS) {
 188                         if (dwc2_is_host_mode(hsotg)) {
 189                                 hsotg->op_state = OTG_STATE_B_HOST;
 190                                 /*
 191                                  * Need to disable SOF interrupt immediately.
 192                                  * When switching from device to host, the PCD
 193                                  * interrupt handler won't handle the interrupt
 194                                  * if host mode is already set. The HCD
 195                                  * interrupt handler won't get called if the
 196                                  * HCD state is HALT. This means that the
 197                                  * interrupt does not get handled and Linux
 198                                  * complains loudly.
 199                                  */
 200                                 gintmsk = readl(hsotg->regs + GINTMSK);
 201                                 gintmsk &= ~GINTSTS_SOF;
 202                                 writel(gintmsk, hsotg->regs + GINTMSK);
 203
 204                                 /*
 205                                  * Call callback function with spin lock
 206                                  * released
 207                                  */
 208                                 spin_unlock(&hsotg->lock);
 209
 210                                 /* Initialize the Core for Host mode */
 211                                 dwc2_hcd_start(hsotg);
 212                                 spin_lock(&hsotg->lock);
 213                                 hsotg->op_state = OTG_STATE_B_HOST;
 214                         }
 215                 } else {
 216                         gotgctl = readl(hsotg->regs + GOTGCTL);
 217                         gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
 218                         writel(gotgctl, hsotg->regs + GOTGCTL);
 219                         dev_dbg(hsotg->dev, "HNP Failed\n");
 220                         dev_err(hsotg->dev,
 221                                 "Device Not Connected/Responding\n");
 222                 }
 223         }
 224
 225         if (gotgint & GOTGINT_HST_NEG_DET) {
 226                 /*
 227                  * The disconnect interrupt is set at the same time as
 228                  * Host Negotiation Detected. During the mode switch all
 229                  * interrupts are cleared so the disconnect interrupt
 230                  * handler will not get executed.
 231                  */
 232                 dev_dbg(hsotg->dev,
 233                         " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
 234                         (dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
 235                 if (dwc2_is_device_mode(hsotg)) {
 236                         dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
 237                                 hsotg->op_state);
 238                         spin_unlock(&hsotg->lock);
 239                         dwc2_hcd_disconnect(hsotg);
 240                         spin_lock(&hsotg->lock);
 241                         hsotg->op_state = OTG_STATE_A_PERIPHERAL;
 242                 } else {
 243                         /* Need to disable SOF interrupt immediately */
 244                         gintmsk = readl(hsotg->regs + GINTMSK);
 245                         gintmsk &= ~GINTSTS_SOF;
 246                         writel(gintmsk, hsotg->regs + GINTMSK);
 247                         spin_unlock(&hsotg->lock);
 248                         dwc2_hcd_start(hsotg);
 249                         spin_lock(&hsotg->lock);
 250                         hsotg->op_state = OTG_STATE_A_HOST;
 251                 }
 252         }
 253
 254         if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
 255                 dev_dbg(hsotg->dev,
 256                         " ++OTG Interrupt: A-Device Timeout Change++\n");
 257         if (gotgint & GOTGINT_DBNCE_DONE)
 258                 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
 259
 260         /* Clear GOTGINT */
 261         writel(gotgint, hsotg->regs + GOTGINT);
 262 }
 263
 264 /**
 265  * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
 266  * Change Interrupt
 267  *
 268  * @hsotg: Programming view of DWC_otg controller
 269  *
 270  * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
 271  * Device to Host Mode transition or a Host to Device Mode transition. This only
 272  * occurs when the cable is connected/removed from the PHY connector.
 273  */
 274 static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
 275 {
 276         u32 gintmsk = readl(hsotg->regs + GINTMSK);
 277
 278         /* Need to disable SOF interrupt immediately */
 279         gintmsk &= ~GINTSTS_SOF;
 280         writel(gintmsk, hsotg->regs + GINTMSK);
 281
 282         dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++  (%s)\n",
 283                 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
 284
 285         /*
 286          * Need to schedule a work, as there are possible DELAY function calls.
 287          * Release lock before scheduling workq as it holds spinlock during
 288          * scheduling.
 289          */
 290         spin_unlock(&hsotg->lock);
 291         queue_work(hsotg->wq_otg, &hsotg->wf_otg);
 292         spin_lock(&hsotg->lock);
 293
 294         /* Clear interrupt */
 295         writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
 296 }
 297
 298 /**
 299  * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
 300  * initiating the Session Request Protocol to request the host to turn on bus
 301  * power so a new session can begin
 302  *
 303  * @hsotg: Programming view of DWC_otg controller
 304  *
 305  * This handler responds by turning on bus power. If the DWC_otg controller is
 306  * in low power mode, this handler brings the controller out of low power mode
 307  * before turning on bus power.
 308  */
 309 static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
 310 {
 311         dev_dbg(hsotg->dev, "++Session Request Interrupt++\n");
 312
 313         /* Clear interrupt */
 314         writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
 315 }
 316
 317 /*
 318  * This interrupt indicates that the DWC_otg controller has detected a
 319  * resume or remote wakeup sequence. If the DWC_otg controller is in
 320  * low power mode, the handler must brings the controller out of low
 321  * power mode. The controller automatically begins resume signaling.
 322  * The handler schedules a time to stop resume signaling.
 323  */
 324 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 325 {
 326         dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
 327         dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
 328
 329         if (dwc2_is_device_mode(hsotg)) {
 330                 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", readl(hsotg->regs + DSTS));
 331                 if (hsotg->lx_state == DWC2_L2) {
 332                         u32 dctl = readl(hsotg->regs + DCTL);
 333
 334                         /* Clear Remote Wakeup Signaling */
 335                         dctl &= ~DCTL_RMTWKUPSIG;
 336                         writel(dctl, hsotg->regs + DCTL);
 337                 }
 338                 /* Change to L0 state */
 339                 hsotg->lx_state = DWC2_L0;
 340         } else {
 341                 if (hsotg->lx_state != DWC2_L1) {
 342                         u32 pcgcctl = readl(hsotg->regs + PCGCTL);
 343
 344                         /* Restart the Phy Clock */
 345                         pcgcctl &= ~PCGCTL_STOPPCLK;
 346                         writel(pcgcctl, hsotg->regs + PCGCTL);
 347                         mod_timer(&hsotg->wkp_timer,
 348                                   jiffies + msecs_to_jiffies(71));
 349                 } else {
 350                         /* Change to L0 state */
 351                         hsotg->lx_state = DWC2_L0;
 352                 }
 353         }
 354
 355         /* Clear interrupt */
 356         writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
 357 }
 358
 359 /*
 360  * This interrupt indicates that a device has been disconnected from the
 361  * root port
 362  */
 363 static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
 364 {
 365         dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
 366                 dwc2_is_host_mode(hsotg) ? "Host" : "Device",
 367                 dwc2_op_state_str(hsotg));
 368
 369         /* Change to L3 (OFF) state */
 370         hsotg->lx_state = DWC2_L3;
 371
 372         writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS);
 373 }
 374
 375 /*
 376  * This interrupt indicates that SUSPEND state has been detected on the USB.
 377  *
 378  * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
 379  * to "a_host".
 380  *
 381  * When power management is enabled the core will be put in low power mode.
 382  */
 383 static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
 384 {
 385         u32 dsts;
 386
 387         dev_dbg(hsotg->dev, "USB SUSPEND\n");
 388
 389         if (dwc2_is_device_mode(hsotg)) {
 390                 /*
 391                  * Check the Device status register to determine if the Suspend
 392                  * state is active
 393                  */
 394                 dsts = readl(hsotg->regs + DSTS);
 395                 dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts);
 396                 dev_dbg(hsotg->dev,
 397                         "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n",
 398                         !!(dsts & DSTS_SUSPSTS),
 399                         hsotg->hw_params.power_optimized);
 400         } else {
 401                 if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
 402                         dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
 403
 404                         /* Clear the a_peripheral flag, back to a_host */
 405                         spin_unlock(&hsotg->lock);
 406                         dwc2_hcd_start(hsotg);
 407                         spin_lock(&hsotg->lock);
 408                         hsotg->op_state = OTG_STATE_A_HOST;
 409                 }
 410         }
 411
 412         /* Change to L2 (suspend) state */
 413         hsotg->lx_state = DWC2_L2;
 414
 415         /* Clear interrupt */
 416         writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
 417 }
 418
 419 #define GINTMSK_COMMON  (GINTSTS_WKUPINT | GINTSTS_SESSREQINT |         \
 420                          GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT |        \
 421                          GINTSTS_MODEMIS | GINTSTS_DISCONNINT |         \
 422                          GINTSTS_USBSUSP | GINTSTS_PRTINT)
 423
 424 /*
 425  * This function returns the Core Interrupt register
 426  */
 427 static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
 428 {
 429         u32 gintsts;
 430         u32 gintmsk;
 431         u32 gahbcfg;
 432         u32 gintmsk_common = GINTMSK_COMMON;
 433
 434         gintsts = readl(hsotg->regs + GINTSTS);
 435         gintmsk = readl(hsotg->regs + GINTMSK);
 436         gahbcfg = readl(hsotg->regs + GAHBCFG);
 437
 438         /* If any common interrupts set */
 439         if (gintsts & gintmsk_common)
 440                 dev_dbg(hsotg->dev, "gintsts=%08x  gintmsk=%08x\n",
 441                         gintsts, gintmsk);
 442
 443         if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
 444                 return gintsts & gintmsk & gintmsk_common;
 445         else
 446                 return 0;
 447 }
 448
 449 /*
 450  * Common interrupt handler
 451  *
 452  * The common interrupts are those that occur in both Host and Device mode.
 453  * This handler handles the following interrupts:
 454  * - Mode Mismatch Interrupt
 455  * - OTG Interrupt
 456  * - Connector ID Status Change Interrupt
 457  * - Disconnect Interrupt
 458  * - Session Request Interrupt
 459  * - Resume / Remote Wakeup Detected Interrupt
 460  * - Suspend Interrupt
 461  */
 462 irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
 463 {
 464         struct dwc2_hsotg *hsotg = dev;
 465         u32 gintsts;
 466         irqreturn_t retval = IRQ_NONE;
 467
 468         if (!dwc2_is_controller_alive(hsotg)) {
 469                 dev_warn(hsotg->dev, "Controller is dead\n");
 470                 goto out;
 471         }
 472
 473         spin_lock(&hsotg->lock);
 474
 475         gintsts = dwc2_read_common_intr(hsotg);
 476         if (gintsts & ~GINTSTS_PRTINT)
 477                 retval = IRQ_HANDLED;
 478
 479         if (gintsts & GINTSTS_MODEMIS)
 480                 dwc2_handle_mode_mismatch_intr(hsotg);
 481         if (gintsts & GINTSTS_OTGINT)
 482                 dwc2_handle_otg_intr(hsotg);
 483         if (gintsts & GINTSTS_CONIDSTSCHNG)
 484                 dwc2_handle_conn_id_status_change_intr(hsotg);
 485         if (gintsts & GINTSTS_DISCONNINT)
 486                 dwc2_handle_disconnect_intr(hsotg);
 487         if (gintsts & GINTSTS_SESSREQINT)
 488                 dwc2_handle_session_req_intr(hsotg);
 489         if (gintsts & GINTSTS_WKUPINT)
 490                 dwc2_handle_wakeup_detected_intr(hsotg);
 491         if (gintsts & GINTSTS_USBSUSP)
 492                 dwc2_handle_usb_suspend_intr(hsotg);
 493
 494         if (gintsts & GINTSTS_PRTINT) {
 495                 /*
 496                  * The port interrupt occurs while in device mode with HPRT0
 497                  * Port Enable/Disable
 498                  */
 499                 if (dwc2_is_device_mode(hsotg)) {
 500                         dev_dbg(hsotg->dev,
 501                                 " --Port interrupt received in Device mode--\n");
 502                         dwc2_handle_usb_port_intr(hsotg);
 503                         retval = IRQ_HANDLED;
 504                 }
 505         }
 506
 507         spin_unlock(&hsotg->lock);
 508 out:
 509         return retval;
 510 }
 511 EXPORT_SYMBOL_GPL(dwc2_handle_common_intr);